Array substrate, preparation method of array substrate and display panel

Abstract

The invention discloses an array substrate, a preparation method of the array substrate and a display panel, and relates to the field of display, the array substrate comprises a substrate, a first metal layer, an insulating layer and a second metal layer, the first metal layer is arranged on one side of the substrate; the insulating layer is arranged on the side, away from the substrate, of the first metal layer; the second metal layer is arranged on one side of the insulating layer away from the first metal layer; the orthographic projection of the first metal layer and the orthographic projection of the second metal layer on the substrate form an overlapping area, the insulating layer comprises two sub-insulating layers which are sequentially stacked, the orthographic projection of one sub-insulating layer on the substrate at least covers the overlapping area, the two sub-insulating layers are made of different materials, and the two sub-insulating layers are made of different materials. The orthographic projection on the substrate at least covers the sub-insulating layer in the overlapping region, and the conductivity of the sub-insulating layer is poorer than that of the other sub-insulating layer; through the above design, the insulation capability is enhanced, and short circuit is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a method for preparing the array substrate, and a display panel. Background Art

[0002] In the field of semiconductor manufacturing technology, thin-film transistors (TFTs) are important devices widely used in display devices. The TFT manufacturing process typically involves the use of various metal materials, such as copper (Cu). This process involves the cross-arrangement of gate lines and data lines. This arrangement easily forms a Cu / GI / Cu sandwich structure in the overlapping area, which can be considered a diffused memristor.

[0003] The scan line layer is the first metal layer, and the data line layer is the second metal layer. The second metal layer serves as the anode (M2). The scan line and the data line are crossed to form an overlapping area. In the overlapping area, Cu undergoes oxidation reaction in the second metal layer to generate Cu 2+ , and diffuses under the action of the electric field, gradually diffusing to the gate insulating layer (GI), the first metal layer serves as the cathode (M1), Cu 2+ The first metal layer can be reduced to Cu element. At this time, as time goes by, the generated Cu will gradually penetrate the insulating layer (GI). At this time, a large current is likely to be generated, causing metal damage, resulting in a short circuit between the second metal layer and the first metal layer, affecting the display.

[0004] Therefore, the above problems need to be solved urgently. Summary of the Invention

[0005] The purpose of the present application is to provide an array substrate, a method for preparing the array substrate, and a display panel that enhances insulation capability and avoids short circuits.

[0006] The present application discloses an array substrate, comprising a substrate, a first metal layer, an insulating layer, and a second metal layer, wherein the first metal layer is arranged on one side of the substrate; the insulating layer is arranged on a side of the first metal layer away from the substrate; the second metal layer is arranged on a side of the insulating layer away from the first metal layer; the orthographic projections of the first metal layer and the second metal layer on the substrate form an overlapping area, the insulating layer comprises two sub-insulating layers stacked in sequence, and the orthographic projection of one of the sub-insulating layers on the substrate at least covers the overlapping area, wherein the two sub-insulating layers are made of different materials, and the orthographic projections on the substrate at least cover the overlapping area, and the conductivity of the sub-insulating layer is worse than that of the other sub-insulating layer.

[0007] Optionally, the two sub-insulating layers include a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is arranged on the side of the first metal layer away from the substrate, and is arranged corresponding to the overlapping area; the second sub-insulating layer is arranged on the side of the first sub-insulating layer away from the first metal layer, and covers the first sub-insulating layer and the first metal layer; the first insulating layer is used to block the copper ions of the second metal layer from diffusing to the first metal layer; along the extension direction of the first metal layer, the width of the positive projection of the first insulating layer on the substrate is at least equal to the width of the overlapping area.

[0008] Optionally, the first insulating layer is copper oxide and is made by an oxygen plasma oxidation process; the second insulating layer is at least one of silicon oxide or silicon oxynitride.

[0009] Optionally, the thickness of the first insulating layer is 30 nm-50 nm, wherein the thickness of the first insulating layer is 5%-10% of the thickness of the first metal layer.

[0010] Optionally, the two sub-insulating layers include a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is arranged on the side of the first metal layer away from the substrate and covers the first metal layer; the second sub-insulating layer is arranged on the side of the first sub-insulating layer away from the first metal layer and is arranged corresponding to the overlapping area; the second insulating layer is used to block the copper ions of the second metal layer from diffusing to the first metal layer; along the extension direction of the first metal layer, the width of the positive projection of the second insulating layer on the substrate is at least equal to the width of the overlapping area; the second insulating layer is copper oxide and is made by an oxygen plasma oxidation process, and the first insulating layer is at least one of silicon oxide or silicon oxynitride.

[0011] Optionally, the non-overlapping position of the first metal layer and the second metal layer forms a non-overlapping area, and the thickness of the second insulating layer corresponding to the non-overlapping area is set to H1, the thickness of the second insulating layer corresponding to the overlapping area is set to H2, and the thickness of the first insulating layer is set to H3, wherein H1>H2; H1≦H2+H3.

[0012] The present application also discloses a method for preparing an array substrate, which is used to prepare the array substrate as described above, comprising the steps of:

[0013] providing a substrate;

[0014] depositing a first metal layer on the substrate;

[0015] depositing a photoresist layer on the first metal layer;

[0016] performing exposure and etching on the overlapping area of ​​the photoresist layer to expose the first metal layer in the overlapping area;

[0017] forming a first insulating layer on the exposed first metal layer;

[0018] removing the photoresist layer;

[0019] forming a second insulating layer over the first insulating layer to cover the first metal layer and the first insulating layer; and

[0020] A second metal layer is formed above the second insulating layer at a position corresponding to the first metal layer.

[0021] Optionally, the step of forming a first insulating layer on the exposed first metal layer by using a process includes:

[0022] The exposed first metal layer is oxidized by an oxygen plasma oxidation process to generate a copper oxide layer in the overlapping area to form the first insulating layer.

[0023] Optionally, in the step of oxidizing the exposed first metal layer using an oxygen plasma oxidation process to generate a copper oxide layer in the overlapping area, the oxygen plasma oxidation process uses gas: O2; power: 200w-10000w; flow: 200sccm-1000sccm; time: 3s-20s.

[0024] The present application also discloses a display panel, comprising a color filter substrate and the array substrate as described above, wherein the array substrate and the color filter substrate are arranged opposite to each other.

[0025] Compared with the prior art, Cu undergoes oxidation reaction in the second metal layer to generate Cu 2+ , and diffuses under the action of the electric field, gradually diffuses to the gate insulating layer, Cu 2+The first metal layer can be reduced to Cu element. At this time, as time goes by, the generated Cu will gradually penetrate the insulating layer (GI). At this time, a large current is easily generated, which causes metal damage, resulting in a short circuit between the second metal layer and the first metal layer, affecting the display scheme. The array substrate of the present application includes a substrate, a first metal layer, an insulating layer and a second metal layer. The first metal layer is arranged on one side of the substrate; the insulating layer is arranged on the side of the first metal layer away from the substrate; the second metal layer is arranged on the side of the insulating layer away from the first metal layer; the orthographic projections of the first metal layer and the second metal layer on the substrate form an overlapping area, and the insulating layer includes a stacked arrangement of The present invention provides two sub-insulating layers, and the orthographic projection of one of the sub-insulating layers on the substrate covers at least the overlapping area, wherein the two sub-insulating layers are made of different materials, and the conductivity of the sub-insulating layer whose orthographic projection on the substrate covers at least the overlapping area is worse than the conductivity of the other sub-insulating layer. In this way, the insulation barrier capability between the second insulating layer and the first metal layer is enhanced by the sub-insulating layer corresponding to the overlapping area, so as to prevent the copper ions of the second metal layer from being reduced to copper element at the first metal layer. The generated copper element gradually accumulates, causing the second insulating layer to be broken down, thereby avoiding the problem of short circuit between the second metal layer and the first metal layer, thereby ensuring the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0027] Figure 1 This is a schematic block diagram of a display panel provided by the present application;

[0028] Figure 2 This is a partial structural diagram of an array substrate provided by the present application;

[0029] Figure 3 The first embodiment of this application provides Figure 2 Schematic diagram of the cross-sectional structure along the cross-sectional line A-A';

[0030] Figure 4 The first embodiment of this application provides Figure 2 Schematic diagram of the cross-sectional structure along the cross-sectional line BB';

[0031] Figure 5 This is a schematic diagram of the process steps provided in the first embodiment of the present application;

[0032] Figure 61 is a schematic flow chart of a method for preparing an array substrate according to the first embodiment of the present application;

[0033] Figure 7 The second embodiment of this application provides Figure 2 Schematic diagram of the cross-sectional structure along the cross-sectional line A-A';

[0034] Figure 8 The third embodiment of this application provides Figure 2 Schematic diagram of the cross-sectional structure along the cross-sectional line A-A';

[0035] Figure 9 This is a schematic diagram of the process steps provided in the third embodiment of the present application;

[0036] Figure 10 3 is a flow chart of a method for preparing an array substrate provided in the third embodiment of the present application.

[0037] Among them, 10, display panel; 100, array substrate; 110, substrate; 120, first metal layer; 130, insulating layer; 131, first insulating layer; 132, second insulating layer; 140, second metal layer; 150, photoresist layer; 160, third metal layer; 170, overlapping area; 180, non-overlapping area. DETAILED DESCRIPTION

[0038] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0039] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of such features; "multiple" means two or more. In addition, terms indicating orientation or positional relationships such as "up", "down", "left", "right", "second direction", and "first direction" are based on the orientation or relative positional relationships shown in the accompanying drawings. They are only simplified descriptions for the convenience of describing this application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0040] Figure 1 is a block diagram of the display panel provided in this application. Figure 2This is a partial structural diagram of an array substrate provided by this application, such as Figure 1-Figure 2 As shown, the present application discloses an array substrate 100, including a substrate 110, a first metal layer 120, an insulating layer 130 and a second metal layer 140, wherein the first metal layer 120 is arranged on one side of the substrate 110; the insulating layer 130 is arranged on the side of the first metal layer 120 away from the substrate 110; the second metal layer 140 is arranged on the side of the insulating layer 130 away from the first metal layer 120; the orthographic projections of the first metal layer 120 and the second metal layer 140 on the substrate 110 form an overlapping area 170, and the insulating layer 130 includes two layers of sub-insulating layers 130 stacked in sequence, and the orthographic projection of one layer of the sub-insulating layers 130 on the substrate 110 at least covers the overlapping area 170, wherein the two layers of the sub-insulating layers 130 are made of different materials, and the orthographic projections on the substrate 110 at least cover the overlapping area 170, and the conductivity of the sub-insulating layer 130 is worse than the conductivity of the other layer of the sub-insulating layer 130.

[0041] Compared with the prior art, Cu undergoes oxidation reaction in the second metal layer 140 to generate Cu 2+ , and diffuses under the action of the electric field, gradually diffuses to the gate insulating layer 130, Cu 2+The first metal layer 120 can be reduced to Cu elemental substance. At this time, as time goes by, the generated Cu will gradually penetrate the insulating layer 130 (GI). At this time, a large current is easily generated, resulting in metal damage, causing a short circuit between the second metal layer 140 and the first metal layer 120, affecting the display scheme. The array substrate 100 of the present application includes a substrate 110, a first metal layer 120, an insulating layer 130 and a second metal layer 140. The first metal layer 120 is arranged on one side of the substrate 110; the insulating layer 130 is arranged on the side of the first metal layer 120 away from the substrate 110; the second metal layer 140 is arranged on the side of the insulating layer 130 away from the first metal layer 120; the orthographic projections of the first metal layer 120 and the second metal layer 140 on the substrate 110 form an overlapping area 170, and the insulating layer 130 includes Two layers of sub-insulating layers 130 are stacked in sequence, and the orthographic projection of one layer of the sub-insulating layers 130 on the substrate 110 covers at least the overlapping area 170. The two layers of sub-insulating layers 130 are made of different materials, and the orthographic projection of the sub-insulating layer 130 on the substrate 110 covers at least the overlapping area 170. The conductivity of the sub-insulating layer 130 is worse than that of the other layer of the sub-insulating layer 130. In this way, the insulation barrier capability between the second insulating layer 132 and the first metal layer 120 is enhanced by the sub-insulating layer 130 corresponding to the overlapping area 170, so as to avoid the copper ions in the second metal layer 140 from being reduced to copper element at the first metal layer 120. The generated copper element gradually accumulates, which will cause the second insulating layer 132 to be broken down, thereby avoiding the problem of short circuit between the second metal layer 140 and the first metal layer 120, thereby ensuring the display effect.

[0042] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0043] First embodiment:

[0044] Specifically, Figure 3 The first embodiment of this application provides Figure 2 Schematic diagram of the cross-sectional structure along the section line A-A', Figure 4 The first embodiment of this application provides Figure 2 Schematic diagram of the cross-section structure along the section line B-B', combined with Figure 3-Figure 4The two sub-insulating layers 130 include a first sub-insulating layer 130 and a second sub-insulating layer 130. The first sub-insulating layer 130 is arranged on the side of the first metal layer 120 away from the substrate 110 and is arranged corresponding to the overlapping area 170; the second sub-insulating layer 130 is arranged on the side of the first sub-insulating layer 130 away from the first metal layer 120 and covers the first sub-insulating layer 130 and the first metal layer 120; the first insulating layer 131 is used to block the copper ions of the second metal layer 140 from diffusing to the first metal layer 120. Specifically, the first metal layer 120 and the second metal layer 140 are both copper layers. Therefore, the present application is set up like this After the first insulating layer 131 is formed, the first insulating layer 131 can be used as a barrier layer to block the diffusion of copper ions in the second metal layer 140, so that the copper ions generated by the second metal layer 140 stay in the second insulating layer 132 and the second metal layer 140 and cannot diffuse, thereby slowing down the speed at which the second metal layer 140 oxidizes to generate copper ions, and then slowing down the diffusion speed of the copper ions, so as to achieve the purpose of preventing the second metal layer 140 from oxidizing to generate a large amount of copper ions to penetrate the second insulating layer 132, thereby reducing the probability of metal copper breakdown failure in the overlapping area 170 of the data line and the scan line during long-term operation of the display device, and improving the service life of the display device.

[0045] Along the extension direction of the first metal layer 120, the width of the positive projection of the first insulating layer 131 on the substrate 110 is equal to the width of the overlapping area 170, that is, the first insulating layer 131 isolates the area between the first metal layer 120 and the second metal layer 140 where copper ion reduction reaction may occur. Even if the copper ions of the second metal layer 140 diffuse, no matter where in the overlapping area 170, they can be blocked by the first insulating layer 131, thereby preventing the copper ions in the second metal layer 140 from contacting the second metal layer 140 to produce an oxidation-reduction reaction.

[0046] The second insulating layer 132 is the gate insulating layer 130 (GI layer). In a TFT, poor insulation performance of the GI layer can cause gate signal leakage, affecting the pixel's charge and discharge process and causing display anomalies. The gate insulating layer 130 is composed of at least one of silicon oxide or silicon oxynitride. The GI layer can also have a multilayer structure, for example, depositing a layer of silicon oxynitride followed by a layer of silicon oxide. This multilayer structure leverages the advantages of different materials, further improving the insulation performance, stability, and interface quality of the GI layer, thereby enhancing the overall performance of the display panel 10.

[0047] The first insulating layer 131 is copper oxide, and the first insulating layer 131 is made by adopting an oxygen plasma oxidation process; the oxygen plasma oxidation process (O-plasma process) is a plasma technology that uses oxygen (O2) as a working gas. During the plasma treatment process, oxygen plasma can produce highly active oxygen free radicals and ozone. These active substances have a strong oxidizing effect on the surface of the material, which can effectively remove surface pollutants, improve surface wettability, enhance surface adhesion, etc. In this application, an oxygen plasma process is used, that is, O-plasma is used to react the photoresist in the unexposed area of ​​the HTM, so that the etching rate of the photoresist by O-plasma can be obtained. When the metal is exposed at the cross-line, the first metal layer 120Cu can be subjected to O-plasma treatment at this time, so that copper oxide is formed in the corresponding overlapping area 170 on the first metal layer 120.

[0048] On the one hand, copper oxide has poor conductivity and is equivalent to an insulator, which can truly block the copper ions generated by the oxidation of the second metal layer 140 and block the copper ions in the second insulating layer 132; on the other hand, the oxygen plasma oxidation process is used to directly react on the first metal layer 120 to form a copper oxide layer, without the need for an additional etching process, thereby reducing production costs.

[0049] Increasing the thickness of the GI layer can improve the above-mentioned problem to a certain extent and further isolate the copper ions. However, as the thickness of the GI layer increases, it becomes more difficult for electrons to cross the band gap, which reduces the TFT Ion and thus affects the display effect of the display device. In addition, increasing the thickness of the GI layer will also increase the transmittance of the OC and affect the image quality. However, the present application does not increase the thickness of the GI layer. Therefore, it will not affect the TFT Ion and ensure the transmittance of the OC.

[0050] Of course, the first insulating layer 131 may also be formed by a deposition process to etch away the photoresist layer 150 on the first metal layer 120 corresponding to the overlapping region 170 , and then deposit copper oxide in the overlapping region 170 .

[0051] The thickness of the copper oxide is 30nm-50nm, which is 5%-10% of the thickness of the first metal layer 120, and the ratio between the first insulating layer 131 and the second insulating layer 132 is 1:50-1:10, that is, only a thin layer is needed to block the copper ions and prevent the diffusion of copper ions.

[0052] The non-overlapping area 180 is formed at the non-overlapping position of the first metal layer 120 and the second metal layer 140. The thickness of the second insulating layer 132 corresponding to the non-overlapping area 180 is H1, the thickness of the second insulating layer 132 corresponding to the overlapping area 170 is H2, and the thickness of the first insulating layer 131 is H3, wherein H1>H2; H1≦H2+H3. Due to the existence of the first metal layer 120 below the overlapping area 170, when preparing the second insulating layer 132, the thickness of the second insulating layer 132 at the overlapping area 170 will be slightly thinner than the thickness of the second insulating layer 132 at the non-overlapping area 180. At this time, the copper oxide layer generated by oxidation just makes up for this difference, so that the thickness of the overall insulating layer 130 formed in the overlapping area 170 is equivalent to the thickness of the second insulating layer 132 in the non-overlapping area 180, ensuring the overall isolation effect.

[0053] Figure 5 This is a schematic diagram of the process steps provided in the first embodiment of the present application. Figure 6 This is a flow chart of a method for preparing an array substrate according to the first embodiment of the present application. Figure 5-Figure 6 The present application also discloses a method for preparing an array substrate 100, which is used to prepare the array substrate 100 as described above, comprising the steps of:

[0054] S1: providing a substrate;

[0055] S2: forming a first metal layer on the substrate;

[0056] S3: forming a photoresist layer on the first metal layer;

[0057] S4: performing exposure and etching on the overlapping area of ​​the photoresist layer to expose the first metal layer in the overlapping area;

[0058] S5: forming a first insulating layer on the exposed first metal layer;

[0059] S6: removing the photoresist layer;

[0060] S7: forming a second insulating layer on the first insulating layer to cover the first metal layer and the first insulating layer; and

[0061] S8: forming a second metal layer above the second insulating layer at a position corresponding to the first metal layer.

[0062] in, Figure 5In the formation of the first metal layer 120, the photoresist layer 150, the second insulating layer 132, and the second metal layer 140, deposition can be used. When removing the photoresist layer 150, the HTM mask technology is adopted to expose and etch the positions to be removed. These are all relatively mature technologies and do not belong to the key inventions of this application, so they will not be elaborated here.

[0063] The step of forming the first insulating layer 131 above the exposed first metal layer 120 by using a process includes:

[0064] Performing an oxidation treatment on the exposed first metal layer 120 by using an oxygen plasma oxidation process to generate a copper oxide layer in the overlapping region 170 to form the first insulating layer 131.

[0065] In the step of performing an oxidation treatment on the exposed first metal layer 120 by using an oxygen plasma oxidation process to generate a copper oxide layer in the overlapping region 170, the oxygen plasma oxidation process uses a gas: O2; power: 200w - 10000w; flow rate: 200sccm - 1000sccm; time: 3s - 20s. Among them, through experiments, the inventor found that when the power is 200w - 2000w, the oxidation effect is the best. At this time, the formation speed of the copper oxide layer is fast and the density of the copper oxide layer is good.

[0066] Second Embodiment:

[0067] Figure 7 is the Figure 2 cross-sectional structure schematic diagram along the section line A - A', as Figure 7 shown. As the second embodiment of this application, the difference between this embodiment and the first embodiment is that along the extension direction of the first metal layer 120, the width of the orthographic projection of the first insulating layer 131 on the substrate 110 is greater than the width of the overlapping region 170. The first insulating layer 131 protrudes from the overlapping region 170 to form a first protrusion and a second protrusion. Let the width of the overlapping region 170 be a, and let the width of the first insulating layer 131 be b, where 0 < b - a < 1.5 microns. In this way, the first protrusion and the second protrusion further form an isolation region. Even if too many copper ions generated after the oxidation of the second metal layer 140 accumulate in the second insulating layer 132, it is difficult to contact the first metal layer 120 and be reduced to elemental copper, and the copper ions are completely isolated at the second insulating layer 132.

[0068] Third Embodiment:

[0069] Figure 8 is the Figure 2The schematic diagram of the cross-sectional structure along the cross-sectional line A-A' is as follows: Figure 8 As shown, as the second embodiment of the present application, this embodiment is different from the first and second embodiments in that the first sub-insulating layer 130 is arranged on a side of the first metal layer 120 away from the substrate 110 and covers the first metal layer 120; the second sub-insulating layer 130 is arranged on a side of the first sub-insulating layer 130 away from the first metal layer 120 and is arranged corresponding to the overlapping area 170;

[0070] The second insulating layer 132 is used to prevent copper ions in the second metal layer 140 from diffusing into the first metal layer 120 . Along the extension direction of the first metal layer 120 , the width of the orthographic projection of the second insulating layer 132 on the substrate 110 is equal to the width of the overlapping area 170 .

[0071] That is, a copper oxide insulating layer 130 is formed under the second metal layer 140. Even if the copper in the second metal layer 140 is oxidized, it is difficult to diffuse through the copper oxide layer.

[0072] The silicon oxide layer or silicon oxide layer plays a protective role, preventing the diffusion of copper ions from damaging the performance of the first insulating layer 131, thereby ensuring the integrity of the film layer.

[0073] Figure 9 This is a schematic diagram of the process steps provided in the third embodiment of the present application. Figure 10 This is a flow chart of a method for preparing an array substrate according to a third embodiment of the present application, Figure 9-10 The method for preparing the array substrate in this embodiment includes the following steps:

[0074] S1: providing a substrate;

[0075] S2: forming a first metal layer on the substrate;

[0076] S3: forming a first insulating layer above the first metal layer;

[0077] S4: forming a third metal layer above the first insulating layer;

[0078] S5: forming a photoresist layer on the third metal layer;

[0079] S6: performing exposure and etching on the non-overlapping area of ​​the photoresist layer to remove the photoresist and the third metal layer in the non-overlapping area;

[0080] S7: removing the photoresist layer corresponding to the overlapping area to expose the third metal layer;

[0081] S8: performing oxidation treatment on the exposed third metal layer to generate copper oxide in the overlapping area to form the second insulating layer; and

[0082] S9: forming a second metal layer on the second insulating layer.

[0083] Wherein, the third metal layer is also made of copper.

[0084] Of course, while copper oxide is provided in the corresponding overlapping area 170 below the second metal layer 140, copper oxide can also be formed in the corresponding overlapping area 170 above the first metal layer 120 by oxidation. In this way, the upper and lower copper oxide insulating layers 130 can better play a role in blocking copper ions.

[0085] In addition, it is also possible to make the width of the second insulating layer 132 slightly wider than the overlapping area 170, that is, the width of the second insulating layer 132 is greater than the width of the second metal layer 140. Even if the second metal layer 140 is completely oxidized, the copper ions on the two side edges of the second metal layer 140 are difficult to contact with the first insulating layer 131 and diffuse, so that the copper ions of the second metal layer 140 can be completely blocked, thereby ensuring the insulation effect between the first metal layer 120 and the second metal layer 140.

[0086] It should be noted that the limitations on the steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0087] It should be noted that the inventive concept of this application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the various embodiments or technical features are combined, the original technical effects will be enhanced.

[0088] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer is provided on one side of the substrate; an insulating layer, disposed on a side of the first metal layer away from the substrate; a second metal layer, disposed on a side of the insulating layer away from the first metal layer; The orthographic projections of the first metal layer and the second metal layer on the substrate form an overlapping area, the insulating layer includes two sub-insulating layers stacked in sequence, and the orthographic projection of one of the sub-insulating layers on the substrate at least covers the overlapping area, wherein The two sub-insulating layers are made of different materials, and their orthographic projections on the substrate at least cover the overlapping area. The conductivity of the sub-insulating layer is lower than that of the other sub-insulating layer.

2. The array substrate according to claim 1, wherein: The two sub-insulating layers include a first sub-insulating layer and a second sub-insulating layer, wherein the first sub-insulating layer is arranged on a side of the first metal layer away from the substrate and corresponding to the overlapping area; the second sub-insulating layer is arranged on a side of the first sub-insulating layer away from the first metal layer and covers the first sub-insulating layer and the first metal layer; The first insulating layer is used to prevent the copper ions of the second metal layer from diffusing into the first metal layer; Along an extension direction of the first metal layer, a width of an orthographic projection of the first insulating layer on the substrate is at least equal to a width of the overlapping region.

3. The array substrate according to claim 2, wherein: The first insulating layer is copper oxide and is made by an oxygen plasma oxidation process; the second insulating layer is at least one of silicon oxide and silicon oxynitride.

4. The array substrate according to claim 3, wherein: The thickness of the first insulating layer is 30 nm to 50 nm, wherein the thickness of the first insulating layer is 5% to 10% of the thickness of the first metal layer.

5. The array substrate according to claim 3, wherein: The two sub-insulating layers include a first sub-insulating layer and a second sub-insulating layer, wherein the first sub-insulating layer is arranged on a side of the first metal layer away from the substrate and covers the first metal layer; the second sub-insulating layer is arranged on a side of the first sub-insulating layer away from the first metal layer and corresponds to the overlapping area; The second insulating layer is used to prevent the copper ions of the second metal layer from diffusing into the first metal layer; Along the extension direction of the first metal layer, the width of the orthographic projection of the second insulating layer on the substrate is at least equal to the width of the overlapping area; The second insulating layer is copper oxide and is made by an oxygen plasma oxidation process. The first insulating layer is at least one of silicon oxide and silicon oxynitride.

6. The array substrate according to claim 4 or 5, wherein: The non-overlapping position of the first metal layer and the second metal layer forms a non-overlapping area, the thickness of the second insulating layer corresponding to the non-overlapping area is set to H1, the thickness of the second insulating layer corresponding to the overlapping area is set to H2, and the thickness of the first insulating layer is set to H3, wherein, H1>H2;H1≦H2+H3.

7. A method for preparing an array substrate, for preparing the array substrate according to any one of claims 1 to 6, characterized in that: Including steps: providing a substrate; forming a first metal layer on the substrate; forming a photoresist layer above the first metal layer; performing exposure and etching on the overlapping area of ​​the photoresist layer to expose the first metal layer in the overlapping area; forming a first insulating layer on the exposed first metal layer; removing the photoresist layer; forming a second insulating layer over the first insulating layer to cover the first metal layer and the first insulating layer; as well as A second metal layer is formed above the second insulating layer at a position corresponding to the first metal layer.

8. The method for preparing an array substrate according to claim 7, wherein: The step of forming a first insulating layer on the exposed first metal layer by using a process includes: The exposed first metal layer is oxidized by an oxygen plasma oxidation process to generate a copper oxide layer in the overlapping area to form the first insulating layer.

9. The method for preparing an array substrate according to claim 8, wherein: In the step of oxidizing the exposed first metal layer by using an oxygen plasma oxidation process to form a copper oxide layer in the overlapping area, the oxygen plasma oxidation process uses gas: O2; power: 200w-10000w; Flow rate: 200sccm-1000sccm; Time: 3s-20s.

10. A display panel, characterized in that: It comprises a color filter substrate and the array substrate according to any one of claims 1 to 6, wherein the array substrate and the color filter substrate are arranged opposite to each other.

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