Image sensor

Abstract

An image sensor includes: a substrate including a first surface and a second surface opposite to the first surface; a first pixel including a first floating diffusion (FD) in the substrate; a conductive layer including a first conductive line layer disposed at a shortest distance from the first surface of the substrate in a first direction perpendicular to the first surface among the conductive line layers of the conductive layer; a first transistor on the first surface of the substrate; and a wiring connecting the first FD and the first transistor and disposed between the first surface of the substrate and the first conductive line layer.

Description

Technical Field

[0001] The present disclosure relates to an image sensor. Background Art

[0002] Image sensors are semiconductor devices that convert optical information into electrical signals. Such image sensors can include charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors.

[0003] The image sensor may be configured in the form of a package, and the package may have a structure that protects the image sensor and allows light to enter a light receiving surface or sensing area of ​​the image sensor. Summary of the Invention

[0004] Aspects of the present disclosure provide an image sensor in which design efficiency of conductive lines connected to transistors of the image sensor is improved and / or enhanced.

[0005] Aspects of the present disclosure also provide an image sensor, wherein the process margin of the image sensor is improved and / or enhanced.

[0006] According to one aspect of the present disclosure, there is provided an image sensor, comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a first pixel comprising a first floating diffusion region (FD) in the substrate; a conductive layer comprising a first conductive wire layer, the first conductive wire layer being arranged at a shortest distance from the first surface of the substrate in a first direction perpendicular to the first surface among the conductive wire layers in the conductive layer; a first transistor on the first surface of the substrate; and wiring connecting the first FD and the first transistor and arranged between the first surface of the substrate and the first conductive wire layer, wherein the wiring includes a first portion extending in a second direction perpendicular to the first direction.

[0007] According to another aspect of the present disclosure, an image sensor is provided, including: a substrate including a first surface and a second surface opposite to the first surface; a first pixel including a first floating diffusion region (FD) in the substrate; a second pixel including a second FD in the substrate; a third pixel including a third FD in the substrate; a fourth pixel including a fourth FD in the substrate; a conductive layer including a first conductive wire layer, the first conductive wire layer being arranged at a shortest distance from the first surface of the substrate in a first direction perpendicular to the first surface among the conductive wire layers in the conductive layer; a first source follower transistor on the first surface of the substrate; and wiring connecting the first FD to the fourth FD and the first source follower transistor, and being arranged between the first surface of the substrate and the first conductive wire layer, wherein the wiring includes a first portion extending in a second direction perpendicular to the first direction.

[0008] According to another aspect of the present disclosure, an image sensor is provided, including: a substrate including a first surface and a second surface opposite to the first surface; first to fourth pixels sharing a first floating diffusion region (FD) in the substrate; a conductive layer including a first conductive wire layer, the first conductive wire layer being arranged at the shortest distance from the first surface in a first direction perpendicular to the first surface among the conductive wire layers in the conductive layer; a first source follower transistor and a second source follower transistor shared by the first to fourth pixels; and wiring connecting the first FD and the first source follower transistor and the second source follower transistor, and being arranged between the first surface of the substrate and the first conductive wire layer, wherein the wiring includes a first portion extending in a second direction perpendicular to the first direction.

[0009] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments;

[0012] Figure 2 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0013] Figure 3 It is along Figure 2 An exemplary cross-sectional view taken along line AA';

[0014] Figure 4 It is along Figure 2 An exemplary cross-sectional view taken along line BB';

[0015] Figure 5 is a diagram illustrating a layout of an image sensor according to some embodiments;

[0016] Figure 6 It is along Figure 5 An exemplary cross-sectional view taken along line CC';

[0017] Figure 7 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0018] Figure 8 It is along Figure 7 An exemplary cross-sectional view taken along line D-D';

[0019] Figure 9 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments;

[0020] Figure 10 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0021] Figure 11 It is along Figure 10 An exemplary cross-sectional view taken along line EE';

[0022] Figure 12 It shows Figure 9 An exemplary layout diagram of an image sensor;

[0023] Figures 13 to 15 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0024] Figure 16 It is along Figure 5 An exemplary cross-sectional view taken along line CC';

[0025] Figure 17 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0026] Figure 18 It is along Figure 17 An exemplary cross-sectional view taken along line FF';

[0027] Figure 19 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments;

[0028] Figure 20 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0029] Figure 21 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments;

[0030] Figure 22 is an exemplary layout diagram illustrating a pixel array of an image sensor according to some embodiments;

[0031] Figure 23 and Figure 24 is an exemplary layout diagram illustrating a pixel array of an image sensor according to some embodiments;

[0032] Figures 25 to 27 is an exemplary layout diagram illustrating a pixel array of an image sensor according to some embodiments;

[0033] Figure 28is a diagram illustrating a conceptual layout of an image sensor according to some embodiments;

[0034] Figure 29 is a diagram illustrating a conceptual layout of an image sensor according to some embodiments; and

[0035] Figures 30 to 34 is a diagram illustrating a method of manufacturing an image sensor according to some embodiments. DETAILED DESCRIPTION

[0036] Hereinafter, the present disclosure will be described in detail by explaining embodiments of the present disclosure with reference to the attached drawings.

[0037] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the operation sequence described herein is merely an example and is not limited to those set forth herein, but can be changed as will be apparent after understanding the disclosure of the application, except for the operations that must occur in a specific order. In addition, in order to increase clarity and conciseness, the description of features known after understanding the disclosure of the application may be omitted.

[0038] The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be apparent upon understanding the disclosure of this application.

[0039] Throughout this specification, when a component is described as being “connected to” or “coupled to” another component, it may be directly “connected to” or “coupled to” the other component, or one or more other components may be interposed therebetween. Conversely, when an element is described as being “directly connected to” or “directly coupled to” another element, no other elements may be interposed therebetween. Likewise, similar expressions such as “between” and “directly between” and “adjacent to” and “directly adjacent to” are to be interpreted in the same manner. As used herein, the term “and / or” includes any one of the associated listed items and any combination of any two or more of the associated listed items.

[0040] Although terms such as "first," "second," and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited by these terms. Instead, these terms are used only to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Thus, a first component, first part, first region, first layer, or first section mentioned in the examples described herein may also be referred to as a second component, second part, second region, second layer, or second section without departing from the teachings of the examples.

[0041] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. The articles "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. The terms "comprise", "include" and "have" specify the presence of the features, numbers, operations, components, elements and / or their combinations, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or their combinations. As used herein, the expression "at least one of..." following a list of elements modifies the entire list of elements and does not modify the individual elements of the list. For example, the expression "at least one of a, b and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b and c.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs, and are based on an understanding of the disclosure of this application. Terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of this application, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, and all example embodiments are not limited thereto.

[0043] Figure 1 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments.

[0044] Reference Figure 1 , a pixel array of an image sensor according to some embodiments includes a plurality of pixel groups PG.

[0045] The pixel group PG may include a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, a fourth photodiode PD4, a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, a fourth transfer transistor TX4, a floating diffusion region FD, a dual conversion gain transistor DCX, a reset transistor RX, a first source follower transistor SX1, and a select transistor AX. The first to fourth photodiodes PD1, PD2, PD3, and PD4 may share the floating diffusion region FD, the dual conversion gain transistor DCX, the reset transistor RX, the first source follower transistor SX1, and the select transistor AX. According to another embodiment, the dual conversion gain transistor DCX may be omitted.

[0046] Each of the first to fourth photodiodes PD1, PD2, PD3, and PD4 may generate charges based on incident light. For example, each of the first to fourth photodiodes PD1, PD2, PD3, and PD4 may generate charges proportional to the amount of light incident from the outside.

[0047] The first transfer transistor TX1 may include a first transfer gate electrode TG1, the second transfer transistor TX2 may include a second transfer gate electrode TG2, the third transfer transistor TX3 may include a third transfer gate electrode TG3, and the fourth transfer transistor TX4 may include a fourth transfer gate electrode TG4. The first transfer gate electrode TG1 is the gate of the first transfer transistor TX1, the second transfer gate electrode TG2 is the gate of the second transfer transistor TX2, the third transfer gate electrode TG3 is the gate of the third transfer transistor TX3, and the fourth transfer gate electrode TG4 is the gate of the fourth transfer transistor TX4. The source of each of the first to fourth transfer transistors TX1, TX2, TX3, and TX4 may be connected to the corresponding first to fourth photodiodes PD1, PD2, PD3, and PD4, and the drain of each of the first to fourth transfer transistors TX1, TX2, TX3, and TX4 may be connected to the floating diffusion region FD. The first to fourth transfer transistors TX1, TX2, TX3, and TX4 may share the floating diffusion region FD as a drain. Charge generated in each of the first to fourth photodiodes PD1, PD2, PD3, and PD4 can be transferred to the floating diffusion region FD by each of the first to fourth transfer transistors TX1, TX2, TX3, and TX4, and can be accumulated in the floating diffusion region FD. Since the floating diffusion region FD is a region that converts charge into voltage and has parasitic capacitance, the charge can be accumulated and stored.

[0048] The first source follower transistor SX1 may include a first source follower gate electrode SF1. The first source follower gate electrode SF1 is the gate of the first source follower transistor SX1. For example, the first source follower transistor SX1 may amplify a change in the potential of the floating diffusion region FD that receives charges from the first to fourth photodiodes PD1, PD2, PD3, and PD4, and may output it to the output line VOUT. The first source follower gate electrode SF1 may be connected to the floating diffusion region FD, the drain of the first source follower transistor SX1 may be connected to the power supply voltage VDD, and the source of the first source follower transistor SX1 may be connected to the drain of the selection transistor AX. In the example case where the first source follower transistor SX1 is turned on, the power supply voltage VDD supplied to the drain of the first source follower transistor SX1 may be transmitted to the drain of the selection transistor AX.

[0049] The select transistor AX including the select gate electrode SEL can select the pixels to be read out row by row. The select gate electrode SEL is the gate of the select transistor AX. In the example case where the select transistor AX is turned on, the power supply voltage VDD connected to the drain of the first source follower transistor SX1 can be transmitted to the source region of the first source follower transistor SX1.

[0050] The dual conversion gain transistor DCX can adjust the conversion gain. The drain of the dual conversion gain transistor DCX can be connected to the source of the reset transistor RX, and the source of the dual conversion gain transistor DCX can be connected to the floating diffusion region FD. The dual conversion gain transistor DCX, which includes a dual conversion gain gate electrode DCG, can be turned on in a high illumination mode and turned off in a low illumination mode. The dual conversion gain gate electrode DCG is the gate of the dual conversion gain transistor DCX.

[0051] The reset transistor RX may include a reset gate electrode RG. The reset gate electrode RG serves as the gate electrode of the reset transistor RX. For example, the reset transistor RX may periodically reset the floating diffusion region FD. In the example case where the reset transistor RX and the dual conversion gain transistor DCX are turned on, the power supply voltage VDD supplied to the drain of the reset transistor RX may be transferred to the floating diffusion region FD.

[0052] Figure 2 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments. Figure 3 It is along Figure 2 An exemplary cross-sectional view taken along line AA'. Figure 4 It is along Figure 2 An exemplary cross-sectional view taken along line BB'.

[0053] Reference Figures 1 to 4The image sensor according to some embodiments includes a substrate 100, a floating diffusion region FD, a pixel separation pattern 120, first to fourth photodiodes PD1, PD2, PD3 and PD4, first to fourth transfer gate electrodes TG1, TG2, TG3 and TG4, a surface insulating film 160, a mesh pattern 170, a first protective film 176, a color filter 180 and a microlens 190.

[0054] The substrate 100 may include a first side 100a and a second side 100b opposite to each other. The first side 100a may be referred to as the front side of the substrate 100, and the second side 100b may be referred to as the back side of the substrate 100. However, the present disclosure is not limited thereto. Thus, in some cases, the first side 100a may be the upper side of the substrate 100, and the second side 100b may be the lower side of the substrate 100. The first direction X and the second direction Y may intersect each other and may be parallel to the first side 100a of the substrate 100. The third direction Z may intersect the first direction X and the second direction Y and may be perpendicular to the first side 100a of the substrate 100. Hereinafter, the upper side and the lower side are defined relative to the third direction Z.

[0055] In some embodiments, the second side 100b of the substrate 100 may be a light-receiving surface onto which light is incident. For example, the image sensor according to some embodiments may be a backside-illuminated (BSI) image sensor. However, the present disclosure is not limited thereto. Therefore, according to some other embodiments, the first side 100a may be referred to as the backside, and the second side 100b of the substrate 100 may be referred to as the frontside, which is the light-receiving surface onto which light is incident.

[0056] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be bulk silicon or silicon-on-insulator (SOI). The substrate 100 may be a silicon substrate. However, the present disclosure is not limited thereto. Therefore, according to some other embodiments, the substrate 100 may include, but is not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In another embodiment, the substrate 100 may include an epitaxial layer formed on a base substrate.

[0057] The pixel group PG may include first to fourth pixels PX1, PX2, PX3, and PX4. The first to fourth pixels PX1, PX2, PX3, and PX4 may be arranged two-dimensionally within a plane including a first direction X and a second direction Y. For example, the first to fourth pixels PX1, PX2, PX3, and PX4 may be arranged in a matrix. For example, the pixel group PG may include first to fourth pixels PX1, PX2, PX3, and PX4 adjacent to each other. The first pixel PX1 and the second pixel PX2 may be adjacent to each other in the first direction X, and the third pixel PX3 and the fourth pixel PX4 may be adjacent to each other in the first direction X. The third pixel PX3 and the first pixel PX1 may be adjacent to each other in the second direction Y, and the fourth pixel PX4 and the second pixel PX2 may be adjacent to each other in the second direction Y. The third pixel PX3 and the second pixel PX2 may be adjacent to each other in a diagonal direction between the first direction X and the second direction Y. The first to fourth pixels PX1, PX2, PX3, and PX4 may be arranged in two rows and two columns.

[0058] The plurality of pixel groups PG may be arranged two-dimensionally on a plane including the first direction X and the second direction Y (or a plane intersecting the third direction Z). For example, the plurality of pixel groups PG may be arranged in a matrix. Thus, a pixel array including a plurality of pixels arranged two-dimensionally (e.g., in a matrix) may be formed.

[0059] The pixel separation pattern 120 may be formed in the substrate 100. For example, the pixel separation pattern 120 may be formed inside the substrate 100. The pixel separation pattern 120 may define a plurality of pixels in the substrate 100. For example, the pixel separation pattern 120 may define first to fourth pixels PX1, PX2, PX3, and PX4 inside the substrate 100. The pixel separation pattern 120 may be provided between the plurality of pixels to separate the plurality of pixels. For example, from a plan viewpoint, the pixel separation pattern 120 may surround each of the plurality of pixels (e.g., first to fourth pixels PX1, PX2, PX3, and PX4). The pixel separation pattern 120 may be referred to as a separation pattern.

[0060] For example, the pixel separating pattern 120 may be formed by embedding an insulating material into a deep trench formed by patterning the substrate 100. For example, the pixel separating pattern 120 may extend from the first side 100a toward the second side 100b.

[0061] The pixel separation pattern 120 may include a filling pattern 122 and a spacer film 124. The filling pattern 122 may include a conductive material, such as, but not limited to, polysilicon (poly-Si). The spacer film 124 may extend along the sides of the filling pattern 122. The spacer film 124 may include an insulating material, such as, but not limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The spacer film 124 may be provided between the filling pattern 122 and the substrate 100. For example, the spacer film 124 may be interposed between the filling pattern 122 and the substrate 100 to electrically separate the filling pattern 122 from the substrate 100.

[0062] Each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include corresponding first to fourth photodiodes PD1, PD2, PD3, and PD4, corresponding first to fourth transfer transistors TX1, TX2, TX3, and TX4, and corresponding first to fourth floating diffusion regions FD1, FD2, FD3, and FD4. Since the structure of each of the second to fourth pixels PX2, PX3, and PX4 is the same as that of the first pixel PX1, the following description focuses on the first pixel PX1. Figure 1 The floating diffusion regions FD correspond to the first to fourth floating diffusion regions FD1 , FD2 , FD3 , and FD4 .

[0063] The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed in the substrate 100. For example, the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed within the substrate 100. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be adjacent to the first side 100a of the substrate 100. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed within the active area ACT of each of the first to fourth pixels PX1, PX2, PX3, and PX4. For example, each of the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed within the active area ACT of each of the first to fourth pixels PX1, PX2, PX3, and PX4. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed, for example, by implanting n-type impurity ions into the p-type substrate 100.

[0064] In an image sensor according to some embodiments, first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be provided at center portions of adjacent pixels within a pixel group PG. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be connected to each other at center portions of adjacent pixels in the pixel group PG.

[0065] In some embodiments, the pixel separation pattern 120 can physically separate the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4. Each of the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 is separated in the substrate 100 and can be connected to each other on the substrate 100 through wiring.

[0066] In some embodiments, the pixel separation pattern 120 does not physically separate the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 in the substrate 100, and the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 form a single large FD. In this case, the portion of the single large FD disposed on the first pixel PX1 is defined as the first floating diffusion region FD1, the portion of the single large FD disposed on the second pixel PX2 is defined as the second floating diffusion region FD2, the portion of the single large FD disposed on the third pixel PX3 is defined as the third floating diffusion region FD3, and the portion of the single large FD disposed on the fourth pixel PX4 is defined as the fourth floating diffusion region FD4. Each of the first to fourth pixels PX1, PX2, PX3, and PX4 can share the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4. The pixel separation pattern 120 may not include a region of the pixel group PG. For example, the pixel separation pattern 120 may not include a cutout region at the center portion of the pixel group PG. For example, the pixel separating pattern 120 may surround each of the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0067] The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be formed within the active areas ACT of the first to fourth pixels PX1, PX2, PX3, and PX4 adjacent to one another. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 provided in the first to fourth pixels PX1, PX2, PX3, and PX4 may be connected to one another at the center portions of the first to fourth pixels PX1, PX2, PX3, and PX4 adjacent to one another in the pixel group PG. The first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be connected to one another in the region where the pixel separation pattern 120 is cut.

[0068] The first photodiode PD1 may be formed in the substrate 100 of the first pixel PX1. For example, the first photodiode PD1 may be formed within the substrate 100 of the first pixel PX1. For example, the substrate 100 may include p-type impurities, and the first photodiode PD1 may be formed by ion-implanting n-type impurities into the p-type substrate 100. The p-type impurities may include, but are not limited to, boron (B), and the n-type impurities may include, but are not limited to, phosphorus (P) or arsenic (As). An example in which the substrate 100 includes p-type impurities will be described below.

[0069] The element isolation film 110 may be formed in the substrate 100. For example, the element isolation film 110 may be formed inside the substrate 100. The element isolation film 110 may be formed, for example, by embedding an insulating material in a shallow trench formed by patterning the substrate 100. The element isolation film 110 may extend from the first surface 100a of the substrate 100, and the lower side of the element isolation film 110 may be located inside the substrate 100. The element isolation film 110 may define an active area ACT inside the first pixel PX1. The element isolation film 110 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0070] Figure 1 The reset transistor RX, the dual conversion gain transistor DCX, the first source follower transistor SX1, and the selection transistor AX may be provided at various locations within the pixel group PG. Hereinafter, an example in which the first source follower transistor SX1 is provided in the first pixel PX1 will be described.

[0071] The first transfer transistor TX1 may be formed on the first side 100a of the substrate 100. Figure 3 The first transfer gate electrode TG1 of the first transfer transistor TX1 may be formed on the active area ACT of the first pixel PX1. The first transfer gate electrode TG1 may be adjacent to the first photodiode PD1. The placement of the first transfer transistor TX1 inside the first pixel PX1 is merely an example and is not limited thereto.

[0072] In image sensors according to some embodiments, the first transfer gate electrode TG1 may be a vertical transfer gate. For example, at least a portion of the first transfer gate electrode TG1 may be provided within the substrate 100. For example, a trench Ta extending from the first side 100a of the substrate 100 may be formed within the substrate 100. The first transfer gate electrode TG1 may include a first extension portion TGa filling the first trench Ta and a second extension portion TGb extending along the first side 100a of the substrate 100 on the first extension portion TGa.

[0073] The first source follower transistor SX1 may be formed on the first side 100a of the substrate 100. Figure 4 A first source follower gate electrode SF1 of the first source follower transistor SX1 may be formed on the first side 100a of the substrate 100. The first source follower gate electrode SF1 may be formed in an active area ACT different from the active area ACT in which the first floating diffusion area FD1 is formed. The placement of the first source follower transistor SX1 within the pixel group PG is merely an example and is not limited thereto. Hereinafter, an example in which the first source follower transistor SX1 is provided in the first pixel PX1 will be described.

[0074] A gate insulating layer GI may be interposed between the first transfer gate electrode TG1 and the substrate 100. The gate insulating layer GI may be interposed between the first source follower gate electrode SF1 and the substrate 100. The first transfer gate electrode TG1 and the first source follower gate electrode SF1 may be provided on the gate insulating layer GI. The gate insulating layer GI may further extend along the first side 100a of the substrate 100. The gate insulating layer GI may extend along the contour of the first side 100a of the substrate 100 (e.g., conformally). For example, the gate insulating layer GI may conformally extend along the contour of the first side 100a of the substrate 100. The gate insulating layer GI may include, for example, but not limited to, silicon oxide or metal oxide.

[0075] A gate spacer GS may be formed on the gate insulating layer GI. The gate spacer GS may be formed on the sidewall of the first transfer gate electrode TG1. For example, the gate spacer GS may be formed on the sidewall of the second extension TGb of the first transfer gate electrode TG1. The gate spacer GS may be formed on the sidewall of the first source follower gate electrode SF1. A pad spacer LS may be formed between the second extension TGb of the first transfer gate electrode TG1 and the gate spacer GS, and between the gate insulating layer GI and the gate spacer GS. The pad spacer LS may be formed between the first source follower gate electrode SF1 and the gate spacer GS, and between the gate insulating layer GI and the gate spacer GS.

[0076] For example, the gate spacer GS may include silicon nitride, and the liner spacer LS may include silicon oxide. However, the present disclosure is not limited thereto, and thus, the gate spacer GS and the liner spacer LS may be made of another material.

[0077] A first insulating layer 131 may be provided on the first transfer gate electrode TG1 and the gate spacer GS. The first insulating layer 131 may extend along the first transfer gate electrode TG1 and the gate spacer GS. The first insulating layer 131 may extend along the contour of the first transfer gate electrode TG1 and the contour of the gate spacer GS (e.g., conformally). The first insulating layer 131 may expose the gate insulating layer GI that does not overlap with the first transfer gate electrode TG1 and the gate spacer GS in the third direction Z. The first insulating layer 131 may extend along the first source follower gate electrode SF1 and the gate spacer GS. The first insulating layer 131 may extend along the contour of the first source follower gate electrode SF1 and the contour of the gate spacer GS (e.g., conformally). The first insulating layer 131 may expose the gate insulating layer GI that does not overlap with the first source follower gate electrode SF1 and the gate spacer GS in the third direction Z.

[0078] A second insulating layer 132 may be provided on the first insulating layer 131 and the gate insulating layer GI. The second insulating layer 132 may extend along the first insulating layer 131 and the gate insulating layer GI. The second insulating layer 132 may extend along (e.g., conformally) the contour of the first insulating layer 131 and the contour of the gate insulating layer GI exposed by the first insulating layer 131.

[0079] According to an embodiment, elements connected to the same node in the pixel array (or elements having the same potential) may be connected via a wiring at a lower level than the first conductive line ML1. For example, the wiring at a lower level connecting elements having the same potential may be lower than the lowest level of the conductive lines ML1 and ML2 formed on the first side 100a of the substrate 100.

[0080] In image sensors according to some embodiments, the first source follower gate electrode SF1 and the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 may be connected to each other via wiring at a lower level than the first conductive line ML1. The number and placement of the gate electrodes connected to the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the first source follower gate electrode SF1 connected to the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 is provided in the first pixel PX1.

[0081] For example, the lower level wiring may be a wiring L connecting the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of the first to fourth pixels PX1, PX2, PX3, and PX4 to the first source follower gate electrode SF1. The wiring L may include, but is not limited to, polysilicon.

[0082] The wiring L may include first first penetration portions P1, P2, P3, and P4, a second first penetration portion P12, and first connection portions C0 and C1. According to some embodiments, the penetration portion may be referred to as a protrusion or an extension.

[0083] Each of the first first penetration portions P1, P2, P3, and P4 may extend into the gate insulating layer GI and the second insulating layer 132. Each of the first first penetration portions P1, P2, P3, and P4 may extend, for example, in the third direction Z. Each of the first first penetration portions P1, P2, P3, and P4 penetrates the gate insulating layer GI and the second insulating layer 132 and may be connected to each of the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of each of the first to fourth pixels PX1, PX2, PX3, and PX4. Each of the first first penetration portions P1, P2, P3, and P4 may contact each of the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of the corresponding first to fourth pixels PX1, PX2, PX3, and PX4.

[0084] The second first penetration portion P12 may extend into the first insulating layer 131 and the second insulating layer 132. The second first penetration portion P12 may extend, for example, in the third direction Z. The second first penetration portion P12 penetrates the first insulating layer 131 and the second insulating layer 132 and may be connected to the first source follower gate electrode SF1. The second first penetration portion P12 may contact the first source follower gate electrode SF1.

[0085] The first connection portions C0 and C1 may extend along the second insulating layer 132. The first connection portions C0 and C1 may extend along the contour of the second insulating layer 132 (e.g., conformally). The first first connection portion C0 extends along the second insulating layer 132 and may connect the first first penetration portions P1, P2, P3, and P4. The second first connection portion C1 extends along the second insulating layer 132 and may connect the second first penetration portion P12 and the first first connection portion C0. The first connection portions C0 and C1 may be insulated from the substrate 100 by the second insulating layer 132, the first insulating layer 131, or the gate insulating layer GI. The placement of the second first connection portion C1 within the pixel group PG is merely an example and is not intended to be limiting. The second first connection portion C1 extends in the first direction X. The first first connection portion C0 partially overlaps each of the floating diffusion regions FD1, FD2, FD3, and FD4 in the third direction Z. The first first connection portion C0 overlaps the pixel separation pattern 120 in the third direction Z. The width of the second first connection portion C1 in the second direction Y is smaller than the width of the first first connection portion C0 in the second direction Y.

[0086] In image sensors according to some embodiments, each element (or portion) connected to the same node (e.g., elements or portions having the same potential) is connected to a respective penetrating portion extending in the third direction Z. The connecting portion extends along the pixel separation pattern 120 from a plan view (e.g., from a plan view including the first direction X and the second direction Y) and may connect the respective penetrating portions to one another. Each penetrating portion may penetrate the first and second insulating layers 131 and 132 or the gate and second insulating layers GI and 132 and may connect to each portion connected to the same node. From a plan view, the connecting portion may extend along the pixel separation pattern 120. The gate and second insulating layers GI and 132 may be interposed between the connecting portion and the pixel separation pattern 120. Hereinafter, a plan view is defined as a plan view including the first and second directions X and Y. For example, from a plan view, the first connection portion C1 may extend along the pixel separation pattern 120. At least a portion of the first connection portion C1 may overlap with the pixel separation pattern 120 in the third direction Z.

[0087] A third insulating layer 133 may be provided on the second insulating layer 132 and the wiring L. The third insulating layer 133 may extend along the second insulating layer 132 and the wiring L. The third insulating layer 133 may extend along (e.g., conformally) the outline of the second insulating layer 132 and the outline of the wiring L exposed by the second insulating layer 132. A fourth insulating layer 134 may be provided on the third insulating layer 133. The fourth insulating layer 134 may extend along (e.g., conformally) the outline of the third insulating layer 133.

[0088] For example, the first insulating layer 131 and the third insulating layer 133 may include silicon oxide, and the second insulating layer 132 and the fourth insulating layer 134 may include silicon nitride. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the first insulating layer 131 and the third insulating layer 133 may be made of another material, and the second insulating layer 132 and the fourth insulating layer 134 may be made of another material.

[0089] An interlayer insulating film ILD may be formed on the first face 100a of the substrate 100. The interlayer insulating film ILD may be provided on the fourth insulating layer 134. For example, the interlayer insulating film ILD may cover the fourth insulating layer 134. The interlayer insulating film ILD may have a single film or multi-film structure of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulator.

[0090] A plurality of conductive lines ML1 and ML2 may be formed in the interlayer insulating film ILD. For example, the plurality of conductive lines ML1 and ML2 may be formed within the interlayer insulating film ILD. The plurality of conductive lines ML1 and ML2 may be electrically connected to the active region ACT and the gate electrode. For example, the first conductive line ML1 and the second conductive line ML2 may be formed along the third direction Z within the interlayer insulating film ILD on the first side 100a of the substrate 100. The second conductive line ML2 may be provided at a higher level than the first conductive line ML1. The first conductive line ML1 may be provided at the lowest level among the plurality of conductive lines ML1 and ML2. The first conductive line ML1 may be closest to the first side 100a of the substrate 100 among the plurality of conductive lines ML1 and ML2. The placement and number of the conductive lines ML1 and ML2 within the interlayer insulating film ILD are merely examples, and the present disclosure is not limited thereto. Therefore, according to another embodiment, the conductive lines may be provided at a higher level. For example, the conductive lines may be provided at a level higher than that of the second conductive line ML2.

[0091] First contacts CT and CT12 may be provided inside the interlayer insulating film ILD. The first contacts CT and CT12 may connect the first conductive line ML1 and the wiring L. The placement and number of the first contacts CT and CT12 are merely exemplary and are not limited thereto. At least one conductive line may be further formed on the second conductive line ML2.

[0092] The wiring L may be connected to the first conductive line ML1 through the first contacts CT and CT12. The first contacts CT and CT12 penetrate the interlayer insulating film ILD, the fourth insulating layer 134, and the third insulating layer 133 and may be connected to the wiring L. The first contacts CT and CT12 may contact the wiring L. For example, the first first contact CT may be connected to the first first connection portion C0, and the second first contact CT12 may be connected to the second first penetration portion P12.

[0093] The wiring L is formed at a lower level than the first conductive line ML1 and the first contacts CT and CT12. The upper side Lus of the wiring L is provided below the upper sides CTus and CT12us of the first contacts CT and CT12. The wiring L connects the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 and the first source follower gate electrode SF1 at a level different from that of the first conductive line ML1 and the first contacts CT and CT12. Therefore, the design efficiency of the first conductive line ML1 can be improved and / or enhanced.

[0094] Furthermore, since the second first connection portion C1 of the wiring L is formed along the pixel separating pattern 120 from a plan viewpoint, the degree of freedom in disposing various elements on the pixel may be improved and / or increased.

[0095] Moreover, since the first contacts CT, CT12 are formed on the wiring L including polysilicon, the resistance can be improved and / or increased compared to the case where the first contacts CT, CT12 are formed in an impurity region such as the floating diffusion region FD, and the process margin of the first contacts CT, CT12 can be improved and / or increased.

[0096] A surface insulating film 160 may be formed on the second side 100b of the substrate 100. The surface insulating film 160 may conformally extend along the second side 100b of the substrate 100. The surface insulating film 160 may include an insulating material such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof.

[0097] Color filters 180 may be provided on the surface insulating film 160. Color filters 180 may be arranged to correspond to each unit pixel (e.g., first pixel PX1). For example, a plurality of color filters 180 may be arranged two-dimensionally (e.g., in a matrix) in a plane including a first direction X and a second direction Y. Color filters 180 may have various colors depending on the pixel (e.g., first pixel PX1). For example, color filters 180 may include a red filter, a green filter, a blue filter, a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0098] The mesh pattern 170 may be formed on the surface insulating film 160. The mesh pattern 170 is formed as a mesh pattern from a planar viewpoint and may be interposed between the color filters 180. The mesh pattern 170 may include a metal pattern 172 and a low refractive index pattern 174. For example, the metal pattern 172 and the low refractive index pattern 174 may be sequentially stacked on the surface insulating film 160.

[0099] The metal pattern 172 may include, for example, but not limited to, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof.

[0100] The low-refractive-index pattern 174 may include a low-refractive-index material having a lower refractive index than silicon (Si). For example, the low-refractive-index pattern 174 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

[0101] A first protective film 176 may be provided on the surface insulating film 160 and the mesh pattern 170. For example, the first protective film 176 may conformally extend along the contours of the surface insulating film 160 and the mesh pattern 170. The first protective film 176 may include, for example, but not limited to, aluminum oxide.

[0102] The microlenses 190 may be formed on the color filter 180. The microlenses 190 may be arranged to correspond to each pixel (eg, the first pixel PX1). For example, a plurality of microlenses 190 may be arranged two-dimensionally (eg, in a matrix) within a plane including the first direction X and the second direction Y.

[0103] The microlens 190 has a convex shape and may have a predetermined radius of curvature. Thus, the microlens 190 may collect light incident on a photodiode (eg, first photodiode PD). The microlens 190 may include, for example, but not limited to, a light-transmitting resin.

[0104] A second protective film 195 may be formed on the microlens 190. The second protective film 195 may extend along the surface of the microlens 190. The second protective film 195 may include, for example, an inorganic oxide film. For example, the second protective film 195 may include, but is not limited to, at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. For example, the second protective film 195 may include a low-temperature oxide (LTO).

[0105] Figure 5 is a diagram illustrating a layout of an image sensor according to some embodiments. Figure 6 It is along Figure 5 For ease of explanation, the description will focus on the example of the cross section taken along the line CC'. Figures 1 to 4 The points described are different.

[0106] For reference, Figure 4 It is along Figure 5 For example, Figure 4 The diagram in can correspond to Figure 2 and Figure 5 Therefore, repeated description can be omitted. Figure 4 The wiring L and the upper side Lus of the wiring L correspond to Figure 5 and Figure 6 The first wiring L1 and the upper side L1us of the first wiring L1.

[0107] Reference Figures 4 to 6 In the image sensor according to some embodiments, the pixel separating pattern 120 may include a cutout region at the center portion of adjacent pixels in the pixel group PG. The pixel separating pattern 120 may not be provided at the center portion of adjacent pixels in the pixel group PG.

[0108] For example, the pixel separation pattern 120 may include a cutout region at the center portions of the first to fourth pixels PX1, PX2, PX3, and PX4 adjacent to each other in the pixel group PG. The pixel separation pattern 120 may be cutout between the first pixel PX1 and the fourth pixel PX4 and / or between the second pixel PX2 and the third pixel PX3. The pixel separation pattern 120 extending between the first pixel PX1 and the second pixel PX2, the pixel separation pattern 120 extending between the first pixel PX1 and the third pixel PX3, the pixel separation pattern 120 extending between the second pixel PX2 and the fourth pixel PX4, and the pixel separation pattern 120 extending between the third pixel PX3 and the fourth pixel PX4 may be disconnected from each other at the center portion of the pixel group PG.

[0109] The first wiring L1 connects the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 and the first source follower gate electrode SF1. The first wiring L1 may include, but is not limited to, polysilicon. The first wiring L1 may include a first first penetration portion P11, a first connection portion C1, and a second first penetration portion P12.

[0110] The first first penetration portion P11 may extend into the gate insulating layer GI and the second insulating layer 132. The first first penetration portion P11 may extend, for example, in the third direction Z. The first first penetration portion P11 penetrates the gate insulating layer GI and the second insulating layer 132 and may be connected to the floating diffusion region FD. The first first penetration portion P11 may contact the floating diffusion region FD.

[0111] The first connection portion C1 extends along the second insulating layer 132 and may connect the first first penetration portion P11 and the second first penetration portion P12 .

[0112] The first contact CT11 may be provided inside the interlayer insulating film ILD. The first contact CT11 may connect the first conductive line ML1 and the first wiring L1. The placement and number of the first contact CT11 are merely exemplary and are not limited thereto. At least one conductive line may be further formed on the second conductive line ML2.

[0113] The first wiring L1 may be connected to the first conductive line ML1 through first contacts CT11 and CT12. The first contacts CT11 and CT12 penetrate the interlayer insulating film ILD, the fourth insulating layer 134, and the third insulating layer 133 and may be connected to the first wiring L1. The first contacts CT11 and CT12 may contact the first wiring L1. For example, the first contact CT11 may be connected to the first first penetration portion P11. The first contact CT12 may be connected to the second first penetration portion P12.

[0114] The first wiring L1 is formed at a lower level than the first conductive line ML1 and the first contacts CT11 and CT12. An upper side L1us of the first wiring L1 is provided below upper sides CT11us and CT12us of the first contacts CT11 and CT12.

[0115] Figure 7 is a diagram illustrating a layout of an image sensor according to some embodiments. Figure 8 It is along Figure 7 For the sake of convenience, the following will mainly describe the example cross-sectional view taken along the line D-D'. Figures 1 to 6 The points described are different.

[0116] In image sensors according to some embodiments, the grounding regions GND1 and GND2 may be connected to each other via wiring at a lower level than the first conductive line ML1. The number and placement of the grounding regions GND1 and GND2 connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the first grounding region GND1 and the second grounding region GND2 connected to each other are provided in each of the second pixel PX2 and the fourth pixel PX4.

[0117] Each of the first grounding region GND1 and the second grounding region GND2 may be formed in the first side 100a of the substrate 100. For example, each of the first grounding region GND1 and the second grounding region GND2 may be formed inside the first side 100a of the substrate 100. Each of the first grounding region GND1 and the second grounding region GND2 may be formed in each of the active area ACT of the second pixel PX2 and the active area ACT of the fourth pixel PX4. Each of the first grounding region GND1 and the second grounding region GND2 may be formed by implanting high-concentration p-type impurity ions into the substrate 100. Each of the first grounding region GND1 and the second grounding region GND2 may be Figure 1 The landing area.

[0118] In the image sensor according to some embodiments, the second wiring L2 connects the first grounding region GND1 and the second grounding region GND2. The second wiring L2 may include, but is not limited to, polysilicon.

[0119] The second wiring L2 may include a first second penetration portion P21 , a second connection portion C2 , and a second second penetration portion P22 .

[0120] The first second penetration portion P21 and the second second penetration portion P22 may extend into the first insulating layer 131 and the second insulating layer 132. The first second penetration portion P21 and the second second penetration portion P22 may extend, for example, in the third direction Z. Each of the first second penetration portion P21 and the second second penetration portion P22 penetrates the first insulating layer 131 and the second insulating layer 132 and may be connected to each of the first grounding region GND1 and the second grounding region GND2. Each of the first second penetration portion P21 and the second second penetration portion P22 may be in contact with each of the first grounding region GND1 and the second grounding region GND2.

[0121] The second connection portion C2 may extend along the second insulating layer 132. The second connection portion C2 may extend along the contour of the second insulating layer 132 (e.g., conformally). The second connection portion C2 extends along the second insulating layer 132 and may connect the first second penetration portion P21 and the second second penetration portion P22. The second connection portion C2 may be insulated from the substrate 100 by the second insulating layer 132 and the gate insulating layer GI.

[0122] For example, from a plan viewpoint, the second connection portion C2 may extend along the pixel separating pattern 120. At least a portion of the second connection portion C2 may overlap the pixel separating pattern 120 in the third direction Z. The placement of the second connection portion C2 inside the pixel group PG is merely exemplary and is not limited thereto.

[0123] The second wiring L2 may be connected to the first conductive line ML1 through a second contact CT2. The second contact CT2 may connect the first conductive line ML1 and the second wiring L2. The second contact CT2 penetrates the interlayer insulating film ILD, the fourth insulating layer 134, and the third insulating layer 133 and may be connected to the second wiring L2. The second contact CT2 may contact the second wiring L2.

[0124] The second wiring L2 is formed at a lower level than the first conductive line ML1 and the second contact CT2. The upper side L2us of the second wiring L2 is provided below the upper side CT2us of the second contact CT2. The second wiring L2 connects the first grounding region GND1 and the second grounding region GND2 at a different level than the first conductive line ML1 and the second contact CT2.

[0125] The image sensor according to some embodiments may further include Figure 5 and Figure 6 The first source follower gate electrode SF1 and the first wiring L1.

[0126] In addition, elements or parts connected to the same node in the pixel array (elements or parts having the same potential) may be connected through wiring at a lower level than the first conductive line ML1. Figure 1In the example case where the source of the reset transistor RX and the drain of the dual conversion gain transistor DCX are provided in different active areas ACT, the source of the reset transistor RX and the drain of the dual conversion gain transistor DCX can be connected via a second wiring L2. In this case, the second wiring L2 can include first and second second penetration portions P21, P22, which penetrate the first and second insulating layers 131, 132 and connect to the source of each of the reset transistor RX and the drain of the dual conversion gain transistor DCX, and a second connection portion C2 connecting the first and second second penetration portions P21, P22. In another example case where the source of the first source follower transistor SX1 and the drain of the select transistor AX are provided in different active areas ACT, the source of the first source follower transistor SX1 and the drain of the select transistor AX can be connected via the second wiring L2.

[0127] In an image sensor according to some embodiments, Figure 7 The pixel group PG may correspond to Figure 2 For example, Figure 7 The pixel separation pattern 120 in the image sensor may not include the cutout regions between the first to fourth pixels PX1, PX2, PX3, and PX4. The image sensor according to some embodiments may further include Figures 2 to 4 The first source follower gate electrode SF1 and the wiring L.

[0128] Figure 9 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments. Figure 10 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments. Figure 11 It is along Figure 10 For the sake of convenience, the following will mainly describe the example cross-sectional view taken along the line EE'. Figure 1 and Figure 8 The points described are different.

[0129] Reference Figures 9 to 11 According to some embodiments, a pixel group PG may include a plurality of source follower transistors SX1 and SX2. The placement of each source follower transistor SX1 and SX2 within the pixel group PG is merely an example and is not limited thereto. Hereinafter, an example will be described in which the pixel group PG includes a first source follower transistor SX1 provided on a first pixel PX1 and a second source follower transistor SX2 provided on a third pixel PX3.

[0130] The first source follower transistor SX1 and the second source follower transistor SX2 may be connected in parallel. Since the operation of the second source follower transistor SX2 is the same as that of the first source follower transistor SX1, a repeated explanation will not be provided.

[0131] The second source follower transistor SX2 may include a second source follower gate electrode SF2. The second source follower gate electrode SF2 is a gate electrode of the second source follower transistor SX2. The second source follower gate electrode SF2 may be formed in the active area ACT of the third pixel PX3. The placement of the second source follower gate electrode SF2 within the third pixel PX3 is merely an example and is not limited thereto.

[0132] A gate insulating layer GI may be interposed between the second source follower gate electrode SF2 and the substrate 100. The second source follower gate electrode SF2 may be provided on the gate insulating layer GI.

[0133] The gate spacer GS may be formed on a sidewall of the second source follower gate electrode SF2 , and the pad spacer LS may be formed between the second source follower gate electrode SF2 and the gate spacer GS and between the gate insulating layer GI and the gate spacer GS.

[0134] A first insulating layer 131 may be provided on the second source follower gate electrode SF2 and the gate spacer GS. For example, the first insulating layer 131 may extend along the second source follower gate electrode SF2 and the gate spacer GS. The first insulating layer 131 may extend along the contour of the second source follower gate electrode SF2 and the contour of the gate spacer GS (e.g., conformally). The first insulating layer 131 may expose the gate insulating layer GI that does not overlap with the second source follower gate electrode SF2 and the gate spacer GS in the third direction Z.

[0135] In image sensors according to some embodiments, gate electrodes may be connected to each other via wiring at a lower level than the first conductive line ML1. The number and placement of gate electrodes connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which a pixel group PG includes a first source follower gate electrode SF1 provided in a first pixel PX1 and a second source follower gate electrode SF2 provided in a third pixel PX3.

[0136] The third wiring L3 connects the first source follower gate electrode SF1 and the second source follower gate electrode SF2. The third wiring L3 may include, but is not limited to, polysilicon.

[0137] The third wiring L3 may include a first third penetration portion P31, a third connection portion C3, and a second third penetration portion P32. Figure 2 and Figure 6 Since the second first penetration portion P12 is shown in FIG.

[0138] The second third penetration portion P32 may extend into the first insulating layer 131 and the second insulating layer 132. The second third penetration portion P32 may extend, for example, in the third direction Z. The second third penetration portion P32 penetrates the first insulating layer 131 and the second insulating layer 132 and may be connected to the second source follower gate electrode SF2. The second third penetration portion P32 penetrates the first insulating layer 131 and the second insulating layer 132 and may be connected to the second source follower gate electrode SF2.

[0139] The third connection portion C3 may extend along the second insulating layer 132. The third connection portion C3 may extend along the contour of the second insulating layer 132 (e.g., conformally). The third connection portion C3 extends along the second insulating layer 132 and may connect the first third penetration portion P31 and the second third penetration portion P32. The third connection portion C3 may be insulated from the substrate 100 by the second insulating layer 132 and the gate insulating layer GI. For example, from a planar viewpoint, the third connection portion C3 may extend along the pixel separation pattern 120. At least a portion of the third connection portion C3 may overlap with the pixel separation pattern 120 in the third direction Z. The placement of the third connection portion C3 within the pixel group PG is merely an example and is not limited thereto.

[0140] The third wiring L3 may be connected to the first conductive line ML1 through a third contact CT3. The third contact CT3 may connect the first conductive line ML1 and the third wiring L3. The third contact CT3 penetrates the interlayer insulating film ILD, the fourth insulating layer 134, and the third insulating layer 133 and may be connected to the third wiring L3. The third contact CT3 may contact the third wiring L3.

[0141] The third wiring L3 is formed at a lower level than the first conductive line ML1 and the third contact CT3. The upper side L3us of the third wiring L3 is provided below the upper side CT3us of the third contact CT3. The third wiring L3 connects the first source follower gate electrode SF1 and the second source follower gate electrode SF2 at a level different from that of the first conductive line ML1 and the third contact CT3.

[0142] In the image sensor according to some embodiments, the pixel group PG may further include Figure 7 The second wiring L2.

[0143] In addition, the gate electrodes with the same potential (gate electrodes connected to the same node) within the pixel group PG can be connected via the third wiring L3. Figure 1, the pixel group PG may further include a transistor having a gate electrode driven by the same signal as the first transfer gate electrode TG1 of the first transfer transistor TX1. The gate electrode of the transistor may be connected to the first transfer gate electrode TG1 via a third wiring L3. In this case, the third wiring L3 may include each of a first third penetration portion P31 and a second third penetration portion P32, and a third connection portion C3 connecting the first third penetration portion P31 and the second third penetration portion P32. The first third penetration portion P31 and the second third penetration portion P32 penetrate the first insulating layer 131 and the second insulating layer 132 and connect to the gate electrode of each transistor and the first transfer gate electrode TG1.

[0144] In an image sensor according to some embodiments, Figure 10 The pixel group PG may correspond to Figure 2 For example, in Figure 10 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0145] Figure 12 It shows Figure 9 For the sake of convenience, the following will mainly describe the layout of the image sensor. Figures 1 to 11 The points described are different.

[0146] Reference Figure 12 In the image sensor according to some embodiments, the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 and the gate electrode may be formed by a conductive line ( Figure 5 The lower level wiring of the floating diffusion regions ML1 is connected to each other. The number and placement of the gate electrodes connected to the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the first source follower transistor SX1 is provided in the first pixel PX1 and the second source follower transistor SX2 is provided in the third pixel PX3.

[0147] The first wiring L1 connects the first to fourth floating diffusion regions FD1 , FD2 , FD3 , and FD4 , the first source follower gate electrode SF1 , and the second source follower gate electrode SF2 .

[0148] The first wiring L1 may further include a third first penetration portion P13. Since the third first penetration portion P13 corresponds to Figure 10 and Figure 11 The second to third penetration portions P32 are described, so repeated description will not be provided.

[0149] The first connection portion C1 may extend along the second insulating layer 132 and connect the first first penetration portion P11 , the second first penetration portion P12 , and the third first penetration portion P13 .

[0150] The image sensor according to some embodiments may further include Figure 7 and Figure 8 The first grounding area GND1 and the second grounding area GND2 and the second wiring L2.

[0151] In an image sensor according to some embodiments, Figure 12 The pixel group PG may correspond to Figure 2 For example, in Figure 12 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0152] Figures 13 to 15 is an exemplary layout diagram showing an image sensor according to some embodiments. Figures 1 to 10 The points described are different.

[0153] Reference Figures 13 to 15 , each of the first pixel group PG1 and the second pixel group PG2 may correspond to a pixel group using Figures 1 to 12 The pixel group PG is described.

[0154] Reference Figure 13 In an image sensor according to some embodiments, some of the plurality of pixel groups may be connected to each other in floating diffusion regions. The number and placement of pixel groups whose floating diffusion regions are connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which a pixel group includes a first pixel group PG1 and a second pixel group PG2 whose first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 are connected to each other.

[0155] The fourth wiring L4 connects the first to fourth floating diffusion regions FD1, FD2, FD3 and FD4 of the first pixel group PG1 and the first to fourth floating diffusion regions FD1, FD2, FD3 and FD4 of the second pixel group PG2. The fourth wiring L4 may include, but is not limited to, polysilicon.

[0156] The fourth wiring L4 may include a first fourth penetration portion P41 , a second fourth penetration portion P42 , and a fourth connection portion C4 .

[0157] The first fourth penetration portion P41 may be connected to the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of the first pixel group PG1. The second fourth penetration portion P42 may be connected to the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of the second pixel group PG2. Figure 5 and Figure 6 Since the first penetration portion P11 is shown in FIG.

[0158] The fourth connection portion C4 may connect the first fourth penetration portion P41 and the second fourth penetration portion P42. The fourth connection portion C4 corresponds to Figure 5 and Figure 6 Therefore, repeated description will not be provided.

[0159] For example, the first pixel group PG1 and the second pixel group PG2 may be adjacent to each other. For example, the second pixel group PG2 and the first pixel group PG1 may be adjacent to each other in the second direction Y. Unlike this example, the first pixel group PG1 and the second pixel group PG2 may be adjacent to each other in the first direction X.

[0160] In the image sensor according to some embodiments, at least a portion of the fourth connection portion C4 may overlap with the pixel separation pattern 120 in the third direction Z. From a plan viewpoint, at least a portion of the fourth connection portion C4 may extend along the pixel separation pattern 120. For example, from a plan viewpoint, the fourth connection portion C4 may extend along the pixel separation pattern 120 between the third pixel PX3 and the fourth pixel PX4 of the first pixel group PG1 and the pixel separation pattern 120 between the first pixel PX1 and the second pixel PX2 of the second pixel group PG2.

[0161] In an image sensor according to some embodiments, Figure 13 The pixel group PG may correspond to Figure 2 For example, in Figure 13 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0162] Reference Figure 14In an image sensor according to some embodiments, some of the plurality of pixel groups may have gate electrodes connected to each other. The number and arrangement of the pixel groups having gate electrodes connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the pixel group includes a first pixel group PG1 including a first source follower gate electrode SF1 and a second pixel group PG2 including a second source follower gate electrode SF2, and the first source follower gate electrode SF1 and the second source follower gate electrode SF2 are connected to each other.

[0163] A first source follower gate electrode SF1 may be provided on the third pixel PX3 of the first pixel group PG1. A second source follower gate electrode SF2 may be provided on the first pixel PX1 of the second pixel group PG2. A third wiring L3 connects the first source follower gate electrode SF1 and the second source follower gate electrode SF2.

[0164] In an image sensor according to some embodiments, some of the plurality of pixel groups may have grounding regions connected to each other. The number and placement of the pixel groups having grounding regions connected to each other are merely exemplary and are not limiting. Hereinafter, an example will be described in which the pixel groups include a first pixel group PG1 and a second pixel group PG2 that share a first grounding region GND1 and a second grounding region GND2.

[0165] A first grounding region GND1 may be provided on the fourth pixel PX4 of the first pixel group PG1. A second grounding region GND2 may be provided on the second pixel PX2 of the second pixel group PG2. A second wiring L2 connects the first grounding region GND1 and the second grounding region GND2.

[0166] In the image sensor according to some embodiments, the first pixel group PG1 and the second pixel group PG2 may include only one of the third wiring L3 and the second wiring L2. In the image sensor according to some embodiments, the first pixel group PG1 and the second pixel group PG2 may further include Figure 13 At this time, the second wiring L2 may be provided to be separated and insulated from the fourth wiring L4.

[0167] In an image sensor according to some embodiments, Figure 14 Each of the first pixel group PG1 and the second pixel group PG2 may correspond to Figure 2 For example, in Figure 14 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0168] Reference Figure 15In an image sensor according to some embodiments, in some pixel groups among a plurality of pixel groups, a floating diffusion region and a gate electrode may be connected to each other. The number and placement of pixel groups having floating diffusion regions and gate electrodes connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which a pixel group includes a first pixel group PG1 including a first source follower gate electrode SF1 and a second pixel group PG2 including a second source follower gate electrode SF2, the first source follower gate electrode SF1 and the second source follower gate electrode SF2 being connected to each other, and the first to fourth floating diffusion regions FD1, FD2, FD3, and FD4 of the first and second pixel groups PG1 and PG2 being connected to each other.

[0169] The fourth wiring L4 may further include a third fourth penetration portion P43 and a fourth fourth penetration portion P44. Since each of the third fourth penetration portion P43 and the fourth fourth penetration portion P44 corresponds to Figure 10 and Figure 11 Each of the first third penetration portion P31 and the second third penetration portion P32 is connected, so repeated description will not be provided. The fourth connection portion C4 connects the fourth penetration portions P41, P42, P43, and P44.

[0170] In the image sensor according to some embodiments, the first pixel group PG1 and the second pixel group PG2 may further include Figure 14 At this time, the second wiring L2 may be provided to be spaced apart and insulated from the fourth wiring L4.

[0171] In an image sensor according to some embodiments, Figure 15 Each of the first pixel group PG1 and the second pixel group PG2 may correspond to Figure 2 For example, in Figure 15 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0172] Figure 16 It is along Figure 5 For the sake of convenience, the following will mainly describe the example cross-sectional view taken along the line CC'. Figures 1 to 6 The points described are different.

[0173] Reference Figure 16In image sensors according to some embodiments, the first transfer gate electrode TG1 may further include a third extension portion TGc. For example, a first trench Ta and a second trench Tb may be formed within the substrate 100, extending from the first side 100a of the substrate 100 and spaced apart from each other. The first transfer gate electrode TG1 may include a first extension portion TGa filling the first trench Ta, a third extension portion TGc filling the second trench Tb, and a second extension portion TGb extending along the first side 100a of the substrate 100 and connecting the first extension portion TGa and the third extension portion TGc.

[0174] In the image sensor according to some embodiments, there may be a plurality of first penetrating portions P11. Each of the first penetrating portions P11 may be in contact with the floating diffusion region FD and may be connected to each other through the first connection portion C1.

[0175] Figure 17 is a diagram illustrating an exemplary layout of an image sensor according to some embodiments. Figure 18 It is along Figure 17 For the sake of convenience, the following will mainly describe the example cross-sectional view taken along the line F-F'. Figures 1 to 6 The points described are different.

[0176] Reference Figure 17 and Figure 18 In the image sensor according to some embodiments, at least a portion of the first connection portion C1 may overlap the element isolation film 110 in the third direction Z. The first connection portion C1 may connect the first first penetration portion P11 and the second first penetration portion P12 on the element isolation film 110 .

[0177] In an image sensor according to some embodiments, Figure 17 The pixel group PG may correspond to Figure 2 For example, in Figure 17 , the pixel separating pattern 120 may not include the cutout regions between the first to fourth pixels PX1 , PX2 , PX3 , and PX4 .

[0178] Figure 19 is an exemplary circuit diagram illustrating a pixel array of an image sensor according to some embodiments.

[0179] Reference Figure 19 , a pixel array according to some embodiments includes a plurality of pixels PX.

[0180] For example, the pixel PX may include a large photodiode LPD, a small photodiode SPD, a first floating diffusion region FD1, a second floating diffusion region FD2, a third floating diffusion region FD3, a first transfer transistor LTX, a second transfer transistor STX, a source follower transistor SX, a selection transistor AX, a connection transistor DRX, a reset transistor RX, a first switching transistor SWX, a capacitor C and a second switching transistor TSWX.

[0181] The large photodiode LPD may generate charges in proportion to the amount of light incident from the outside. The large photodiode LPD may convert light incident on the first pixel LPX1 into charges. One end of the large photodiode LPD may be connected to a ground voltage.

[0182] The first transfer transistor LTX may be connected between the large photodiode LPD and the first floating diffusion region FD1. One end of the first transfer transistor LTX may be connected to the large photodiode LPD, and the other end of the first transfer transistor LTX may be connected to the first floating diffusion region FD1. The first transfer transistor LTX may be driven by a first transfer signal applied via a first transfer gate electrode LTG of the first transfer transistor LTX. The first transfer transistor LTX may transfer charge generated by the large photodiode LPD to the first floating diffusion region FD1.

[0183] The source follower gate electrode SF of the source follower transistor SX can be connected to the first floating diffusion region FD1. The source follower gate electrode SF is connected to the first floating diffusion region FD1 and can be charged. The source follower transistor SX can amplify the change in the potential of the first floating diffusion region FD1 and output it as the output voltage VOUT. In the example case where the source follower transistor SX is turned on, the source follower transistor SX can transmit the first voltage VPIX to the select transistor AX.

[0184] The selection transistor AX can be connected to the source follower transistor SX and the output voltage VOUT. The selection transistor AX can select the pixel area to be read out row by row. The selection transistor AX can be driven by a row selection signal applied to the selection gate electrode SEL of the selection transistor AX.

[0185] The connection transistor DRX may connect the first floating diffusion region FD1 and the second floating diffusion region FD2 . The connection transistor DRX may be driven by a connection signal applied to a connection gate electrode DRG of the connection transistor DRX.

[0186] The reset transistor RX can be driven by a reset signal applied to the reset gate electrode RG of the reset transistor RX. In the example case where the reset transistor RX is turned on, the reset transistor RX can transmit the second voltage VRD to the second floating diffusion area FD2. Therefore, the first pixel LPX1 and the second pixel SPX1 can be reset.

[0187] The first switching transistor SWX may be located between the second floating diffusion region FD2 and the third floating diffusion region FD3. The first switching transistor SWX may be driven by a first switching signal applied to a first switching gate electrode SW of the first switching transistor SWX. When the first switching transistor SWX is turned on, the first switching transistor SWX may connect the second floating diffusion region FD2 and the third floating diffusion region FD3.

[0188] The capacitor C and the second switching transistor TSWX may be located between the third voltage VSC and the third floating diffusion region FD3. The second switching transistor TSWX may be driven by a second switching signal applied to the second switching gate electrode TSW of the second switching transistor TSWX. In the example case where the second switching transistor TSWX is turned on, the second switching transistor TSWX may connect the third floating diffusion region FD3 and the capacitor C. The second switching transistor TSWX may transfer charge overflowing from the small photodiode SPD to the capacitor C. The capacitor C may store the charge overflowing from the small photodiode SPD. For example, the capacitor C may not be provided in the first region REG1 or the second region REG2.

[0189] At least some of the first to third voltages VPIX, VRD, and VSC may be the same as one another. In another embodiment, the first to third voltages VPIX, VRD, and VSC may be different from one another.

[0190] The small photodiode SPD may generate charges in proportion to the amount of light incident from the outside. The small photodiode SPD may convert light incident on the second pixel SPX1 into charges. One end of the small photodiode SPD may be connected to a ground voltage.

[0191] The second transfer transistor STX can be connected between the small photodiode SPD and the second floating diffusion area FD2. One end of the second transfer transistor STX can be connected to the small photodiode SPD, and the other end of the second transfer transistor STX can be connected to the third floating diffusion area FD3. The second transfer transistor STX may include a second transfer gate electrode STG. The second transfer transistor STX may be driven by a second transfer signal, and the second transfer signal may be applied through the second transfer gate electrode STG. The second transfer transistor STX may transfer the charge generated by the small photodiode SPD to the third floating diffusion area FD3. The first floating diffusion area FD1 and the third floating diffusion area FD3 may be connected via a first switching transistor SWX and a connecting transistor DRX.

[0192] Figure 20 is an exemplary layout diagram showing an image sensor according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 19 The points described are different.

[0193] Reference Figure 19 and Figure 20 In an image sensor according to some embodiments, a pixel PX may include a first region REG1 and a second region REG2. A large photodiode LPD may be formed in the first region REG1, and a small photodiode SPD may be formed in the second region REG2. From a plan viewpoint, the area of ​​the first region REG1 may be larger than the area of ​​the second region REG2. From a plan viewpoint, the total area of ​​the large photodiode LPD may be larger than the total area of ​​the small photodiode SPD. The large photodiode LPD may have a relatively large light receiving area compared to the small photodiode SPD.

[0194] In an image sensor according to some embodiments, from a plan viewpoint, the first region REG1 may have an octagonal shape, and the second region REG2 may have a square shape. One second region REG2 may be surrounded by four first regions REG1. The four second regions REG2 may be provided adjacent to four of the eight sides of the first region REG1. However, the present disclosure is not limited thereto, and thus, the shapes of the first region REG1 and the second region REG2 may vary.

[0195] In an image sensor according to some embodiments, the first impurity regions 101a and 101b of the first region REG1 and the second impurity region 101b of the second region REG2 of the pixel PX may be formed by a first conductive line ( Figure 3The lower-level wiring of ML1 (e.g., the first impurity regions 101a and 101b) is connected to each other. The number and arrangement of the first impurity regions 101a and 101b and the number and arrangement of the second impurity regions 102 connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the first region REG1 of the pixel PX includes the first impurity regions 101a and 101b, and the second region REG2 includes the second impurity region 102.

[0196] The sixth wiring L6 may connect the second impurity region 102 of the second region REG2 and the first impurity regions 101a and 101b of the first region REG1. The sixth wiring L6 may include, but is not limited to, polysilicon.

[0197] In the image sensor according to some embodiments, the first region REG1 may include a plurality of first impurity regions 101a and 101b. The plurality of first impurity regions 101a and 101b may be formed by being lower than the first conductive line ( Figure 3 The lower level wirings of the sixth wiring L6 may connect the plurality of first impurity regions 101a and 101b.

[0198] The sixth wiring L6 may include a first sixth penetrating portion P61, a second sixth penetrating portion P62, a third sixth penetrating portion P63, and a sixth connection portion C6. The first sixth penetrating portion P61 is connected to the first first impurity region 101a, the second sixth penetrating portion P62 is connected to the second first impurity region 101b, and the third sixth penetrating portion P63 may be connected to the second impurity region 102. The sixth connection portion C6 may connect the first sixth penetrating portion P61, the second sixth penetrating portion P62, and the third sixth penetrating portion P63.

[0199] Because the first first impurity region 101a, the second first impurity region 101b, the first sixth penetrating portion P61, the second sixth penetrating portion P62, and the sixth connection portion C6 connecting the first sixth penetrating portion P61 and the second sixth penetrating portion P62 correspond to Figure 5 and Figure 6 Each of the first grounding region GND1, the second grounding region GND2, the first second penetrating portion P21, the second second penetrating portion P22, and the second connection portion C2, so repeated description will not be provided. The first first impurity region 101a, the second impurity region 102, the first sixth penetrating portion P61, the third sixth penetrating portion P63, and the sixth connection portion C6 connecting the first sixth penetrating portion P61 and the third sixth penetrating portion P63 correspond to Figure 5 and Figure 6For each of the first grounding region GND1, the second grounding region GND2, the first second penetration portion P21, the second second penetration portion P22, and the second connection portion C2, repeated description will not be provided. For example, the first impurity regions 101a and 101b and the second impurity region 102 are formed in the substrate 100, the first sixth penetration portion P61, the second sixth penetration portion P62, and the third sixth penetration portion P63 may penetrate the gate insulating layer GI and the second insulating layer 132, and the sixth connection portion C6 may extend along the second insulating layer 132. However, the first impurity regions 101a and 101b and the second impurity region 102 may be various impurity regions other than the grounding region. For example, the first impurity regions 101a and 101b and the second impurity region 102 may be Figure 19 The third floating diffusion region FD3.

[0200] In the image sensor according to some embodiments, the sixth connection portion C6 may extend along the pixel separating pattern 120 from a plan viewpoint.

[0201] Figure 21 is an exemplary layout diagram showing an image sensor according to some embodiments. Figures 1 to 20 The points described are different.

[0202] Reference Figure 21 , each of the first pixel PX1 and the second pixel PX2 may correspond to a pixel using Figures 19 to 20 The pixel PX is described.

[0203] In an image sensor according to some embodiments, gate electrodes of different pixels may be arranged below the first conductive line ( Figure 3 The lower level wiring of ML1 is connected to each other. The number and placement of pixels whose gate electrodes are connected to each other are merely exemplary and are not limited thereto. Hereinafter, an example will be described in which the gate electrode G of the first pixel PX1 and the gate electrode G of the second pixel PX2 are connected to each other.

[0204] The seventh wiring L7 may connect the first gate electrode G1 of the first pixel PX1 and the second gate electrode G2 of the second pixel PX2. The seventh wiring L7 may include, but is not limited to, polysilicon. For example, the first gate electrode G1 and the second gate electrode G2 may be provided in the first region REG1 of each of the first pixel PX1 and the second pixel PX2. The placement of the first gate electrode G1 in the first pixel PX1 and the placement of the second gate electrode G2 in the second pixel PX2 is merely exemplary and is not limited thereto.

[0205] The seventh wiring L7 may include a first seventh penetration portion P71, a second seventh penetration portion P72, and a seventh connection portion C7. The first seventh penetration portion P71 is connected to the first gate electrode G1 of the first pixel PX1, the second seventh penetration portion P72 is connected to the second gate electrode G2 of the second pixel PX2, and the seventh connection portion C7 may connect the first seventh penetration portion P71 and the second seventh penetration portion P72. Because the first gate electrode G1, the second gate electrode G2, the first seventh penetration portion P71, the second seventh penetration portion P72, and the seventh connection portion C7 correspond to Figure 8 and Figure 9 Each of the first source follower gate electrode SF1, the second source follower gate electrode SF2, the first third penetration portion P31, the second third penetration portion P32 and the third connection portion C3, so repeated description will not be provided. For example, the first gate electrode G1 and the second gate electrode G2 are formed on the first side 100a of the substrate 100, and the first seventh penetration portion P71 and the second seventh penetration portion P72 can penetrate the first insulating layer 131 and the second insulating layer 132. The seventh connection portion P7 can extend along the second insulating layer 132. For example, each of the first gate electrode G1 and the second gate electrode G2 can be Figure 19 The source follower gate electrode SF.

[0206] In the image sensor according to some embodiments, the seventh connection portion C7 may extend along the pixel separating pattern 120 from a plan viewpoint.

[0207] In the image sensor according to some embodiments, the first region REG1 may include one first impurity region 101 .

[0208] Figure 22 1 is an exemplary layout diagram showing a pixel array of an image sensor according to some embodiments. Figures 1 to 20 The points described are different.

[0209] Reference Figure 22 In the image sensor according to some embodiments, the gate electrode G and the first impurity regions 101a and 101b in the pixel PX can be formed by a first conductive line ( Figure 3 The number and arrangement of the gate electrodes G and the first impurity regions 101 a and 101 b connected to each other are merely exemplary and are not limited thereto.

[0210] A gate electrode G may be further provided in the first region REG1 . A sixth wiring L6 may further connect the gate electrode G and the first impurity regions 101 a and 101 b .

[0211] The sixth wiring L6 may further include a fourth sixth penetration portion P64. The sixth connection portion C6 may connect the first sixth penetration portion P61, the second sixth penetration portion P62, the third sixth penetration portion P63, and the fourth sixth penetration portion P64. The gate electrode G may be Figure 19 The source follower gate electrode SF of the gate electrode G and the fourth and sixth penetration portions P64 correspond to Figures 2 to 4 The first source follower gate electrode SF1 and the second first penetration portion P12 are formed on the first side 100a of the substrate 100, so repeated description will not be provided. The gate electrode G is formed on the first side 100a of the substrate 100, and the fourth sixth penetration portion P64 can penetrate the first insulating layer 131 and the second insulating layer 132 and can be connected to the gate electrode G. For example, although the gate electrode G and the first and second impurity regions 101a, 101b and 102 can be Figure 19 Each of the source follower gate electrode SF and the third floating diffusion region FD3 , but the embodiment is not limited thereto.

[0212] Figure 23 and Figure 24 is an exemplary layout diagram showing a pixel array of an image sensor according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 22 The points described are different.

[0213] Reference Figure 23 and Figure 24 In an image sensor according to some embodiments, the first region REG1 and the second region REG2 may each have a square shape from a plan view perspective. The second region REG2 may be provided in an outer portion of the interior of the first region REG1. A pixel PX composed of the first region REG1 and the second region REG2 may also have a rectangular shape. The first region REG1 may have a rectangular shape excluding only the second region REG2. The second region REG2 may be provided at a vertex portion of the first region REG1, but the placement of the second region REG2 inside the pixel PX is not limited thereto.

[0214] In the image sensor according to some embodiments, the first region REG1 may include one first impurity region 101 .

[0215] Reference Figure 23 The sixth wiring L6 may connect the first impurity region 101 of the first region REG1 and the second impurity region 102 of the second region REG2.

[0216] Reference Figure 24 The sixth wiring L6 may connect the first impurity region 101 of the first region REG1 , the second impurity region 102 of the second region REG2 , and the gate electrode G of the first region REG1 .

[0217] Figures 25 to 27 is an exemplary layout diagram showing a pixel array of an image sensor according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 23 The points described are different.

[0218] Reference Figures 25 to 27 , each of the first to fourth pixels PX1, PX2, PX3, and PX4 may correspond to a pixel using Figure 23 The first pixel PX1 and the second pixel PX2 may be adjacent to each other in the first direction X, and the third pixel PX3 and the fourth pixel PX4 may be adjacent to each other in the first direction X. The third pixel PX3 and the first pixel PX1 may be adjacent to each other in the second direction Y, and the fourth pixel PX4 and the second pixel PX2 may be adjacent to each other in the second direction Y. The third pixel PX3 and the second pixel PX2 may be adjacent to each other in a diagonal direction between the first direction X and the second direction Y. The first to fourth pixels PX1, PX2, PX3 and PX4 may be arranged in two rows and two columns.

[0219] Reference Figure 25 In the image sensor according to some embodiments, the sixth wiring L6 may connect the first impurity region 101 and the second impurity region 102 of each of the first to fourth pixels PX1, PX2, PX3, and PX4 to each other. For example, the first impurity region 101 and the second impurity region 102 may be Figure 19 The third floating diffusion region FD3.

[0220] Reference Figure 26 In the image sensor according to some embodiments, each of the first to fourth pixels PX1, PX2, PX3, and PX4 may further include a gate electrode G. The sixth wiring L6 may connect the first and second impurity regions 101 and 102 of each of the first and third pixels PX1 and PX3, and the gate electrode G to one another. The sixth wiring L6 may connect the first and second impurity regions 101 and 102 of each of the second and fourth pixels PX2 and PX4, and the gate electrode G to one another.

[0221] Reference Figure 27 In the image sensor according to some embodiments, each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include a first impurity region 201 and a second impurity region 202. The seventh wiring L7 may connect the first impurity region 201 and the second impurity region 202 of each of the first to fourth pixels PX1, PX2, PX3, and PX4 to each other. For example, the first impurity region 201 and the second impurity region 202 may be Figure 19The arrangement and number of the second impurity regions 202 inside the second region REG2 and the arrangement and number of the first impurity regions 201 inside the first region REG1 are merely exemplary and are not limited thereto.

[0222] Each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include a gate electrode G. The sixth wiring L6 may connect the gate electrodes G of each of the first pixel PX1 and the third pixel PX3 to each other. The sixth wiring L6 may connect the gate electrodes G of each of the second pixel PX2 and the fourth pixel PX4 to each other.

[0223] Figure 28 is a diagram illustrating a conceptual layout of an image sensor according to some embodiments.

[0224] Reference Figure 28 According to some embodiments, the image sensor 10 may include an upper chip 1100 and a lower chip 1200. The upper chip 1100 and the lower chip 1200 may be stacked. A plurality of pixels may be provided on the upper chip 1100 in a two-dimensional array structure. For example, the plurality of pixels may be arranged as a pixel array (PA). For example, the pixel array may be provided on the upper chip 1100. For example, the pixel array may include Figures 1 to 27 Any of the pixel arrays shown.

[0225] The lower chip 1200 may include, but is not limited to, a logic area LC, a memory area, etc. The lower chip 1200 may be provided below the upper chip 1100 and may be electrically connected to the upper chip 1100. The lower chip 1200 may allow pixel signals transmitted from the upper chip 1100 to be transmitted to the logic area LC of the lower chip 1200.

[0226] Logic elements may be provided in the logic region LC of the lower chip 1200. The logic elements may include circuits for processing pixel signals from pixels. For example, the logic elements may include a control register block, a timing generator, a ramp signal generator, a row driver, a readout circuit, a buffer unit, etc.

[0227] Figure 29 is a diagram showing a conceptual layout of an image sensor according to some embodiments. Figures 1 to 28 The points described are different.

[0228] Reference Figure 29 , the image sensor 10 according to some embodiments may include a first chip 1110 , a second chip 1120 , and a lower chip 1200 .

[0229] The pixel array may include a first pixel array PA1 and a second pixel array PA2. The first pixel array PA1 may be provided on a first chip 1110, and the second pixel array PA2 may be provided on a second chip 1120. For example, the pixel array PA1 and / or PA2 may include Figures 1 to 27 Any pixel array shown.

[0230] In the image sensor according to some embodiments, the second pixel array PA2 may be provided on either the upper side or the lower side of the second chip 1120. In some other embodiments, the second pixel array PA2 may be provided on either the upper side or the lower side of the second chip 1120.

[0231] Figures 30 to 34 is a diagram illustrating a method of manufacturing an image sensor according to some embodiments. Figures 1 to 29 The points described are different.

[0232] Reference Figure 30 The method may include providing a substrate 100. For example, the method may include providing a substrate 100 including a first side 100a and a second side 100b opposite to each other. The method may include forming a photodiode PD, a pixel separation pattern 120, an element separation film 110, and an active area ACT in the substrate 100. Furthermore, the method may include forming a gate insulating layer GI, a gate spacer GS, a pad spacer LS, a transfer gate electrode TG, and a source follower gate electrode SF on the first side 100a of the substrate 100.

[0233] For example, the photodiode PD may be formed by implanting n-type impurity ions into the p-type substrate 100. The photodiode PD may be formed inside each pixel disposed inside the substrate 100.

[0234] The element isolation film 110 may define an active area ACT within the pixel. The element isolation film 110 may extend from the first side 100 a of the substrate 100 and may define the active area ACT extending from the first side 100 a within the substrate 100. For example, the element isolation film 110 may be formed on the first side 100 a of the substrate 100 using a shallow trench isolation (STI) process.

[0235] The active area ACT may include a floating diffusion area FD. For example, the floating diffusion area FD may be formed by implanting n-type impurity ions into the p-type substrate 100 .

[0236] The method may include forming a first trench Ta extending from the first side 100a of the substrate 100. The gate insulating layer GI may extend along the first side 100a of the substrate 100 and the first trench Ta. The method may include forming a transfer gate electrode TG filling the first trench Ta on the gate insulating layer GI. The method may include forming a source follower gate electrode SF on the gate insulating layer GI. The method may include forming a liner spacer LS and a gate spacer GS on side surfaces of the transfer gate electrode TG and side surfaces of the source follower gate electrode SF.

[0237] Reference Figure 31 , the method may include forming a first insulating layer 131 and a second insulating layer 132 .

[0238] A first insulating layer 131 may be provided on the transmission gate electrode TG, the source follower gate electrode SF, and the gate spacer GS. For example, the first insulating layer 131 may cover the transmission gate electrode TG, the gate spacer GS on the transmission gate electrode TG, the source follower gate electrode SF, and the gate spacer GS on the source follower gate electrode SF. The first insulating layer 131 may be conformally formed along the transmission gate electrode TG, the gate spacer GS, and the source follower gate electrode SF.

[0239] The second insulating layer 132 may be conformally formed along the first insulating layer 131 .

[0240] Reference Figure 32 The method may include forming a first mask pattern PR1 including a first hole H1 and a second hole H2 on the second insulating layer 132. The first hole H1 is formed on the floating diffusion region FD, and the second hole H2 is formed on the source follower gate electrode SF. The second insulating layer 132 and the gate insulating layer GI exposed by the first hole H1 are removed, exposing a portion of the floating diffusion region FD. The second insulating layer 132 and the first insulating layer 131 exposed by the second hole H2 are removed, exposing a portion of the source follower gate electrode SF.

[0241] The first mask pattern PR1 may include, for example, a photoresist material.

[0242] Reference Figure 33 The method may include forming a preliminary wiring PL1. The preliminary wiring PL1 may be formed on the second insulating layer 132, the exposed floating diffusion region FD, and the source follower gate electrode SF. For example, the preliminary wiring PL1 may cover the second insulating layer 132, the exposed floating diffusion region FD, and the source follower gate electrode SF.

[0243] Reference Figure 34The method may include forming a second mask pattern PR2 on the preliminary wiring PL1 and patterning the preliminary wiring PL1 using the second mask pattern PR2. Thus, a first wiring L1 connecting the floating diffusion region FD and the source follower gate electrode SF is formed.

[0244] The second mask pattern PR2 may include, for example, a photoresist material.

[0245] Reference Figure 18 The method may include forming a third insulating layer 133, a fourth insulating layer 134, and an interlayer insulating film ILD on the second insulating layer 132 and the first wiring L1. For example, the third insulating layer 133, the fourth insulating layer 134, and the interlayer insulating film ILD may be sequentially formed on the second insulating layer 132 and the first wiring L1. The first contact CT12, the first conductive line ML1, and the second conductive line ML2 may be formed.

[0246] A surface insulating film 160 , a mesh pattern 170 , a first protective film 176 , a color filter 180 , and a microlens 190 may be formed on the second side 100 b of the substrate 100 .

[0247] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be manufactured in various forms. It will be understood by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, the above embodiments should be understood in all aspects to be illustrative rather than restrictive.

[0248] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0036369 filed in the Korean Intellectual Property Office on March 15, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensor, comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a first pixel comprising a first floating diffusion region in the substrate; a conductive layer including a first conductive line layer, the first conductive line layer being disposed at a shortest distance from the first surface of the substrate in a first direction perpendicular to the first surface among the conductive line layers in the conductive layer; a first transistor on the first surface of the substrate; as well as a wiring connecting the first floating diffusion region and the first transistor and disposed between the first surface of the substrate and the first conductive line layer; The wiring includes a first portion extending in a second direction perpendicular to the first direction.

2. The image sensor according to claim 1, further comprising: a second pixel comprising a second floating diffusion region in the substrate; a third pixel comprising a third floating diffusion region in the substrate; a fourth pixel comprising a fourth floating diffusion region in the substrate; as well as a separation pattern in the substrate and defining the first pixel, the second pixel, the third pixel, and the fourth pixel, The first transistor is shared by the first floating diffusion region to the fourth floating diffusion region, The wiring connects the first transistor and the first floating diffusion region to the fourth floating diffusion region. 3 . The image sensor according to claim 2 , wherein the wiring includes a second portion partially overlapping each of the first to fourth floating diffusion regions in the first direction. 4 . The image sensor according to claim 3 , wherein the second portion of the wiring vertically overlaps the separation pattern in the first direction.

5. The image sensor according to claim 4 , wherein the first portion of the wiring has a first width in a third direction perpendicular to the second direction, wherein the second portion of the wiring has a second width in the third direction, The first width of the first portion is smaller than the second width of the second portion.

6. The image sensor according to claim 4, further comprising: The separation pattern contacts and overlaps with the separation pattern in the first direction. 7 . The image sensor of claim 6 , wherein the separation pattern is in contact with the first surface of the substrate and the second surface of the substrate.

8. The image sensor according to claim 6, further comprising: a first insulating layer on the first portion of the wiring, The first insulating layer is disposed between the first portion of the wiring and the first conductive line layer.

9. The image sensor according to claim 8, further comprising: a second insulating layer on the first insulating layer, The second insulating layer is disposed between the first insulating layer and the first conductive line layer.

10. The image sensor according to claim 9, further comprising: A third insulating layer is provided between the first surface of the substrate and the first portion of the wiring. 11 . The image sensor of claim 9 , wherein the contact penetrates the first insulating layer and the second insulating layer. 12 . The image sensor of claim 1 , wherein a portion of the first transistor extends from the first surface of the substrate into the substrate. 13 . The image sensor of claim 1 , wherein the first transistor is a first source follower transistor.

14. The image sensor according to claim 13, further comprising: The second source follower transistor, The first source follower transistor and the second source follower transistor are configured to be connected to the first floating diffusion region to the fourth floating diffusion region. 15 . The image sensor according to claim 14 , wherein the wiring is configured to connect the first source follower transistor and the second source follower transistor.

16. An image sensor comprising: a substrate comprising a first surface and a second surface opposite to the first surface; a first pixel comprising a first floating diffusion region in the substrate; a second pixel comprising a second floating diffusion region in the substrate; a third pixel comprising a third floating diffusion region in the substrate; a fourth pixel comprising a fourth floating diffusion region in the substrate; a conductive layer including a first conductive line layer, the first conductive line layer being disposed at a shortest distance from the first surface of the substrate in a first direction perpendicular to the first surface among the conductive line layers in the conductive layer; a first source follower transistor on the first surface of the substrate; as well as a wiring connecting the first floating diffusion region to the fourth floating diffusion region and the first source follower transistor, and disposed between the first surface of the substrate and the first conductive line layer, The wiring includes a first portion extending in a second direction perpendicular to the first direction. The image sensor according to claim 16 , wherein the wiring comprises polysilicon.

18. The image sensor according to claim 17, further comprising: a first insulating layer on the first portion of the wiring, The first insulating layer is disposed between the first portion of the wiring and the first conductive line layer.

19. The image sensor according to claim 18, further comprising: A second insulating layer is provided between the first surface and the first portion of the wiring.

20. An image sensor comprising: a substrate comprising a first surface and a second surface opposite to the first surface; The first pixel to the fourth pixel share a first floating diffusion region in the substrate; a conductive layer including a first conductive line layer, the first conductive line layer being arranged at a shortest distance from the first surface in a first direction perpendicular to the first surface among the conductive line layers in the conductive layer; a first source follower transistor and a second source follower transistor, shared by the first to fourth pixels; as well as a wiring connecting the first floating diffusion region and the first source follower transistor and the second source follower transistor, and disposed between the first surface of the substrate and the first conductive line layer, The wiring includes a first portion extending in a second direction perpendicular to the first direction.

Images