Quantum chip manufacturing method and quantum chip

Abstract

The invention discloses a manufacturing method of a quantum chip and the quantum chip, and belongs to the technical field of quantum computing. The manufacturing method of the quantum chip comprises the following steps: providing a substrate of which the surface is provided with a bit structure and a superconducting metal layer for providing a ground plane; wherein the bit structure is not in contact with the superconducting metal layer; and forming a through hole in the superconducting metal layer. According to the mode, the quasi-particles generated by the superconducting material in the low-temperature environment can be limited, and bit energy de-coherence caused by the fact that the quasi-particles participate in the tunneling process of the Josephson junction is avoided, so that the performance of the superconducting quantum chip is improved.

Description

Technical Field

[0001] The present application belongs to the field of quantum computing technology, and in particular relates to a method for manufacturing a quantum chip and a quantum chip. Background Art

[0002] Based on what we know so far, a superconducting quantum chip is an electronic circuit based on a Josephson junction, and also a quantum circuit based on superconducting materials. It uses the superconducting properties of superconducting materials at low temperatures to realize quantum bit manufacturing.

[0003] Superconducting quantum chips, the core of superconducting quantum computers, are often placed in the ultra-cold chamber of a dilution refrigerator during computation. However, in this extremely low temperature environment, the concentration of quasiparticles increases, causing interference with quantum bits (qubits), resulting in energy decoherence and degrading the performance of the superconducting quantum chip.

[0004] How to reduce the interference of quasiparticles on quantum bits and improve the performance of superconducting quantum chips is an urgent problem that needs to be solved in the design and manufacturing process of superconducting quantum chips. Summary of the Invention

[0005] The purpose of this application is to provide a method for manufacturing a quantum chip and a quantum chip to solve the problem in the prior art that quasiparticles approach the junction area of ​​the Josephson junction and participate in the tunneling process of the junction area, thereby causing bit energy decoherence. The application can limit the position of quasiparticles to a certain extent, so that the quasiparticles cannot approach the junction area of ​​the Josephson junction, thereby improving the performance of the superconducting quantum chip.

[0006] To solve the above technical problems, the present invention provides a method for manufacturing a quantum chip, comprising the following steps:

[0007] Providing a substrate having a bit structure formed on its surface and a superconducting metal layer providing a ground plane; wherein the bit structure is not in contact with the superconducting metal layer;

[0008] A through hole is formed penetrating the superconducting metal layer.

[0009] Preferably, there are multiple through holes.

[0010] Preferably, the through hole is in the shape of a quadrangular prism, a triangular prism or a cylinder.

[0011] Preferably, the step of providing a substrate having a bit structure and a superconducting metal layer formed on the surface includes:

[0012] Etching the superconducting metal layer to form a window exposing a portion of the substrate;

[0013] A bit structure is formed within the window.

[0014] Preferably, the bit structure includes a Josephson junction, a capacitor plate and a connection block;

[0015] The Josephson junction does not contact the capacitor plate and is electrically connected to the capacitor plate through the connection block.

[0016] Preferably, after the step of forming a bit structure within the window, the method further includes:

[0017] The capacitor plate is etched to form a through hole penetrating the capacitor plate; wherein there are a plurality of through holes.

[0018] Preferably, after the step of etching the capacitor plate and forming a through hole through the capacitor plate, the method further comprises:

[0019] A metal film layer is formed at one end of the superconducting layer of the Josephson junction away from the junction region; wherein the metal film layer is not in contact with the capacitor plate.

[0020] Preferably, the material of the metal film layer is a superconducting metal or a common metal;

[0021] The superconducting energy gap of the superconducting metal is smaller than the superconducting energy gap of the superconducting metal layer.

[0022] The present application also provides a quantum chip, including a quantum chip manufactured according to the quantum chip manufacturing method described above.

[0023] Preferably, the material of the superconducting metal layer is aluminum;

[0024] And / or, there are multiple bit structures.

[0025] Compared with the prior art, the present application provides a method for manufacturing a quantum chip, specifically, manufacturing a through hole in a superconducting metal layer (ground plane) formed on a substrate coplanar with the Josephson junction. According to the inventors' multiple tests and reproduction behaviors on the quantum chip structure manufactured by this method, it can be clearly seen that the quantum chip manufactured by this method has a better confinement effect on quasiparticles in the superconducting material; in fact, the quasiparticles will be confined in the through hole, preventing them from approaching the Josephson junction, which significantly improves the bit coherence time compared to before the improvement, thereby improving the performance of the quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the planar structure of a quantum chip provided in an embodiment of the present application;

[0027] Figure 2 A flowchart of the manufacturing process of the quantum chip provided in the embodiment of the present application;

[0028] Figure 3A schematic diagram of a structure of a superconducting metal layer with through holes provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of the bit structure provided in an embodiment of the present application;

[0030] Figure 5 Schematic diagram of the Josephson junction and metal film layer structure provided in an embodiment of the present application.

[0031] Explanation of reference numerals: 1 - substrate, 2 - superconducting metal layer, 3 - bit structure, 31 - Josephson junction, 32 - capacitor plate, 33 - connection block, 4 - metal film layer, 5 - through hole. DETAILED DESCRIPTION

[0032] The following describes a specific embodiment of the present invention in more detail with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0033] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0035] According to the BCS (Bardeen-Cooper-Schrieffer) superconductivity theory, when a superconducting quantum chip enters the ultra-low temperature space provided by a dilution refrigerator, some Cooper pairs in the superconducting material are decomposed into quasiparticles because the ambient temperature provided by the ultra-low temperature space is far below the superconducting critical temperature. The behavior of these quasiparticles near the junction area of ​​the Josephson junction is very complex. For example, they may absorb or emit photons or phonons, causing energy loss, and eventually release it into the low-temperature test environment in the form of heat. This will cause the tunneling process in the junction area of ​​the Josephson junction to introduce losses, which is specifically manifested as energy relaxation (the quantum bit changes its state) or dephasing (the quantum bit loses its phase coherence).

[0036] To address this phenomenon, in the embodiments of the present application, a "vortex-like" structure and a "capture" structure are constructed to limit quasiparticles, and the quasiparticles are captured and dissipated or imprisoned in the non-core area of ​​the superconducting quantum chip (the core area refers to the junction area of ​​the Josephson junction 31), that is, the area away from the junction area of ​​the Josephson junction 31, so that the quasiparticles cannot participate in the tunneling process of the Josephson junction 31, thereby reducing the loss introduced by the tunneling process of the junction area, thereby reducing the negative impact of the above-mentioned quasiparticles on the superconducting quantum chip.

[0037] Please refer to Figure 1 and Figure 2 , provides a method for manufacturing a quantum chip, the main steps comprising:

[0038] S1: providing a substrate 1 having a bit structure 3 formed on its surface and a superconducting metal layer 2 providing a ground plane; wherein the bit structure 3 is not in contact with the superconducting metal layer 2;

[0039] S2: forming a through hole 5 penetrating the superconducting metal layer 2 .

[0040] Specifically, a substrate 1 is first provided. The material of the substrate 1 can be selected as a silicon substrate or a sapphire substrate according to actual needs, and the specific material only needs to meet the basic manufacturing requirements of the quantum chip base; a superconducting metal layer 2 is formed on one surface of the substrate 1 (an exemplary formation method: magnetron sputtering); the superconducting metal layer 2 is operated by a micro-nano processing technology to form quantum bits, quantum devices required for the quantum chip other than the quantum bits, and other transmission lines on the superconducting metal layer 2, wherein the quantum bits are connected to the above-mentioned quantum devices through electrical coupling or other means, and the quantum bits, quantum devices in the form of coplanar waveguides and transmission lines do not contact the superconducting metal layer 2, and the superconducting metal layer 2 is defined as a ground plane structure corresponding to the quantum bits.

[0041] Please refer to Figure 3 The through hole 5 is a through-shaped structure connecting two opposite surfaces of the superconducting metal layer 2. When manufacturing the through hole 5, in order to ensure that the through hole 5 definitely penetrates the superconducting metal layer 2, part of the process is to process the superconducting metal layer 2 (such as etching), and the etching uses the substrate 1 as the etching stop layer. When the superconducting metal layer 2 is completely penetrated, part of the substrate 1 can be further etched to achieve the purpose of completely etching through the superconducting metal layer 2.

[0042] In one embodiment of the present application, there are multiple through holes 5; in addition, the through holes 5 are evenly arranged on the surface of the superconducting metal layer 2, and specifically, the distances between any adjacent through holes can be set to be consistent; under the support of current processes, multiple through holes 5 are etched and manufactured on the superconducting metal layer 2, specifically with the density being as high as possible and the number being as large as possible, so as to achieve the maximum restriction effect on quasiparticles in the superconducting material.

[0043] It is worth noting that the manufacturing process of the through hole 5 is generally after the manufacturing process of the bit structure 3, quantum device and transmission line. Therefore, when etching to manufacture the through hole 5, in addition to meeting the aforementioned conditions, the above-mentioned components should also be avoided to prevent damage to the integrity of the above-mentioned components, thereby producing a quantum chip with complete functions that can suppress quasiparticles and improve performance.

[0044] In one embodiment of the present application, the through hole 5 is shaped as a quadrangular prism, a triangular prism, or a cylinder. In practice, there are no specific limitations on the shape of the through hole 5; the specific shape can be selected as needed and is not limited to the above examples. The inventors have experimentally found that almost all through holes 5 with completely through-hole spaces can effectively restrict the position of alignment particles; therefore, when etching to form the through hole 5, the shape of the through hole 5 can be selected as needed and is not limited to the above examples.

[0045] In addition, the arrangement density and specific size of the through holes 5 need to be determined according to the quantum devices on the superconducting metal layer 2. The arrangement of the through holes 5 can satisfy the requirement that the minimum distance between all through holes 5 and the nearest quantum device is 10 μm.

[0046] In this regard, the through hole 5 manufactured by the above design can be understood as the aforementioned "vortex-like" structure. When the superconducting quantum chip enters the extremely low temperature space of the dilution refrigerator, the Cooper pairs in the superconducting material decompose into quasiparticles. This "vortex-like" structure can confine the quasiparticles within the through hole 5 to prevent the quasiparticles from approaching the Josephson junction 31 and participating in the tunneling process of the junction area, thereby avoiding the energy decoherence of the bit and improving the performance of the superconducting quantum chip.

[0047] Alternatively, in one embodiment of the present application, the "vortex-like" structure is configured as a plurality of uniformly distributed through-holes 5 with a square cross-section, the side length of the square cross-section being set to 2μm-5μm, and the depth of the through-holes 5 being consistent with the thickness of the superconducting metal layer 2. During the operation of the quantum chip, it is affected by various environmental factors, such as radiation, light, sound, vibration, temperature, and magnetic fields. These environmental factors may cause the concentration of quasiparticles in the quantum chip to increase. In response to this, the present application provides a grid-like "vortex-like" structure that limits the diffusion rate of quasiparticles in the superconducting metal layer 2. This limiting effect greatly suppresses the density of quasiparticles that would generate the tunneling process of the Josephson junction 31, reduces the probability of energy loss caused by the absorption or emission of photons or phonons by the quasiparticles, and thus significantly improves the decoherence time of the quantum bit.

[0048] Moreover, the above-mentioned “vortex-like” structure is also applicable to the flip-chip structure. For a flip-chip chip, that is, including a Base layer (bottom layer), a Flip layer (upper layer) and an interconnection structure located between the two substrate layers and electrically connecting the two layers, when the “vortex-like” structure of the present application is used for the above-mentioned flip-chip structure, through holes can be made on the metal layer made of superconducting metal in the Flip layer, or through holes can be made on the metal layer made of superconducting metal in the Base layer, or through holes can be made on the metal layers made of superconducting metal formed on the surfaces of the Flip layer and the Base layer, so as to limit the quasiparticles on each metal layer and achieve the purpose of improving the performance of the superconducting chip.

[0049] The method for manufacturing the quantum chip described above, wherein step S1: providing a substrate 1 having a bit structure 3 and a superconducting metal layer 2 formed on the surface; wherein the bit structure 3 is not in contact with the superconducting metal layer 2, comprises:

[0050] S11: etching the superconducting metal layer 2 to form a window exposing a portion of the substrate 1;

[0051] S12: Form a bit structure 3 within the window.

[0052] The above step S11: etching the superconducting metal layer 2 to form a window exposing a portion of the substrate 1 specifically includes the following steps:

[0053] S111: forming a photoresist layer covering the superconducting metal layer 2 on the surface of the superconducting metal layer 2;

[0054] S112: exposing and developing the photoresist layer to expose a portion of the superconducting metal layer 2;

[0055] S113: etching the exposed portion of the superconducting metal layer 2 to form a window exposing a portion of the substrate 1;

[0056] S114: removing the photoresist layer.

[0057] Step S12: forming a bit structure 3 within the window:

[0058] S121: forming a photoresist layer on the surface of the substrate 1 within the window;

[0059] S122: exposing and developing the photoresist layer;

[0060] S123: forming a Josephson junction 31 and a capacitor plate 32;

[0061] S124: removing the photoresist layer.

[0062] The above steps include but are not limited to processes such as coating, developing, etching, and washing.

[0063] Please refer to Figure 4 The bit structure 3 manufactured according to the above method steps includes a Josephson junction 31, a capacitor plate 32, and a connecting block 33; wherein the Josephson junction 31 and the capacitor plate 32 do not contact each other and are electrically connected through the connecting block 33. In the bit structure 3, the Josephson junction 31 is constructed to include an upper superconducting layer, a lower superconducting layer, and an intermediate barrier layer. One end of the connecting block 33 is electrically connected to the superconducting layer of the Josephson junction 31, and the other end is electrically connected to the capacitor plate 32, thereby realizing the electrical connection between the Josephson junction 31 and the capacitor plate 32; wherein the material of the connecting block 33 can be ordinary metal, such as: elemental metals such as gold, silver, and copper, and its form can be a device with electrical connection function such as a metal flying lead or a connection port.

[0064] The method for manufacturing the quantum chip described above, wherein step S12: forming the bit structure 3 in the window, further comprises the following steps:

[0065] S13: Etching the capacitor plate 32 to form a through hole 5 penetrating the capacitor plate 32; this is also a part of the aforementioned "vortex-like" structure. Based on the aforementioned conditions, providing a through hole 5 penetrating the opposite surface of the capacitor plate 32 near the Josephson junction 31 can restrict quasiparticles and prevent quasiparticles from approaching the Josephson junction 31. In addition, a plurality of through holes 5 are provided on the capacitor plate 32. If the process permits, the density of the plurality of through holes 5 manufactured on the capacitor plate 32 should be as high as possible, and the shape of the through holes 5 can also be triangular prisms, quadrangular prisms, cylinders, etc., so as to achieve the purpose of having the maximum restrictive effect on the quasiparticles.

[0066] Please refer to Figure 4 and Figure 5 The above-mentioned method for manufacturing a quantum chip, wherein step S13: etching the capacitor plate 32, after forming a through hole 5 through the capacitor plate 32, further comprises the following steps:

[0067] S14 : forming a metal film layer 4 at one end of the superconducting layer of the Josephson junction 31 away from the junction region; wherein the metal film layer 4 is not in contact with the capacitor plate 32 .

[0068] The structure based on the quantum bit is composed of a Josephson junction 31 and a parallel capacitor, wherein the Josephson junction 31 can be equivalent to a nonlinear inductor, and the Josephson junction 31 is a structure composed of a superconductor-insulator-superconductor, the most common of which is an Al-AlOx-Al junction; and the Josephson junction 31 includes an upper superconducting layer, an intermediate barrier layer and a lower superconducting layer, wherein the upper superconducting layer and the lower superconducting layer have an intersecting portion, and the intermediate barrier layer is sandwiched in the intersecting portion, wherein the overlapping portion is defined as a junction region, and the portion of the upper superconducting layer and the lower superconducting layer leaving the junction region is defined as an electrode, and the above-mentioned metal film layer 4 is located at one end of the Josephson junction 31 close to the electrode and extends back to the junction region; and according to tests, when the metal film layer 4 extends to contact with the capacitor plate 32, the metal film layer 4 has no inhibitory effect on quasi-particles; therefore, in the embodiment of the present application, the metal film layer 4 is in contact with the capacitor plate 32.

[0069] In one embodiment of the present application, the material of the metal film layer 4 can be selected as a superconducting metal or an ordinary metal; when the material of the metal film layer 4 is selected as a superconducting metal, the superconducting energy gap of the selected superconducting metal material pair is smaller than the superconducting energy gap of the superconducting metal layer 2.

[0070] Specifically, the quasiparticle trapping structure made of ordinary metal material creates an effective potential well with an energy gap depth Δ for the quasiparticles. When the quasiparticles diffuse into the potential well, they are captured by the ordinary metal and their energy is dissipated into the normal metal, preventing them from participating in the tunneling process of the Josephson junction 31, thereby improving the performance of the quantum chip. Furthermore, when the metal film layer 4 is selected to be an ordinary metal, ordinary metals include elemental metals such as gold, silver, and copper, and are manufactured into the aforementioned "trapping" structure using methods such as magnetron sputtering coating.

[0071] In addition, the selection of the material of the metal film layer 4 as a superconducting metal is based on the size of the superconducting energy gap of the superconducting metal; that is, when the metal is in a superconducting state, the formula for the superconducting gap Δ is: Δ = 1.75kTc, where k is the Boltzmann constant and Tc is the superconducting critical temperature; if the material of the metal film layer 4 is set to titanium (Ti) or zirconium (Zr) metal, and the material of the superconducting metal layer 2 is set to aluminum, where the Tc of aluminum is 1.2K, the Tc of Ti is 0.39K, and the Tc of Zr is 0.55K, the superconducting gap is smaller than that of aluminum.

[0072] Furthermore, superconducting metals with a smaller superconducting energy gap limit the energy of quasiparticles to below the small superconducting energy gap through inelastic electron-phonon interaction, thereby preventing them from destroying the Cooper pairs in the quantum bit layer, preventing the quasiparticles from approaching the junction region of the Josephson junction 31 and participating in the tunneling process in the junction region, thereby improving the performance of the quantum chip.

[0073] In addition, the size of the metal film layer 4 is often determined according to the electrode size of the Josephson junction 31. According to the inventor's experiments, the size of the metal film layer 4 is generally smaller than the electrode size of the Josephson junction 31; for example, if the electrode size is set to 3μm*6μm and the junction length is 12μm, the corresponding size of the metal film layer 4 can be set to a rectangular structure of 1μm*3μm, and it is 2μm away from the edge of the junction electrode and has a thickness of 100nm; in the actual manufacture of the metal film layer 4, it needs to be satisfied that the size of the metal film layer 4 does not exceed the size of the electrode, and one end of the metal film layer 4 can extend beyond the electrode but does not contact the capacitor plate 32, so as to achieve the most efficient confinement effect on the aligning particles.

[0074] From the above, it can be concluded that since the quasiparticle "capture" structure - the metal film layer 4 leaves the junction area of ​​the Josephson junction 31, the quasiparticles in the superconducting material will be trapped in the non-core area (junction area) of the superconducting quantum device, so that the quasiparticles cannot participate in the tunneling process of the Josephson junction 31, thereby reducing the loss introduced by the tunneling process in the junction area and improving the decoherence time of the quantum bit.

[0075] The present application also provides a quantum chip manufactured according to the aforementioned quantum chip manufacturing method.

[0076] In one embodiment of the present application, the material of the superconducting metal layer 2 is selected to be aluminum; and a quantum chip is provided with one or more bit structures 3.

[0077] At present, any conductive material has a certain value of resistance when it exists at room temperature; however, there is also a type of metal that exhibits zero resistance at both ends when it exists at a specific extremely low temperature, such as lead, tin, niobium, aluminum and other metals. This phenomenon is defined as the superconducting effect; therefore, the material of the superconducting metal layer 2 can be selected from any metal that exhibits superconducting effect, and is not limited to the above examples.

[0078] In addition, the quantum chip also includes devices such as a resonant cavity, a bus, and a readout line, and these devices are manufactured on the same surface of the substrate 1 as the Josephson junction 31. Therefore, according to the above description of the through hole 5, the through hole 5 should be manufactured after the devices on the quantum chip are basically manufactured. It should be laid out according to the arrangement of the above devices on the superconducting metal layer 2, and the through hole 5 is required to be away from all quantum devices.

[0079] At present, quantum chips are called multi-bit superconducting quantum chips, that is, a quantum chip is often provided with multiple bit units to achieve its increasingly advanced computing performance; therefore, a quantum chip is often also accompanied by multiple Josephson junctions 31, and a corresponding number of read lines, control lines, resonant cavities and capacitors, etc.; in this design scenario, in order to make each Josephson junction 31 as unaffected by quasiparticles as possible, multiple capacitor plates 32 and through holes 5 connected to the Josephson electrodes should also be provided to achieve the maximum limiting effect on the quasiparticles.

[0080] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "example," or "specific example" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. Furthermore, those skilled in the art may combine and reconcile different embodiments or examples described in this specification.

[0081] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A method for manufacturing a quantum chip, characterized in that: The following steps are involved: A substrate (1) having a bit structure (3) formed on its surface and a superconducting metal layer (2) providing a ground plane is provided; wherein the bit structure (3) is not in contact with the superconducting metal layer (2); A through hole (5) is formed in the superconducting metal layer (2).

2. The method for manufacturing a quantum chip according to claim 1, wherein: There are multiple through holes (5).

3. The method for manufacturing a quantum chip according to claim 1, wherein: The through hole (5) is in the shape of a quadrangular prism, a triangular prism or a cylinder.

4. The method for manufacturing a quantum chip according to any one of claims 1 to 3, characterized in that: The step of providing a substrate (1) having a bit structure (3) and a superconducting metal layer (2) formed on its surface comprises: Etching the superconducting metal layer (2) to form a window exposing a portion of the substrate (1); A bit structure (3) is formed within the window.

5. The method for manufacturing a quantum chip according to claim 4, characterized in that: The bit structure (3) includes a Josephson junction (31), a capacitor plate (32) and a connection block (33); The Josephson junction (31) is not in contact with the capacitor plate (32), and is electrically connected via the connecting block (33).

6. The method for manufacturing a quantum chip according to claim 5, characterized in that: After the step of forming the bit structure (3) within the window, the method further comprises: The capacitor plate (32) is etched to form a through hole (5) penetrating the capacitor plate (32); wherein there are a plurality of through holes (5).

7. The method for manufacturing a quantum chip according to claim 6, characterized in that: After the step of etching the capacitor plate (32) and forming a through hole (5) through the capacitor plate (32), the method further includes: A metal film layer (4) is formed at one end of the superconducting layer of the Josephson junction (31) away from the junction region; wherein the metal film layer (4) is not in contact with the capacitor plate (32).

8. The method for manufacturing a quantum chip according to claim 7, characterized in that: The material of the metal film layer (4) is a superconducting metal or a common metal; The superconducting energy gap of the superconducting metal is smaller than the superconducting energy gap of the superconducting metal layer (2).

9. A quantum chip, characterized in that: A quantum chip manufactured by the method for manufacturing a quantum chip according to any one of claims 1 to 8.

10. The quantum chip according to claim 9, characterized in that The material of the superconducting metal layer (2) is aluminum; And / or, there are multiple bit structures (3).

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