Method and apparatus for reducing memory capacity for storing page related information in NAND flash device

Abstract

The size of a page mapping memory for storing page-related information in a NAND flash device is reduced by embedding a page type in a row address. The NAND flash device receives the row address from a host over a data bus in a six-cycle sequence. The received row address is used for decoding a physical page address received in a row address period so as to obtain a word line of the NAND flash array and a block segment number of a block segment in the word line. Each page type in the block segment uses the same block segment number.

Description

[0001] Priority claim

[0002] This application claims priority under 35 U.S.C. §365(c) to U.S. Application No. 18 / 107,677, filed on February 9, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to nonvolatile memory devices, and in particular, to NAND flash memory devices. Background Art

[0004] Non-volatile memory refers to memory whose state remains deterministic even if power to the device is interrupted. Storage devices containing non-volatile memory include secure digital cards, multimedia cards, flash drives (e.g., Universal Serial Bus (USB) flash drives, also known as "USB flash drives" or "USB memory sticks," which contain non-volatile memory and have an integrated USB interface), and solid-state drives.

[0005] The non-volatile memory may include block-addressable memory devices such as NAND, or more specifically, multi-threshold level NAND flash memory (e.g., single-level cell (“SLC”), multi-level cell (“MLC”), triple-level cell (“TLC”), quad-level cell (“QLC”), penta-level cell (“PLC”), or some other NAND).

[0006] NAND flash memory devices typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. Memory cells are typically arranged in a memory array and can be addressed in a row / column format. NAND flash cells use the threshold voltage of a floating-gate transistor to represent the data stored in the cell.

[0007] Three-dimensional (3D) NAND is a type of non-volatile flash memory in which memory cells are stacked vertically in multiple layers. For example, 32, 48, 64, or more cell layers can be stacked vertically. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds and with reference to the accompanying drawings, in which like numerals represent like parts, and in which:

[0009] Figure 1 is a block diagram of a three-dimensional (3D) NAND flash device;

[0010] Figure 2 yes Figure 1A block diagram of an array organization of a three-dimensional (3D) NAND flash array in a 3D NAND flash device is shown;

[0011] Figure 3 is included Figure 1 A block diagram of a system for a 3D NAND flash device is shown;

[0012] Figure 4 shows a six-cycle sequence of addresses used by a host to load a 3D NAND flash array;

[0013] Figure 5 is a table showing the mapping of page type bits sent through data pins DQ (DQ7:DQ5) to page types in a 3D NAND device in the fourth cycle;

[0014] Figure 6 yes Figure 1 An example of a word line / block segment table 152 is shown.

[0015] Figure 7 is a timing diagram illustrating a six-cycle sequence used by a host to load an address into a 3D NAND flash array;

[0016] Figure 8 is a flow chart of a method for loading addresses of a 3D NAND flash array; and

[0017] Figure 9 is a block diagram of a computer system including a 3D NAND device.

[0018] Although the following detailed description will refer to illustrative embodiments of the claimed subject matter, numerous alternatives, modifications, and variations thereof will be apparent to those skilled in the art. It is therefore intended that the claimed subject matter be viewed broadly and defined in accordance with the provisions of the appended claims. DETAILED DESCRIPTION

[0019] A 3D NAND device includes a 3D NAND flash array containing multiple NAND cells organized into rows and columns. A 3D NAND device does not have dedicated address pins. Addresses (row and column addresses) are loaded by the host via the data pins on the 3D NAND device using a six-cycle sequence. During the first and second cycles of the six-cycle sequence, the 3D NAND flash receives the column address via the data pins. During the third, fourth, fifth, and sixth cycles of the six-cycle sequence, the 3D NAND flash receives the row address via the data pins during the row address cycle. The row address includes the page address, block address, and logical unit (LUN) address.

[0020] The host accesses the pages sequentially according to the page number order defined in the page mapping table. The 3D NAND device uses the row address to decode the word lines, segments in the block (block segments), word line types, and word line groups stored in the page mapping table of the static random access memory (SRAM) of the 3D NAND flash array. The word line type can be single-level cell ("SLC"), multi-level cell ("MLC"), triple-level cell ("TLC"), quad-level cell ("QLC"), or penta-level cell ("PLC"), and the word line types of native word lines and edge word lines can be different. For example, in a 3D NAND device whose native word line type is QLC, the edge word line type can be SLC. Each block in the 3D NAND flash array contains pages. Page groups reside in sub-segments, which can be called block segments. Block segments and word lines are used to access a memory location in the 3D NAND flash array. Word lines grouped in a word line group receive the same voltage during operation of the 3D NAND flash array.

[0021] Furthermore, the page type of the array operation is decoded in the control circuitry of the 3D NAND device. As the number of layers (also called tiers or word lines) in a 3D NAND flash array increases, the size of the page mapping table storing page-related information in the SRAM of the 3D NAND flash array also increases, and the control circuitry for page type decoding in the 3D NAND flash array also increases.

[0022] By embedding the page type in the row address, the size of the page mapping table used to store page-related information in the SRAM of a 3D NAND flash device is reduced. The 3D NAND flash device receives the row address from the host via the data bus in a six-cycle sequence. The received row address and column address are used to access the 3D NAND flash array in the 3D NAND flash device.

[0023] Various embodiments and aspects of the present invention will be described with reference to the details discussed below, and the accompanying drawings will illustrate various embodiments. The following description and drawings illustrate the present invention and should not be construed as limiting the present invention. Many specific details are described to provide a thorough understanding of the various embodiments of the present invention. However, in some cases, well-known or conventional details will not be described in order to provide a concise discussion of embodiments of the present invention.

[0024] Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0025] Figure 1FIG1 is a block diagram of a three-dimensional (3D) NAND device 100. The 3D NAND device 100 includes input / output control circuitry 102 and control circuitry 104, which are coupled to a host memory controller (not shown) via a plurality of control and data signals. The 3D NAND device 100 also includes a 3D NAND flash array 106, which includes a plurality of NAND cells organized into rows and columns. The 3D NAND device 100, also referred to as a logical unit (LUN), may include one or more NAND flash dies. A NAND flash die is the smallest unit that can independently execute commands and report status.

[0026] A row decoder 110 and a column decoder 108 are provided for decoding address signals to access the 3D NAND flash array 106. The 3D NAND device 100 further includes input / output (I / O) control circuitry 102 for managing the input of commands, addresses, and data to the 3D NAND device 100, and the output of data and status information from the 3D NAND device 100. An address register 116 communicates with the I / O control circuitry 102, the row decoder 110, and the column decoder 108 to latch address signals prior to decoding. A command register 112 communicates with the I / O control circuitry 102 and the control circuitry 104 to latch incoming commands. A status register 114 communicates with the I / O control circuitry 102 and the control circuitry 104 to latch status.

[0027] Control circuitry 104 controls access to 3D NAND flash array 106 in response to commands and generates status information. Control circuitry 104 communicates with row decoder 110 and column decoder 108 to control row decoder 110 and column decoder 108 in response to addresses. Control circuitry 104 includes static random access memory (SRAM) 150 for storing page-related information for pages in NAND flash array 106 in word line / block segment table 152.

[0028] The Open NAND Flash Interface (ONFI) is a standard that defines the operation of the data bus and control signals 118. The ONFI standard supports an 8-bit or 16-bit data bus (two independent 8-bit data buses) and multiple NAND flash dies in one package (3D NAND device 100).

[0029] The input / output control circuitry 102 in the 3D NAND device 100 communicates with the host memory controller via a bidirectional data bus (DQ) and a bidirectional data strobe (DQS) signal. The DQS signal is used to indicate the data valid window. The control circuitry 104 in the 3D NAND device 100 receives control signals 118 from the host memory controller. The received control signals 118 include: a chip enable (CE#) for selecting the 3D NAND device 100 for data transfer with the host memory controller; an address latch enable (ALE) for indicating the type of bus cycle (command, address, or data); a command latch enable (CLE) for indicating the type of bus cycle (command, address, or data); a read enable (RE#); a write enable (WE#); and a write protect (WP#) for disabling program and erase operations. The 3D NAND device 100 also includes control signals 118 output by the control circuitry 104, including a ready / busy (R / B#) signal that indicates whether the 3D NAND device 100 is currently executing an operation ("busy") or is ready for the next operation. In a NAND flash device 100 having multiple LUNs, there is one CE# per LUN for controlling the LUN.

[0030] The NAND flash device 100 does not have dedicated address pins. Addresses are loaded using a six-cycle sequence. During the first and second cycles of the six-cycle sequence, the 3D NAND flash receives the column address via the data pins. During the third, fourth, fifth, and sixth cycles, the 3D NAND flash receives the row address via the data pins.

[0031] It should be understood that Figure 1 The memory device of the embodiment may include additional circuit systems and signals, and the functional blocks of the memory device may not necessarily be separated as shown in this example. For example, a single component or component portion of an integrated circuit device may be used to perform Figure 1 Alternatively or additionally, Figure 1 The functionality of a single block component can be distributed across multiple blocks. Additionally, while specific I / O pins are described according to the general conventions of receiving and outputting various signals, it should be noted that other combinations of I / O pins or other numbers of I / O pins can be used in various embodiments. It should be understood that many variations exist.

[0032] Figure 2 yes Figure 1 A block diagram of the array organization of a three-dimensional (3D) NAND flash array 106 in a 3D NAND flash device 100 is shown.

[0033] The 3D NAND flash array 106 is divided into multiple physical planes. Figure 2In the example shown, there are four physical planes, namely, plane 0 (P0) 202-1, plane 1 (P1) 202-2, plane 2 (P2) 202-3, and plane 3 (P3) 202-4. Each physical plane 202-1, 202-2, 202-3, 202-4 has corresponding cache registers (not shown) and data registers (not shown), which are not affected by other planes, thereby allowing multi-plane operations, so that read, program, or erase operations can be performed in parallel on multiple planes. Each physical plane 202-1, 202-2, 202-3, 202-4 contains multiple blocks 204. Each block 204 is subdivided into multiple pages 206.

[0034] A block of planar NAND flash contains a grid of cells connected by word lines (WL) and bit lines (BL). A word line is the set of all cells corresponding to a row across the block bit lines. A page is the set of bits in a word line that correspond to the same bit level. Data is programmed / read from NAND flash page by page. The number of pages for each WL in a block is based on the type of memory cell. Single-level cells (“SLC”) store one bit of information per cell in one page (bottom page). Multi-level cells (“MLC”) store two bits of information per cell in two pages (bottom page, top page). Triple-level cells (“TLC”) store three bits of information per cell in three pages (bottom page, top page, extra page). Quad-level cells (“QLC”) store four bits of information per cell in four pages (bottom page, top page, extra page, top page). A five-level cell ("PLC") stores five bits of information per cell in five pages: Lower Page (LP), Upper Page (UP), Extra Page (XP), Top Page (TP), Europa Page (EP).

[0035] Figure 3 is included Figure 1 FIG2 is a block diagram of a system 300 for a 3D NAND flash device 100. The system 300 includes a host circuit system 310 and the 3D NAND flash device 100. The host circuit system 310 includes a processor 302, a 3D NAND device controller 304, and a memory 306. The 3D NAND device controller 304 is configured by the processor 302 to send commands to the 3D NAND device 100. The memory 306 stores a page mapping lookup table 308 for use by the processor 302 in sending commands to the 3D NAND device 100.

[0036] Figure 4 4 shows a six-cycle sequence 400 that the host circuitry 310 uses to load the address of the 3D NAND flash array 106. The address includes a column address 402 and a row address 404. The six-cycle sequence will be combined with Figure 11. The three-dimensional (3D) NAND flash device shown in FIG. In the first and second cycles of a six-cycle sequence, the 3D NAND flash array 106 receives a column address 402 via data pins DQ (DQ7:DQ0). In the first cycle, the 3D NAND flash array 106 receives column address bits CA7:CA0 via data pins DQ (DQ7:DQ0). In the second cycle, the 3D NAND flash receives column address bits CA14:CA8 via data pins DQ (DQ6:DQ0).

[0037] In the third, fourth, fifth, and sixth cycles, the 3D NAND flash receives a row address 404 through the data pins (DQ7:DQ0). The row address includes the physical page address (PA), page type, block address (BA), and LUN address (LA). The block address (BA) includes the plane address (e.g., BA[2:0]) and block address (e.g., BA[10:3]) of each plane.

[0038] In the third cycle, the 3D NAND flash array 106 receives eight physical page address bits ( PA7 : PA0 ) through data pins DQ ( DQ7 : DQ0 ) as part of a row address cycle.

[0039] In the fourth cycle, the 3D NAND flash array 106 receives five physical page address bits (PA12:PA8) and three page type bits (Page Type 2:Page Type 0) via data pins DQ (DQ7:DQ0). The word line number, block segment number, word line type, block type, and word line group number are the same for each page type in a single row and block segment.

[0040] In the fifth cycle, the 3D NAND flash array 106 receives eight block address bits (BA7:BA0) through data pins DQ (DQ7:DQ0), including three-bit plane addresses (BA[2:0]) and five bits (BA[7:3]) of the 8-bit block address per plane.

[0041] In the sixth cycle, the 3D NAND flash array 106 receives three bits (BA[10:8]) of the 8-bit block address per plane and a three-bit LUN address (LA2-LA0) through the data pins DQ (DQ5:DQ0).

[0042] Figure 5 : is a table showing the mapping of the page type bits sent through the data pins DQ (DQ7:DQ5) to the page types in the 3D NAND device 100 in the fourth cycle. Figure 5 In the illustrated embodiment, seven page types are encoded with three bits as the encoded page type.

[0043] Page type bits '001' (binary) map to the lower page (LP). Page type bits '001' (binary) map to the lower page (LP). Page type bits '010' (binary) map to the upper page (UP). Page type bits '011' (binary) map to the extra page (XP). Page type bits '100' (binary) map to the top page (TP). Page type bits '101' (binary) map to the Europa page (EP).

[0044] Page type bits '110' (binary) map to static single-level cells (sSLC), and page type bits '111' (binary) map to dynamic single-level cells (dSLC). The word line type of a native mode (e.g., QLC) corresponding to the block type of the native mode can be converted to sSLC mode throughout the lifecycle of the 3D NAND device 100, or converted to dSLC mode for a period of time and then converted back to native mode after the dSLC mode operation is completed.

[0045] Figure 6 yes Figure 1 1 . An example of a word line / segment table 152 is shown. The word line / segment table 150 has one entry 602 for each word line in a 3D NAND device. Each page type in a segment uses the same segment number. A single entry 602 for each word line is used for the page and segment in that word line. Each entry 602 includes a word line number field 604 and at least one segment field 606. The number of segment fields 606 in each entry 602 depends on the number of segments for each word line in the block. The word line number field 604 stores the word line number (e.g., '1'), and the segment field 606 stores the segment number (e.g., 'A', 'B'). Each segment in the 3D NAND flash array 106 is assigned a unique segment number.

[0046] Figure 7 is a timing diagram illustrating a six-cycle sequence used by the host circuitry 310 to load addresses into the 3D NAND flash array 106 .

[0047] At time 702 , host circuitry 310 sends a start command via data pins DQ ( DQ7 : DQ0 ).

[0048] At time 704 , the host circuitry 310 sends column address bits CA7 : CA0 to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ).

[0049] At time 706 , the host circuitry 310 sends column address bits CA14 : CA8 to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ).

[0050] At time 708 , the host circuitry 310 sends eight physical page address bits ( PA7 : PA0 ) to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ).

[0051] At time 710 , the host circuitry 310 sends five physical page address bits ( PA12 : PA8 ) and three page type bits ( Page Type 2 : Page Type 0 ) to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ).

[0052] At time 712 , the host circuitry 310 sends eight block address bits ( BA7 : BA0 ) to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ), including three-bit plane addresses ( BA[2 : 0 ]) and five bits of the 8-bit block address per plane ( BA[7 : 3 ]).

[0053] At time 714 , the host circuitry 310 sends three bits (BA[10:8]) of the 8-bit block address per plane and the three-bit LUN address ( LA2 - LA0 ) to the 3D NAND flash array 106 via data pins DQ ( DQ7 : DQ0 ).

[0054] At time 716 , host circuitry 310 sends an acknowledge command via data pins DQ ( DQ7 : DQ0 ).

[0055] Figure 8 1 is a flow chart of a method for decoding a physical page address of the 3D NAND flash array 106 .

[0056] At block 800, the word line number of the physical page address received in the six-cycle sequence is extracted from the physical page address. The eight physical page address bits (PA7:PA0) received by the 3D NAND flash array 106 via data pins DQ (DQ7:DQ0) in the third cycle and the five physical page address bits (PA12:PA8) received by the 3D NAND flash array 106 via data pins DQ (DQ7:DQ0) in the fourth cycle provide the word line number of the page.

[0057] At block 802, the extracted word line number is used to read the block segment field 606 in the entry 602 for the word line number in the word line / block segment table 152. The block segment field 606 stores the block segment number of the physical page address received in the six-cycle sequence. The block segment number is the remainder of the physical page address modulo the block segment number.

[0058] Figure 9is a block diagram of a computer system 900 including a 3D NAND device 100. The computer system 900 may correspond to a computing device including, but not limited to, a server, a workstation computer, a desktop computer, a laptop computer, and / or a tablet computer.

[0059] The computer system 900 includes a system on a chip (SOC or SoC) 904 that combines a processor, graphics, memory, and input / output (I / O) control logic into a single SoC package. The SoC 904 includes at least one central processing unit (CPU) module 908, a volatile memory controller 914, and a graphics processing unit (GPU) 910. In other embodiments, the volatile memory controller 914 may be external to the SoC 904. Although not shown, each processor core 902 may internally include one or more instruction / data caches, execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating point units, deregistration units, etc. According to one embodiment, the CPU module 908 may correspond to a single-core or multi-core general-purpose processor, such as a processor core. Those provided by the company.

[0060] The graphics processing unit (GPU) 910 may include one or more GPU cores and a GPU cache that can store graphics-related data of the GPU core. The GPU core may internally include one or more execution units and one or more instruction and data caches. In addition, the graphics processing unit (GPU) 910 may include other Figure 9 Graphics logic units not shown in the figure, such as one or more vertex processing units, rasterization units, media processing units, and codecs.

[0061] Within the I / O subsystem 912, there are one or more I / O adapters 916 that convert the host communication protocol utilized within the processor core 902 to a protocol compatible with a particular I / O device. Some of the protocols that the adapters can convert include: Peripheral Component Interconnect (PCI)-Express (PCIe); Universal Serial Bus (USB); Serial Advanced Technology Attachment (SATA); and Institute of Electrical and Electronics Engineers (IEEE) 1594 "FireWire."

[0062] The I / O adapter 916 can communicate with external I / O devices 924, which may include, for example, a user interface device including a display and / or touch screen display 940, a printer, a keypad, a keyboard, communication logic (wired and / or wireless), and storage devices including a hard disk drive ("HDD"), a solid state drive ("SSD") 918, removable storage media, a digital video disc (DVD) drive, a compact disc (CD) drive, a redundant array of independent disks (RAID), a tape drive, or other storage devices. The storage devices may be communicatively and / or physically coupled together using one or more protocols over one or more buses, including, but not limited to, Serial Attached Small Computer System Interface (SCSI) (SAS), Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe) based on Peripheral Component Interconnect Express (PCIe), and Serial Advanced Technology Attachment (ATA) (SATA).

[0063] In addition, there may be one or more wireless protocol I / O adapters. Examples of wireless protocols are used for personal area networks, such as IEEE 802.15 and Bluetooth 4.0; wireless local area networks, such as wireless protocols based on IEEE 802.11; and cellular protocols, among others.

[0064] I / O adapter 916 may also communicate with a storage device, which may be a hard disk drive (HDD) or solid state drive (“SSD”) 918 , including an SSD controller 920 , a host interface 928 , and 3D NAND device 100 .

[0065] The computer system 900 may include a 3D NAND device 100 and a 3D NAND device controller 304, which are communicatively coupled to a CPU module 908 in the SoC 904. The 3D NAND device 100 may be included in a dual in-line memory module (DIMM), which may be referred to as a non-volatile dual in-line memory module (NVDIMM).

[0066] A non-volatile memory (NVM) device is a type of memory whose state remains deterministic even if power to the device is interrupted. In one embodiment, the NVM device may comprise a block-addressable memory device, such as NAND technology, or more specifically, multi-threshold level NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), quad-level cell ("QLC"), triple-level cell ("TLC"), or some other NAND).

[0067] The I / O adapter 916 may include a Peripheral Component Interconnect Express (PCIe) adapter that is communicatively coupled to the host interface 928 in the solid-state drive 918 via bus 944 using the NVM Express (NVMe) protocol over Peripheral Component Interconnect Express (PCIe). The Non-Volatile Memory Express (NVMe) standard defines a register-level interface for host software to communicate with a non-volatile memory subsystem (e.g., a solid-state drive (SSD)) over Peripheral Component Interconnect Express (PCIe), a high-speed serial computer expansion bus. The NVM Express standard is available at www.nvmexpress.org. The PCIe standard is available at www.pcisig.com.

[0068] Applications 930 and an operating system (OS) 942 may be stored in volatile memory 926. Volatile memory is memory whose state (and therefore the data stored therein) cannot be determined when power to the device is interrupted. Dynamic volatile memory requires refreshing of the data stored in the device to maintain the state. An example of dynamic volatile memory includes dynamic random access memory (DRAM), or a variant such as synchronous DRAM (SDRAM). The memory subsystem described herein is compatible with a variety of memory technologies, such as DDR3 (Double Data Rate Version 3, originally released by the Joint Electron Device Engineering Council (JEDEC) on June 27, 2007), DDR4 (DDR Version 4, initial specifications released by JEDEC in September 2012), DDR4E (DDR Version 4), LPDDR3 (Low Power DDR Version 3, JESD209-3B, released by JEDEC in August 2013), LPDDR4 (LPDDR Version 4, JESD209-4, originally released by JEDEC in August 2014), and DDR3 (Low Power DDR Version 3, JESD209-3B, released by JEDEC in August 2014). C (published in August 2014), WIO2 (Wide Input / Output Revision 2, JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013), DDR5 (DDR Revision 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM Revision 2, currently under discussion by JEDEC), or other memory technologies or combinations of memory technologies, as well as technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0069] Operating system 942 is software that manages computer hardware and software including memory allocation and access to I / O devices. Examples of operating systems include and

[0070] The power supply 946 provides power to the components of the computer system 900. More specifically, the power supply 946 typically interfaces with one or more power supplies 948 in the computer system 900 to provide power to the components of the system X00. In one example, the power supply 948 includes an AC to DC (alternating current to direct current) adapter that can be plugged into a wall outlet. This AC power can be a renewable energy (e.g., solar) power source 946. In one example, the power supply 946 includes a DC power source, such as an external AC to DC converter. In one example, the power supply 946 or the power supply 948 includes wireless charging hardware that can be charged by approaching a charging field. In one example, the power supply 946 may include an internal battery or fuel cell.

[0071] The flowcharts shown herein provide examples of sequences of various process actions. A flowchart may indicate operations to be performed by software or firmware routines, as well as physical operations. In one embodiment, a flowchart may illustrate the states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular order or sequence, the order of the actions may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples, and the processes may be performed in different orders, and certain actions may be performed in parallel. Additionally, in various embodiments, one or more actions may be omitted; thus, not all actions are required in every embodiment. Other process flows are possible.

[0072] With respect to the various operations or functions described herein, they may be described or defined as software code, instructions, configurations, and / or data. The content may be directly executable ("object" or "executable" form), source code, or differential code ("incremental" or "patch" code). The software content of the embodiments described herein may be provided by a product storing the content, or by a method of operating a communication interface to send data via the communication interface. A machine-readable storage medium may enable a machine to perform the functions or operations described, and may include any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism for interfacing with a hardwired, wireless, optical, or other medium in order to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters and / or sending signals so that the communication interface is ready to provide data signals describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

[0073] The various components described herein may be means for performing the described operations or functions. Each component described herein comprises software, hardware, or a combination thereof. Components may be implemented as software modules, hardware modules, dedicated hardware (e.g., dedicated hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuit systems, etc.

[0074] Besides what is described herein, various modifications may be made to the disclosed embodiments and implementations of the invention without departing from the scope of the invention.

[0075] Therefore, the illustrations and examples herein should be regarded as illustrative only and not restrictive. The scope of the present invention should be determined solely by the appended claims.

Claims

1. A nonvolatile memory device comprising: A NAND flash array comprising a plurality of NAND cells; as well as Control circuitry is provided for decoding a physical page address received during a row address cycle to obtain a word line in the NAND flash array and a block segment number for a block segment in the word line, wherein each page type in the block segment uses the same block segment number. 2 . The nonvolatile memory device of claim 1 , wherein the word line and the block segment number are stored in a table in a static random access memory.

3. The non-volatile memory device of claim 2, wherein each block segment has an entry in the table.

4. The non-volatile memory device of any one of claims 1 to 3, wherein the physical page address including an encoded page type is received as part of the row address cycle.

5. The non-volatile memory device of claim 4, wherein the encoded page type is encoded in three bits.

6. The non-volatile memory device of claim 4, wherein the encoded page type is static single-level cell (SLC).

7. The non-volatile memory device of claim 4, wherein the encoded page type is dynamic single-level cell (DLC).

8. The nonvolatile memory device of claim 4, wherein the NAND cell is a quad-level cell and the encoded page type is a lower page, an upper page, an extra page, or a top page.

9. The nonvolatile memory device of claim 4, wherein the NAND cell is a five-level cell, and the encoded page type is a lower page, an upper page, an extra page, a top page, or a Europa page.

10. The non-volatile memory device of any one of claims 1 to 9, wherein the NAND cell is a three-dimensional (3D) NAND cell.

11. A system comprising: Memory controller; and a nonvolatile memory device comprising a NAND flash array including a plurality of NAND cells; as well as Control circuitry is provided for decoding a physical page address received during a row address cycle to obtain a word line in the NAND flash array and a block segment number for a block segment in the word line, wherein each page type in the block segment uses the same block segment number.

12. The system of claim 11, wherein the word line and the block segment number are stored in a table in static random access memory.

13. The system of claim 12, wherein each chunk has an entry in the table.

14. The system of any one of claims 11 to 13, wherein the physical page address including an encoded page type is received as part of the row address cycle.

15. The system of claim 14, wherein the encoded page type is encoded in three bits.

16. The system of claim 14, wherein the encoded page type is static single-level cell.

17. The system of claim 14, wherein the encoded page type is dynamic single-level unit.

18. The system of claim 14, wherein the NAND cell is a five-level cell and the encoded page type is a lower page, an upper page, an extra page, a top page, or a Europa page.

19. The system of any one of claims 11 to 18, wherein the NAND cell is a three-dimensional (3D) NAND cell.

20. The system of claim 11, further comprising: One or more of the following: processor, power supply, and A display is coupled to the non-volatile memory device.

21. A method comprising: decoding, by control circuitry in a nonvolatile memory device, a physical page address received during a row address cycle to obtain a word line in a NAND flash array in the nonvolatile memory device and a block segment number of a block segment in the word line; as well as By the control circuitry, the same block segment number is used for each page type in the block segment.

22. The method of claim 21, wherein the word line and the block segment number are stored in a table in static random access memory.

23. The method of claim 22, wherein each chunk has an entry in the table.

24. The method of any one of claims 21 to 23, wherein the physical page address including an encoded page type is received as part of the row address cycle.

25. An apparatus comprising means for performing the method according to any one of claims 21 to 24.

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