Data processing network with super home nodes

Abstract

A super home node of a first chip of a multi-chip data processing system manages consistency of both a local cache line and a remote cache line accessed by a local cache proxy; and a local cache line accessed by the cache proxy of the one or more second chips. Both the local cache line and the remote cache line are stored in a shared cache, and the requests are stored in a shared coherency point queue. An entry in a snoop filter table of the hyperhome node includes a presence vector indicating that a remote cache line is present at a particular cache agent of the first chip, or a local cache line is present at the particular cache agent of the first chip and any cache agent of the second chip. All cache agents of the second chip are represented as a single cache agent in the presence vector.

Description

Background Art

[0001] In large multi-chip data processing systems with many cache agents, it is challenging to track the presence of cache lines at all cache agents. Tracking is typically accomplished by storing an entry for each cache line in a snoop filter table, where each entry contains a list of multi-bit device identifiers (IDs) for each cache agent or a single logical ID indirection to indicate at which cache agents the cache line exists. This approach is not practical for large-scale systems because the snoop filter table becomes too large. For example, in a system with 512 cache agents being tracked, it is impractical to store an identifier for each cache agent in each cache line entry in the snoop filter table. Even using a logical ID indirection for each cache agent, each cache line would still require a 512-bit presence vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings provide visual representations that will be used to more fully describe various representative embodiments and that can be used by those skilled in the art to better understand the disclosed representative embodiments and their inherent advantages. In the accompanying drawings, like reference numerals indicate corresponding or similar elements.

[0003] Figure 1 is a simplified block diagram of a multi-chip data processing system according to a representative embodiment.

[0004] Figure 2 is a block diagram of a data processing apparatus according to various representative embodiments.

[0005] Figure 3 is a block diagram of a hierarchical super home node according to various representative embodiments.

[0006] Figure 4 and Figure 5 is a diagrammatic representation of a snoop filter hierarchy according to various representative embodiments.

[0007] Figure 6 is a flow chart of a consistency management method according to various representative embodiments. DETAILED DESCRIPTION

[0008] Various apparatus and devices described herein provide mechanisms for cache coherency management in multi-chip and multi-block data processing networks.

[0009] Although the present disclosure is capable of many different forms of embodiment, specific embodiments are shown in the drawings and will be described in detail herein, it should be understood that the embodiments shown and described herein should be considered as providing examples of the principles of the present disclosure and are not intended to limit the disclosure to the specific embodiments shown and described. In the following description, like reference numerals are used to describe the same, similar, or corresponding parts in the several views of the drawings. For simplicity and clarity of illustration, reference numerals may be repeated in the drawings to indicate corresponding or similar elements.

[0010] Figure 1 1 is a simplified block diagram of a multi-chip data processing system 100 according to an embodiment of the present disclosure. A first host chip 102 (host 0) is coupled to a second host chip 106 (host 1) via a symmetric link 104 and to a device chip 110 via a link 108. The host chip 102 includes multiple request and local cache agents 112, such as a central processing core with a core-private level 1 (L1) cache and a cluster-private level 2 (L2) cache. For example, these components can be coupled via a coherent mesh network. The processing core accesses local directly coupled memory 114, which can be located on the chip, off the chip, or both. The processing core can also access remote memory 116 directly coupled to the second host chip 106 and remote memory 118 directly coupled to the device chip 110. As used herein, the term "memory" refers to any computer-readable medium, including but not limited to volatile, non-volatile, and persistent memory.

[0011] Cache coherency for data mapped to local directly coupled memory 114 is maintained by the local home agent 120. The home agent 120 is a cache manager (CM-L) for data mapped to local memory 114. The home agent 120 may also manage a system level cache (SLC) 122, which is a coherent cache (CC-L) for data mapped to local memory 114. The home agent 120 includes a snoop filter that tracks local data accessed by both the local caching agent and remote caching agents, such as the host 106 and the device 110.

[0012] The local coherence node (LCN) 124 is a cache manager (CM-R) for data mapped to remote memory 118 when the local caching agent accesses the data. In one embodiment, a request for remote memory access by the local request agent is received at a first interface 126, and the request for local memory access is passed to the home agent 120. In another embodiment, requests for both local and remote memory access are received at the first interface 126, and the request for local memory access is forwarded to the home agent 120 via an interface 128. The LCN 124 may also manage a coherence cache (CC-R) 130 that caches data mapped to remote memory 118. The LCN 124 includes a snoop filter that tracks remote data accessed by the local caching agent 112.

[0013] Device 110 includes its own home agent 130, which manages the coherency of the local caching agent.

[0014] Although Figure 1 Only a single device chip and two host chips are shown, but a large-scale data processing system may include many cache agents across multiple chips. Multiple levels of a cache and snoop filter hierarchy may be used to maintain data and instruction consistency across all cache agents. The snoop filter tracks the cache lines accessed by each cache agent so that any subsequent access to that address by another cache agent can be easily found for consistency resolution. In a hierarchical system, each level of the cache / snoop filter hierarchy acts as an aggregation layer for the caches of the previous level. For example, multiple private level 1 (L1) data and instruction caches are tracked at a shared level 2 (L2) snoop filter. If the L2 cache is private to each agent, tracking is done at a shared level 3 (L3) snoop filter, and so on. At the level of the system level cache (SLC), the snoop filter tracks all cache lines in the L3 or last level cache (L3 / LLC) and higher levels. (In this article, L1 is considered the highest level).

[0015] When scaling to large multi-chip systems with a large number of caching agents, it becomes challenging to track multiple caching agents for each cache line entry in the snoop filter. This tracking is accomplished using a unique multi-bit device identifier (ID) or logical ID indirect identification for each caching agent. For example, in a system with 512 caching agents being tracked at the next shared level, it is impractical to store an identifier for each caching agent in each cache line entry. Even using logical ID indirect identification for each caching agent, a 512-bit presence vector is still required for each cache line.

[0016] Table 1 shows example entries in an example snoop filter table. Each entry has an address tag, the current coherence state of the cache line, and a presence vector for each caching agent. The presence vector is a logical ID bit vector where each bit position corresponds to a caching agent. The coherence state is one of modified (M), exclusive (E), shared (S), or invalid (I).

[0017] Table 1 Snoop filter table content items for 512 proxy traces .

[0018]

[0019] Snoop filter clustering has been implemented to reduce the size of the snoop filter presence. However, snoop filter clustering can lead to inaccurate tracking of caching agents and, therefore, performance degradation, such as monopolized processing and unnecessary snooping.

[0020] In a flat uniform system, coherence requests are transmitted to the home node that serves as the point of coherence (PoC) for the data. This can be inefficient for local sharing of remote cache lines (i.e., cache lines that map to remote memory). For example, when a cache agent requests a shared copy of a remote cache line, both the coherence read message and the data transfer must cross the chip-to-chip link. This introduces significant latency even when a shared copy of the cache line exists in a peer cache agent on the same chip.

[0021] Reference again Figure 1 , the standalone LCN 124 and home agent 120 can be configured in series using link 128. For example, where requests are directed to the LCN 124 and forwarded to the home agent 120 as needed. However, this adds an additional caching layer, which may result in longer latency when the caching agent accesses local memory 114.

[0022] Alternatively, a standalone LCN can be used only for remote memory access. Link 128 is not implemented, so access latency to local memory 114 is not affected. However, a standalone LCN device may still introduce unnecessary snoop filter overhead because the LCN snoop filter is completely unused when all cache agents access only local memory 114.

[0023] According to an embodiment of the present disclosure, the home agent and LCN are combined as a super home node (HNS). Compared to an inline LCN, this still allows a level of caching for local memory, and access to local memory is not affected. In addition, this combination allows both local and remote services to efficiently utilize shared hardware resources.

[0024] Figure 22 is a block diagram of a data processing apparatus 200 according to various representative embodiments. A first integrated circuit or chip 202 includes a plurality of request and caching agents 204, such as a central processing core having a core-private level 1 (L1) cache and a cluster-private level 2 (L2) cache. For example, these components may be coupled via a coherent mesh network. The processing core accesses local directly coupled memory 206, which may be located on-chip, off-chip, or both. The processing core may also access one or more remote memories directly coupled to one or more second integrated circuits via a chip-to-chip gateway 208. The one or more second integrated circuits may include, for example, another processing circuit, an accelerator circuit, a cache, or a memory.

[0025] The one or more second integrated circuits may include circuits on two or more integrated circuit dies (chiplets) within the same package.

[0026] According to an embodiment of the present disclosure, the apparatus 200 includes a super home node (HNS) 210. The HNS 210 includes a consistency manager 212 that manages local consistency and cache data for data mapped to addresses in remote memory, and also manages consistency across multiple chips for data mapped to addresses in local memory 206. Thus, the HNS 210 combines the functionality of a local consistency node (LCN). The HNS 210 acts as a home node for a series of data addresses in the local memory 206 and manages system cache consistency across multiple chips. The HNS 210 also acts as a local consistency node (LCN) for data addresses in a memory device coupled to one or more remote integrated circuits or located in one or more remote integrated circuits.

[0027] The HNS 210 also includes a data cache 214 that caches lines of data from both the local memory 206 and one or more remote memories.

[0028] HNS210 has the following features:

[0029] • Each remote integrated circuit or chip appears as a single caching agent, which simplifies scaling of multi-chip systems.

[0030] Cache coherency for remote addresses is managed locally, rather than always going off-chip to the remote home node.

[0031] • HNS 210 provides an alternative cache hierarchy for remote rows while local memory latency is not affected.

[0032] The HNS210 supports different flexible topologies and system configurations, such as input / output (I / O) hubs and Compute Express Link from the Compute Express Link Consortium, Inc. TM (CXL TM ) protocol.

[0033] The advantage of the super-home node is scalability. Hierarchical HNS allows each remote integrated circuit to appear as a single caching agent. This avoids the need for snoop filter tracking of all caching agents on the remote chip. Therefore, it can scale to large multi-chip systems.

[0034] For example, in a 4-chip system with 128 cache agents on each chip, accurate tracking in a flat system requires a 512-bit snoop filter presence vector (as shown in Table 1 above). In contrast, in a hierarchical system with HNS, the presence vector uses 128 bits for the local cache agent and 3 bits for the remote chip, for a total of 131 bits. For a remote chip, a specified bit in the presence vector is set when a cache line is present in at least one cache of that remote chip. Table 2 shows example snoop filter table entries in a hierarchical super home node. Each entry includes a trace or presence vector.

[0035] Table 2 Snoop filter table for cluster agent tracking .

[0036]

[0037] Bits 0-127 each correspond to a single local cache agent, and bits 128-130 each correspond to a remote chip. For each local cache agent, a presence vector indicates when a cache line is present at that cache agent. For each remote integrated circuit, a presence vector indicates when a cache line is present at any cache agent on that integrated circuit.

[0038] In a flat system, the home agent implements snoop filter clustering that groups multiple caching agents into a cluster. In the same system described above with four caching agents in each cluster, the snoop filter requires a 128-bit presence vector. If any of the four agents in the cluster have accessed a cache line, any access to that cache line will result in a snoop on all four agents. Furthermore, if multiple clusters share a cache line, more snoops are transmitted across the chip-to-chip link. In contrast, using the hierarchical HNS of the present disclosure, only a single snoop is transmitted to the remote chip.

[0039] Hierarchical HNS allows cache coherence for remote addresses to be managed locally, eliminating the need to always communicate with the home node of the remote chip. For addresses mapped to remote memory, the HNS is a cache agent and tracks the MESI coherence state. If an early access obtains chip ownership of a cache line mapped to a remote address, the HNS acting as the LCN becomes the point of coherence (PoC) and the ownership request can be processed within the chip. For local sharing, when a cache agent requests a shared copy of a remote address, a coherent read for that address is transmitted to the HNS acting as the LCN. The HNS can return data cached in the local coherence cache or transmit a forward snoop to a peer cache agent.

[0040] By adding another cache hierarchy to the system, HNS significantly improves remote memory access latency compared to a flat system. While cache agents access local memory, HNS still provides a level of cache in the SLC. Thus, HNS improves remote memory access performance without sacrificing local memory access performance.

[0041] In summary, various embodiments of the present disclosure provide a data processing device having multiple cache agents in a first integrated circuit. A chip-to-chip gateway is configured to be coupled between the first integrated circuit and the second integrated circuit. The snoop filter table of the first integrated circuit is configured to store entries associated with cache lines. Each entry includes an existence vector, a coherence state of the cache line, and an address tag of the cache line. For each cache agent of the first integrated circuit, the existence vector indicates when the cache line is present at the particular cache agent. For the second integrated circuit, the existence vector indicates when the cache line is present at any cache agent of the second integrated circuit. The snoop filter table is included in a snoop filter that filters transaction requests for the cache line, wherein the filtering is based on the existence vector of the storage entry associated with the cache line. The cache agent of the first integrated circuit or the second integrated circuit may include, for example, a cluster of one or more processors and one or more caches.

[0042] Figure 3 is a block diagram of a hierarchical HNS 210 according to various representative embodiments. Local and remote memory access uses shared hardware resources with low overhead. In addition, reservations are used in each hardware resource to avoid deadlock. HNS 210 includes a shared coherence manager 212 and a shared data cache 214. Shared coherence manager 212 includes a point of coherence queue (POCQ) 302 and a shared snoop filter and snoop filter eviction queue (SEQ) 304.

[0043] The shared data cache 214 provides caching for: (a) cache lines mapped to local memory and requested by local or remote agents; and (b) cache lines mapped to remote memory when these lines have been requested by local requests / cache agents. In one embodiment, the HNS implements dynamic, portion-based partitioning between cache lines mapped to local memory and cache lines mapped to remote memory. This provides more efficient cache utilization when local and remote mapped cache lines compete for cache resources. In addition, the HNS can implement an eviction strategy that selects a victim cache line to avoid victim oscillation, wherein a remote mapped line evicted from one HNS is assigned to a local partition of the remote HNS and triggers eviction at that local partition.

[0044] POCQ 302 is a shared consistency point queue. The shared consistency point queue is configured to store: transaction requests for data in a memory coupled to or located in a first integrated circuit; and transaction requests for data in a memory coupled to or located in one or more second integrated circuits. Transactions accessing local memory and transactions accessing remote memory can both be allocated in the shared POCQ. POCQ 302 can be configured to allow class-based partitioning, such as quality of service (QoS) classes, so that transactions can use QoS overlays to provide flexible POCQ utilization. At least one POCQ entry is reserved for transactions from a remote chip accessing local memory. This avoids cross-dependency deadlocks. In one embodiment, space in the POCQ is dynamically allocated between transaction requests for data in a memory coupled to or located in a first integrated circuit and transaction requests for data in a memory coupled to or located in one or more second integrated circuits.

[0045] The snoop filter and snoop filter eviction queue 304 are shared for both locally mapped addresses and remotely mapped addresses and enable tracking of caching agents. To avoid deadlock, at least a portion of the snoop filter table is reserved for locally mapped addresses. For example, when the snoop filter table is implemented as a set-associative cache, one slot in each cache group can be reserved for locally mapped addresses. In addition, at least one entry in the snoop filter eviction queue is reserved for a locally mapped address.

[0046] Figure 4FIG4 is a diagrammatic representation of a snoop filter hierarchy 400 according to various representative embodiments. In the simple example shown, snoop filter hierarchy 400 includes snoop filters on integrated circuits 402, 404, 406, and 408. Integrated circuit 402 has directly coupled memory (denoted as Memory 0) and four local caching agents (denoted as C01, C02, C03, and C04). A single entry 410 in the snoop filter table for integrated circuit 402 is shown. In an implementation, the cache may contain multiple entries. Entry 410 includes an address tag field, a coherence state field, and a presence vector. The presence vector has one bit for each local caching agent (denoted as 01, 02, 03, and 04) and one bit for each of the three remote chips to which it is coupled (denoted as 1x, 2x, and 3x). Similarly, chip 404 has directly coupled memory (denoted as Memory 1) and four local caching agents (denoted as C11, C12, C13, and C14). The presence vector in snoop filter entry 412 has one bit for each local caching agent (denoted as 11, 12, 13, and 14) and one bit for the cache on chip 402 to which it is coupled (denoted as 0x). Chip 406 has directly coupled memory (denoted as memory 2) and four local caching agents (denoted as C21, C22, C23, and C24). The presence vector in snoop filter entry 414 has one bit for each local caching agent (denoted as 21, 22, 23, and 24) and one bit for the cache on chip 402 to which it is coupled (denoted as 0x). Chip 408 has directly coupled memory (denoted as memory 3) and two local caching agents (denoted as C31 and C32). The presence vector in snoop filter entry 416 has one bit for each local caching agent (denoted as 31 and 32) and one bit for the cache on chip 402 to which it is coupled (denoted as 0x).

[0047] When a cache line is transferred to a local caching agent, the presence vector in the entry of the local snoop filter table is updated to indicate that the cache line is present at the caching agent. When a cache line is transferred to any caching agent of a remote integrated circuit, the presence vector in the entry of the local snoop filter table is updated to indicate that the cache line is present at the caching agent of the remote integrated circuit. All caching agents of the second integrated circuit are represented as a single caching agent in the presence vector.

[0048] In the example shown, memory 0 has been accessed by caching agents C01 and C03 on chip 402 and caching agents C11 and C12 on chip 404. Figure 4Thus, bits 01 and 03 in the presence vector of chip 402 are set to indicate that the data is present at the local caching agent, and bit 1x is set to indicate that the data is present at one or more caching agents of chip 404. Additionally, bits 11 and 12 in the presence vector of chip 404 are set to indicate that the data is present at the corresponding local caching agents.

[0049] When a request for data of a cache line is received, a local caching agent is selected based on the presence vector for the cache line in the snoop filter table, and a snoop request for the cache line is sent to the selected local caching agent. In addition, when the presence vector for the cache line in the snoop filter table indicates that the cache line exists at a caching agent of any remote integrated circuit, the snoop request for the cache line is sent to the remote integrated circuit via the chip-to-chip gateway.

[0050] Figure 5 Shown with Figure 4 The same snoop filter hierarchy is shown in Figure 5 In the example shown, memory 1 has been accessed by cache agents C03 and C04 on chip 402, as shown in FIG. Figure 5 Thus, bits 03 and 04 in the presence vector for chip 402 are set to indicate that the data is present at the local caching agent, and bit 0x in the presence vector for chip 404 is set to indicate that the data is present at one or more caching agents on chip 402.

[0051] In this way, a shared snoop filter is used to track cache data for both locally mapped addresses and remotely mapped addresses. The presence vector in snoop filter entry 410 uses only 7 bits, but tracks the consistency of 14 tracking agents. When implemented in a large-scale data processing system, the hierarchical tracking system results in much smaller memory requirements than the flat tracking system.

[0052] Figure 66 is a flow chart of a coherency management method 600 according to various representative embodiments. At block 602, read access data is received at a coherency manager that is mapped to an address in local memory or remote memory. If the address does not match any entry in the coherency manager's snoop filter table, as depicted by the negative branch of decision block 604, a row is allocated in the snoop table at block 606. When the address is mapped to local memory, a cache line is requested from the local memory at block 610, as depicted by the "local" branch of decision block 608, and the flow continues to block 612. Otherwise, when the address is mapped to remote memory, a cache line is requested from the remote memory at block 614, as depicted by the "remote" branch of decision block 608, and the flow continues to block 612.

[0053] When the address matches an entry in the snoop filter table of the coherency manager, i.e., the address "hit" in the snoop, as depicted by the affirmative branch of decision block 604, a snoop request is transmitted at block 616 based on the contents of the presence vector. Specifically, if the bit corresponding to the local cache agent is set, the snoop request is transmitted to that agent. If the bit corresponding to the remote chip is set, the snoop request is transmitted to the home agent on that chip. The home agent forwards the snoop request to the local cache agent based on its own snoop filter table. At block 618, the cache line containing the requested data is forwarded from the local cache to the requestor, and the process continues to block 612.

[0054] When the cache line containing the requested data is transferred to the local chip's cache agent, as depicted by the "local" branch of decision block 612, a specific bit in the presence vector of the snoop filter table entry is set at block 620 to indicate that the cache line is present at that location. At block 622, the cache's coherency state is updated in the snoop filter table entry.

[0055] When a cache line containing requested data is transferred to a remote local caching agent, as depicted by the "remote" branch of decision block 612, a bit in the presence vector of the snoop filter table entry is set at block 624 to indicate that the cache line is present at one or more caching agents on the remote chip. All remote caching agents are represented as a single (representative) caching agent in the presence vector. Flow continues to block 622 where the cache coherency state is updated in the snoop filter table entry.

[0056] The HNS disclosed herein enables local management of cache coherence in a multi-chip data processing system when multiple caching agents access remote addresses simultaneously. It also provides scalability for multi-chip systems. Furthermore, the HNS can be used in different topologies and system configurations.

[0057] In this document, relational terms such as first and second, top and bottom, etc. may be used solely to distinguish one entity or action from another entity or action and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," "containing," "having," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may include additional elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by "comprises ... and a" does not, without more limitations, preclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0058] Reference throughout this document to "one embodiment," "certain embodiments," "an embodiment," "an implementation," "an aspect," or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0059] As used herein, the term "or" is to be interpreted as inclusive or meaning any one or any combination. Thus, "A, B, or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." An exception to this definition occurs only when a combination of elements, functions, steps, or actions are inherently mutually exclusive in some way.

[0060] As used herein, the term "configured to," when applied to an element, means that the element can be designed or constructed to perform a specified function, or has a desired structure enabling it to be reconfigured or adapted to perform that function.

[0061] Numerous details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other cases, well-known methods, procedures, and components are not described in detail to avoid obscuring the embodiments. The present disclosure should not be construed as being limited to the scope of the embodiments described herein.

[0062] Those skilled in the art will recognize that the present disclosure has been described by way of example. The present disclosure may be implemented using hardware component equivalents such as dedicated hardware and / or dedicated processors, which are equivalent to the present disclosure as described and claimed. Similarly, dedicated processors and / or dedicated hard-wired logic may be used to construct alternative equivalent embodiments of the present disclosure.

[0063] Dedicated or reconfigurable hardware components for implementing the disclosed mechanisms can be described, for example, by instructions in a hardware description language (HDL), such as VHDL, Verilog, or RTL (Register Transfer Language), or by a netlist of components and connectivity. The instructions can be at the functional level or the logic level, or a combination thereof. The instructions or netlist can be input to an automated design or manufacturing process (sometimes called high-level synthesis), which interprets the instructions and creates digital hardware that implements the described functions or logic.

[0064] The HDL instructions or netlist may be stored on a non-transitory computer-readable medium, such as an electrically erasable programmable read-only memory (EEPROM); a non-volatile memory (NVM); a mass storage device, such as a hard disk drive, a floppy disk drive, an optical disk drive; an optical storage element, a magnetic storage element, a magneto-optical storage element, flash memory, core memory, and / or other equivalent storage technologies, without departing from the present disclosure. Such alternative memories should be considered equivalents.

[0065] The various embodiments described herein are implemented using dedicated hardware, configurable hardware, or programmed processors to execute programming instructions, which are broadly described in the form of flow charts. These programming instructions can be stored on any suitable electronic storage medium or transmitted via any suitable electronic communication medium. Combinations of these elements can be used. It will be understood by those skilled in the art that the above-mentioned processes and mechanisms can be implemented with any number of variations without departing from the present disclosure. For example, the order of certain operations performed can generally be changed, additional operations can be added, or operations can be deleted without departing from the present disclosure. Such variations are conceivable and are considered equivalent.

[0066] The embodiments described herein are combinable.

[0067] A data processing apparatus has: a plurality of cache agents of a first integrated circuit; and a device coupled to the plurality of cache agents and configured to store a plurality of entries, each entry being associated with a cache line and including a presence vector indicating: for each cache agent of the first integrated circuit, when the cache line is present at the cache agent, and for each of one or more second integrated circuits, when the cache line is present at any cache agent of the second integrated circuit.

[0068] In another embodiment, the data processing apparatus, wherein the device is included in a snoop filter for filtering transaction requests for a cache line, wherein the filtering is based on the presence vector of a memory entry associated with the cache line.

[0069] In another embodiment, the data processing apparatus further includes a chip-to-chip gateway configured to be coupled between the first integrated circuit and a second integrated circuit of the one or more second integrated circuits.

[0070] In another embodiment, the data processing apparatus, wherein each entry further indicates a coherency state of the cache line and an address tag of the cache line.

[0071] In another embodiment, the data processing apparatus, wherein the caching agent of the first integrated circuit or the second integrated circuit of the one or more second integrated circuits comprises a cluster of one or more processors and one or more caches.

[0072] In another embodiment, the data processing apparatus, wherein a second integrated circuit of the one or more second integrated circuits includes or is coupled to a memory.

[0073] In another embodiment, the data processing device also has a consistency point queue, which is configured to store: transaction requests for data coupled to the first integrated circuit or in a memory located in the first integrated circuit; and transaction requests for data coupled to the one or more second integrated circuits or in a memory located in the one or more second integrated circuits.

[0074] In another embodiment, the data processing apparatus, wherein space in the coherence point queue is dynamically allocated between transaction requests for data in the memory coupled to or located in the first integrated circuit and transaction requests for data in the memory coupled to or located in a second integrated circuit among the one or more second integrated circuits.

[0075] In another embodiment, the data processing apparatus further has a cache memory configured to store: cache lines requested from a memory coupled to or located in the first integrated circuit; and cache lines requested from a memory coupled to or located in a second integrated circuit among the one or more second integrated circuits.

[0076] In another embodiment, the data processing apparatus, wherein the device is configured as: a home node for coupling to a series of data addresses in the first integrated circuit or a memory located in the first integrated circuit; and a local consistency node for coupling to a data address in a second integrated circuit in the one or more second integrated circuits or a memory located in the second integrated circuit in the one or more second integrated circuits.

[0077] In another embodiment, a data processing device has multiple local cache agents of a first chip and a coherence manager, the coherence manager being configured to manage the coherence of: local cache lines of the first chip and remote cache lines of a second chip when accessed by one or more local cache agents; and local cache lines accessed by cache agents of one or more second chips, wherein the coherence manager includes: a shared coherence point queue for transaction requests from the first chip and the second chip; a shared cache for both local cache lines and remote cache lines accessed by local cache agents; and a snoop filter table, wherein an entry in the snoop filter table includes an existence vector indicating that a remote cache line exists at a specific cache agent of the first chip, or that a local cache line exists at a specific cache agent of the first chip and at any cache agent of the second chip.

[0078] In another embodiment, the data processing apparatus further has a snoop filter configured to filter transaction requests for a cache line, wherein the filtering is based on the presence vector in the snoop filter table entry associated with the cache line.

[0079] In another embodiment, a method has the steps of: in response to transferring a cache line to a caching agent of a first integrated circuit, updating a presence vector in an entry of a snoop filter table of the first integrated circuit to indicate that the cache line is present at the caching agent; and in response to transferring the cache line to a caching agent of a second integrated circuit, updating the presence vector in the entry of the snoop filter table of the first integrated circuit to indicate that the cache line is present at the caching agent of the second integrated circuit, wherein multiple caching agents of the second integrated circuit appear as a single caching agent in the presence vector.

[0080] In another embodiment, the method further has the following steps: in response to receiving a request for data in the cache line: selecting a cache agent of the first integrated circuit based on the presence vector for the cache line in the snoop filter table; sending a snoop request for the cache line to the selected cache agent of the first integrated circuit; and when the presence vector for the cache line in the snoop filter table indicates that the cache line is present at the cache agent of the second integrated circuit, sending the snoop request for the cache line to the second integrated circuit via a chip-to-chip gateway.

[0081] In another embodiment, the method further comprises the following steps: storing transaction requests for data in a memory coupled to or located in the first integrated circuit in a consistency point queue of the first integrated circuit; and storing transaction requests for data in a memory coupled to or located in the second integrated circuit in the consistency point queue of the first integrated circuit.

[0082] In another embodiment, the method further has the following steps: dynamically allocating space in the consistency point queue between transaction requests for data coupled to the first integrated circuit or in the memory located in the first integrated circuit and transaction requests for data coupled to the second integrated circuit or in the memory located in the second integrated circuit.

[0083] In another embodiment, the method further comprises the step of reserving at least one entry in the coherence point queue for a transaction request for data in the memory coupled to or located in the first integrated circuit.

[0084] In another embodiment, the method further has the step of maintaining data consistency between a series of data addresses in a memory coupled to or located in the first integrated circuit and data addresses in a memory coupled to or located in the second integrated circuit.

[0085] In another embodiment, the method further has the step of storing in a cache of the first integrated circuit a cache line requested from a memory coupled to or located in the first integrated circuit or the second integrated circuit.

[0086] In another embodiment, the method further comprises the step of reserving space in a snoop filter table cache line mapped to a memory coupled to or located in the first integrated circuit.

[0087] The various representative embodiments described in detail herein are given by way of example and not limitation. Those skilled in the art will appreciate that various changes in the form and details of the embodiments described may be made to produce equivalent embodiments that are within the scope of the appended claims.

Claims

1. A data processing device, comprising: a plurality of caching agents of the first integrated circuit; and a device coupled to the plurality of cache agents and configured to store a plurality of entries, each entry being associated with a cache line and comprising a presence vector indicating: For each caching agent of the first integrated circuit, when the cache line was present at the caching agent, and For each second integrated circuit of the one or more second integrated circuits, when the cache line is present at any caching agent of the second integrated circuit.

2. The data processing apparatus according to claim 1 , wherein the device is included in a snoop filter, the snoop filter being configured to filter transaction requests for the cache line, wherein the filtering is based on the presence vector of a memory entry associated with the cache line. 3 . The data processing device according to claim 1 , further comprising a chip-to-chip gateway configured to be coupled between the first integrated circuit and a second integrated circuit among the one or more second integrated circuits.

4. The data processing apparatus according to claim 1 , wherein each entry further indicates: the coherency state of the cache line; and The address tag of the cache line. 5 . The data processing apparatus according to claim 1 , wherein the cache agent of the first integrated circuit or the second integrated circuit among the one or more second integrated circuits comprises a cluster of one or more processors and one or more caches. 6 . The data processing apparatus according to claim 1 , wherein a second integrated circuit of the one or more second integrated circuits includes or is coupled to a memory.

7. The data processing device according to claim 1, further comprising: A consistency point queue, configured to store: a transaction request for data in a memory coupled to or located in the first integrated circuit; and A transaction request is for data in a memory coupled to or located in the one or more second integrated circuits.

8. The data processing apparatus of claim 7 , wherein space in the coherence point queue is dynamically allocated between transaction requests for data in the memory coupled to or located in the first integrated circuit and transaction requests for data in the memory coupled to or located in a second integrated circuit among the one or more second integrated circuits.

9. The data processing apparatus according to claim 1 , further comprising a cache memory configured to store: a cache line requested from a memory coupled to or located in the first integrated circuit; and A cache line is requested from a memory coupled to or located in a second integrated circuit of the one or more second integrated circuits.

10. The data processing apparatus according to claim 1, wherein the device is configured as: a home node for coupling to a range of data addresses in the first integrated circuit or a memory located in the first integrated circuit; and A local coherence node is configured to be coupled to a data address in a second integrated circuit of the one or more second integrated circuits or in a memory located in the second integrated circuit of the one or more second integrated circuits.

11. A data processing device, comprising: a plurality of local caching agents of the first chip; and A consistency manager configured to manage the consistency of: a local cache line of the first chip and a remote cache line of the second chip when accessed by one or more local cache agents; and a local cache line accessed by one or more cache agents of the second chip; The consistency manager includes: a shared coherence point queue for transaction requests from the first chip and the second chip; a shared cache for both local cache lines and remote cache lines accessed by the local caching agent; and a snoop filter table, when an entry in the snoop filter table includes a presence vector, the presence vector indicating: The remote cache line exists at a specific cache agent of the first chip, or A local cache line exists at a specific cache agent of the first chip and at any cache agent of the second chip.

12. The data processing device according to claim 11, further comprising: A snoop filter is configured to filter transaction requests for a cache line, wherein the filtering is based on the presence vector in the snoop filter table entry associated with the cache line.

13. A method comprising: responsive to transferring a cache line to a caching agent of a first integrated circuit, updating a presence vector in an entry of a snoop filter table of the first integrated circuit to indicate that the cache line is present at the caching agent; as well as In response to transferring the cache line to a caching agent of a second integrated circuit, updating the presence vector in the entry of the snoop filter table of the first integrated circuit to indicate that the cache line is present at the caching agent of the second integrated circuit, wherein the plurality of caching agents of the second integrated circuit appear as a single caching agent in the presence vector.

14. The method according to claim 13, further comprising: In response to receiving a request for data in the cache line: selecting a caching agent of the first integrated circuit based on the presence vector for the cache line in the snoop filter table; sending a snoop request for the cache line to a selected caching agent of the first integrated circuit; as well as When the presence vector for the cache line in the snoop filter table indicates that the cache line is present at a caching agent of the second integrated circuit, a snoop request for the cache line is sent to the second integrated circuit via a chip-to-chip gateway.

15. The method according to claim 13, further comprising: storing, in a coherence point queue of the first integrated circuit, a transaction request for data in a memory coupled to or located in the first integrated circuit; as well as Transaction requests for data in a memory coupled to or located in the second integrated circuit are stored in the coherence point queue of the first integrated circuit.

16. The method according to claim 15, further comprising: Space in the coherence point queue is dynamically allocated between transaction requests for data in the memory coupled to or located in the first integrated circuit and transaction requests for data in the memory coupled to or located in the second integrated circuit.

17. The method according to claim 16, further comprising: At least one entry in the coherence point queue is reserved for a transaction request for data in the memory coupled to or located in the first integrated circuit.

18. The method according to claim 15, further comprising: Data consistency is maintained between a series of data addresses in a memory coupled to or located in the first integrated circuit and data addresses in a memory coupled to or located in the second integrated circuit.

19. The method according to claim 13, further comprising: A cache line requested from a memory coupled to or located in the first integrated circuit or the second integrated circuit is stored in a cache of the first integrated circuit.

20. The method according to claim 13, further comprising: Space is reserved in a snoop filter table cache line mapped to a memory coupled to or located in the first integrated circuit.

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