Electronic device manufacturing using region selective deposition

Abstract

A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; and selectively forming at least one supplemental dielectric layer using at least one catalyst layer. The at least one catalyst layer causes formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to electronic device fabrication. Specifically, embodiments of the present disclosure relate to electronic device fabrication using area selective deposition. Background Art

[0002] Electronic device manufacturing equipment may include multiple chambers, such as processing chambers and load lock chambers. Such electronic device manufacturing equipment may employ robotic equipment in a transfer chamber, configured to transport substrates between the multiple chambers. In some cases, multiple substrates are transported together. Processing chambers in electronic device manufacturing equipment may be used to perform one or more processes on substrates, such as deposition and etching processes. For many processes, gases are flowed into the processing chambers.

[0003] Electronic devices, such as semiconductor devices, are manufactured by performing a series of operations that may include deposition, oxidation, photolithography, ion implantation, etching, and the like to form a number of patterned layers. It is often beneficial to align features between layers. In some cases, misalignment of features (e.g., due to photolithography and / or patterning limitations) can result in shorts and / or capacitive coupling between, for example, a via and an underlying conductive line. Such shorts and / or capacitive coupling can impair the functionality of the manufactured electronic device. Summary of the Invention

[0004] According to one embodiment, a method is provided. The method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer; selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; and selectively forming at least one supplementary dielectric layer using the at least one catalyst layer. The at least one catalyst layer causes formation of the at least one supplementary dielectric layer, and the at least one supplementary dielectric layer includes a dielectric material having a dielectric constant less than or equal to approximately 4.

[0005] According to one embodiment, a system is provided. The system includes at least one chamber operatively coupled to at least one storage device. The at least one chamber is configured to: selectively form at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively form at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; and selectively form at least one supplementary dielectric layer using the at least one catalyst layer. The at least one catalyst layer causes formation of the at least one supplementary dielectric layer, and the at least one supplementary dielectric layer includes a dielectric material having a dielectric constant less than or equal to approximately 4. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements. It should be noted that in the present disclosure, different references to "an" or "one" embodiment are not necessarily to the same embodiment, and such references mean at least one.

[0007] Figures 1A to 1F is a cross-section illustrating an example method of fabricating an electronic device using area-selective deposition, according to some embodiments.

[0008] Figure 2 is a flow chart of an example method for fabricating an electronic device using area-selective deposition, according to some embodiments.

[0009] Figures 3 to 4I is a diagram of an example method for selectively forming at least one supplemental dielectric layer during fabrication of an electronic device, according to some embodiments.

[0010] Figure 5 is a block diagram of an example electronic device processing system that may be used to fabricate electronic devices using area-selective deposition, in accordance with some embodiments. DETAILED DESCRIPTION

[0011] Embodiments described herein relate to electronic device fabrication using area selective deposition. The electronic device may include a dielectric material and a conductive layer. For example, the electronic device may include a dielectric layer and several conductive layers disposed within (e.g., within) the dielectric layer. More specifically, the electronic device may include several metallization levels, wherein each metallization level includes a corresponding set of conductive layers, and each pair of metallization levels is separated by a corresponding dielectric layer (e.g., an interlayer dielectric (ILD) layer). Each conductive layer may be formed within a corresponding trench.

[0012] For example, the conductive layer may be a via. A via refers to an electrical connection or contact between conductive lines within an electronic device. Each via may serve as a corresponding interconnection between at least two metallization levels. For example, a via is a via that is exposed at both ends of a device (i.e., a via is formed through each metallization level from the top of the device to the bottom of the device). As another example, a buried via is a via that is not exposed at both ends of a device (i.e., a buried via serves as an interconnection between internal metallization levels). As yet another example, a blind via is a via that is exposed at a single end of a device.

[0013] Electronic device processing techniques can involve performing patterning (e.g., photolithography). For example, patterning can include multiple and repeated deposition and etching processes using a photomask ("mask") and a resist film, such as wet etching or dry etching (e.g., plasma etching). Illustratively, the conductors and vias can be formed using a suitable patterning process. For example, the conductors and vias can be formed using a single damascene process, during which the conductors and vias are formed sequentially. As another example, the conductors and vias can be formed using a dual damascene process, during which the conductors and vias can be formed simultaneously (e.g., by simultaneously filling both the via and the trench with a conductive material). The conductors and vias can include any suitable conductive material (e.g., metal).

[0014] In one example, assume that a device includes a first metallization level that includes a first via disposed in an ILD layer. To pattern a second via of a second metallization level above the first metallization level, a dielectric material comprising the second ILD layer can be formed across the first metallization level using any suitable deposition process. The dielectric material can further include a dielectric cap that can be deposited across the first metallization level. The second ILD layer can be etched to form a trench. The dielectric cap can serve as an etch stop layer to define the bottom of the trench. The via opening can include a trench. For example, a portion of the dielectric cap can be removed using an etching process (e.g., an anisotropic etching process) to expose the first via. A conductive material can be formed within the via opening to form a second via.

[0015] If the second via has substantially correct edge placement relative to the first via (e.g., the via is centered relative to the first via), the second via can be considered an aligned via. However, as electronic device dimensions shrink (e.g., as transistor dimensions decrease), process variations may be introduced during lithography / patterning (e.g., nanoscale patterning). One example of process variation is mask misalignment between the mask and the patterned substrate. During exposure to light, mask misalignment may result in an edge placement error equal to the distance between the target position of the feature edge and the actual position of the feature edge. Edge placement errors may result in detrimental effects that may degrade device performance, such as shorts, increased resistance, capacitive coupling, etc. In the example above, mask misalignment during the initial patterning of the trench within the second ILD layer may result in misalignment of the second via relative to the first via. In particular, edge placement errors relative to the edge of the second via may result. Consequently, during formation of the via, the edge of the second via may be formed in an area between its corresponding conductive line and another adjacent conductive line on a portion of the dielectric layer.

[0016] Such via misalignment (i.e., edge placement error) can result in a short circuit or capacitive coupling between the first and second vias, which can be a function of the horizontal spacing between the first and second vias (e.g., the distance between the upper surface of the first via and the lower surface of the second via). As transistor dimensions become smaller (e.g., on a nanometer (nm) scale), the effects of via misalignment can become more pronounced. Thus, as transistor device dimensions further shrink, it is important to maintain a minimum amount of spacing to prevent short circuits or capacitive coupling due to process variations that result in via misalignment.

[0017] In some embodiments, a fully self-aligned via (FSAV) process can be employed to address via misalignment (i.e., edge placement errors). One example of an FSAV process employs a recessing method. During the recessing method, after a trench within a first ILD layer is filled with a conductive material (e.g., metal) to form, for example, a first via, the conductive material can be recessed to a specific depth within its corresponding trench using an etching process. A second via can then be formed such that the upper surface of the first via is located below the upper surface of the first ILD layer. Therefore, if the second via is misaligned relative to the first via, the second via can have an edge formed on the dielectric layer that is located a certain distance above the upper surface of the first via. This can result in the upper surface of the first via and the lower surface of the second via being separated by a diagonal spacing. The diagonal spacing is a function of the horizontal spacing described above and the vertical distance between the upper surface of the first via and the lower surface of the second via. That is, the diagonal spacing has a greater length than the horizontal spacing, which can help prevent shorting or capacitive coupling.

[0018] However, the recessing approach has several drawbacks. For example, it can exhibit poor uniformity across the wafer and across different pitch sizes, high wire surface roughness, and material degradation. Furthermore, etching some conductive materials to achieve the recess, such as for the first via, can be difficult (e.g., copper etching can be challenging).

[0019] Another example of a method that can be used to address process variations (such as via misalignment) is an area-selective deposition method. More specifically, the selective material deposition path can include a dielectric-on-dielectric (DoD) selective deposition path. For example, after the trench in the first ILD layer is filled with a conductive material to form, for example, a first via as described above, a supplemental dielectric layer can be selectively deposited on the exposed upper surface of the first ILD layer in preference to the first conductive material. Selectivity can be defined as, for example, the ratio of the film thickness (e.g., the thickness of the supplemental dielectric layer) on the target surface (e.g., the first ILD layer) to the film thickness on the non-target surface (e.g., the conductive material). Other definitions of selectivity can be used. The supplemental dielectric layer can be formed to a height that is similar in magnitude to the depth achieved during the recess method described above. Similar to the recess method, if the second via is formed to be misaligned relative to the first via, the second via can have an edge formed on the supplemental dielectric layer that is located a certain distance above the upper surface of the first via. Similar to the recess method, the area-selective deposition method can result in the upper surface of the first via and the lower surface of the second via being separated by a diagonal spacing having a length greater than the horizontal spacing, which can help prevent shorting or capacitive coupling.

[0020] It may be beneficial to form a supplementary dielectric layer having a relatively low dielectric constant (i.e., a low-k dielectric material). For example, the low-k dielectric material may have a dielectric constant of less than or equal to about 4. However, area-selective deposition methods are generally limited to forming a supplementary dielectric layer having a relatively high dielectric constant (i.e., a high-k dielectric material). Examples of such high-k dielectric materials include zinc oxide (ZnO), aluminum oxide (Al2O3), and the like. Furthermore, achieving selectivity of dielectric materials relative to conductive materials (e.g., metals) greater than 10 nanometers (nm) using conventional techniques is challenging.

[0021] To address these and other shortcomings, embodiments described herein can be used to manufacture electronic devices using areoselective deposition. Embodiments described herein can be used to form electronic devices that include at least one supplemental dielectric layer to address misalignment (e.g., via misalignment). More specifically, at least one supplemental dielectric layer can be formed using an areoselective dielectric-on-dielectric (DoD) approach. In some embodiments, areoselective deposition enables FSAV leakage control with respect to vias formed during the FSAV process.

[0022] In an example, forming an electronic device may include obtaining a base structure including at least one conductive layer disposed in (e.g., within) a first ILD layer. For example, the at least one conductive layer may include a first via. The at least one conductive layer and the first ILD layer may form at least a portion of a first metallization level of the device. Examples of suitable conductive materials that may be used to form the at least one conductive layer include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), and the like. x )wait.

[0023] Forming the electronic device may further include selectively forming at least one supplementary dielectric layer on the first ILD layer. More specifically, each supplementary dielectric layer may be formed on the first ILD layer in preference to at least one conductive layer of the base structure (i.e., DoD selective deposition). In some embodiments, selectively forming at least one supplementary dielectric layer includes: selectively forming a passivation layer on the first conductive material; selectively forming at least one catalyst layer on the first ILD layer; and selectively forming at least one supplementary dielectric layer using the at least one catalyst layer. More specifically, each catalyst layer may be formed using one or more catalyst layer precursors, and each passivation layer may include a material that can prevent each catalyst layer from being formed using the one or more catalyst layer precursors. In some embodiments, each supplementary dielectric layer includes a dielectric material with a low dielectric constant. For example, each supplementary dielectric layer may include a dielectric material having a dielectric constant less than or equal to about 4.

[0024] Each catalyst layer is used to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can be used to achieve a suitably high growth per cycle (GPC) of the deposition process for forming each supplementary dielectric layer (e.g., catalytic growth). Each catalyst layer may include suitable chemicals to cause the formation of each supplementary dielectric layer. For example, each catalyst layer may include a strong reducing agent, a metal hydride, an alkyl metal, an aryl metal, a silane, etc. Each catalyst layer may be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer may be an aluminum (Al)-catalyst layer, a titanium (Ti)-catalyst layer, a hafnium (Hf)-catalyst layer, a zirconium (Zr)-catalyst layer, a tantalum (Ta)-catalyst layer, a boron (B)-catalyst layer, a germanium (Ge)-catalyst layer, a tin (Sn)-catalyst layer, a gallium (Ga)-catalyst layer, an indium (In)-catalyst layer, etc. As an illustrative example, the Al-catalyst layer may include Al 2 O 3 and the one or more catalyst layer precursors may include one or more of trimethylaluminum (TMA), tri(neopentyl)aluminum, and the like.

[0025] Each catalyst layer and each supplemental dielectric layer can be formed by performing any suitable number of cycles of the respective deposition processes to form each supplemental dielectric layer having a target thickness. In some embodiments, the deposition process is an atomic layer deposition (ALD) process. In some embodiments, the deposition process is a thermal ALD process. A thermal ALD process is an ALD process performed using thermal energy. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm.

[0026] In some embodiments, selectively forming each supplemental dielectric layer includes regenerating each passivation layer after selectively forming each catalyst layer, and selectively forming each supplemental dielectric layer using each catalyst layer after regenerating each passivation layer. In some embodiments, selectively forming each supplemental dielectric layer includes regenerating each passivation layer after selectively forming each supplemental dielectric layer on each catalyst layer. Each passivation layer may be regenerated to further improve selectivity of the catalyst layer and / or the supplemental dielectric layer.

[0027] Forming the electronic device may further include forming a second ILD layer on the base structure and each supplemental dielectric layer, forming at least one opening in the second ILD layer, and forming at least one conductive layer in the at least one opening. The at least one conductive layer and the second ILD layer formed in the at least one opening may form at least a portion of the second metallization level of the electronic device. For example, the at least one conductive layer formed in the at least one opening may include a second via formed to contact the first via. In the event that the second via is poorly aligned with respect to the first via, the corresponding supplemental dielectric layer may increase the diagonal distance between the first via and the second via. Thus, the supplemental dielectric layer may reduce or eliminate the effects of short circuits or capacitive coupling between the first via and the second via. Additional device processing steps may be performed to complete the formation of the electronic device. Further details regarding the formation of the electronic device (including the selective formation of each supplemental dielectric layer) will be referred to below. Figures 1A to 5 describe.

[0028] Figures 1A to 1F is a cross-section illustrating an example method of forming an electronic device ("device") 100 using area selective deposition, according to some embodiments. Figure 1AAs shown, a base structure 102 is obtained. The base structure 102 includes an ILD layer 110-1 and a conductive layer including a conductive layer 120 disposed in (e.g., within) the ILD layer 110-1. For example, obtaining the base structure 102 may include forming the base structure 102. Forming the base structure 102 may include forming a plurality of trenches in the ILD layer 110-1, and forming a conductive material in corresponding trenches of the plurality of trenches to form a conductive layer including the conductive layer 120. The ILD layer 110-1 and the conductive layer including the conductive layer 120 may define a first metallization level of the device 100. Although Figure 1A

[0026] Not shown, the base structure 102 may further include a substrate layer (e.g., a semiconductor wafer) as the initial layer of the device 100, and the first metallization level may be formed on the substrate layer. For example, the substrate layer may be a Si substrate layer. In some embodiments, the first metallization level is formed directly on the substrate layer. In some embodiments, one or more interposers (e.g., one or more metallization levels) are disposed between the first metallization level and the substrate layer.

[0029] Although not shown, base structure 102 may include one or more additional layers, such that ILD layer 110-1 and conductive layers including conductive layer 120 are disposed on the one or more additional layers. For example, device 100 may further include at least a substrate layer (e.g., a silicon (Si) substrate) (not shown) as an initial layer of the device.

[0030] The ILD layer 110-1 may include any suitable dielectric material. In some embodiments, the ILD layer 110-1 may include an oxide (e.g., a metal oxide). Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), etc. The conductive layer including the conductive layer 120 may include any suitable conductive material (e.g., a metal). In some embodiments, the conductive layer includes a conductive material that includes a transition metal. Examples of suitable conductive materials that can be used to form the conductive layer including the conductive layer 120 include Cu, W, Co, Mo, Ru, TiN, TaN, MoN, etc. x wait.

[0031] like Figure 1BAs shown, the passivation layers, including passivation layer 125, are selectively formed on corresponding ones of the conductive layers. For example, passivation layer 125 may be preferentially adsorbed onto the upper surface of conductive layer 120 over the upper surface of ILD layer 110-1. The passivation layers, including passivation layer 125, may include a material selected to enable selective formation of a catalyst layer and / or a supplementary dielectric layer on ILD layer 110-1 during a subsequent deposition process. The catalyst layer may be used to induce the formation (e.g., catalyze growth) of the supplementary dielectric layer, as described in further detail below. More specifically, the passivation layers, including passivation layer 125, may include a material selected to prevent (e.g., block) adsorption of a catalyst layer precursor during a deposition process for forming the catalyst layer and / or to prevent adsorption of a supplementary dielectric layer precursor during a deposition process for forming the supplementary dielectric layer (i.e., prevent the deposition precursor from nucleating on the first conductive material). In some embodiments, and as described in further detail below, the deposition process for forming the supplementary dielectric layer is an atomic layer deposition (ALD) process. For example, the ALD process may be a thermal ALD process. Thus, the passivation layer including the passivation layer 125 may prevent (e.g., block) the formation of a catalyst layer and / or a supplementary dielectric layer on the conductive layer including the conductive layer 125. Further details regarding the selective formation of the passivation layer including the passivation layer 125 will be referred to below. Figures 2 to 5 describe.

[0032] like Figure 1C As shown, after selectively forming the passivation layer including the passivation layer 125 (and optional pre-cleaning), the catalyst layer including the catalyst layer 130 is selectively formed on the ILD layer 110-1. The passivation layer including the passivation layer 125 prevents (e.g., blocks) the adsorption of catalyst precursors used to form the catalyst layer including the catalyst layer 130. Further details on the selective formation of the catalyst layer including the catalyst layer 130 will be referred to below. Figures 2 to 5 describe.

[0033] like Figure 1D As shown, a supplementary dielectric layer including dielectric layer 140 is selectively formed on the catalyst layer including catalyst layer 130. Selectively forming the supplementary dielectric layer including dielectric layer 140 may include depositing a dielectric material using a deposition process. In some embodiments, the deposition process is an ALD process. For example, the ALD process may be a thermal ALD process. Other deposition processes may also be performed to produce the supplementary dielectric layer including dielectric layer 140. As described above, the catalyst layer including catalyst layer 130 is used to induce the formation (e.g., catalytic growth) of the supplementary dielectric layer including dielectric layer 140.

[0034] The supplementary dielectric layer comprising dielectric layer 140 may include any suitable dielectric material. In some embodiments, the supplementary dielectric layer comprising dielectric layer 140 may include a dielectric material having a low dielectric constant. For example, the supplementary dielectric layer comprising dielectric layer 140 may include a dielectric material having a dielectric constant less than or equal to about 4. In some embodiments, the supplementary dielectric layer comprising dielectric layer 140 includes a silicate (i.e., a material including silicon (Si) and oxygen (O)). Examples of suitable dielectric materials that may be included in the supplementary dielectric layer comprising dielectric layer 140 include SiO x , SiOC, etc. The supplementary dielectric layer including the dielectric layer 140 can be formed to have a target thickness. In some embodiments, the thickness of the supplementary dielectric layer including the dielectric layer 140 is between about 5 nm and about 30 nm. In some embodiments, the thickness of the supplementary dielectric layer including the dielectric layer 140 is between about 10 nm and about 20 nm. Further details on the selective formation of the supplementary dielectric layer including the dielectric layer 140 will be referred to below. Figures 2 to 5 describe.

[0035] like Figure 1E As shown, after selectively depositing a supplementary dielectric layer including dielectric layer 140 on ILD layer 110-1, ILD layer 110-2 may be formed. ILD layer 110-2 may include any suitable dielectric material. In some embodiments, ILD layer 110-2 includes oxide. In some embodiments, ILD 110-2 includes nitride. Examples of suitable dielectric materials include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, ILD layer 110-2 includes the same dielectric material as ILD layer 110-1. In some embodiments, ILD layer 110-2 includes a different dielectric material from ILD layer 110-1. Further details on forming ILD layer 110-2 will be referred to below. Figure 2 describe.

[0036] like Figure 1F As shown, conductive layer 150 is formed to contact conductive layer 120. Forming conductive layer 150 may include forming an opening (e.g., a via opening) in ILD layer 110-2, and forming a conductive material in the opening to form conductive layer 150. Conductive layer 150 may include any suitable conductive material (e.g., a metal). In some embodiments, conductive layer 150 includes a transition metal. Examples of suitable conductive materials that can be used to form conductive material 150 include Cu, W, Co, Mo, Ru, etc. In some embodiments, conductive layer 150 may include the same material as conductive layer 120. In some embodiments, conductive material 150 may include a different material than conductive layer 120. Further details on forming conductive layer 150 will be described below with reference to Figure 2 describe.

[0037] In this example, conductive layer 150 is directed to a second via that is misaligned with respect to the first via of conductive layer 120. More specifically, the second via has an edge disposed on dielectric layer 140 that is off-center with respect to the first via. A diagonal distance exists between the first via and the second via. The diagonal distance has a greater length than a horizontal distance that would define the separation between the first via and the second via in the absence of dielectric layer 140. Thus, forming dielectric layer 140 can achieve FSAV leakage control to improve the performance of device 100 by reducing shorting or capacitive coupling between the first via and the second via. Further details regarding the fabrication of device 100 will now be referred to below. Figure 2 describe.

[0038] Figure 2 An example method 200 for manufacturing an electronic device using area selective deposition according to some embodiments is depicted. The method 200 can be performed within an electronic device processing system. More specifically, the method 200 can be performed within one or more processing chambers of the electronic device processing system. The example electronic device processing system will be referred to below. Figure 5 describe.

[0039] In step 210, a base structure including at least one conductive layer disposed on a first ILD layer is obtained. In some embodiments, the at least one conductive layer of the base structure is disposed within (e.g., within) the first ILD layer. The at least one conductive layer includes a first conductive layer. For example, the first conductive layer may be a via. The first conductive material and the first ILD layer may together form at least a portion of a first metallization level of the electronic device. The first metallization level may be formed on a substrate layer as an initial layer of the base structure (e.g., a Si substrate layer). In some embodiments, the first metallization level is formed directly on the substrate layer. In some embodiments, one or more interposers are disposed between the substrate layer and the first metallization level.

[0040] In some embodiments, obtaining the base structure includes receiving a preformed base structure. In some embodiments, obtaining the base structure includes forming at least a portion of the base structure. For example, forming at least a portion of the base structure may include at least one of forming one or more interposer layers on the substrate layer, forming a first ILD layer on the substrate layer (e.g., directly on the substrate layer or on one or more interposer layers), forming at least one opening (e.g., at least one trench) in the first ILD layer, or forming a conductive material in the at least one trench to form at least one conductive layer including the first conductive layer.

[0041] The first ILD layer may include any suitable dielectric material. In some embodiments, the first ILD layer includes a first silicate. For example, the first ILD layer may include SiO2. The first conductive material may include any suitable conductive material (e.g., a metal). In some embodiments, at least one conductive layer of the base structure includes a transition metal. Examples of suitable conductive materials that can be used to form at least one conductive layer of the base structure include Cu, W, Co, Mo, Ru, TiN, TaN, MoN, etc. x wait.

[0042] At step 220, at least one supplemental dielectric layer is selectively formed on the first ILD layer. In some embodiments, the at least one supplemental dielectric layer comprises a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant less than or equal to about 4. In some embodiments, the first ILD layer comprises a first silicate (e.g., SiO2) and the supplemental dielectric layer comprises a second silicate. For example, the first silicate may comprise silicon oxide (SiO X ), and the second silicate may be a low dielectric constant dielectric silicate (i.e., a silicate having a dielectric constant less than or equal to about 4). Examples of low dielectric constant dielectric silicates include SiOx, silicon oxycarbide (SiOC), and the like. The at least one supplementary dielectric layer may be formed to have a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, selectively forming the at least one supplementary dielectric layer includes employing at least one catalyst layer to induce the formation of the at least one supplementary dielectric layer. In some embodiments, selectively forming the at least one supplementary dielectric layer includes selectively forming at least one passivation layer on at least one conductive layer of the base structure, selectively forming at least one catalyst layer on the ILD layer of the base structure, and selectively forming at least one supplementary dielectric layer on the at least one catalyst layer. More specifically, the at least one passivation layer may include a material selected to prevent (e.g., block) adsorption of a deposition precursor during the formation of the at least one catalyst layer and / or adsorption of a deposition precursor during the formation of the at least one supplementary dielectric layer.

[0043] Each catalyst layer may include suitable chemicals to cause the formation of each supplementary dielectric layer. For example, each catalyst layer may include a strong reducing agent, a metal hydride, an alkyl metal, an aryl metal, a silane, etc. Each catalyst layer may be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer may be an Al-catalyst layer, a Ti-catalyst layer, an Hf-catalyst layer, a Zr-catalyst layer, a Ta-catalyst layer, a B-catalyst layer, a Ge-catalyst layer, a Sn-catalyst layer, a Ga-catalyst layer, an In-catalyst layer, etc. As an illustrative example, the Al-catalyst layer may include Al2O3. Further details on the selective formation of at least one supplementary dielectric layer on the first ILD layer will be referred to below. Figures 3 to 5 describe.

[0044] In step 230, a second ILD layer is formed on the base structure and the at least one supplemental dielectric layer. The second ILD layer may include any suitable dielectric material. In some embodiments, the second ILD layer may include an oxide. In some embodiments, the second ILD layer may include a nitride. Examples of suitable dielectric materials that can be used to form the second ILD layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. In some embodiments, the second ILD layer includes the same dielectric material as the first ILD layer. In some embodiments, the second ILD layer includes a dielectric material different from the first ILD layer.

[0045] In step 240, at least one opening is formed in the second ILD layer. More specifically, the at least one opening includes an upper surface of the second ILD layer to expose the upper surface of the first conductive material. Forming the at least one opening may include forming at least one trench in the second ILD layer. For example, forming the at least one trench may include performing an etching process. If the base structure does not include a dielectric cap, and the dielectric cap includes an etch stop layer formed on the first ILD layer, the at least one trench may correspond to the at least one opening. Alternatively, if the base structure further includes a dielectric cap disposed on the first ILD layer, the trench formed using the etching process may terminate at the etch stop layer. Therefore, forming the at least one opening may further include performing an additional etching process (e.g., an anisotropic etching process) to remove the dielectric cap. In some embodiments, the at least one opening is a via opening. In some embodiments, the at least one opening is formed by drilling a hole through the first ILD layer.

[0046] In step 250, at least one conductive layer is formed within the at least one opening. More specifically, the at least one conductive layer formed within the at least one opening may include a second conductive layer formed to contact the first conductive layer. In some embodiments, the second conductive layer is a second via. The at least one conductive layer formed within the at least one opening may include any suitable conductive material (e.g., a metal). Examples of suitable conductive materials that may be used to form the at least one conductive layer within the at least one opening include Cu, W, Co, Mo, Ru, TiN, TaN, MoN, etc. x In some embodiments, the at least one conductive layer formed within the at least one opening comprises the same material as the at least one conductive layer disposed on the first ILD layer. In some embodiments, the at least one conductive layer formed within the at least one opening comprises a different material than the at least one conductive layer disposed on the first ILD layer. Further details regarding steps 210-250 are provided above with reference to Figures 1A to 1F Described and now referred to below Figures 3 to 5 describe.

[0047] Figures 3 to 4I is a diagram illustrating example methods 300-400I for selectively forming at least one supplemental dielectric layer during fabrication of an electronic device, according to some embodiments. For example, one or more of the methods 300-400I may be used to implement Figure 2 Step 220 of method 200. One or more of methods 300-400I may be performed within an electronic device processing system. More specifically, one or more of methods 300-400I may be performed within one or more processing chambers of an electronic device processing system. An example electronic device processing system will be described below with reference to Figure 5 describe.

[0048] Figure 3 is a flow chart illustrating an example method 300 for selectively forming at least one supplemental dielectric layer during the manufacture of an electronic device. At step 310, at least one passivation layer is selectively formed. More specifically, the at least one passivation layer can be selectively formed on at least one conductive layer of the base structure by performing a passivation process prior to the ILD layer of the base structure. For example, the at least one conductive layer of the base structure can be formed within the ILD layer of the base structure. In some embodiments, the at least one conductive layer of the base structure includes at least one via. In some embodiments, the at least one passivation layer is formed as a self-assembled monolayer (SAM). A SAM is a material layer having a monomolecular thickness formed by surface adsorption (e.g., chemical adsorption) during a deposition process.

[0049] Performing the passivation process may include exposing the base structure to at least one passivating agent (i.e., a passivating agent). The at least one passivating agent is selected to selectively adsorb to at least one conductive layer of the base structure in preference to the ILD layer of the base structure. In some embodiments, the at least one passivating agent includes a vapor-phase passivating agent. For example, the at least one passivating layer may be formed as a SAM grown in a vapor phase by the at least one vapor-phase passivating agent. Examples of vapor-phase passivating agents that can be used to form the at least one passivating layer include amines (e.g., N-ethylethylenediamine, N,N'-diethylethylenediamine, N,N,N',N'-tetraethylethylenediamine, and N,N,N',N'-tetramethylethylenediamine), silanes (e.g., dodecylsilane and N-octylsilane), alkynes (e.g., 5-decyne), alcohols (e.g., 2,5-dimethyl-3-hexyne-2,5-diol), and the like.

[0050] The vapor phase passivation process for forming at least one passivation layer can be performed using any suitable process parameters. In some embodiments, the vapor phase passivation process can be performed at a pressure between about 1 Torr and about 10 Torr. In some embodiments, the dose time per cycle can be between about 0.1 s and about 2 s. In some embodiments, the number of cycles can be in the range of about 500 cycles to about 1,500 cycles.

[0051] In some embodiments, at least one passivating agent comprises a solution phase passivating agent. For example, at least one passivating layer can be formed from at least one solution phase passivating agent as a SAM grown in the solution phase. In some embodiments, at least one solution phase passivating agent is an organophosphorus compound (i.e., a phosphorus-containing organic compound). For example, the passivating layer can comprise a monolayer of an organophosphorus compound. In some embodiments, the organophosphorus compound is an organophosphonic acid. For example, the passivating layer can comprise a monolayer of an organophosphonic acid. An example of an organophosphonic acid is octadecylphosphonic acid (ODPA). ODPA can be formed by C 18 H 39 Molecular / empirical formula of O3P and CH3(CH2) 16 The solution-phase passivating agent can be represented by the compressed structural formula of CH2P(O)(OH2). For example, the solution-phase passivating agent can include a 1:10 millimolar (mM) solution of ODPA in toluene (C7H8). The substrate structure can be immersed in the solution for a predetermined period of time. For example, the period of time can be approximately 48 hours. A post-cleaning process (e.g., decontamination) can be performed after the immersion.

[0052] The passivation process for selectively forming at least one passivation layer on at least one conductive layer of the substrate structure can be performed using any suitable process parameters. Examples of process parameters for performing the passivation process include temperature, passivation agent exposure time (e.g., time of exposure to the passivation agent), pressure, etc. In some embodiments, the passivation process is performed at a temperature between about 100°C and about 350°C. In some embodiments, the passivation process is performed at a temperature between about 250°C and about 350°C. At sufficiently high temperatures, passivation degradation may occur (e.g., a temperature exceeding 350°C). Therefore, the passivation process can be performed at a temperature below the threshold to maintain the quality of the passivation layer (e.g., less than or equal to about 350°C). In some embodiments, the passivation process is performed at a pressure between about 100 mTorr and about 10 mTorr. In some embodiments, the passivation process is performed at a pressure between about 500 mTorr and about 10 mTorr. In some embodiments, the passivation process is performed at a pressure between about 750 mTorr and about 10 mTorr. In some embodiments, the passivation agent exposure time is less than or equal to about 60 minutes. In some embodiments, the passivation agent exposure time is less than or equal to about 50 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 40 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 30 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 20 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 10 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 5 minutes. In some embodiments, the passivating agent exposure time is less than or equal to about 1 minute.

[0053] In some embodiments, before selectively forming at least one passivation layer (e.g., before exposing the substrate structure to at least one passivating agent), an optional pre-cleaning process is performed. The pre-cleaning process can improve the selectivity of the supplementary dielectric layer to be formed on the first ILD layer and / or reduce the selectivity of the supplementary dielectric layer to be formed on the first conductive material. The pre-cleaning process can include surface cleaning to remove native oxide on the surface of at least one conductive layer. The pre-cleaning process can further remove contaminants from the surface of at least one conductive layer. The pre-cleaning process can further reduce defect growth on at least one conductive layer. For example, the pre-cleaning process can include a thermal EtOH treatment, a hydrogen radical treatment, or the like.

[0054] In step 320, at least one catalyst layer is selectively formed. More specifically, each catalyst layer is selectively formed on the ILD layer of the base structure in preference to each conductive layer of the base structure. Each passivation layer prevents each catalyst layer from being formed on each conductive layer. Each catalyst layer may include suitable chemicals to induce the formation of each supplementary dielectric layer. For example, each catalyst layer may include a strong reducing agent, a metal hydride, an alkyl metal, an aryl metal, a silane, etc. Each catalyst layer may be formed using one or more catalyst layer precursors. In some embodiments, each catalyst layer is a metal catalyst layer. In some embodiments, each catalyst layer is a metalloid catalyst layer. For example, the catalyst layer may be an Al-catalyst layer, a Ti-catalyst layer, an Hf-catalyst layer, a Zr-catalyst layer, a Ta-catalyst layer, a B-catalyst layer, a Ge-catalyst layer, a Sn-catalyst layer, a Ga-catalyst layer, an In-catalyst layer, etc. As an illustrative example, the Al-catalyst layer may include Al2O3.

[0055] In some embodiments, at least one catalyst layer includes at least one catalyst layer monolayer. In some embodiments, at least one catalyst layer includes at least one catalyst layer membrane. For example, the catalyst layer monolayer can be an Al-catalyst layer, and the catalyst layer membrane can be an Al-containing membrane. In some embodiments, the Al-containing membrane includes Al2O3. For example, at least one catalyst layer precursor can include at least one of an Al-precursor or an O-precursor. Examples of Al-precursors include trimethylaluminum (TMA), tri(neopentyl)aluminum (TNpAl), etc. Examples of O-precursors include water (H2O), ozone (O3), hydrogen peroxide (H2O2), etc.

[0056] The catalyst layer formation process can be performed using any suitable process parameters. In some embodiments, the catalyst layer formation process is performed at a temperature between about 20°C (i.e., about room temperature) and about 600°C. In some embodiments, the catalyst layer formation process is performed at a temperature between about 100°C and about 300°C. In some embodiments, the catalyst layer formation process is performed at a pressure between about 1 mTorr and about 760 Torr (i.e., about 1 atmosphere). In some embodiments, the catalyst layer formation process is performed at a pressure between about 1 Torr and about 10 Torr. In some embodiments, the feed time of at least one catalyst layer precursor is between about 0.1s per cycle and about 60s per cycle. For example, if at least one catalyst layer is formed as a single layer, the feed time of at least one catalyst layer precursor can be about 1s to about 2s. As another example, if at least one catalyst layer includes a film (e.g., Al2O3) formed using a deposition process (e.g., an ALD process), the feed time of each catalyst layer precursor (e.g., Al-precursor and O-precursor) can be about 0.1s.

[0057] In step 330, at least one supplementary dielectric layer is selectively formed using at least one catalyst layer. Each catalyst layer is used to cause the formation of each supplementary dielectric layer. For example, each catalyst layer can catalyze the growth of at least one supplementary dielectric layer (e.g., to achieve a suitably high GPC for the deposition process used to form each supplementary dielectric layer). In some embodiments, at least one supplementary dielectric layer comprises a low dielectric constant dielectric material. In some embodiments, the low dielectric constant dielectric material has a dielectric constant of less than or equal to about 4. In some embodiments, at least one supplementary dielectric layer comprises a silicate. For example, at least one supplementary dielectric layer comprises a low dielectric constant dielectric silicate (i.e., a silicate having a dielectric constant of less than or equal to about 4). Examples of low dielectric constant dielectric silicates include SiO x , SiOC, etc.

[0058] At least one supplementary dielectric layer can be formed using any suitable supplementary dielectric layer formation process. In some embodiments, the supplementary dielectric layer formation process is an ALD process. For example, the ALD process can be a thermal ALD process. At least one supplementary dielectric layer can be formed by performing a suitable number of cycles of a passivation layer formation process, a catalyst layer formation process, and / or a supplementary dielectric layer formation process to achieve a target thickness of at least one supplementary dielectric layer. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. For example, each cycle of the catalyst layer formation process can include a catalyst layer deposition precursor pulse and a purge gas pulse. As another example, each cycle of the supplementary dielectric layer formation process can include a supplementary dielectric layer deposition precursor pulse and a purge gas pulse. The purge gas can be any suitable inert gas. For example, the purge gas can be argon (Ar), nitrogen (N2), etc.

[0059] In some embodiments, the supplemental dielectric layer formation process utilizes at least one supplemental dielectric layer deposition precursor. For example, the at least one supplemental dielectric layer deposition precursor may include at least one deposition precursor that can form at least one supplemental dielectric layer comprising a silicate. Examples of silicates include SiO x , SiOC, etc.

[0060] In some embodiments, at least one supplemental dielectric precursor has the form:

[0061]

[0062] wherein each R is at least one of an alkyl or alkoxy group (wherein the number of carbon (C) atoms is independently between 1 and 8), a hydrogen (H) group, an aldehyde group, a carboxyl group (e.g., a carboxylic acid), an ether group, an alcohol group, a phenyl group, or other groups containing a combination of C, O, and H. In some embodiments, at least one supplemental dielectric precursor has the following form:

[0063]

[0064] wherein each R is at least one of an alkyl or alkoxy group (wherein the number of carbon atoms is independently between 1 and 8), a hydrogen (H) group, an aldehyde group, a carboxyl group (e.g., a carboxylic acid), an ether group, an alcohol group, a phenyl group, or other groups containing a combination of C, O, and H, x∈(0, 1, 2} and n∈{0, 1, 2, 3, 4, 5, 6}.

[0065] In some embodiments, at least one supplementary dielectric layer comprises SiO x , and at least one of the supplementary dielectric layer precursors includes SiO x Precursors. For example, SiO x The precursor can be Al-catalyzed SiO x Precursor: Al-catalyzed SiO x Examples of the precursor include Si(OH)(t-BuO)3, Si(OH)(t-PeO)3, and the like.

[0066] In some embodiments, at least one supplementary dielectric layer comprises SiOC, and at least one supplementary dielectric layer precursor comprises a SiOC precursor. For example, the SiOC precursor can be an Al-catalyzed SiOC precursor. Examples of Al-catalyzed SiOC precursors include Si(OH)(Me)(t-BuO)2, Si(OH)(Et)(t-BuO)2, Si(OH)(Me)(t-PeO)2, Si(OH)(Et)(t-PeO)2, Si(OH)(i-Bu)(t-BuO)2, and Si(OH)(i-Bu)(t-PeO)2. Thus, the SiOC precursor can form at least one supplementary dielectric layer that is doped in carbon to reduce the dielectric constant of the at least one supplementary dielectric layer.

[0067] In some embodiments, forming at least one supplementary dielectric layer includes forming at least one base supplementary dielectric layer and doping the at least one base supplementary dielectric layer with a doping agent. That is, the at least one supplementary dielectric precursor may include a base supplementary dielectric layer precursor and a doping agent. The doping agent may be used to dope each base supplementary dielectric layer to reduce the dielectric constant. For example, the at least one base supplementary dielectric layer may be formed using at least one SiO x Precursor is formed to form SiO xAt least one base supplementary dielectric layer is provided, and at least one base supplementary dielectric layer can be doped with at least one doping agent to form at least one supplementary dielectric layer comprising SiOC. In some embodiments, at least one doping agent comprises a silanol agent. Silanol is a compound having a Si-OH functional group. Examples of silanol agents include diethyl (isopropyl) silanol, dimethylphenyl silanol, (4-methoxyphenyl) dimethyl silanol, diphenylsilanediol, methyl silanetriol, tertiary butyl dimethyl silanol, triethyl silanol, triisopropyl silanol, trimethyl silanol, triphenyl silanol, tri(tertiary butyloxy) silanol, tri(tert-amyloxy) silanol, tri(trimethylsilyl) silanol, tri(trimethylsiloxy) silanol, tri(2-methoxyphenyl) silanol, 1,1,1,3,5,5,5-heptamethyltrisiloxane, etc. Thus, in this example, SiOC can be formed by doping carbon into SiO x It is formed in the middle rather than directly forming SiOC.

[0068] The process parameters of the supplementary dielectric layer formation process (e.g., a thermal ALD process) may depend on the supplementary dielectric layer precursor used to form the supplementary dielectric layer and the target thickness of the resulting supplementary dielectric layer. The target thickness can be achieved by performing a target number of deposition cycles. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the supplementary dielectric layer formation process is performed at a temperature between about 20° C. (i.e., about room temperature) and about 600° C. In some embodiments, the supplementary dielectric layer formation process is performed at a temperature between about 100° C. and about 300° C. In some embodiments, the supplementary dielectric layer formation process is performed at a pressure between about 1 mTorr and about 760 Torr. In some embodiments, the supplementary dielectric layer formation process is performed at a pressure between about 1 Torr and about 10 Torr. A sufficiently high pressure may be required to fully saturate the catalytic formation of at least one supplementary dielectric layer. In some embodiments, the feed time of at least one supplementary dielectric layer deposition precursor (e.g., silanol) is between about 0.1 s per cycle and about 60 s per cycle. In some embodiments, the feeding time of at least one supplemental dielectric layer deposition precursor (eg, silanol) is between about 1 s and about 10 s.

[0069] As mentioned above, the at least one passivation layer can prevent adsorption of deposition precursors used to form the at least one catalyst layer and / or the at least one supplemental dielectric layer. Thus, due to the at least one passivation layer, a negligible thickness of dielectric material (e.g., a low-k dielectric material) can be formed on the at least one conductive layer during the supplemental dielectric layer deposition process (e.g., a thickness less than about 1 nm).

[0070] In some embodiments, selectively forming at least one passivation layer includes regenerating at least one passivation layer. More specifically, after selectively forming at least one catalyst layer, at least one passivation layer may be regenerated to address possible degradation of the at least one passivation layer caused by the catalyst layer formation process.

[0071] In some embodiments, an optional post-cleaning process is performed after forming the at least one supplemental dielectric layer. Performing the post-cleaning process may include removing the at least one passivation layer from the surface of the at least one conductive layer. Performing the post-cleaning process may further include removing defects (e.g., dielectric material that may have formed on the at least one conductive layer during the deposition process).

[0072] Figure 4A is a diagram illustrating an example method 400A for selectively forming at least one supplementary dielectric (SD) layer, the method comprising a passivation layer forming step 410, a catalyst layer forming step of forming at least one catalyst layer, and an SD layer forming step of forming at least one SD layer using the at least one catalyst layer. The catalyst layer forming step comprises a catalyst layer precursor step 420 and a purge / pumping step 430. In some embodiments, the catalyst layer precursor step 420 is an Al-catalyst layer precursor step. The SD layer forming step comprises a SD layer precursor step 440 and a purge / pumping step 450 that form cycles such that X cycles are performed. The number of cycles (i.e., the value of X) can be selected such that at least one SD layer reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer comprises a dielectric material with a low dielectric constant (e.g., a dielectric silicate with a low dielectric constant). Examples of dielectric materials with a low dielectric constant include SiO x , SiOC, etc. Thus, method 400A involves a single application of a passivation layer and a single application of a catalyst layer.

[0073] Figure 4Bis a diagram illustrating an example method 400B for selectively forming at least one SD layer. Method 400B includes a passivation layer formation step 410, a catalyst layer formation step (including a catalyst layer precursor step 420 and a purge / pumping step 430 to form at least one catalyst layer), and an SD layer formation step (including an SD layer precursor step 440 and a purge / pumping step 450 to form at least one SD layer). In this example, the catalyst layer formation step and the SD layer formation step form a cycle (i.e., the catalyst layer formation step is repeated after the SD layer formation step) such that X cycles are performed. The number of cycles (i.e., the value of X) can be selected so that at least one SD layer reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer includes a dielectric material with a low dielectric constant (e.g., a dielectric silicate with a low dielectric constant). Examples of dielectric materials with a low dielectric constant include SiO x , SiOC, etc. Thus, method 400B involves a single application of at least one passivation layer and multiple applications of at least one catalyst layer.

[0074] Figure 4C 4 is a flow chart illustrating an exemplary method 400C for selectively forming at least one SD layer. The method 400C includes a passivation layer forming step 410, a catalyst layer forming step (including a catalyst layer precursor step 420 and a purge / pumping step 430 to form at least one catalyst layer), and an SD layer forming step (including an SD layer precursor step 440 and a purge / pumping step 450 to form at least one SD layer).

[0075] In this example, the passivation layer step, the catalyst layer formation step, and the SD layer formation step are cycled (i.e., the passivation layer formation step is repeated after the SD layer formation step) such that X cycles are performed. The number of cycles (i.e., the value of X) can be selected so that at least one SD layer formed during the SD layer formation step reaches a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, at least one SD layer includes a low dielectric constant dielectric material (e.g., a low dielectric constant dielectric silicate). Examples of low dielectric constant dielectric materials include SiO x , SiOC, etc. Thus, method 400C involves multiple applications of at least one passivation layer and multiple applications of at least one catalyst layer.

[0076] Figure 4D4 is a flow chart illustrating an example method 400D for selectively forming at least one SD layer. Method 400D includes a PL formation step 410 for forming at least one passivation layer (PL), a first CL formation step for forming at least one first catalyst layer (CL), a second CL layer formation step for forming at least one second CL, and an SD layer formation step comprising an SD layer precursor step 440 and a purge / pump step 450 for forming at least one SD layer. More specifically, the first CL formation step includes a CL precursor 1 step 420-1, a purge / pump step 430-1, a CL precursor 2 step 420-2, and a purge / pump step 430-2. The second CL formation step includes a CL precursor 3 step 420-3 and a purge / pump step 430-3. In some embodiments, the CL precursor 3 step 420-3 is the same as the CL precursor 1 step 420-1. For example, the CL precursor 3 step 420-3 can be performed to alkylate the surface of the at least one first CL.

[0077] In this example, steps 420-1 through 430-2 of the first CL formation step form a first cycle, whereby X1 cycles of the first cycle are performed. Furthermore, steps 440 and 450 of the SD layer formation step form a second cycle, whereby X2 cycles of the second cycle are performed. In some embodiments, at least one first CL comprises Al2O3, and at least one second CL comprises an Al-catalyst layer. For example, CL Precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL Precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL Precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) may be selected so that the at least one CL formed during the first CL formation step and the at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between approximately 5 nm and approximately 30 nm. In some embodiments, the target thickness is between approximately 10 nm and approximately 20 nm. In some embodiments, at least one SD layer comprises a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, method 400D involves a single application of at least one PL, multiple applications of at least one first CL, a single application of at least one second CL, and multiple applications of at least one SD layer.

[0078] Figure 4E4 is a flow chart illustrating an exemplary method 400E for selectively forming at least one SD layer. The method 400E includes a PL formation step 410 for forming at least one PL, a first CL formation step including steps 420-1 through 430-2 for forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 for forming at least one second CL, and an SD layer formation step including steps 440 and 450 for forming at least one SD layer.

[0079] In this example, steps 420-1 through 430-2 of the first CL formation step form a first cycle, such that X1 cycles of the first cycle are performed. Furthermore, steps 420-3 and 430-3 of the second CL layer formation step and steps 440 and 450 of the SD layer formation step form a second cycle, such that X2 cycles of the second cycle are performed. In some embodiments, at least one first CL comprises Al2O3, and at least one second CL comprises an Al-catalyst layer. For example, CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL precursor 3 step 4203 may be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) may be selected so that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer forming step forms at least one SD layer comprising a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, method 400E involves a single application of at least one PL, and multiple applications of at least one first CL, at least one second CL, and at least one SD layer (eg, at least one second CL is regenerated after each SD layer formation cycle).

[0080] Figure 4F 4 is a flow chart illustrating an exemplary method 400F for selectively forming at least one SD layer. The method 400F includes a PL formation step 410 for forming at least one PL, a first CL formation step including steps 420-1 to 420-2 for forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 for forming at least one second CL, and an SD layer formation step including steps 440 and 450 for forming at least one SD layer.

[0081] In this example, the PL formation step 410, steps 420-1 through 430-2 of the first CL formation step form a first cycle, such that X1 cycles of the first cycle are performed. Furthermore, steps 440 and 450 of the SD layer formation step form a second cycle, such that X2 cycles of the second cycle are performed. In some embodiments, at least one first CL comprises Al2O3, and at least one second CL comprises an Al-catalyst layer. For example, CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) may be selected so that the at least one CL formed during the first CL formation step and the at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer forming step forms at least one SD layer comprising a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, method 400F involves a single application of at least one second CL, and multiple applications of at least one passivation layer, at least one first CL, at least one second CL, and at least one SD layer (e.g., at least one PL is regenerated after each first / second CL layer formation cycle).

[0082] Figure 4G 4 is a flow chart illustrating an exemplary method 400G for selectively forming at least one SD layer. The method 400G includes a PL formation step 410 for forming at least one PLM, a first CL formation step including steps 420-1 through 420-2 for forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 for forming at least one second CL, and an SD layer formation step including steps 440 and 450 for forming at least one SD layer.

[0083] In this example, the PL formation step 410 and steps 420-1 through 430-2 of the first CL formation step form a first cycle, whereby X1 cycles of the first cycle are performed. Furthermore, steps 420-3 and 430-3 of the second CL layer formation step and steps 440 and 450 of the SD layer formation step form a second cycle, whereby X2 cycles of the second cycle are performed. In some embodiments, at least one first CL comprises Al2O3, and at least one second CL comprises an Al-catalyst layer. For example, CL precursor 1 step 420-1 may be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 may be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 may be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) may be selected so that the at least one CL formed during the first CL formation step and the at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between approximately 5 nm and approximately 30 nm. In some embodiments, the target thickness is between approximately 10 nm and approximately 20 nm. In some embodiments, the SD layer forming step forms at least one SD layer comprising a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, method 400G involves a single application of at least one PL, and multiple applications of at least one first CL, at least one second CL, and at least one SD layer (eg, the second CL is regenerated after each SD layer formation cycle).

[0084] Figure 4H 4 is a flow chart illustrating an exemplary method 400H for selectively forming at least one SD layer. The method 400H includes a PL formation step 410 for forming at least one PL, a first CL formation step including steps 420-1 through 420-2 for forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 for forming at least one second CL, and an SD layer formation step including steps 440 and 450 for forming at least one SD layer.

[0085] In this example, steps 420-1 through 430-2 of the first CL formation step form a first cycle, such that X1 cycles of the first cycle are performed. In this example, an additional PL formation step 410 (e.g., to regenerate at least one PL) is performed after X1 cycles of the first cycle are performed. Furthermore, steps 420-3 and 430-3 of the second CL formation step and steps 440 and 450 of the SD layer formation step form a second cycle, such that X2 cycles of the second cycle are performed. In some embodiments, at least one first CL includes Al2O3, and at least one second CL includes an Al-catalyst layer. For example, CL precursor 1 step 420-1 can be an Al-catalyst layer precursor step, CL precursor 2 step 420-2 can be an O-catalyst layer precursor step, and CL precursor 3 step 420-3 can be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) can be selected so that the at least one CL formed during the first CL formation step and the at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer forming step forms at least one SD layer comprising a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, method 400H involves a single application of at least one PL before the first CL formation step, a single application of at least one PL after the first CL formation step, and multiple applications of at least one first CL, at least one second CL, and at least one SD layer (e.g., regenerating at least one second CL after each SD layer formation cycle).

[0086] Figure 4I 4 is a flow chart illustrating an exemplary method 400I for selectively forming at least one SD layer. The method 400I includes a PL formation step 410 for forming at least one PL, a first CL formation step including steps 420-1 through 420-2 for forming at least one first CL, a second CL layer formation step including steps 420-3 and 430-3 for forming at least one second CL, and an SD layer formation step including steps 440 and 450 for forming at least one SD layer.

[0087] In this example, the PL formation step 410, steps 420-1 to 430-2 of the first CL formation step form a first cycle, so that X1 cycles of the first cycle are performed. In this example, the additional PL formation step 410 is performed after performing X1 cycles of the first cycle (for example, to regenerate at least one PL). In addition, the additional PL formation step 410 and steps 420-3 and 430-3 of the second CL formation step and steps 440 and 450 of the SD layer formation step form a second cycle, so that X2 cycles of the second cycle are performed. In some embodiments, at least one first CL includes Al2O3, and at least one second CL includes an Al-catalyst layer. For example, the CL precursor 1 step 420-1 can be an Al-catalyst layer precursor step, the CL precursor 2 step 420-2 can be an O-catalyst layer precursor step, and the CL precursor 3 step 420-3 can be another Al-catalyst layer precursor step. The number of cycles (i.e., the values ​​of X1 and X2) can be selected so that at least one CL formed during the first CL formation step and at least one SD layer formed during the SD layer formation step reach a target thickness. In some embodiments, the target thickness is between about 5 nm and about 30 nm. In some embodiments, the target thickness is between about 10 nm and about 20 nm. In some embodiments, the SD layer formation step forms at least one SD layer comprising a low-k dielectric material (e.g., a low-k dielectric silicate). Examples of low-k dielectric materials include SiO x , SiOC, etc. Thus, the method 400I involves applying at least one PL multiple times before the first CL formation step (e.g., regenerating the at least one PL after each first CL formation cycle), and applying at least one PL layer, at least one first CL, at least one second CL, and at least one SD layer multiple times after the first CL formation step (e.g., regenerating the at least one PL and at least one second CL after each SD layer formation cycle).

[0088] Figure 5 is a block diagram of an example electronic device processing system ("system") 500 that can be used to manufacture electronic devices using area selective deposition according to some embodiments. For example, system 500 can be used to form the above-referenced Figure 1A As another example, the system 500 may implement the device 100 described in FIG. Figures 2 to 4I Method 200-400I described.

[0089] As shown, the system 500 includes a passivation chamber 510, a transfer chamber 520, and a deposition chamber 530. An interface 540-1 can be provided between the passivation chamber 510 and the transfer chamber 520, and an interface 540-2 can be provided between the transfer chamber 520 and the deposition chamber 530. In some embodiments, the interfaces 540-1 and 540-2 are respective gate valves. The transfer chamber 520 can include a transfer robot (not shown). The transfer chamber 520, the passivation chamber 510, and the deposition chamber 530 can each be maintained under vacuum under controlled conditions (e.g., with little or no humidity). Although not shown, the system 500 can further include at least one load lock chamber and at least one factory interface to enable substrates to be moved from the atmosphere to the transfer chamber 520. Thus, substrates can be transferred between chambers without breaking the vacuum, and thus without exposing the substrates to air and / or humidity.

[0090] The passivation chamber 510 can passivate at least one conductive layer of the base structure by exposing the at least one conductive layer to a passivating agent. The passivation chamber 510 can be operably coupled to at least one storage device 512. In some embodiments, the at least one storage device 512 includes at least one passivating agent storage device for storing at least one passivating agent. In some embodiments, the at least one passivating agent storage device stores a gas phase passivating agent. In some embodiments, the at least one passivating agent storage device stores a solution phase passivating agent. The at least one storage device 512 can further include at least one purge gas storage device for storing any suitable inert gas (e.g., Ar or N2) for purging the passivation chamber 512 during the passivation process. Further details regarding passivating conductive materials using a passivating agent are provided above with reference to Figure 1B and Figures 2 to 4I describe.

[0091] The deposition chamber 530 can be operably coupled to at least one storage device 532. The deposition chamber 530 can perform a deposition process for selectively forming a catalyst layer on the first ILD layer and / or a deposition process for selectively forming a supplementary dielectric layer on the first ILD layer. The at least one storage device 532 can include at least one deposition precursor storage device. The at least one deposition precursor storage device can store any suitable deposition precursor for forming the catalyst layer and / or the supplementary dielectric layer. The at least one storage device 532 can further include a purge gas storage device for storing any suitable inert gas (e.g., Ar or N2) for purging the deposition chamber 530 during the deposition process. After passivating the at least one conductive layer, in some embodiments, the transfer robot can transfer the electronic device to the deposition chamber 530. Further details about performing a deposition process for selectively forming a catalyst layer on the first ILD layer and / or a deposition process for selectively forming a supplementary dielectric layer on the first ILD layer are described above with reference to Figure 1CTo the image ID and Figures 2 to 4I describe.

[0092] In some embodiments, the deposition process is performed in the passivation chamber 510 (i.e., the passivation chamber 510 is a processing chamber configured to perform both the passivation process and the deposition process). In these embodiments, at least one storage device 532 is operatively coupled to the passivation chamber 510. In some embodiments, the passivation process is performed in the deposition chamber 530 (i.e., the deposition chamber 530 is a processing chamber configured to perform both the passivation process and the deposition process). In these embodiments, at least one storage device 512 is operatively coupled to the deposition chamber 530.

[0093] In some embodiments, the system 500 may optionally include a cleaning chamber 550 to perform an optional cleaning process (i.e., a pre-cleaning process) before passivation and / or to perform an optional cleaning process (i.e., a post-cleaning process) after forming the supplemental dielectric layer. An interface 540-3 may be provided between the cleaning chamber 550 and the transfer chamber 520. In some embodiments, the cleaning chamber 550 is an in-situ cleaning chamber and the interface 540-3 is a gate valve. In some embodiments, the cleaning chamber 550 is an ex-situ cleaning chamber and the interface 540-3 is a load lock chamber. The cleaning chamber 550 may be operably coupled to at least one storage device 552. The at least one storage device 552 may include any suitable cleaning chemicals for performing pre-cleaning and / or post-cleaning. The at least one storage device 552 may further include a purge gas storage device for storing a suitable inert gas (e.g., Ar or N2) for purging the cleaning chamber 552 during the cleaning process. In some embodiments, the pre-cleaning process may be performed in the same chamber as the passivation process (e.g., the passivation chamber 510 or the deposition chamber 530). In these embodiments, at least one storage device 552 may be operatively coupled to the passivation chamber 510 and / or the deposition chamber 530. In some embodiments, the post-cleaning process may be performed in the passivation chamber 510 and / or the deposition chamber 530. In these embodiments, at least one storage device 552 may be operatively coupled to the passivation chamber 510 and / or the deposition chamber 530. Further details regarding performing cleaning processes (e.g., pre-cleaning processes and / or post-cleaning processes) are provided above with reference to Figure 2 Description. As mentioned above Figures 1E to 2 Further electronic device processing described may be performed using one or more of chambers 510 - 530 and 550 .

[0094] The foregoing description has been set forth several specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be put into practice without these specific details. In other examples, well-known components or methods are not described in detail and are provided in a simple block diagram format to avoid unnecessarily confusing the present disclosure. Therefore, the specific details set forth are merely exemplary. Specific embodiments may be changed from these exemplary details and are still contemplated to be within the scope of the present disclosure.

[0095] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the term "or" is intended to mean an inclusive or rather than an exclusive or. When the terms "about" or "approximately" are used herein, this is intended to mean that the nominal value provided is accurate to within ±10%.

[0096] Although the operations of the methods herein are shown and described in a particular order, the order of operations of each method may be changed so that some operations may be performed in reverse order, or so that some operations may be performed at least partially simultaneously with other operations. In another embodiment, the instructions or sub-operations of different operations may be performed intermittently and / or in an alternating manner.

[0097] It will be understood that the above description is intended to be illustrative and not restrictive. After reading and understanding the above description, numerous other embodiments will be apparent to those skilled in the art. Thus, the scope of this disclosure should be determined with reference to the appended claims together with the full scope of equivalents given by such claims.

Claims

1. A method comprising: selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; as well as At least one supplementary dielectric layer is selectively formed using the at least one catalyst layer, wherein the at least one catalyst layer causes formation of the at least one supplementary dielectric layer, and wherein the at least one supplementary dielectric layer comprises a dielectric material having a dielectric constant less than or equal to about 4. 2 . The method of claim 1 , wherein selectively forming the at least one passivation layer comprises forming the at least one passivation layer using a vapor-phase passivating agent. 3 . The method of claim 1 , wherein selectively forming the at least one passivation layer comprises forming the at least one passivation layer using a solution-phase passivating agent. 4 . The method of claim 1 , wherein the at least one catalyst layer comprises at least one of a metal catalyst layer or a metalloid catalyst layer. 5 . The method of claim 4 , wherein selectively forming the at least one supplementary dielectric layer comprises forming the at least one supplementary dielectric layer using a catalytic precursor. The method of claim 1 , wherein the at least one supplemental dielectric layer comprises silicate.

7. The method of claim 6, wherein the silicate comprises at least one of: silicon oxide (SiOX) or silicon oxycarbide (SiOC).

8. The method of claim 1, wherein the at least one supplemental dielectric layer has a thickness of about 10 nm to about 20 nm.

9. The method of claim 1, further comprising: forming a second ILD layer over the at least one supplementary dielectric layer and the at least one first conductive layer; as well as At least one second conductive layer is formed in the second ILD layer in contact with the at least one first conductive layer. 10 . The method of claim 9 , wherein the at least one first conductive layer includes a first via, and the at least one second conductive layer includes a second via in contact with the first via.

11. A system comprising at least one chamber operatively coupled to at least one storage device, the at least one chamber configured to: selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlayer dielectric (ILD) layer; selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer; as well as At least one supplementary dielectric layer is selectively formed using the at least one catalyst layer, wherein the at least one catalyst layer causes formation of the at least one supplementary dielectric layer, and wherein the at least one supplementary dielectric layer comprises a dielectric material having a dielectric constant less than or equal to about 4.

12. The system of claim 11, wherein the at least one storage device maintains at least one of: a vapor-phase passivating agent for selectively forming the at least one passivation layer, or a solution-phase passivating agent for selectively forming the at least one passivation layer.

13. The system of claim 11, wherein the at least one storage device maintains at least one catalyst layer precursor for selectively forming the at least one catalyst layer.

14. The system of claim 11, wherein the at least one catalyst layer comprises at least one of: a metal catalyst layer or a metalloid catalyst layer.

15. The system of claim 11, wherein the at least one chamber is configured to form the at least one supplemental dielectric layer using a catalytic precursor.

16. The system of claim 11, wherein the at least one supplemental dielectric layer comprises a silicate, wherein the at least one storage device maintains a silanol, and wherein the at least one chamber is configured to form the at least one supplemental dielectric layer using the silanol as a deposition precursor.

17. The system of claim 16, wherein the silicate comprises at least one of: silicon oxide (SiOX) or silicon oxycarbide (SiOC).

18. The system of claim 11, wherein the at least one supplemental dielectric layer has a thickness between about 10 nm and about 20 nm.

19. The system of claim 11, wherein the at least one chamber is further configured to: forming a second ILD layer over the at least one supplementary dielectric layer and the at least one first conductive layer; and At least one second conductive layer is formed in the second ILD layer in contact with the at least one first conductive layer.

20. The system of claim 19, wherein the at least one first conductive layer includes a first via, and the at least one second conductive layer includes a second via in contact with the first via.

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