Light detection device and manufacturing method thereof

Abstract

The invention provides a light detection device and a method for manufacturing the same, wherein the light detection device can restrain yield reduction. The light detection device includes: a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface; a plurality of pixels provided on the semiconductor substrate and having photoelectric conversion elements; an inter-pixel separation portion that is provided between one pixel and another adjacent pixel among the plurality of pixels and penetrates between the first surface and the second surface of the semiconductor substrate; and a surrounding portion provided on the first surface side of the semiconductor substrate and surrounding an end portion of the inter-pixel separation portion. The surrounding portion is made of a material different from that of the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a light detection device and a method for manufacturing the same. Background Art

[0002] As an inter-pixel separation portion of a pixel having a photoelectric conversion element, an inter-pixel separation portion that penetrates a semiconductor substrate in a depth direction is known (for example, see Patent Document 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1] JP 2020-013909 A Summary of the Invention

[0006] [Technical Issues]

[0007] In the process of forming an inter-pixel separation portion that penetrates a semiconductor substrate, the semiconductor substrate is etched using a mask to form a trench penetrating the semiconductor substrate. After the trench is formed, the mask is removed by wet etching. During mask removal, if a chemical liquid passes through the trench and reaches the side of the semiconductor substrate opposite to the mask-formed surface, the chemical liquid may corrode the insulating film covering the side opposite to the mask-formed surface, potentially reducing the yield of the light detection device.

[0008] The present disclosure has been devised in consideration of the above-described circumstances, and an object of the present disclosure is to provide a light detecting device and a method of manufacturing the same that are capable of suppressing a reduction in yield.

[0009] [Solution to the problem]

[0010] According to one aspect of the present disclosure, a light detection device includes: a semiconductor substrate having a first surface and a second surface located on the opposite side of the first surface; a plurality of pixels arranged on the semiconductor substrate and having a photoelectric conversion element; an inter-pixel separation portion arranged between an adjacent pixel and another pixel among the plurality of pixels and passing through the first surface and the second surface of the semiconductor substrate; and an enclosing portion arranged on the first surface side of the semiconductor substrate and surrounding an end portion of the inter-pixel separation portion, wherein the enclosing portion is made of a material different from that of the semiconductor substrate.

[0011] Thus, when removing the mask used to form the trench for the pixel isolation portion by wet etching, even if a chemical liquid enters the first surface side from the second surface side of the semiconductor substrate through the trench, the surrounding portion prevents the chemical liquid from contacting the insulating film covering the first surface side. Therefore, since the insulating film covering the first surface side of the semiconductor substrate is prevented from being corroded by the chemical liquid used to remove the mask, a decrease in the yield of the light detection device can be suppressed.

[0012] According to one aspect of the present disclosure, a method for manufacturing a light detection device includes: a process of forming a first material film on a first surface side of a semiconductor substrate and covering a predetermined area with the first material film from the first surface side, wherein the semiconductor substrate has a first surface and a second surface located on the opposite side of the first surface and is provided with a plurality of pixels having photoelectric conversion elements, and the predetermined area is used to separate adjacent pixels among the plurality of pixels from each other; a process of forming a second material film on the opposite side of the predetermined area with the first material film clamped therebetween; a process of forming a third material film on the opposite side of the first material film with the second material film clamped therebetween and covering the second material film with the first material film and the third material film; a process of forming a mask having a shape that exposes the predetermined area and covers an area other than the predetermined area on the second surface side; a process of forming a groove that passes through the semiconductor substrate and the first material film by etching the predetermined area exposed by the mask from the second surface side using the second material film as an etching stop layer; and a process of removing the mask by wet etching after forming the groove, wherein in the wet etching, a chemical liquid is used that is easy to etch the mask and the second material film and difficult to etch the first material film and the third material film.

[0013] Thus, even if a chemical liquid used for mask removal enters the first surface of the semiconductor substrate from the second surface through the groove during mask removal, the surrounding portion prevents the chemical liquid from contacting the insulating film covering the first surface of the semiconductor substrate. Therefore, since the insulating film covering the first surface of the semiconductor substrate is prevented from being corroded by the chemical liquid used for mask removal, a decrease in the yield of the light detection device can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : is a cross-sectional view showing a configuration example of a light detection device having an inter-pixel separation portion according to an embodiment of the present disclosure.

[0015] Figure 2 1 is a cross-sectional view illustrating a method of manufacturing a light detecting device according to an embodiment of the present disclosure in order of processes.

[0016] Figure 3 1 is a cross-sectional view illustrating a method of manufacturing a light detecting device according to an embodiment of the present disclosure in order of processes.

[0017] Figure 4 1 is a cross-sectional view illustrating a method of manufacturing a light detecting device according to an embodiment of the present disclosure in order of processes.

[0018] Figure 5 1 is a cross-sectional view illustrating a method of manufacturing a light detecting device according to an embodiment of the present disclosure in order of processes.

[0019] Figure 6is a cross-sectional view illustrating a light detecting device according to Modification 1 of the embodiment of the present disclosure.

[0020] Figure 7 is a cross-sectional view illustrating a light detecting device according to Modification 2-1 of the embodiment of the present disclosure.

[0021] Figure 8 is a cross-sectional view illustrating a light detecting device according to Modification 2-2 of the embodiment of the present disclosure.

[0022] Figure 9 is a cross-sectional view illustrating a light detecting device according to Modification 3 of the embodiment of the present disclosure.

[0023] Figure 10 4-1 is a cross-sectional view showing a light detecting device according to Modification 4-1 of the embodiment of the present disclosure.

[0024] Figure 11 is a cross-sectional view illustrating a light detecting device according to Modification 4-2 of the embodiment of the present disclosure.

[0025] Figure 12 5 is a cross-sectional view showing a light detecting device according to Modification 5-1 of the embodiment of the present disclosure.

[0026] Figure 13 is a cross-sectional view illustrating a light detecting device according to Modification 5-2 of the embodiment of the present disclosure.

[0027] Figure 14 : is a cross-sectional view showing a light detecting device according to Modification 6-1 of the embodiment of the present disclosure.

[0028] Figure 15 6-2 is a cross-sectional view illustrating a light detecting device according to Modification 6-2 of the embodiment of the present disclosure.

[0029] Figure 16 1 is a diagram illustrating a configuration of an imaging element according to Application Example 1-1 of the present disclosure.

[0030] Figure 17 1 is a cross-sectional view illustrating the configuration of a pixel array section according to Application Example 1-1 of the present disclosure.

[0031] Figure 18 1 is a cross-sectional view illustrating a configuration of a pixel array portion of a light receiving element according to Application Example 1-2 of the present disclosure.

[0032] Figure 19 1 is a cross-sectional view illustrating a configuration of a pixel array portion of a light receiving element according to Application Example 1-3 of the present disclosure.

[0033] Figure 20 2 is a cross-sectional view showing the configuration of a sensor chip according to Application Example 2-1 of the present disclosure.

[0034] Figure 21 2 is a cross-sectional view showing the configuration of a back-illuminated pixel according to Application Example 2-2 of the present disclosure.

[0035] Figure 22 is a cross-sectional view illustrating the configuration of a pixel in an imaging device according to Application Example 3-1 of the present disclosure.

[0036] Figure 23 3-2 is a cross-sectional view illustrating the configuration of a pixel array portion of an imaging device according to Application Example 3-2 of the present disclosure. DETAILED DESCRIPTION

[0037] The embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the description of the drawings referred to in the following description, the same or similar parts will be represented by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and plane size, the ratio of the thickness of each layer, etc. will be different from the actual ones. Therefore, the specific thickness and size should be determined according to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0038] Furthermore, it should be understood that the definitions of directions such as up and down in the following description are provided merely for simplicity and are not intended to limit the technical spirit of the present disclosure. For example, it is obvious that when an object is rotated 90 degrees and observed, up and down are converted to and interpreted as left and right, while when the object is rotated 180 degrees and observed, up and down are interpreted as inverted.

[0039] <Implementation Plan>

[0040] (structure)

[0041] Figure 1 1 is a cross-sectional view showing a configuration example of the light detection device 1 having the inter-pixel separation unit 20 according to an embodiment of the present disclosure. Figure 1 As shown, the light detection device 1 includes a semiconductor substrate 10, a plurality of pixels 12 provided on the semiconductor substrate 10, an inter-pixel separation portion 20 provided on the semiconductor substrate 10, and a surrounding portion 30 provided on the front face 10a side of the semiconductor substrate 10 and surrounding an end portion 20a of the inter-pixel separation portion 20.

[0042] The semiconductor substrate 10 has a front surface 10a ( Figure 1 in the following; an example of a "first surface" in the present disclosure) and a back surface 10b ( Figure 1 The semiconductor substrate 10 is made of, for example, single crystal silicon (Si).

[0043] Each of the multiple pixels 12 provided on the semiconductor substrate 10 is composed of a photodiode PD (an example of a "photoelectric conversion element" in this disclosure) and multiple pixel transistors. The photodiode PD is formed to extend across the entire thickness of the semiconductor substrate 10 and is configured, for example, as a pn junction photodiode composed of an n-type semiconductor region and a p-type semiconductor region. When viewed from a plane in the thickness direction of the semiconductor substrate 10, the multiple pixels 12 are arranged in a matrix.

[0044] The inter-pixel separator 20 is provided between one adjacent pixel 12 and another adjacent pixel 12 among the plurality of pixels 12. The inter-pixel separator 20 extends between the back surface 10b and the front surface 10a of the semiconductor substrate 10. For example, the inter-pixel separator 20 includes a groove 21 extending between the back surface 10b and the front surface 10a of the semiconductor substrate 10 and a separation film 22 embedded in the groove 21. The separation film 22 is a film for electrically and optically separating adjacent pixels 12, and is made of, for example, silicon oxide (SiO), polycrystalline silicon (Poly-Si), tungsten (W), aluminum (Al), or copper (Cu), or a plurality of films including one or more of these.

[0045] Since the pixel isolation portion 20 passes through the semiconductor substrate 10, it can be called full trench isolation (FTI). In addition, as described later, the pixel isolation portion 20 is formed from the back surface 10b side of the semiconductor substrate 10, so it can be called reverse full trench isolation (RFTI).

[0046] The surrounding portion 30 is provided on the front surface 10a side of the semiconductor substrate 10. The surrounding portion 30 is made of a material different from that of the semiconductor substrate 10. For example, the surrounding portion 30 is made of silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN). The surrounding portion 30 can be formed by stacking two or more films of SiN film, SiON film, and SiCN film.

[0047] like Figure 1 As shown, the surrounding portion 30 has a bottom portion 31 and a side portion 32. The bottom portion 31 is arranged at a position away from the front surface 10a of the semiconductor substrate 10. The bottom portion 31 faces the front surface 10a side (of the two ends of the inter-pixel separation portion 20 in the thickness direction of the semiconductor substrate 10). Figure 1 The side portion 32 connects the front surface 10a of the semiconductor substrate 10 to the bottom portion 31.

[0048] Therefore, the shape of the surrounding portion 30 is recessed relative to the end portion 20a of the inter-pixel isolation portion 20. The end portion 20a of the inter-pixel isolation portion 20 is arranged in the space 33 inside the surrounding portion 30 and is surrounded from the outside by the surrounding portion 30. The end portion 20a of the inter-pixel isolation portion 20 is separated from the insulating films 41, 42, 43, and 44 described later by the surrounding portion 30 without any gap.

[0049] For example, the side portion 32 has an extension portion 32e extending in a direction away from the inter-pixel separation portion 20 along the front surface 10a of the semiconductor substrate 10. Furthermore, a step portion G32 is provided on the inner side surface of the side portion 32.

[0050] like Figure 1 As shown, an insulating film is provided on the front face 10a side of the semiconductor substrate 10 so as to be adjacent to the surrounding portion 30 from the outside of the surrounding portion 30. For example, on the front face 10a side of the semiconductor substrate 10, insulating films 41, 42, 43, and 44 are provided so as to be adjacent to the surrounding portion 30 from the outside of the surrounding portion 30. The insulating films 41 and 42 are provided between the front face 10a of the semiconductor substrate 10 and the extension portion 32e. In addition, the insulating films 43 and 44 are provided on opposite sides of the insulating films 41 and 42 across the extension portion 32e. The insulating films 41, 42, 43, and 44 are formed in this order from the front face 10a of the semiconductor substrate 10. The film forming direction is Figure 1 The insulating films 41 , 42 , 43 , and 44 are made of a material different from that of the semiconductor substrate 10 and the surrounding portion 30 , and are made of, for example, silicon oxide (SiO).

[0051] For example, the insulating film 41 is used as a gate insulating film of a pixel transistor (not shown) provided on the semiconductor substrate 10. The insulating film 42 is used as a protective film for protecting the gate electrode of the pixel transistor. The insulating films 43 and 44 are used as interlayer insulating films. However, the respective uses of the insulating films 41, 42, 43 and 44 are not limited to the above uses, and they can be formed for other uses. In this example, the insulating films 41, 42, 43 and 44 are examples of “insulating films” in the present disclosure. In addition, among these insulating films, the insulating films 41 and 42 are examples of “first insulating films” in the present disclosure.

[0052] The light detecting device 1 also includes a via 50 connected to the front surface 10a of the semiconductor substrate 10. The via 50 penetrates the insulating films 41, 42, 43, and 44 and the extension 32e. For example, the charge generated by photoelectric conversion in the photodiode PD is transferred to a readout circuit provided on the front surface 10a side of the semiconductor substrate 10 via the via 50.

[0053] (Manufacturing Method)

[0054] Next, we will explain Figure 1The photodetection device 1 is manufactured using various apparatuses such as a resist coating apparatus, an exposure apparatus, an etching apparatus, and a film forming apparatus. These apparatuses will be collectively referred to as manufacturing apparatuses.

[0055] Figures 2 to 5 1 is a cross-sectional view showing a method for manufacturing the light detecting device 1 according to an embodiment of the present disclosure in the order of processes. Figure 2 As shown in step ST1 in FIG. 1 , the manufacturing apparatus prepares a semiconductor substrate 10 on which insulating films 41 and 42 are sequentially formed on the front surface 10a. The insulating films 41 and 42 cover a predetermined region 20′ where an inter-pixel separation portion 20 (see FIG. 1 ) for separating adjacent pixels 12 from each other will be formed. Figure 1 ). The semiconductor substrate 10 is made of, for example, single-crystal silicon. The insulating films 41 and 42 are made of, for example, SiO. The total thickness of the insulating films 41 and 42 is, for example, 11 nm.

[0056] In this example, the width of the predetermined region 20' is set to be wider than the width of the pixel separation portion 20 to be formed eventually. This is to ensure a margin for misalignment in the multiple mask forming process described below. Figure 2 In step ST1 , an annealing process for forming a source and a drain of a pixel transistor is performed.

[0057] Next, if Figure 2 As shown in step ST2, the manufacturing apparatus forms a mask M1 on the insulating film 42. The mask M1 has a shape that exposes a predetermined region 20' and covers other regions. The mask M1 is made of, for example, a photoresist.

[0058] Next, the manufacturing apparatus performs an etching process on the front surface 10a side of the semiconductor substrate 10 on which the mask M1 is formed, to sequentially remove the insulating films 42 and 41 from the predetermined region 20' exposed by the mask M1. Figure 2 As shown in step ST3 , an opening H11 having the front surface 10 a of the semiconductor substrate 10 as a bottom surface is formed in the predetermined region 20 ′.

[0059] Next, if Figure 3 As shown in step ST4, the manufacturing apparatus forms a first material film MF1 on the front surface 10a side of the semiconductor substrate 10 to fill the opening H11. The first material film MF1 is a film that constitutes the surrounding portion 30 (see FIG. Figure 1 ) and is made of, for example, SiN. The first material film MF1 has a film thickness of, for example, 20 nm.

[0060] Next, if Figure 3As shown in step ST5, the manufacturing apparatus forms a second material film MF2 on the first material film MF1. The second material film MF2 is formed in the process of forming the groove 21 described later (refer to Figure 5 The second material film MF2 is a film used as an etching stopper in step ST11 of the etching process and is made of, for example, SiO. The second material film MF2 has a film thickness of, for example, 20 nm.

[0061] Next, if Figure 3 As shown in step ST6, the manufacturing apparatus forms a mask M2 on the second material film MF2. The mask M2 has a shape that covers the opening H11 and exposes other areas. The mask M2 is made of, for example, photoresist. To allow for a misalignment margin between the mask M2 and the opening H11, the width of the mask M2 may be smaller than the width of the opening H11.

[0062] Next, the manufacturing apparatus performs etching processing on the front surface 10a side of the semiconductor substrate 10 where the mask M2 is formed, so as to remove the portion of the second material film MF2 exposed by the mask M2. Figure 4 As shown in step ST7 , the second material film MF2 is provided above the opening H11 (ie, in a region overlapping the opening H11 in the thickness direction of the semiconductor substrate 10 ), and is not provided in other regions.

[0063] Next, if Figure 4 As shown in step ST8, the manufacturing apparatus forms a third material film MF3 on the front surface 10a side of the semiconductor substrate 10 so as to cover the second material film MF2 from above and below with the first material film MF1 and the third material film MF3. The third material film MF3 is a film that constitutes the aforementioned surrounding portion 30 (see FIG. Figure 1 ) and is made of, for example, SiN. The third material film MF3 has a film thickness of, for example, 20 nm.

[0064] In the process of forming the pixel separation portion 20, the process performed on the front surface 10a side of the semiconductor substrate 10 is as described above. Figure 4 As shown in step ST9, the back surface 10b of the semiconductor substrate 10 is processed to form the pixel separation unit 20. Before the back surface 10b of the semiconductor substrate 10 is processed, the insulating films 43 and 44 may be formed on the front surface 10a of the semiconductor substrate 10, or the via hole 50 may be formed. For example, after forming the third material film MF3, the manufacturing apparatus forms the insulating film 43 and performs chemical mechanical polishing (CMP) on the insulating film 43 to flatten the surface of the insulating film 43. The insulating film 43 is made of, for example, SiO.

[0065] Next, the manufacturing apparatus forms an insulating film 44 on the flat insulating film 43. The insulating film 44 is made of, for example, SiO. Thereafter, the manufacturing apparatus forms a via hole 50 that penetrates the insulating films 44 and 43, the third material film MF3, the first material film MF1, and the insulating films 42 and 41, and connects to the front surface 10a. This processing can be performed on the front surface 10a side of the semiconductor substrate 10.

[0066] like Figure 4 As shown in step ST9, for example, after forming the via hole 50, the manufacturing apparatus forms an insulating film 46 on the back surface 10b side of the semiconductor substrate 10. The insulating film 46 is, for example, a SiO film.

[0067] Next, if Figure 5 As shown in step ST10, the manufacturing apparatus forms a mask M3 on the insulating film 46. The mask M3 has a shape that exposes a predetermined region 20' and covers other regions. For example, in the thickness direction of the semiconductor substrate 10, a region 20" where the third material film MF3, the second material film MF2, and the first material film MF1 overlap (hereinafter referred to as an overlapping region) is located inside the predetermined region 20'. The mask M3 has a shape that exposes the overlapping region 20" and covers other regions.

[0068] Next, if Figure 5 As shown in step ST11, the manufacturing apparatus performs etching processing on the insulating film 46 on which the mask M3 is formed to remove the portion of the insulating film 46 exposed by the mask M3. Figure 5 As shown in step ST11 , the manufacturing apparatus forms a hard mask HM composed of an insulating film 46 .

[0069] Next, the manufacturing apparatus dry-etches the region of the semiconductor substrate 10 exposed by the hard mask HM on the back surface 10b of the semiconductor substrate 10. By dry etching, a trench 21 penetrating the semiconductor substrate 10 and the first material film MF1 and having the second material film MF2 as a bottom surface is formed.

[0070] Next, if Figure 5As shown in step ST12, the manufacturing apparatus performs wet etching on the semiconductor substrate 10 in which the trench 21 is formed, so as to remove the hard mask HM from the back side 10b of the semiconductor substrate 10. For example, since the hard mask HM is made of SiO, a chemical solution containing hydrofluoric acid (HF) is used for wet etching. In addition, similar to the hard mask HM, the second material film MF2 located at the bottom of the trench 21 is also made of SiO. Therefore, the second material film MF2 is also removed together with the hard mask HM by wet etching using a chemical solution containing HF. On the other hand, the first material film MF1 and the third material film MF3 are made of SiN and are therefore not etched by wet etching using a chemical solution containing hydrofluoric acid. Thus, the surrounding portion 30 composed of the first material film MF1 and the third material film MF3 is completed.

[0071] Next, the manufacturing apparatus fills the trench 21 with the separation film 22. Next, the manufacturing apparatus performs CMP processing on the surface of the separation film 22 to remove the separation film 22 from the region other than the trench 21 on the back surface 10b side of the semiconductor substrate 10. Figure 1 The light detecting device 1 shown is completed through the above-mentioned process.

[0072] (Advantageous Effects of the Implementation Method)

[0073] As described above, the light detecting device 1 according to the embodiment of the present disclosure includes a semiconductor substrate 10 having a front face 10a and a back face 10b located on the opposite side of the front face 10a, a plurality of pixels 12 arranged on the semiconductor substrate 10 and having a photodiode PD, an inter-pixel separation portion 20 arranged between adjacent one pixel 12 and another pixel 12 among the plurality of pixels 12 and passing through the front face 10a and the back face 10b of the semiconductor substrate 10, and a surrounding portion 30 arranged on the front face 10a side of the semiconductor substrate 10 and surrounding the end 20a of the inter-pixel separation portion 20, wherein the surrounding portion 30 is made of a material different from that of the semiconductor substrate 10.

[0074] For example, the semiconductor substrate 10 is made of single-crystal silicon (Si). The surrounding portion 30 is made of silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN). In addition, the mask M3 used when forming the trench 21 of the pixel separation portion 20 is made of silicon oxide (SiO).

[0075] Accordingly, the surrounding portion 30 is placed between the open end of the groove 21 of the inter-pixel separation portion 20 and the insulating films 41, 42, 43, and 44 covering the front surface 10a on the side of the semiconductor substrate 10. When the mask M3 is removed by wet etching, even if a chemical liquid (for example, a solution containing hydrofluoric acid (HF)) enters the front surface 10a of the semiconductor substrate 10 from the back surface 10b side of the semiconductor substrate 10 through the groove 21, the surrounding portion 30 can prevent the chemical liquid from contacting the insulating films 41, 42, 43, and 44.

[0076] Therefore, the chemical liquid used to remove the mask M3 can be prevented from penetrating from the open end of the groove 21 along the front surface 10a of the semiconductor substrate 10. The insulating films 41, 42, 43, and 44 covering the front surface 10a of the semiconductor substrate 10 and the via 50 connected to the front surface 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical liquid used to remove the mask M3, and the occurrence of poor contact of the via 50 due to penetration and corrosion of the chemical liquid can be suppressed. This makes it possible to suppress a reduction in the yield of the light detection device 1.

[0077] The manufacturing method of the light detecting device 1 according to the embodiment of the present disclosure includes a process of forming a first material film MF1 on the front surface 10a side of a semiconductor substrate 10 and covering a predetermined area 20' with the first material film MF1 from the front surface 10a side, the semiconductor substrate 10 having a front surface 10a and a back surface 10b located on the opposite side of the front surface 10a and having a plurality of pixels 12 provided with photodiodes PD, the predetermined area 20' being used to separate adjacent pixels 12 from each other among the plurality of pixels 12, and a process of forming a second material film MF2 on the opposite side of the predetermined area 20' with the first material film MF1 interposed therebetween. The process F2 includes forming a third material film MF3 on the opposite side of the first material film MF1 and covering the second material film MF2 with the first material film MF1 and the third material film MF3, forming a mask M3 on the back surface 10b side that has a shape that exposes a predetermined region 20' and covers areas other than the predetermined region 20', etching the predetermined region 20' exposed by the mask M3 from the back surface 10b side using the second material film MF2 as an etch stopper to form a trench 21 penetrating the semiconductor substrate 10 and the first material film MF1, and removing the mask M3 by wet etching after forming the trench 21. In the wet etching, a chemical liquid is used that easily etches the mask M3 and the second material film MF2 but has difficulty etching the first material film MF1 and the third material film MF3.

[0078] For example, the mask M3 and the second material film MF2 are made of silicon oxide. The first material film MF1 and the third material film MF3 are made of silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN). The chemical liquid used to remove the mask M3 contains hydrofluoric acid (HF).

[0079] Accordingly, even if a chemical liquid for removing the mask M3 enters the front face 10a side from the back face 10b side of the semiconductor substrate 10 through the groove 21 during the process of removing the mask M3, the surrounding portion 30 can prevent the chemical liquid from contacting the insulating films 41, 42, 43, and 44 covering the front face 10a side of the semiconductor substrate 10. Therefore, the chemical liquid for removing the mask M3 can be prevented from penetrating from the open end of the groove 21 along the front face 10a of the semiconductor substrate 10.

[0080] During the process of removing the mask M3, the insulating films 41, 42, 43, and 44 covering the front surface 10a of the semiconductor substrate 10 and the via 50 connected to the front surface 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical liquid used to remove the mask M3, and the occurrence of poor contact of the via 50 due to penetration or corrosion of the chemical liquid can be suppressed. This makes it possible to suppress a reduction in the yield of the light detection device 1.

[0081] As a comparative example of the present disclosure, a method of filling the trench with photoresist without pre-setting an enclosure when removing the mask can be considered. In the method of this comparative example, the resist is easily cracked, and the chemical liquid may penetrate into the front side of the semiconductor substrate through the cracks. In this case, since there is no enclosure below the trench, poor contact may occur due to erosion. On the other hand, in the embodiment of the present disclosure, the above-mentioned enclosure 30 is provided below the trench, so that the occurrence of poor contact due to erosion can be suppressed. In addition, in the embodiment of the present disclosure, when removing the mask M3, it is not necessary to fill the trench 21 with resist.

[0082] (Variation)

[0083] A number of modifications of the embodiments of the present disclosure will be described below. Figures 6 to 15 In the embodiment, the separation membrane 22 is omitted (refer to Figure 1 ) so that the shape of the surrounding portion 30 is easy to see.

[0084] (1) Modification 1

[0085] Figure 6 : is a cross-sectional view showing a light detecting device 1A according to Modification 1 of the embodiment of the present disclosure. Figure 6 The light detecting device 1A shown is Figure 1 The difference of the light detection device 1 shown is that no step portion G32 is provided on the inner side surface of the side portion 32 of the surrounding portion 30 (see FIG. Figure 1 ). This structure can be achieved by, for example, Figure 3 This is achieved by forming a mask M2 having a narrow width in step ST6 so that the mask M2 does not cover the edge of the opening H11.

[0086] In the optical detection device 1A having this form, as in the optical detection device 1, the insulating films 41, 42, 43 and 44 covering the front face 10a side of the semiconductor substrate 10 and the via 50 connected to the front face 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical liquid used to remove the mask, thereby suppressing a reduction in yield.

[0087] (2) Modification 2

[0088] Figure 7 2 is a cross-sectional view illustrating a light detecting device 1B- 1 according to Modification 2-1 of the embodiment of the present disclosure. Figure 8 2 is a cross-sectional view illustrating a light detecting device 1B-2 according to a modification 2-2 of the embodiment of the present disclosure. Figure 7 and Figure 8 The illustrated light detecting devices 1B-1 and 1B-2 differ from the light detecting devices 1 and 1A in that the line width W32 of the portion of the side portion 32 in contact with the front surface 10a of the semiconductor substrate 10 is increased toward the outside of the inter-pixel separator 20 (i.e., toward the pixel 12). The light detecting device 1B-2 is an example in which the line width W32 is further increased compared to the light detecting device 1B-1. For example, the side portion 32 extends over the entire surface of the pixel 12, excluding the region in contact with the via 50 or the region where the gate electrode (not shown) of the pixel transistor is arranged.

[0089] This structure can be achieved by, for example, Figure 3 This is achieved by forming an opening H11 wider than a predetermined region 20 ′ where the inter-pixel separation portion 20 is to be formed in step ST4 .

[0090] In the optical detection devices 1B-1 and 1B-2 having this form, as in the optical detection devices 1 and 1A, the insulating film covering the front face 10a side of the semiconductor substrate 10 and the via 50 connected to the front face 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical liquid used to remove the mask, thereby suppressing a reduction in yield.

[0091] Furthermore, since the horizontal distance from the groove 21 of the inter-pixel separation portion 20 to the insulating film can be increased in the light detection devices 1B-1 and 1B-2, the chemical liquid can be further prevented from penetrating in the horizontal direction from the groove 21, for example, Figure 5 When the hard mask HM is removed as shown in steps ST11 and ST12, for example, poor contact of the via hole 50 due to penetration or corrosion of the chemical liquid can be further suppressed, and the margin for poor contact can be further increased.

[0092] (3) Modification 3

[0093] Figure 9: is a cross-sectional view showing a configuration example of a light detection device 1C according to Modification 3 of the embodiment of the present disclosure. Figure 9 The illustrated light detecting device 1C differs from the aforementioned light detecting devices 1 and 1A in that the surrounding portion 30 is formed so as to be buried in the semiconductor substrate 10. For example, the edge of the trench 21 is dug into the front surface 10a of the semiconductor substrate 10 by a depth d. The side portions 32 of the surrounding portion 30 are provided at the dug-in edge of the trench 21.

[0094] This structure can be achieved by, for example, Figure 2 This is achieved by etching and digging the semiconductor substrate 10 from the front surface 10 a side using the insulating film 42 as a mask and forming the first material film MF1 on the front surface 10 a side of the dug-in semiconductor substrate 10 in step ST3 .

[0095] In the optical detection device 1C having this form, as in the optical detection devices 1 and 1A, the insulating film covering the front face 10a side of the semiconductor substrate 10 and the via 50 connected to the front face 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical liquid used to remove the mask, thereby suppressing a reduction in yield.

[0096] In addition, in the process of manufacturing the light detection device 1C, since the front surface 10a side of the semiconductor substrate 10 is previously dug, Figure 5 In step ST11, the etching depth of the trench 21 formed on the back surface 10b side can be reduced. This facilitates the formation of the trench 21 even if the thickness of the semiconductor substrate 10 increases.

[0097] (4) Modification 4

[0098] Figure 10 4 is a cross-sectional view showing a light detecting device 1D-1 according to Modification 4-1 of the embodiment of the present disclosure. Figure 11 4 is a cross-sectional view illustrating a light detecting device 1D-2 according to Modification 4-2 of the embodiment of the present disclosure. Figure 10 and Figure 11 The illustrated light detecting devices 1D-1 and 1D-2 differ from the aforementioned light detecting devices 1 and 1A in the thickness T31 of the bottom 31 of the surrounding portion 30. The light detecting device 1D-1 is an example in which the thickness T31 of the bottom 31 is increased (i.e., the bottom 31 has an increased thickness). The light detecting device 1D-2 is an example in which the thickness T31 of the bottom 31 is decreased (i.e., the bottom 31 has a decreased thickness).

[0099] As shown in the light detecting devices 1D-1 and 1D-2, the bottom 31 of the surrounding portion 30 can be made thick or thin. The thickness of the bottom 31 is determined by, for example, Figure 4 The thickness of the third material film MF3 formed in step ST8 is adjusted.

[0100] In the photodetecting devices 1D-1 and 1D-2 having such configurations, as in the photodetecting devices 1 and 1A, the insulating film covering the front surface 10a of the semiconductor substrate 10 and the via 50 connected to the front surface 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical solution used for mask removal, thereby suppressing a decrease in yield. Furthermore, since the bottom portion 31 can be made thicker or thinner, for example, the film thickness margin of the third material film MF3 can be increased.

[0101] (5) Modification 5

[0102] Figure 12 5 is a cross-sectional view showing a light detecting device 1E-1 according to Modification 5-1 of the embodiment of the present disclosure. Figure 13 5 is a cross-sectional view showing a light detecting device 1E-2 according to Modification 5-2 of the embodiment of the present disclosure. Figure 12 and Figure 13 The illustrated light detecting devices 1E-1 and 1E-2 differ from the aforementioned light detecting devices 1 and 1A in the thickness T33 of the space 33 inside the enclosure 30. The light detecting device 1E-1 is an example in which the depth T33 of the space 33 is increased. The light detecting device 1E-2 is an example in which the depth T33 of the space 33 is decreased.

[0103] As shown in the light detecting devices 1E-1 and 1E-2, the space 33 of the surrounding portion 30 can be deep or shallow. The depth of the space 33 is determined by, for example, Figure 3 The thickness of the second material film MF2 formed in step ST5 is adjusted.

[0104] In the light detecting devices 1E-1 and 1E-2 having these configurations, as in the light detecting devices 1 and 1A, the insulating film covering the front surface 10a of the semiconductor substrate 10 and the via 50 connected to the front surface 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical solution used for mask removal, thereby suppressing a decrease in yield. Furthermore, since the space 33 can be made deep or shallow, the film thickness margin of the second material film MF2 can be increased.

[0105] (6) Modification 6

[0106] Figure 14 : is a cross-sectional view showing a light detecting device 1F-1 according to Modification 6-1 of the embodiment of the present disclosure. Figure 15 : is a cross-sectional view showing a light detecting device 1F-2 according to Modification 6-2 of the embodiment of the present disclosure. Figure 14 and Figure 15The illustrated light detecting devices 1F-1 and 1F-2 differ from the aforementioned light detecting devices 1 and 1A in the width of the space 33 inside the enclosure 30. The light detecting device 1F-1 is an example in which the width of the space 33 is increased. The light detecting device 1F-2 is an example in which the width of the space 33 is decreased.

[0107] As shown in the light detecting devices 1F-1 and 1F-2, in the space 33 of the surrounding portion 30, the width W33 of the area close to the bottom 31 can be increased or decreased. The width W33 of the area close to the bottom 31 can be increased or decreased by, for example, Figure 3 The line width of the mask M2 formed in step ST6 (ie, Figure 4 The line width of the second material film MF2 shown in step ST7 is adjusted.

[0108] In the photodetection devices 1F-1 and 1F-2 having these configurations, as in the photodetection devices 1 and 1A, the insulating film covering the front surface 10a of the semiconductor substrate 10 and the via 50 connected to the front surface 10a of the semiconductor substrate 10 can be prevented from being corroded by the chemical solution used for mask removal, thereby suppressing a decrease in yield. Furthermore, since the line width of the second material film MF2 can be increased or decreased, the line width margin of the second material film MF2 can be increased.

[0109] <Application Examples>

[0110] The technology disclosed herein can be applied to various light detection devices, such as indirect ToF (Time of Flight) ranging sensors, direct ToF ranging sensors, and CMOS image sensors. The following shows several examples to which the technology disclosed herein can be applied.

[0111] (1) Application Example 1: Application of indirect ToF ranging sensors

[0112] Application Example 1 is an example of applying the technology of this disclosure to an imaging element (light-receiving element) that constitutes a distance-measuring sensor that uses an indirect ToF method to measure distances, and an imaging device that includes such an imaging element. For example, the distance-measuring sensor can be applied to an in-vehicle system that is installed in a vehicle and measures the distance to objects outside the vehicle, or a gesture recognition system that measures the distance to an object such as a user's hand and recognizes the user's gestures based on the measurement results. In this case, the results of gesture recognition can be used, for example, to operate a car navigation system.

[0113] (1-1) Application Example 1-1

[0114] Figure 16 1 is a diagram illustrating a configuration of an imaging element according to Application Example 1-1 of the present disclosure. Figure 16The imaging element 111 shown is a backside-illuminated current-assisted photon demodulator (CAPD) sensor, which is included in an imaging device with distance measurement capabilities. A CAPD is an indirect time-of-flight distance sensor that applies a voltage directly to the sensor substrate to generate a current within the substrate, enabling rapid modulation of a large area within the substrate, for example.

[0115] The imaging element 111 includes a pixel array section 121 formed on a semiconductor substrate (not shown) and peripheral circuits integrated on the same semiconductor substrate as the pixel array section 121. The peripheral circuits include, for example, a vertical drive section 122, a column processing section 123, a horizontal drive section 124, and a system control section 125.

[0116] The imaging element 111 is also provided with a signal processing section 126 and a data storage section 127. The signal processing section 126 and the data storage section 127 may be mounted on the same substrate as the imaging element 111, or may be provided on a substrate different from the imaging element 111 in the imaging device.

[0117] The pixel array section 121 has a configuration in which unit pixels (hereinafter referred to as "pixels"), which generate charge corresponding to the amount of received light and output signals corresponding to the charge, are arranged in rows and columns, i.e., in a two-dimensional matrix. Specifically, the pixel array section 121 includes a plurality of pixels that perform photoelectric conversion on incident light and output signals corresponding to the charge obtained as a result of the photoelectric conversion.

[0118] Here, the row direction is the direction in which pixels in a pixel row are arranged (i.e., horizontally), and the column direction is the direction in which pixels in a pixel column are arranged (i.e., vertically). That is, in the figure, the row direction is horizontal, and the column direction is vertical.

[0119] In the pixel array section 121, in a matrix-shaped pixel array, a pixel drive line 128 is arranged along the row direction for each pixel row, and two vertical signal lines 129 are arranged along the column direction for each pixel column. For example, the pixel drive line 128 transmits a drive signal for driving when reading a signal from a pixel. Note that although Figure 16 , one wiring line is shown as the pixel drive line 128 , but the present disclosure is not limited to one line. One end of the pixel drive line 128 is connected to the output terminal corresponding to each row of the vertical drive unit 122 .

[0120] The vertical drive section 122 is composed of a shift register, an address decoder, and the like, and simultaneously drives all pixels of the pixel array section 121 in units of rows, etc. Specifically, the vertical drive section 122 and the system control section 125 that controls the vertical drive section 122 together constitute a drive section that controls the operation of each pixel of the pixel array section 121 .

[0121] In indirect ToF distance measurement, the number of elements (CAPD elements) connected to one control line and performing high-speed driving affects the controllability of high-speed driving and the accuracy of driving. Many solid-state image sensors used for indirect ToF distance measurement have a pixel array that is long in the horizontal direction. Therefore, in this case, the vertical signal line 129 or other vertically long control lines can be used as the control line of the element that performs high-speed driving. In this case, for example, a plurality of pixels arranged in the vertical direction are connected to the vertical signal line 129 or other vertically long control lines, and the pixels are driven by a drive section or a horizontal drive section 124 that is set separately from the vertical drive section 122 via the vertical signal line 129 or other control lines, that is, the CAPD sensor is driven.

[0122] The signals output from each pixel in the pixel row in response to the drive control of the vertical drive section 122 are input to the column processing section 123 via the vertical signal line 129. The column processing section 123 performs predetermined signal processing on the signals output from each pixel via the vertical signal line 129, and temporarily holds the pixel signals after the signal processing. Specifically, the column processing section 123 performs noise removal processing, analog-to-digital (AD) conversion processing, and the like as signal processing.

[0123] The horizontal drive unit 124 is composed of a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 123. As a result of selective scanning by the horizontal drive unit 124, pixel signals processed for each unit circuit in the column processing unit 123 are sequentially output.

[0124] The system control unit 125 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical drive unit 122 , the column processing unit 123 , the horizontal drive unit 124 , and the like based on the various timings generated by the timing generator.

[0125] The signal processing unit 126 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing based on the pixel signal output from the column processing unit 123. The data storage unit 127 temporarily stores data required for signal processing in the signal processing unit 126 when performing signal processing.

[0126] Next, a configuration example of the pixels provided in the pixel array section 121 will be described. For example, the pixels provided in the pixel array section 121 are as follows: Figure 17 As shown.

[0127] Figure 17 1 is a cross-sectional view showing the configuration of the pixel array section 121 according to Application Example 1-1 of the present disclosure. Figure 17The figure shows a cross section of one pixel 151 provided in pixel array section 121. Pixel 151 receives and photoelectrically converts externally incident light, particularly infrared light, and outputs a signal corresponding to the generated charge. Pixel 151 includes, for example, a silicon substrate (i.e., substrate 161 (an example of a "semiconductor substrate" in this disclosure), which is a P-type semiconductor substrate composed of a P-type semiconductor region) and an on-chip lens 162 formed on substrate 161.

[0128] In the figure, on the upper surface of substrate 161, that is, on the surface of substrate 161 on which light from the outside is incident (an example of a "second surface" in this disclosure; hereinafter also referred to as the incident surface), an on-chip lens 162 is formed to collect light incident from the outside and allow it to enter substrate 161. In addition, in pixel 151, an inter-pixel light shielding portion 163 is formed at the end of pixel 151 on the light incident surface of substrate 161 to prevent color mixing between adjacent pixels.

[0129] In this example, light from the outside is incident on the inside of the substrate 161 via the on-chip lens 162, but the light incident from the outside passes through the on-chip lens 62 and a portion of the substrate 161 and is prevented from being incident on regions of other pixels disposed adjacent to the pixel 151 on the substrate 161. That is, light that is incident on the on-chip lens 162 from the outside and is guided into the other pixels adjacent to the pixel 151 is blocked by the inter-pixel light shielding portion 163 and does not therefore become incident on the other adjacent pixels.

[0130] Since the imaging element 111 is a back-illuminated CAPD sensor, the light incident surface of the substrate 161 is the so-called back surface, and a wiring layer composed of wiring and the like is not formed on the back surface. In addition, on the surface of the substrate 161 opposite to the light incident surface, a wiring layer is formed in a stacked manner, in which wiring for driving transistors and the like within the pixels 151, wiring for reading signals from the pixels 151, and the like are formed.

[0131] An oxide film 164 and a signal extraction portion 165 called a tap are formed on the side of the substrate 161 opposite to the incident surface (an example of “first surface” in this disclosure), that is, inside the lower surface in the drawing.

[0132] In this example, the oxide film 164 is formed in the center portion of the pixel 151 near the surface of the substrate 161 opposite to the light incident surface, and the signal extraction unit 165 is formed at both ends of the oxide film 164 .

[0133] Here, the signal extraction unit 165 includes an N- semiconductor region 172 having a lower donor impurity concentration than an N+ semiconductor region 171, which is an N-type semiconductor region, a P+ semiconductor region 173, which is a P-type semiconductor region, and a P- semiconductor region 174 having a lower acceptor impurity concentration than the P+ semiconductor region 173. Here, the donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) and arsenic (As) for Si. The acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B) for Si. Elements used as donor impurities will be referred to as donor elements, and elements used as acceptor impurities will be referred to as acceptor elements.

[0134] Furthermore, a separation portion 175 for separating the N + semiconductor region 171 and the P + semiconductor region 173 from each other is formed by an oxide film or the like between regions in the substrate 161 .

[0135] The N+ semiconductor region 171 provided in the substrate 161 serves as a charge detection portion for detecting the amount of light incident on the pixel 151 from the outside, that is, the amount of signal carriers generated by photoelectric conversion in the substrate 161. In addition to the N+ semiconductor region 171, the charge detection portion can also be considered to include an N- semiconductor region 172 having a low donor impurity concentration. Furthermore, the P+ semiconductor region 173 serves as a voltage application portion for injecting majority carrier current into the substrate 161, that is, directly applying a voltage to the substrate 161 to generate an electric field within the substrate 161. Note that in addition to the P+ semiconductor region 173, the P- semiconductor region 174 having a low acceptor impurity concentration can also be considered as a voltage application portion.

[0136] exist Figure 17 In each of the multiple pixels 151 shown, a floating diffusion (FD) portion (hereinafter also referred to as FD portion A) which is a floating diffusion region not shown is directly connected to one of the two N+ semiconductor regions 171, and the FD portion A is connected to the vertical signal line 129 via an amplifying transistor not shown, etc.

[0137] Similarly, another FD portion different from the FD portion A (hereinafter also referred to as the FD portion B) is directly connected to the other of the two N+ semiconductor regions 171, and the FD portion B is connected to the vertical signal line 129 via an amplifying transistor or the like not shown. The FD portion A and the FD portion B are connected to different vertical signal lines 129.

[0138] For example, when the distance to an object is to be measured by an indirect ToF method, infrared light is emitted from an imaging device provided with an imaging element 111 toward the object. Then, when the infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 161 of the imaging element 111 receives and photoelectrically converts the incident reflected light (infrared light). At this time, the vertical drive section 122 drives the pixel 151 and distributes a signal based on the charge obtained due to the photoelectric conversion to the FD section A and the FD section B. As described above, the pixel 151 can be driven not by the vertical drive section 122 but by a separately provided drive section or the horizontal drive section 124 via the vertical signal line 129 or other vertically long control line.

[0139] For example, at a certain moment, the vertical drive unit 122 applies a voltage to the two P+ semiconductor regions 173 via a contact portion or the like. Specifically, for example, the vertical drive unit 122 applies a voltage of 1.5 V to one of the two P+ semiconductor regions 173 provided in the pixel 151, and applies a voltage of 0 V to the other P+ semiconductor region 173. An electric field is then generated between the two P+ semiconductor regions 173 in the substrate 161, and current flows from one P+ semiconductor region 173 to the other P+ semiconductor region 173. In this case, holes in the substrate 161 move toward the other P+ semiconductor region 173, and electrons move toward one P+ semiconductor region 173.

[0140] Therefore, in this state, when infrared light (reflected light) from the outside is incident on the substrate 161 via the on-chip lens 162 and the infrared light is photoelectrically converted into electron-hole pairs within the substrate 161, the obtained electrons are guided by the electric field between the P+ semiconductor regions 173 along the direction of a P+ semiconductor region 173 and move to an N+ semiconductor region 171 adjacent to the P+ semiconductor region 173 via the separation portion 175.

[0141] In this case, the electrons generated by the photoelectric conversion are used as signal carriers for detecting a signal according to the amount of infrared light incident on the pixel 151 (i.e., the amount of received infrared light). Therefore, charges corresponding to the electrons that have moved into one N+ semiconductor region 171 are accumulated in one N+ semiconductor region 171, and these charges are detected by the column processing section 123 via the FD section A, the amplifying transistor, the vertical signal line 129, and the like.

[0142] That is, the charges accumulated in one N+ semiconductor region 171 are transferred to the FD portion A directly connected to the one N+ semiconductor region 171, and a signal corresponding to the charges transferred to the FD portion A is read out by the column processing portion 123 via the amplifying transistor and the vertical signal line 129. Then, the column processing portion 123 performs processing such as AD conversion on the readout signal, and supplies a pixel signal obtained as a result of the processing to the signal processing portion 126.

[0143] The pixel signal is a signal indicating the amount of charge corresponding to electrons detected by one N+ semiconductor region 171 , that is, the amount of charge accumulated in the FD portion A. In other words, the pixel signal may be a signal indicating the amount of infrared light received by the pixel 151 .

[0144] In this case, similarly to the case of one N+ semiconductor region 171 , a pixel signal based on electrons detected by another N+ semiconductor region 171 adjacent to another P+ semiconductor region 173 via the separator 175 can be appropriately used for distance measurement.

[0145] Furthermore, at the next moment, a voltage is applied to the two P+ semiconductor regions 173 via the contact portion by the vertical drive section 122, so that an electric field is generated in a direction opposite to the electric field generated so far in the substrate 161. Specifically, for example, a voltage of 1.5 V is applied to the other of the two P+ semiconductor regions 173 provided in the pixel 151, and a voltage of 0 V is applied to one of the P+ semiconductor regions 173.

[0146] As a result, an electric field is generated between the two P+ semiconductor regions 173 in the substrate 161, and current flows from the other P+ semiconductor region 173 to one P+ semiconductor region 173. In this state, when infrared light (reflected light) from the outside is incident on the substrate 161 via the on-chip lens 162 and the infrared light is photoelectrically converted into electron-hole pairs within the substrate 161, the resulting electrons are guided in the direction of the other P+ semiconductor region 173 by the electric field between the P+ semiconductor regions 173 and move into the other N+ semiconductor region 171. Therefore, charges corresponding to the electrons that have moved into the other N+ semiconductor region 171 are accumulated in the other N+ semiconductor region 171, and these charges are detected by the column processing section 123 via the FD section B, the amplifier transistor, the vertical signal line 129, and the like.

[0147] That is, the charges accumulated in the other N+ semiconductor region 171 are transferred to the FD portion B directly connected to the other N+ semiconductor region 171, and a signal corresponding to the charges transferred to the FD portion B is read out by the column processing portion 123 via the amplifying transistor and the vertical signal line 129. Then, the column processing portion 123 performs processing such as AD conversion on the readout signal, and supplies a pixel signal obtained as a result of the processing to the signal processing portion 126.

[0148] In this case, similarly to the case of the other N + semiconductor region 171 , a pixel signal according to electrons detected by one N + semiconductor region 171 can be appropriately used for distance measurement.

[0149] In this way, when pixel signals are obtained through photoelectric conversion performed in different periods in the same pixel 151, the signal processing unit 126 calculates distance information indicating the distance to the object based on the pixel signals and outputs the distance information to the next stage. This method of distributing signal carriers to different N+ semiconductor regions 171 and calculating distance information based on the signals corresponding to these signal carriers is called an indirect ToF method.

[0150] Although an example has been described here in which the vertical drive unit 122 controls the application of voltage to the P+ semiconductor region 173, as described above, the imaging element 111 can be provided with a drive unit (block) serving as a voltage application control unit separately from the vertical drive unit 122, which is used to control the application of voltage to the P+ semiconductor region 173.

[0151] Furthermore, in this example, a buried separation region is formed in the pixel 151. For example, Figure 17 As shown in FIG. 1 , a pixel separation portion 20 is provided that penetrates the entire substrate 161. Figure 17 In the illustrated pixel 151 , an inter-pixel separation portion 20 penetrating the entire substrate 161 is formed in the substrate 161 at a boundary portion between the pixel 151 and another pixel 151 adjacent to the pixel 151 .

[0152] For example, when forming the inter-pixel separator 20, a groove 21 is formed from the surface on the light incident side of the substrate 161 (i.e., the upper surface in the figure). At this time, the groove is formed to penetrate the substrate 161. Then, a separation film 22 such as a light-shielding film is formed by embedding in the groove portion formed in this manner to form the inter-pixel separator 20. This embedded inter-pixel separator 20 can improve the separation characteristics of infrared light between pixels and can suppress the occurrence of color mixing.

[0153] Furthermore, a surrounding portion 30, which surrounds the end of the inter-pixel isolation portion 20, is provided on the surface of the substrate 161 opposite the light incident surface, i.e., the lower side in the figure. The surrounding portion 30 is covered from below by, for example, an interlayer insulating film 181 of the multilayer wiring layer arranged on the lower side in the figure. As in the above-described embodiment, in this application example 1-1, the surrounding portion 30 is made of a material different from that of the substrate 161, for example, silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN).

[0154] In the above-described application example 1-1, the surrounding portion 30 is also formed in advance when the trench 21 is formed. Therefore, as in the above-described embodiment, when the hard mask (e.g., SiO) used when forming the trench 21 is removed, the insulating film (e.g., the interlayer insulating film 181) covering the side opposite to the light incident surface of the substrate 161 and the through hole connected to the side opposite to the light incident surface of the substrate 161 can be prevented from being corroded by the chemical solution used for removing the hard mask, thereby suppressing a decrease in yield.

[0155] (1-2) Application Example 1-2

[0156] Figure 18 This is a cross-sectional view illustrating the configuration of a pixel array portion of a light receiving element 201 according to Application Example 1-2 of the present disclosure. Light receiving element 201 includes a semiconductor substrate 241 and a multilayer wiring layer 242 formed on the front surface (an example of a "first surface" in this disclosure) side (the lower side in the figure) of semiconductor substrate 241.

[0157] The semiconductor substrate 241 is made of, for example, silicon (Si) and has a thickness of, for example, 1 to 6 μm. In the semiconductor substrate 241, for example, an N-type (second conductivity type) semiconductor region 252 is formed within a P-type (first conductivity type) semiconductor region 251 of a unit pixel, thereby forming a photodiode PD for the unit pixel. The P-type semiconductor regions 251 provided on the front and back surfaces of the semiconductor substrate 241 also function as hole charge accumulation regions to suppress dark current.

[0158] Figure 18 The upper surface of the semiconductor substrate 241 located on the upper side is the back surface of the semiconductor substrate 241 and is a light incident surface into which light is incident. An anti-reflection film 243 is formed on the upper surface of the back surface side of the semiconductor substrate 241 .

[0159] The anti-reflection film 243 has a stacked structure in which, for example, a fixed charge film and an oxide film are stacked, and a high dielectric constant (high-k) insulating film formed according to an atomic layer deposition (ALD) method can be used as the anti-reflection film 243. Specifically, hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), or strontium titanium oxide (STO) can be used. Figure 18In the example of FIG, the antireflection film 243 is formed by stacking a hafnium oxide film 253, an aluminum oxide film 254, and a silicon oxide film 255.

[0160] On the upper surface of the anti-reflection film 243, an inter-pixel light-shielding film 245 is formed at the boundary portion 244 (hereinafter also referred to as the pixel boundary portion 244) between adjacent pixels 210 of the semiconductor substrate 241 to prevent incident light from entering the adjacent pixels. The material of the inter-pixel light-shielding film 245 can be any material as long as it can block light, and for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu) can be used.

[0161] For example, on top of the anti-reflection film 243 and on top of the inter-pixel light shielding film 245, the planarization film 246 is formed of an insulating film such as silicon oxide (SiO), silicon nitride (SiN) or silicon oxynitride (SiON) or an organic material such as resin.

[0162] Furthermore, an on-chip lens 247 is formed for each pixel on the upper surface of the planarization film 246. The on-chip lens 247 is formed of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a silicone resin. Light collected by the on-chip lens 247 is efficiently incident on the photodiode PD.

[0163] In addition, at the pixel boundary portion 244 on the back side of the semiconductor substrate 241, an inter-pixel separation portion 20 is formed in the depth direction of the semiconductor substrate 241 to separate adjacent pixels from each other, from the back side of the semiconductor substrate 241 (on-chip lens 247 side) to a predetermined depth in the depth direction of the substrate.

[0164] The pixel separator 20 is formed by forming a trench extending from the back side (on-chip lens 247 side) of the semiconductor substrate 241 to the front side on the opposite side, and embedding a silicon oxide film 255 (an example of a "separation film" in this disclosure), which is the uppermost layer material of the anti-reflection film 243, in the trench. In addition to insulating films such as the silicon oxide film 255, the material embedded in the trench as the pixel separator 20 can also be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN).

[0165] By forming such an inter-pixel separator 20 , adjacent pixels can be completely electrically separated from each other, thereby preventing incident light from passing through adjacent pixels 210 and being captured within the corresponding pixels, and preventing incident light from leaking from adjacent pixels 210 .

[0166] On the other hand, on the front side of the semiconductor substrate 241 on which the multilayer wiring layer 242 is formed, two transfer transistors TRG1 and TRG2 are formed for each photodiode PD formed in each pixel 210. In addition, on the front side of the semiconductor substrate 241, floating diffusion regions FD1 and FD2, which serve as charge accumulation portions for temporarily storing charge transferred from the photodiode PD, are formed as high-concentration N-type semiconductor regions (N-type diffusion regions).

[0167] The multilayer wiring layer 242 is composed of a plurality of metal films MT and interlayer insulating films 262 therebetween. Figure 18 An example is shown in which the multilayer wiring layer 242 is composed of three layers, ie, the first metal film MT1 to the third metal film MT3 .

[0168] In an area below the area where the photodiode PD is formed in the first metal film MT1 closest to the semiconductor substrate 241 among the multiple metal films MT of the multilayer wiring layer 242, in other words, in an area partially overlapping with the area where the photodiode PD is formed in a plan view, a metal wiring made of copper, aluminum, etc. is formed as a shading member 263.

[0169] The light shielding member 263 uses the first metal film MT1 closest to the semiconductor substrate 241 to block infrared light that enters the semiconductor substrate 241 from the light incident surface via the on-chip lens 247 and passes through the semiconductor substrate 241 without undergoing photoelectric conversion within the semiconductor substrate 241. Furthermore, the light shielding member 263 prevents infrared light from passing through the second metal film MT2 and the third metal film MT3 below the first metal film MT1. This light shielding function prevents infrared light that passes through the semiconductor substrate 241 without undergoing photoelectric conversion within the semiconductor substrate 241 from being scattered by the metal film MT below the first metal film MT1 and incident on surrounding pixels. Consequently, erroneous light detection in surrounding pixels can be prevented.

[0170] The light shielding member 263 also functions to reflect infrared light that enters the semiconductor substrate 241 from the light incident surface via the on-chip lens 247 and passes through the semiconductor substrate 241 without undergoing photoelectric conversion within the semiconductor substrate 241, causing it to re-enter the semiconductor substrate 241. Therefore, the light shielding member 263 can also be said to be a reflective member. This reflective function increases the amount of infrared light that undergoes photoelectric conversion within the semiconductor substrate 241, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel 210 to infrared light.

[0171] Note that the light blocking member 263 may be formed to have a structure that achieves reflection or light blocking using polysilicon, an oxide film, or the like in addition to a metal material.

[0172] In addition, the light shielding member 263 may be composed of a plurality of metal films MT. For example, the light shielding member 263 may be formed in a lattice shape by the first metal film MT1 and the second metal film MT2 instead of being composed of one metal film MT.

[0173] For example, the wiring capacitor 264 is formed by patterning a comb-teeth shape in a predetermined metal film MT (e.g., the second metal film MT2) among the plurality of metal films MT of the multilayer wiring layer 242. Although the light shielding member 263 and the wiring capacitor 264 can be formed in the same layer (metal film MT), when they are formed in different layers, the wiring capacitor 264 is formed in a layer farther from the semiconductor substrate 241 than the light shielding member 263. In other words, the light shielding member 263 is formed closer to the semiconductor substrate 241 than the wiring capacitor 264.

[0174] As described above, the light receiving element 201 has a back-illuminated structure in which the semiconductor substrate 241 as a semiconductor layer is arranged between the on-chip lens 247 and the multilayer wiring layer 242, and incident light is incident on the photodiode PD from the back side where the on-chip lens 247 is formed.

[0175] Furthermore, the pixel 210 includes two transfer transistors TRG1 and TRG2 for the photodiode PD provided for each pixel, and is configured to be able to distribute charges (electrons) generated by photoelectric conversion by the photodiode PD to the floating diffusion region FD1 or FD2 .

[0176] Furthermore, since the inter-pixel separation portion 20 is formed at the pixel boundary portion 244, the pixel 210 prevents incident light from passing through an adjacent pixel 210 and being captured within the pixel itself, and prevents incident light from leaking from the adjacent pixel 210. Furthermore, by providing the light shielding member 263 in the metal film MT below the region where the photodiode PD is formed, infrared light that has passed through the semiconductor substrate 241 but has not been photoelectrically converted within the semiconductor substrate 241 is reflected by the light shielding member 263 and then enters the semiconductor substrate 241 again.

[0177] With the above configuration, the amount of infrared light photoelectrically converted in the semiconductor substrate 241 can be increased, and the quantum efficiency (QE), that is, the sensitivity of the pixel 210 to infrared light can be improved.

[0178] Furthermore, a surrounding portion 30, which surrounds the end of the inter-pixel separator 20, is provided on the surface of the semiconductor substrate 241 opposite the light incident surface, i.e., the lower side in the figure. The surrounding portion 30 is covered from below by an interlayer insulating film 262 or the like disposed on the lower side in the figure. Similar to the above-described embodiment, in this application example 1-2, the surrounding portion 30 is made of a material different from that of the semiconductor substrate 241, for example, silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN).

[0179] In the above-described application example 1-2, the surrounding portion 30 is also formed in advance when the groove 21 for the inter-pixel separation portion 20 is formed. Therefore, as in the above-described embodiment, when the hard mask (e.g., SiO) used when forming the groove 21 is removed, the insulating film (e.g., the interlayer insulating film 262) covering the side opposite to the light incident surface of the semiconductor substrate 241 and the through hole connected to the side opposite to the light incident surface of the semiconductor substrate 241 can be prevented from being corroded by the chemical solution used for removing the hard mask, thereby suppressing a decrease in yield.

[0180] (1-3) Application Example 1-3

[0181] Figure 19 This is a cross-sectional view showing the configuration of a pixel array portion of a light receiving element 201A according to Application Example 1-3 of the present disclosure. Application Example 1-3 is a modification of Application Example 1-2. Application Example 1-3 differs from Application Example 1-2 in that the PD upper region 223 has a substrate interface with a moth-eye structure and an anti-reflection film 221.

[0182] In the light receiving element according to Application Example 1-3, the PD upper region 223 located above the photodiode PD formation region of the semiconductor substrate 241 (the P-type semiconductor region 51) has a moth-eye structure formed with fine concave and convex portions. In addition, the anti-reflection film 221 formed thereon is also formed into a moth-eye structure corresponding to the moth-eye structure of the PD upper region 223 of the semiconductor substrate 241. Figure 18 ), the anti-reflection film 221 is formed by stacking a hafnium oxide film 253, an aluminum oxide film 254, and a silicon oxide film 255.

[0183] In this manner, by forming the PD upper region 223 of the semiconductor substrate 241 in the moth-eye structure, it is possible to alleviate a sudden change in the refractive index at the substrate interface and reduce the influence of reflected light.

[0184] In Application Example 1-3, the pixel separation portion 20 and the surrounding portion 30 have the same configuration as in Application Example 1-2. The effects of preventing chemical liquid corrosion during hard mask removal and suppressing yield reduction by preventing corrosion are similar to those in Application Example 1-2.

[0185] (2) Application Example 2: Application of Direct ToF Distance Measurement Sensor

[0186] Application Example 2 is an example in which the technology of the present disclosure is applied to an imaging element (light receiving element) constituting a distance measuring sensor that performs distance measurement using a direct ToF method, an imaging device having such an imaging element, and the like.

[0187] (2-1) Application Example 2-1

[0188] Figure 20 : is a cross-sectional view showing the configuration of a sensor chip 311 according to Application Example 2-1 of the present disclosure. The sensor chip 311 is an imaging element (light receiving element) constituting a distance measuring sensor that performs distance measurement by a direct ToF method. Figure 20 The configuration of the sensor chip 311 will be described.

[0189] like Figure 20 As shown, the sensor chip 311 has a stacked structure in which a sensor substrate 341 (an example of a "semiconductor substrate" in the present disclosure), a sensor side wiring layer 342, and a logic side wiring layer 343 are stacked, and for the logic side wiring layer 343, a logic circuit substrate not shown is stacked. For example, a bias voltage application portion, a p-type MOSFET, a CMOS inverter, etc. are formed on the logic circuit substrate. For example, the sensor chip 311 can be manufactured by the following manufacturing method: forming the sensor side wiring layer 342 on the sensor substrate 341, forming the logic side wiring layer 343 on the logic circuit substrate, and then bonding the sensor side wiring layer 342 to the logic circuit substrate at the bonding surface ( Figure 20 The sensor side wiring layer 342 and the logic side wiring layer 343 are bonded to the surface (shown by the dotted line).

[0190] The sensor substrate 341 is, for example, a semiconductor substrate obtained by slicing single crystal silicon and has a controlled p-type or n-type impurity concentration, and forms a single photon avalanche diode (SPAD) element 331 for each SPAD pixel 321. Figure 20 In the embodiment, the upward-facing surface of the sensor substrate 341 serves as a light-receiving surface for receiving light, and the sensor-side wiring layer 342 is stacked on the surface opposite the light-receiving surface. The light-receiving surface is an example of a "second surface" in this disclosure. The surface opposite the light-receiving surface is a "first surface" in this disclosure.

[0191] Wiring for supplying a voltage to be applied to the SPAD element 331 , wiring for extracting electrons generated in the SPAD element 311 from the sensor substrate 341 , and the like are formed in the sensor-side wiring layer 342 and the logic-side wiring layer 343 .

[0192] The SPAD element 331 includes an N-well 351, a P-type diffusion layer 352, an N-type diffusion layer 353, a hole accumulation layer 354, a pinning layer 355, and a high-concentration P-type diffusion layer 356 formed in the sensor substrate 341. Furthermore, a depletion layer formed in the region where the P-type diffusion layer 352 and the N-type diffusion layer 353 are connected forms an avalanche multiplication region 357 in the SPAD element 331.

[0193] The N-well 351 is formed by controlling the impurity concentration of the sensor substrate 341 to be N-type, and forms an electric field by which electrons generated by photoelectric conversion in the SPAD element 331 are transferred to the avalanche multiplication region 357. Note that, instead of the N-well 351, a P-well may be formed by controlling the impurity concentration of the sensor substrate 341 to be P-type.

[0194] The P-type diffusion layer 352 is located near the front surface of the sensor substrate 341 and on the back surface side relative to the N-type diffusion layer 353 ( Figure 20 A heavily doped P-type diffusion layer (P+) is formed on the upper side of the SPAD element 331 and is formed to extend over substantially the entire surface of the SPAD element 331.

[0195] The N-type diffusion layer 353 is located near the front surface of the sensor substrate 341 and is located on the front side relative to the P-type diffusion layer 352 ( Figure 20 A heavily doped N-type diffusion layer (N+) is formed on the lower side of the sensor substrate 341 and is formed to extend over substantially the entire surface of the SPAD element 331. Furthermore, the N-type diffusion layer 353 has a convex shape such that a portion thereof extends to the front of the sensor substrate 341 so as to be connected to a contact electrode 371 for supplying a negative voltage to form the avalanche multiplication region 357.

[0196] Hole accumulation layer 354 is a P-type diffusion layer (P) formed around the sides and bottom of N-well 351, and accumulates holes therein. Furthermore, hole accumulation layer 354 is electrically connected to the anode of SPAD element 331 to allow bias adjustment. As a result, for example, the hole concentration in hole accumulation layer 354 increases, and pinning by pinning layer 355 is strengthened, thereby suppressing the generation of dark current.

[0197] The pinning layer 355 is a heavily doped P-type diffusion layer (P+) formed on the surface outside the hole accumulation layer 354 (the side in contact with the back surface of the sensor substrate 341 and the insulating film 62), and suppresses the generation of dark current similar to the hole accumulation layer 354.

[0198] The high concentration P-type diffusion layer 356 is a heavily doped P-type diffusion layer (P++) formed around the periphery of the N-well 351 near the front of the sensor substrate 341 and is used to connect to the contact electrode 372 for electrically connecting the hole accumulation layer 354 to the anode of the SPAD element 331.

[0199] The avalanche multiplication region 357 is a high electric field region formed at the interface between the P-type diffusion layer 352 and the N-type diffusion layer 353 by a high negative voltage applied to the N-type diffusion layer 353, and multiplies electrons (e-) generated by one photon incident on the SPAD element 331.

[0200] Furthermore, in the sensor chip 311, each SPAD element 331 is insulated and separated by an inter-pixel separator 20. This inter-pixel separator 20 has a dual structure formed by a metal film 361 and an insulating film 362 formed between adjacent SPAD elements 311. In this application example 2-1, the metal film 361 and the insulating film 362 are examples of "separation films" in the present disclosure. For example, the inter-pixel separator 20 is formed so as to penetrate the sensor substrate 341 from the back to the front.

[0201] The metal film 361 is a film formed of a light-reflecting metal (e.g., tungsten), and the insulating film 362 is an insulating film, such as SiO. For example, the inter-pixel separator 20 is formed by embedding the metal film 361 in the sensor substrate 341 so that the surface of the metal film 361 is covered by the insulating film 362. The inter-pixel separator 20 electrically and optically separates adjacent SPAD elements 331.

[0202] Contact electrodes 371 to 373 , metal wirings 374 to 375 , contact electrodes 377 and 378 , and metal pads 380 to 382 are formed in the sensor-side wiring layer 342 .

[0203] The contact electrode 371 connects the N-type diffusion layer 353 and the metal wiring 374 , and the contact electrode 372 connects the high-concentration P-type diffusion layer 356 and the metal wiring 375 .

[0204] For example, the metal wiring 374 is formed to be wider than the avalanche multiplication region 357 so as to at least cover the avalanche multiplication region 357. In addition, the metal wiring 374 reflects the light transmitted through the SPAD element 331 back to the SPAD element 311, as shown in FIG. Figure 20 As shown by the hollow arrows in .

[0205] For example, the metal wiring 375 is formed to overlap with the high-concentration P-type diffusion layer 356 so as to surround the outer periphery of the metal wiring 374 .

[0206] Contact electrode 377 connects metal wiring 374 and metal pad 380 . Contact electrode 378 connects metal wiring 375 and metal pad 381 .

[0207] The metal pads 380 to 382 are used to electrically and mechanically bond to the metal pads 401 to 403 formed in the logic-side wiring layer 343 through the metal (Cu) forming each metal pad.

[0208] Electrode pads 391 to 393 , an insulating layer 394 , contact electrodes 395 to 400 , and metal pads 401 to 403 are formed in the logic-side wiring layer 343 .

[0209] The electrode pads 391 - 393 are used to connect to a logic circuit substrate (not shown), and the insulating layer 394 insulates the electrode pads 391 - 393 from each other.

[0210] Contact electrodes 395 and 396 connect electrode pad 391 and metal pad 401. Contact electrodes 397 and 398 connect electrode pad 392 and metal pad 402. Contact electrodes 399 and 400 connect electrode pad 393 and metal pad 403.

[0211] Metal pad 401 is bonded to metal pad 380. Metal pad 402 is bonded to metal pad 381. Metal pad 403 is bonded to metal pad 382.

[0212] With this wiring structure, electrode pad 391 is connected to N-type diffusion layer 353 via, for example, contact electrodes 395 and 396, metal pad 401, metal pad 380, contact electrode 377, metal wiring 374, and contact electrode 371. Therefore, in SPAD pixel 321, a high negative voltage applied to N-type diffusion layer 353 can be supplied to electrode pad 391 from the logic circuit substrate.

[0213] Furthermore, the electrode pad 392 is connected to the high-concentration P-type diffusion layer 356 via the contact electrodes 397 and 398, the metal pad 402, the metal pad 381, the contact electrode 378, the metal wiring 375, and the contact electrode 372. Therefore, in the SPAD pixel 321, the anode of the SPAD element 331 electrically connected to the hole accumulation layer 354 is connected to the electrode pad 392, so that the bias voltage applied to the hole accumulation layer 354 can be adjusted via the electrode pad 392.

[0214] Furthermore, as described above, in the SPAD pixel 321, the metal wiring 374 is formed wider than the avalanche multiplication region 357 so as to at least cover the avalanche multiplication region 357, and the metal film 361 is formed to penetrate the sensor substrate 341. In other words, the SPAD pixel 321 is formed to have a reflective structure in which the metal wiring 374 and the metal film 361 surround all areas other than the light incident surface of the SPAD element 331. Therefore, the SPAD pixel 321 can prevent the occurrence of optical crosstalk by reflecting light from the metal wiring 374 and the metal film 361, and can improve the sensitivity of the SPAD element 331.

[0215] In the SPAD pixel 321 , the side surfaces and bottom surface of the N-well 351 are surrounded by the hole accumulation layer 354 , and the hole accumulation layer 353 is electrically connected to the anode of the SPAD element 331 , thereby enabling bias adjustment.

[0216] The SPAD pixel 321 configured as described above prevents the occurrence of crosstalk and increases the sensitivity of the SPAD element 331 , thereby improving characteristics.

[0217] Furthermore, an enclosure 30 surrounding the end of the inter-pixel isolation portion 20 is provided on the surface of the sensor substrate 341 opposite the light incident surface, i.e., the lower side in the figure. The enclosure 30 is covered from below by an interlayer insulating film, etc., of the sensor-side wiring layer 342, which is disposed on the lower side in the figure. As in the above-described embodiment, in this application example 2-1, the enclosure 30 is made of a material different from that of the sensor substrate 341, for example, silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN).

[0218] In the above-described application example 2-1, the surrounding portion 30 is formed in advance when the groove 21 for the pixel separation portion 20 is formed. Therefore, as in the above-described embodiment, when the hard mask (e.g., SiO) used when forming the groove 21 is removed, the effect of preventing chemical liquid corrosion and suppressing yield reduction by preventing corrosion is achieved.

[0219] (2-2) Application Example 2-2

[0220] Figure 21 This is a cross-sectional view showing the configuration of a back-illuminated pixel 630 according to Application Example 2-2 of the present disclosure. Figure 21 The pixel 630 is constructed such that an avalanche photodiode (APD) 621 is stacked on an on-chip lens 623, a sensor substrate 641 (an example of a “semiconductor substrate” in the present disclosure) is stacked on the APD 621, and a circuit substrate 642 is stacked on the sensor substrate 641. The sensor substrate is made of, for example, single-crystal Si (silicon).

[0221] Light from the on-chip lens 623 side ( Figure 21 In the case of a back-illuminated pixel 630, the circuit may also have a Figure 21 In the stacked structure of the circuit substrate 642 shown, the circuit can be arranged in an area outside the pixel area, or the circuit can be arranged within the same substrate.

[0222] like Figure 21 As shown, an N-type semiconductor region 701 and a P-type semiconductor region 702 in contact with a lower portion of the N-type semiconductor region 701 are formed in the APD 621. The N-type semiconductor region 701 and the P-type semiconductor region 702 are formed in a well layer 703.

[0223] The well layer 703 can be an N-type semiconductor region or a P-type semiconductor region. Furthermore, the well layer 703 is preferably an N-type or P-type semiconductor region with a low concentration, for example, at a level of 1E14 or less. This facilitates depletion of the well layer 703 and can improve detection efficiency, known as photon detection efficiency (PDE).

[0224] The P-type semiconductor region 702 forms a pn junction at the interface with the N-type semiconductor region 701. The P-type semiconductor region 702 has a multiplication region in which avalanche multiplication of carriers generated by the incident light to be detected is performed. Preferably, the P-type semiconductor region 702 is depleted to improve PDE.

[0225] N-type semiconductor region 701 functions as a cathode and is connected to a circuit via contact 704. Anode 705, which corresponds to the cathode, is formed in the same layer as N-type semiconductor region 701 and between N-type semiconductor region 701 and separation region 708. Anode 705 is connected to a circuit via contact 706.

[0226] A separation region 708 is formed to separate the APDs 621 from each other, and a hole accumulation region 707 is formed between the separation region 708 and the well layer 703. The hole accumulation region 707 is formed on the lower side of the anode 705 and is electrically connected to the anode 705. The hole accumulation region 707 is formed between the well layer 703 and the separation region 708. In addition, the hole accumulation region 707 is also formed on the lower portion of the well layer 703 (on the back side of the APD 621).

[0227] The hole accumulation region 707 is formed at a portion where different materials come into contact with each other. Figure 21 In the example shown, the separation region 708 is made of, for example, a silicon oxide film, and since the material of the separation region 708 is different from that of the well layer 703 , a hole accumulation region 707 for suppressing dark current generated at the interface is formed.

[0228] In addition, when the APD 621 is applied to the back-illuminated type, for example, Figure 21 As shown, the on-chip lens 723 is stacked on the lower portion of the well layer 703 (on the side opposite to the side where the N-type semiconductor region 701 is formed), but the hole accumulation region 707 is also formed at the interface between the side where the on-chip lens 23 is formed and the well layer 703. The hole accumulation region 707 can be formed as a P-type semiconductor region.

[0229] Furthermore, a surrounding portion 30 surrounding the end of the isolation region 708 is provided on the side of the APD 621 opposite the light incident surface (i.e., the side opposite the on-chip lens 623 across the APD 621). The surrounding portion 30 is covered from the upper side in the figure by an interlayer insulating film or the like. As in the above-described embodiment, in this application example 2-2, the surrounding portion 30 is made of a material different from that of the sensor substrate 641, for example, silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN).

[0230] In the above-mentioned application example 2-2, the surrounding portion 30 is also formed in advance when the trench for separating the region 708 is formed. Therefore, as in the above-mentioned embodiment, when the hard mask (e.g., SiO) used when forming the trench is removed, the effect of preventing chemical liquid corrosion and suppressing yield reduction by preventing corrosion is achieved.

[0231] (3) Application Example 3: Application of CMOS image sensors

[0232] Application Example 3 is an example in which the technology of the present disclosure is applied to a CMOS image sensor.

[0233] (3-1) Application Example 3-1

[0234] Figure 22 is a cross-sectional view illustrating a configuration of a pixel in an imaging device 731 according to Application Example 3-1 of the present disclosure. Figure 22 1 shows a cross-sectional view of a visible light pixel 751 and an infrared light pixel 752 in the imaging device 731. The visible light pixel 751 is configured as three types of pixels, for example, an R pixel, a G pixel, and a B pixel.

[0235] In the visible light pixel 751, a photoelectric conversion unit 762, consisting of a photodiode (PD) that receives incident light and performs photoelectric conversion on it, is formed in a semiconductor substrate 761. An insulating layer (not shown) made of silicon oxide (SiO), a wiring layer (not shown) made of copper (Cu) or aluminum (Al), and the like are formed on the semiconductor substrate 761. An infrared cut filter 763 is formed thereon as a first optical filter layer. A color filter 766 having spectral characteristics corresponding to each visible light pixel 751 is formed on the infrared cut filter 763 as a second optical filter layer. Microlenses 767 are formed on the color filter 766.

[0236] In the infrared light pixel 752, the photoelectric conversion unit 762 is formed in the semiconductor substrate 761. An insulating layer, a wiring layer, etc. (not shown) are formed on the semiconductor substrate 761, and, for example, a B (blue) color filter 764 is formed thereon as a first optical filter layer. For example, an R (red) color filter 766 is formed on the color filter 764 as a second optical filter layer. A microlens 767 is formed on the color filter 766. Both the color filters 764 and 766 are configured as filters that transmit infrared light, and the combination of the two layers of color filters can reduce the transmittance of light in the visible light region.

[0237] In addition, each pixel (the visible light pixel 751 and the infrared light pixel 752) has an inter-pixel separator 20 that separates the first optical filter layer for each pixel. The inter-pixel separator 20 is formed by a metal film 765a made of tungsten (W), aluminum (Al), etc. and a Si oxide film 765b made of silicon oxide (SiO), silicon nitride (SiN), etc. Figure 22 In the example of , the height of the inter-pixel separator 20 is set to the same height as the first optical filter layer (the infrared cut filter 763 or the color filter 764 ).

[0238] For example, Figure 22 As shown, a portion corresponding to the PD separation wall in the inter-pixel separation section 20 for separating the photoelectric conversion section 762 and the first optical filter layer for each pixel is formed of a Si oxide film 765b made of SiO, SiN, or the like.

[0239] In addition, the surrounding portion 30 surrounding the end of the inter-pixel separation portion 20 is provided on the surface of the semiconductor substrate 761 opposite to the light incident surface, that is, the lower side in the figure. The lower side of the inter-pixel separation portion 20 is formed by, for example, a Si oxide film 765b. As shown in the figure, the surrounding portion 30 is covered from the lower side by an interlayer insulating film 770 or the like arranged on the lower side. As in the above embodiment, in this application example 3-1, the surrounding portion 30 is made of a material different from the semiconductor substrate 761, for example, silicon nitride (SiN) or silicon nitride containing at least one of oxygen and carbon (SiON, SiCN).

[0240] In the above-described application example 3-1, the surrounding portion 30 is also formed in advance when the groove 21 for the pixel separation portion 20 is formed. Therefore, as in the above-described embodiment, when the hard mask (e.g., SiO) used when forming the groove 21 is removed, the effect of preventing chemical liquid corrosion and suppressing yield reduction by preventing corrosion is achieved.

[0241] (3-2) Application Example 3-2

[0242] Figure 23 This is a cross-sectional view illustrating the configuration of a pixel array section of an imaging device 731A according to Application Example 3-2 of the present disclosure. Application Example 3-2 is a modification of Application Example 3-1. Application Example 3-2 differs from Application Example 3-1 in that the portion of the inter-pixel separation section 20 corresponding to the PD separation wall is formed from a metal film made of W, Al, or the like. In this manner, by additionally providing a PD separation wall for separating the photoelectric conversion section 762 for each pixel, the occurrence of color mixing between pixels can be more reliably suppressed.

[0243] In imaging device 731A according to application example 3-2, the end of pixel isolation portion 20 is also surrounded by surrounding portion 30. In application example 3-2, the lower end of pixel isolation portion 20 is formed of, for example, metal film 765a. In this embodiment, imaging device 731A, like imaging device 731, has the effect of preventing chemical liquid corrosion during hard mask removal and suppressing yield reduction by preventing corrosion.

[0244] <Other Implementation Options>

[0245] Although the present disclosure has been described above based on embodiments, variations and applicable examples, the description and drawings constituting a part of the present disclosure should not be understood as limiting the present disclosure. Through the present disclosure, various alternative embodiments, examples and operable technologies will be clear to those skilled in the art. Needless to say, the present technology includes various embodiments not described herein. Without departing from the gist of the above-mentioned embodiments, variations and applicable examples, at least one of the various omissions, replacements and changes of the constituent elements may be performed. In addition, the advantageous effects described in this specification are merely exemplary and are not intended to be limiting, and other advantageous effects may be obtained.

[0246] The present disclosure can also be configured as follows.

[0247] (1) A light detection device comprising:

[0248] a semiconductor substrate having a first surface and a second surface opposite to the first surface;

[0249] a plurality of pixels provided on the semiconductor substrate and having a photoelectric conversion element;

[0250] an inter-pixel separator provided between adjacent pixels among the plurality of pixels and extending between the first surface and the second surface of the semiconductor substrate; and

[0251] a surrounding portion provided on the first surface side of the semiconductor substrate and surrounding an end portion of the inter-pixel isolation portion,

[0252] The surrounding portion is made of a material different from that of the semiconductor substrate.

[0253] (2) The light detecting device according to (1), wherein the semiconductor substrate is made of silicon, and

[0254] The surrounding portion is made of silicon nitride or silicon nitride containing at least one of oxygen and carbon.

[0255] (3) The light detecting device according to (1) or (2), wherein the surrounding portion includes

[0256] a bottom portion facing the end portion in the thickness direction of the semiconductor substrate, and

[0257] A side portion connects the first surface and the bottom portion.

[0258] (4) The light detection device according to any one of (1) to (3), further comprising an insulating film provided on the first surface side of the semiconductor substrate and adjacent to the surrounding portion from the outside of the surrounding portion,

[0259] The insulating film is made of a material different from that of the semiconductor substrate and the surrounding portion.

[0260] (5) The light detecting device according to (4), wherein the insulating film is made of silicon oxide.

[0261] (6) A method for manufacturing a light detection device, comprising:

[0262] A process of forming a first material film on a first surface side of a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to the first surface and provided with a plurality of pixels having photoelectric conversion elements, and covering a predetermined area with the first material film from the first surface side, the predetermined area being for separating adjacent pixels from each other among the plurality of pixels;

[0263] forming a second material film on the opposite side of the predetermined area while sandwiching the first material film;

[0264] a process of forming a third material film on the opposite side of the first material film with the second material film interposed therebetween and covering the second material film with the first material film and the third material film;

[0265] forming a mask having a shape that exposes the predetermined area and covers areas other than the predetermined area on the second surface side;

[0266] forming a trench penetrating the semiconductor substrate and the first material film by etching the predetermined region exposed through the mask from the second surface side using the second material film as an etching stopper; and

[0267] a process of removing the mask by wet etching after forming the trench,

[0268] In the wet etching, a chemical liquid is used that easily etches the mask and the second material film but hardly etches the first material film and the third material film.

[0269] (7) The method for manufacturing a light detecting device according to (6), wherein each of the mask and the second material film is made of silicon oxide, and

[0270] Each of the first material film and the third material film is made of silicon nitride or silicon nitride containing at least one of oxygen and carbon.

[0271] (8) The method for manufacturing a light detection device according to (7), wherein the chemical liquid contains hydrofluoric acid.

[0272] (9) The method for manufacturing a light detection device according to any one of (6) to (8), further comprising, before forming the first material film:

[0273] forming an insulating film on the first surface of the semiconductor substrate; and

[0274] a process of forming an opening by removing a portion of the insulating film that overlaps the predetermined region in the thickness direction of the semiconductor substrate,

[0275] In the process of forming the first material film,

[0276] forming a first material film on the insulating film so as to fill the opening, and

[0277] During the formation of the second material film,

[0278] The second material film is formed in a region overlapping with the opening in the thickness direction of the semiconductor substrate.

[0279] (10) The method for manufacturing a light detecting device according to (9), wherein the insulating film is made of silicon oxide.

[0280] (11) The method for manufacturing a light detection device according to any one of (6) to (10), further comprising a step of embedding a separation film in the groove after removing the mask.

[0281] [Reference Signs List]

[0282] 1, 1A, 1B-1, 1B-2, 1C, 1D-1, 1D-2, 1E-1, 1E-2, 1F-1, 1F-2 Photodetection device

[0283] 10,241 semiconductor substrate

[0284] 10a front

[0285] 10b Back

[0286] 12, 151, 210 pixels

[0287] 20'' overlap area

[0288] 20 pixel separation

[0289] 20 reserved areas

[0290] 20a end

[0291] 21 Grooves

[0292] 22 Separation membrane

[0293] 23 On-chip lens

[0294] 30 Encirclement

[0295] 31 bottom

[0296] 32 Side

[0297] 32e extension

[0298] 33 Space

[0299] 41, 42, 43, 44, 46 Insulation film

[0300] 50 vias

[0301] 51, 171, 172, 173, 174, 251, 252 semiconductor regions

[0302] 62 Insulation film

[0303] 111 Imaging Element

[0304] 121 Pixel array unit

[0305] 122 vertical drive unit

[0306] 123 column processing unit

[0307] 124 horizontal drive unit

[0308] 125 System Control Department

[0309] 126 Signal Processing Department

[0310] 127 Data Storage Department

[0311] 128 pixel drive lines

[0312] 129 vertical signal line

[0313] 135 connection pads

[0314] 161 substrate

[0315] 162, 247, 623, 723 On-chip lenses

[0316] 163 inter-pixel light shielding

[0317] 164 oxide film

[0318] 165 Signal Extraction Department

[0319] 175 Separation Department

[0320] 181, 262, 770 Interlayer insulating film

[0321] 201, 201A light receiving element

[0322] 221 Anti-reflective film

[0323] 223 upper area

[0324] 242 multi-layer wiring layer

[0325] 243 Anti-reflective film

[0326] 244-pixel boundary

[0327] 244 Border Department

[0328] 245 inter-pixel light shielding

[0329] 246 planarization film

[0330] 253 Hafnium Oxide Film

[0331] 254 Aluminum Oxide Film

[0332] 255 silicon oxide film

[0333] 263 Shading member

[0334] 264 Wiring Capacitance

[0335] 311 sensor chip

[0336] 321 SPAD pixels

[0337] 331 SPAD element

[0338] 341 sensor substrate

[0339] 342 Sensor side wiring layer

[0340] 343 Logic side wiring layer

[0341] 351 N-well

[0342] 352 P-type diffusion layer

[0343] 353 N-type diffusion layer

[0344] 354 Hole Accumulation Layer

[0345] 355 pinning layer

[0346] 356 High concentration P-type diffusion layer

[0347] 357 Avalanche Multiplication Zone

[0348] 361 metal film

[0349] 362 Insulation Film

[0350] 371, 372, 373, 377, 378, 395, 396, 397, 398, 399, 400 contact electrodes

[0351] 374, 375 Metal wiring

[0352] 380, 381, 382, ​​401, 402, 403 metal pads

[0353] 391, 392, 393 electrode pads

[0354] 394 insulation layer

[0355] 621 Avalanche Photodiode Sensor (APD)

[0356] 630 pixels

[0357] 641 sensor substrate

[0358] 642 circuit board

[0359] 701 N-type semiconductor region

[0360] 703 Well Layer

[0361] 704, 706 Contact Department

[0362] 705 anode

[0363] 707 Accumulation Area

[0364] 707 Hole Accumulation Region

[0365] 708 Separation Area

[0366] 731, 731A Imaging Device

[0367] 751 pixels for visible light

[0368] 752 infrared light pixels

[0369] 761 Semiconductor Substrate

[0370] 762 Photoelectric Conversion Department

[0371] 763 Infrared Cutoff Filter

[0372] 764, 766 color filters

[0373] 765a, MT metal film

[0374] 765b Si oxide film

[0375] 767 Microlens

[0376] A, B FD department

[0377] FD1, FD2 floating diffusion regions

[0378] G32 step

[0379] H11 opening

[0380] HM Hard Mask

[0381] M1, M2, M3 masks

[0382] MF1 First Material Film

[0383] MF2 Second Material Film

[0384] MF3 third material film

[0385] MT1 First Metal Film

[0386] MT2 Second Metal Film

[0387] MT3 third metal film

[0388] TRG1, TRG2 pass transistors

Claims

1. A light detection device, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a plurality of pixels provided on the semiconductor substrate and having a photoelectric conversion element; an inter-pixel separator provided between adjacent pixels among the plurality of pixels and extending between the first surface and the second surface of the semiconductor substrate; and a surrounding portion provided on the first surface side of the semiconductor substrate and surrounding an end portion of the inter-pixel isolation portion, The surrounding portion is made of a material different from that of the semiconductor substrate.

2. The light detecting device according to claim 1, wherein the semiconductor substrate is made of silicon, and The surrounding portion is made of silicon nitride or silicon nitride containing at least one of oxygen and carbon.

3. The light detecting device according to claim 1, wherein the surrounding portion comprises a bottom portion facing the end portion in the thickness direction of the semiconductor substrate, and A side portion connects the first surface and the bottom portion.

4. The light detecting device according to claim 1 , further comprising an insulating film provided on the first surface side of the semiconductor substrate and adjacent to the surrounding portion from the outside of the surrounding portion, The insulating film is made of a material different from that of the semiconductor substrate and the surrounding portion. The light detecting device according to claim 4 , wherein the insulating film is made of silicon oxide.

6. A method for manufacturing a light detection device, comprising: A process of forming a first material film on a first surface side of a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to the first surface and provided with a plurality of pixels having photoelectric conversion elements, and covering a predetermined area with the first material film from the first surface side, the predetermined area being for separating adjacent pixels from each other among the plurality of pixels; forming a second material film on the opposite side of the predetermined area while sandwiching the first material film; a process of forming a third material film on the opposite side of the first material film with the second material film interposed therebetween and covering the second material film with the first material film and the third material film; forming a mask having a shape that exposes the predetermined area and covers areas other than the predetermined area on the second surface side; a process of forming a trench penetrating the semiconductor substrate and the first material film by etching the predetermined region exposed through the mask from the second surface side using the second material film as an etching stopper; and a process of removing the mask by wet etching after forming the trench, In the wet etching, a chemical liquid is used that easily etches the mask and the second material film but hardly etches the first material film and the third material film.

7. The method for manufacturing a light detecting device according to claim 6, wherein each of the mask and the second material film is made of silicon oxide, and Each of the first material film and the third material film is made of silicon nitride or silicon nitride containing at least one of oxygen and carbon. 8 . The method for manufacturing a light detection device according to claim 7 , wherein the chemical liquid contains hydrofluoric acid.

9. The method for manufacturing a light detecting device according to claim 6, further comprising, before forming the first material film: forming an insulating film on the first surface of the semiconductor substrate; and a process of forming an opening by removing a portion of the insulating film that overlaps the predetermined region in the thickness direction of the semiconductor substrate, In the process of forming the first material film, forming a first material film on the insulating film so as to fill the opening, and During the formation of the second material film, The second material film is formed in a region overlapping with the opening in the thickness direction of the semiconductor substrate. 10 . The method for manufacturing a light detecting device according to claim 9 , wherein the insulating film is made of silicon oxide. 11 . The method for manufacturing a light detecting device according to claim 6 , further comprising a step of embedding a separation film in the groove after removing the mask.

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