Low-cost motor coding system and method, medium, program product and terminal

Abstract

The invention provides a low-cost motor coding system and method, a medium, a program product and a terminal, through a collaborative cooperation scheme of an input cache unit, a computing resource control unit and a coding output control unit, the input cache unit is responsible for receiving an original angle signal from a position management system and caching the original angle signal. And the computing resource control unit performs various corresponding coding and angle quantization operations according to different types of coding parameters and angle signals to be calculated through time division multiplexing of a lookup table module, a multiplication calculation module and an addition calculation module in the computing resource control unit. And the coding output control unit receives an angle quantization result and completes a final coding signal. According to the invention, a single chip can support multiple coding types, hardware resource optimization is realized, the system cost is reduced, the integration level is improved, and the application flexibility is enhanced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a low-cost motor encoding system, method, medium, program product and terminal. Background Art

[0002] Currently, a common solution to the problem of supporting multiple encoding types in motor encoders is to implement the encoding function using a separate chip. Existing technologies typically design dedicated circuits for specific encoding types, using optical, magnetic, or inductive sensing methods to detect changes in the motor rotor's position. The separate chip then performs signal processing and encoding conversion. While these separate chips can reliably implement specific encoding functions, their main limitation is that they generally only support a limited number of encoding formats.

[0003] Therefore, existing technologies face significant cost and complexity challenges when supporting multiple encoding types. To achieve compatibility with multiple encoding types, multiple independent, dedicated chips for different encoding types must be used. This significantly increases the required circuit area and hardware costs. Especially in applications with strict size and cost requirements, such as compact robots or consumer electronics, this solution that relies on multiple independent chips struggles to provide multi-encoding support while also meeting economical requirements. Furthermore, the design and integration of multiple independent chips increases system complexity and development difficulty. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a low-cost motor encoding system, method, medium, program product and terminal, which is used to solve the problem that the prior art implements the encoding function through independent dedicated chips, resulting in the need for multiple chips to support multiple encoding types, significantly increasing the circuit area and cost.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a low-cost motor encoding system, including: an input cache unit, which is communicatively connected to a position management system and a computing resource control unit respectively; used to receive an original angle signal from the position management system and a computing idle indication signal from the computing resource control unit; the input cache unit caches the original angle signal, and when the computing idle indication signal is valid, sends the cached angle signal to be calculated to the computing resource control unit; the computing resource control unit includes a multiplication calculation module, an addition calculation module and a lookup table module; the computing resource control unit is communicatively connected to an encoding output control unit; used Receive multiple coding parameters and the angle signal to be calculated; the computing resource control unit time-share multiplexes the lookup table module, the multiplication calculation module and the addition calculation module, performs the corresponding first coding operation and second coding operation on each coding parameter according to the angle signal to be calculated, and generates a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated; when the multiplication calculation module, the addition calculation module and the lookup table module are in an idle state, the computing idle indication signal is sent to the input cache unit; a coding output control unit is used to receive the third angle parameter from the computing resource control unit; and perform a third coding operation based on the third angle parameter to generate a third coding signal.

[0006] In some embodiments of the first aspect of the present application, the computing resource control unit time-shares the lookup table module, the multiplication calculation module and the addition calculation module, performs the corresponding first encoding operation and second encoding operation on each encoding parameter according to the angle signal to be calculated, and generates a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated. The process includes: in each preset clock cycle, when the computing resource control unit performs the first encoding operation, the second encoding operation or the third angle quantization operation, one or more of the following operations are performed simultaneously in each clock cycle: configure the lookup table module to receive the input signal in the current clock cycle and directly output the read result corresponding to the input signal; configure the addition calculation module to receive the input signal in the current clock cycle, perform the addition operation, and directly output the calculation result corresponding to the input signal; configure the multiplication calculation module to receive the input signal in the current clock cycle, perform the multiplication operation, and store the calculation result corresponding to the input signal in the latch for output in the next clock cycle; read and output the multiplication calculation result stored in the latch of the previous clock cycle.

[0007] In some embodiments of the first aspect of the present application, the process of the computing resource control unit performing a corresponding first encoding operation on the sine wave encoding parameter in each encoding parameter according to the angle signal to be calculated includes: performing an angle offset operation and a line number modulation operation on the sine wave encoding parameter and the angle signal to be calculated to generate a sine wave angle modulation signal; generating a corresponding segment index value based on the sine wave angle modulation signal; performing a shift operation on the sine wave angle modulation signal based on a preset reference angle to generate a residual angle value; inputting the segment index value as an input signal into the lookup table module to read the corresponding sine wave parameter value; and inputting the sine wave parameter value and the residual angle value as input. A signal is input into the multiplication calculation module to calculate a sine wave increment value; the sine wave parameter value and the sine wave increment value are input as input signals into the addition calculation module to calculate and output a sine wave encoding signal; or a preset PWM periodic signal is received, the sine wave parameter value and the sine wave increment value are input as input signals into the addition calculation module to generate a sine wave encoding signal, and the sine wave encoding signal and the PWM periodic signal are input as input signals into the multiplication calculation module to calculate and output a PWM sine wave encoding signal; wherein the sine wave parameter value is a sine or cosine function value; and the lookup table module stores pre-calculated sine or cosine function values ​​corresponding to multiple angles.

[0008] In some embodiments of the first aspect of the present application, the process of the computing resource control unit performing a corresponding second encoding operation on the PWM encoding parameter in each of the encoding parameters according to the angle signal to be calculated includes: performing an angle offset operation and a line number modulation operation on the PWM encoding parameter and the angle signal to be calculated to generate a PWM modulation signal; inputting the PWM modulation signal and a preset PWM cycle parameter as input signals into the multiplication calculation module to calculate a first PWM encoding signal; inputting the preset PWM cycle parameter and the first PWM encoding signal as input signals into the addition calculation module to calculate a second PWM encoding signal.

[0009] In some embodiments of the first aspect of the present application, the process of the computing resource control unit performing a corresponding third encoding operation on the incremental encoding parameter in each encoding parameter according to the angle signal to be calculated includes: inputting the incremental encoding parameter and the angle signal to be calculated as input signals into the addition calculation module to perform angle offset operation and line number modulation operation, and generate an ABZ incremental modulation signal.

[0010] In some embodiments of the first aspect of the present application, the encoding output control unit performs a third encoding operation based on the third angle parameter to generate a third encoding signal. The process includes: inverting the lowest bit data of the ABZ incremental modulation signal, and outputting an A-phase incremental signal according to the inversion result; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low; performing an exclusive OR operation on the lowest two bits of the ABZ incremental modulation signal, and outputting a B-phase incremental signal according to the operation result; if the levels of the lowest two bits are consistent, the output B-phase incremental signal is low; otherwise, the output B-phase incremental signal is high; performing an equality judgment operation on all bit data of the ABZ incremental modulation signal and a preset ABZ zero-position reference value, and outputting a high-level Z-phase incremental signal if they are equal; and outputting a low-level Z-phase incremental signal if they are not equal.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a low-cost motor encoding method, which is applied to an encoder, and the method includes: receiving an original angle signal and a calculation idle indication signal, caching the original angle signal, and when the calculation idle indication signal is valid, reading the cached original angle signal; receiving multiple encoding parameters; time-sharing multiplexing the lookup table module, the multiplication calculation module and the addition calculation module, performing corresponding first encoding operations and second encoding operations on each encoding parameter according to the angle signal to be calculated, and generating a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated; performing a third encoding operation based on the third angle parameter to generate a third encoding signal.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the low-cost motor encoding method is implemented.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements the low-cost motor encoding method.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the low-cost motor encoding method.

[0015] As described above, the low-cost motor encoding system, method, medium, program product and terminal of the present application have the following beneficial effects: the present application realizes the optimization of hardware resources, significant cost reduction, and improved integration, and provides a more flexible application adaptation capability for the motor control system. Specifically, the present application supports multiple encoding types on a single chip, which greatly reduces the consumption of hardware resources and reduces the overall cost. By time-sharing multiplexing the core computing modules and sending a computing idle indication signal according to the idle state of the module, the extremely efficient utilization of resources is ensured. In addition, the output granularity can be adjusted by configuring parameters, providing flexible configuration options for different application scenarios. The present application is suitable for applications with strict requirements on size and cost, such as compact robots and consumer electronics. Its integrated design built into a general-purpose microcontroller further simplifies the hardware structure, improves reliability, and accelerates product development and market launch. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an embodiment of a low-cost motor encoding system of the present application is shown.

[0017] Figure 2 A schematic diagram of the structure of the input buffer unit in one embodiment of the low-cost motor encoding system of the present application is shown.

[0018] Figure 3 A schematic diagram of the structure of a computing resource control unit in an embodiment of the low-cost motor encoding system of the present application is shown.

[0019] Figure 4 A schematic diagram of the structure of the encoding output control unit in one embodiment of the low-cost motor encoding system of the present application is shown.

[0020] Figure 5 A structural diagram of an embodiment of the low-cost motor encoding method of the present application is shown.

[0021] Figure 6 A structural diagram of an embodiment of a low-cost motor encoding terminal of the present application is shown. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0023] Before further explaining the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations:

[0024] <1> Sine wave encoders take rotation angle as input and output corresponding sine and cosine wave analog signals. They are used to accurately reflect angular position and are suitable for analog signal measurement and control.

[0025] <2> Sine wave PWM encoding: Input the rotation angle signal, convert the corresponding sine wave signal into PWM pulse sequence output through pulse width modulation, and realize digital transmission and processing of analog angle.

[0026] <3> ABZ encoding: Receives mechanical shaft rotation as input and outputs two incremental square wave signals A and B with a phase difference of 90 degrees for direction and speed determination, and a periodic signal Z as a position reference.

[0027] <4> PWM encoding: takes angle or speed signals as input and generates corresponding PWM signal output by adjusting the pulse width. It is widely used in digital control of analog quantities such as speed or position.

[0028] <5> Buffer: Receives data stream input and stores it for a short period of time, outputs data in an orderly manner on demand, and plays a role in coordinating processing speed differences and ensuring data continuity.

[0029] <6> Line number modulation: The original pulse signal of the encoder is input, and the modified pulse signal is output by adjusting the number of output pulses per revolution to adjust the system resolution.

[0030] <7> Sin-cosine lookup table: takes an angle index as input and quickly outputs the corresponding sine and cosine values, replacing real-time calculations to improve system computing efficiency.

[0031] The technical solutions of the embodiments of the present application are widely applicable to a variety of industrial automation and intelligent control fields, such as industrial robot systems (IRS), intelligent manufacturing equipment (IME), motor drive control systems (MDCS), automated production lines (APL) and compact consumer electronics (CCE). Among them, the motor drive control system includes key components such as multi-type encoder decoding modules (MEDM), encoder signal converters (ESC) and embedded system integrated circuits (ESIC) that support multiple encoder interfaces. This technical solution can simultaneously realize sinusoidal encoding, ABZ encoding and pulse width modulation encoding, which greatly improves the compatibility and flexibility of the system for different encoding types. In addition, this technical solution can also be expanded to industrial Internet of Things devices (IIoT), smart sensing and positioning systems (SSPS), and high-precision positioning and control fields to meet the compatibility requirements of various complex application scenarios for multiple motor encoding methods. By adopting this technical solution, the hardware redundancy and cost increase problems caused by the existing use of multiple independent chips to support a single encoding type can be effectively solved, significantly improving system integration and reliability. This solution is particularly suitable for application environments with strict requirements on volume, cost and performance, such as robot joint drives, automated assembly lines, and portable medical equipment, helping to achieve more efficient and economical intelligent control solutions.

[0032] To facilitate understanding of the embodiments of this application, first Figure 1 Detailed description. Figure 1 The following is a flow chart of a low-cost motor encoding system 100 according to an embodiment of the present invention. The low-cost motor encoding system 100 according to this embodiment mainly includes the following units:

[0033] An input cache unit 101 is communicatively connected to a location management system and a computing resource control unit, respectively; it is used to receive an original angle signal from the location management system and a computing idle indication signal from the computing resource control unit; the input cache unit caches the original angle signal, and when the computing idle indication signal is valid, sends the cached angle signal to be calculated to the computing resource control unit.

[0034] In one embodiment of the present application, the input buffer unit obtains an electrical angle or a mechanical angle from a position management system of a microcontroller. The angle represents the position of the motor movement, and the electrical angle in the motor rotational motion is information that changes periodically. The present application creatively performs sine wave encoding operations, incremental digital pulse (ABZ) encoding operations, and PWM control encoding operations on the electrical signal of the same multi-bit digital signal input. These three types of encoding operations are time-shared and multiplexed to share the multiplication calculation unit, addition calculation unit, and sine lookup table unit in the computing resource control unit. Among them, the sine lookup table unit is used to perform the sine and cosine value calculations in the sine wave encoding operation.

[0035] In one embodiment of the present application, the input cache unit communicates data with the location management system and the computing resource control unit. The input cache unit receives the original angle signal from the location management system and receives the computing idle indication signal from the computing resource control unit. The input cache unit performs a cache operation on the received original angle signal. When the computing idle indication signal is in a valid state, the input cache unit sends the cached angle signal to be calculated to the computing resource control unit. When the input cache unit is specifically implemented, its input end includes: a system bus, which is used to send a system working clock signal and a reset signal; an angle signal from the location management system, the bit width of the angle signal is n+1 bits, denoted as angle[n:0]; an angle signal valid indication signal angle_valid from the location management system; and a computing idle indication signal cal_idle from the computing resource control unit.

[0036] The input buffer unit also receives configuration parameters, such as the angle update hysteresis threshold value angle_filter, which also has a bit width of n+1 bits. The output signals of the input buffer unit include: the angle signal to be calculated, angle_cal, which has a bit width of n+1 bits; and the angle calculation enable pulse signal cal_valid. The input buffer unit caches the input angle signal and outputs the angle signal to be calculated and the enable signal when calculation conditions are met.

[0037] In one embodiment of the present application, the input cache unit includes multiple caches; the input cache unit also receives an angle update hysteresis threshold value, and the process of caching the original angle signal includes: when the input cache unit calculates the absolute difference between the original angle information received at the current moment and the original angle information last stored in the cache; if the absolute difference is greater than or equal to the angle update hysteresis threshold value, the original angle information received at the current moment is stored in the cache in a first-in-first-out manner; otherwise, the original angle information received at the current moment is discarded, and the original angle information at the next moment is continued to be received.

[0038] In this embodiment, the input buffer unit includes multiple buffers and is used to receive an angle update hysteresis threshold value to cache the raw angle signal. The caching process includes: first, calculating the absolute difference between the raw angle information received at the current moment and the last piece of raw angle information stored in the buffer. When this difference is greater than or equal to the set angle update hysteresis threshold value, the raw angle information at the current moment is stored in the buffer on a first-in, first-out basis. If the difference is less than the threshold value, the raw angle information received at this moment is discarded, and the raw angle signal at the next moment is received. This mechanism ensures that only angle signals with significant changes are stored.

[0039] In this embodiment, the input buffer unit has x built-in data buffers, labeled BUF(1), BUF(2), ..., BUF(x). Each buffer can store n+1 bits of binary data. When the system bus (system_bus) is reset, the angle information stored in all data buffers is cleared, and the index to be output, BUF_INDEX, is initialized to 0. After the system reset is released and the operating clock is started, the input buffer unit begins normal operation.

[0040] For each operation cycle, if the angle signal valid indication signal (angle_valid) of the position management system is in a valid state, the input buffer unit calculates the absolute difference between the unsigned binary value of the current input angle signal angle[n:0] and the value in BUF(1). If the calculation result shows that the absolute difference between the two is less than the unsigned binary value of the corresponding angle_filter[n:0], the current input angle signal is discarded; otherwise, in the next clock cycle, the content of BUF(x) is updated to the value of BUF(x-1) in the current cycle, and so on, until BUF(1) is updated to the current input angle signal. The output index BUF_INDEX is incremented by 1 in sequence, and the value of BUF_INDEX is 0, 1, 2, and so on until x.

[0041] In the p+1th clock cycle, if the calculation idle indication signal (cal_idle) from the calculation resource control unit is a valid signal and BUF_INDEX is not 0, an angle calculation enable pulse signal (cal_valid) lasting one clock cycle is generated, and the value in the data buffer pointed to by BUF_INDEX is output to angle_cal[n:0] of the calculation resource control unit. After the operation, the value of BUF_INDEX will be subtracted by 1. In the same clock cycle, BUF_INDEX can be added by 1 and subtracted by 1 at the same time, thereby keeping its value unchanged. When the result of BUF_INDEX is equal to x in the pth clock cycle, the output state (BUF_FULL) of the input buffer unit becomes a valid state, thereby triggering an interrupt of the system processor to notify that the current input buffer is full. This means that the angle signal update frequency of the position management system exceeds the rate accepted by the present invention. In this case, the old angle information will be replaced by the new angle information, ensuring that the input buffer always stores the latest x sets of valid input angle information to ensure the real-time performance and accuracy of the system.

[0042] The computing resource control unit 102 includes a multiplication calculation module, an addition calculation module and a lookup table module; the computing resource control unit is communicatively connected to the encoding output control unit; and is used to receive multiple encoding parameters and the angle signal to be calculated; the computing resource control unit time-shares the lookup table module, the multiplication calculation module and the addition calculation module, performs the corresponding first encoding operation and second encoding operation on each encoding parameter according to the angle signal to be calculated, and generates a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated; when the multiplication calculation module, the addition calculation module and the lookup table module are in an idle state, they send the computing idle indication signal to the input cache unit.

[0043] In one embodiment of the present application, the computing resource control unit 102 integrates the system bus system_bus, which is responsible for providing the system working clock and reset functions, and introduces a flexibly configurable encoding output mode enable_mode. The user can decide whether the output of phase A, phase B or phase C in the sine wave encoding is enabled by setting the enable_mode parameter, or choose to enable the ABZ incremental encoding output and PWM control encoding. This parameter can be dynamically modified through the system bus during system operation. The unit can output three groups of encoding signals: phase A ana_a[n:0], phase B ana_b[n:0] and phase C ana_c[n:0], as well as the status indication signal ana_valid and the calculation status indication signal cal_idle. When the calculation is completed, cal_idle is in a valid state, and in an invalid state when the calculation is in progress. The cal_idle signal is connected to the input cache unit. The computing resource control unit includes computing modules such as adders, multipliers and sine and cosine lookup tables to provide support for encoding-related calculations.

[0044] In one embodiment of the present application, the computing resource control unit 102 is configured to perform various line number modulation operations and encoding operations on the input angle signal to be calculated, angle_cal[n:0], based on different encoding modes, by time-division multiplexing a lookup table module, a multiplication module, and an addition module. The line number modulation operations include performing corresponding offset and line number conversion operations based on each encoding operation; the encoding operations include calculating sine and cosine values ​​and PWM duty cycle.

[0045] Specifically, the various encoding parameters include sine wave encoding parameters, PWM encoding parameters, and ABZ encoding parameters. These encoding parameters can be flexibly configured based on specific needs, with the specific encoding method being implemented by setting the enable_mode parameter. This parameter can be pre-set or dynamically determined via a signal input from the system bus, ensuring the system is highly adaptable and flexible to meet the requirements of different application scenarios.

[0046] Among them, the sine wave encoding parameters include three groups of sine wave output signals (ana_a[n:0] / ana_b[n:0] / ana_c[n:0]) and three groups of angle differences (angle_shift_a[n:0] / angle_shift_b[n:0] / angle_shift_c[n:0]) corresponding thereto, wherein the number of effective bits of the output signal and its angle difference is n+1 bits. It should be noted that the output signal and its angle difference are both configurable parameters. For example, when the three groups of sine wave encoding outputs are configured as three-phase orthogonal outputs (when the angle difference is 120°), angle_shift_a[n:0] is configured to 0; angle_shift_b is configured to (2 n+1 / 3)*2; configure angle_shift_c to 2 n+1 / 3, at this time, phase a ana_a[n:0] leads phase b ana_b[n:0] by 120°, and phase b ana_b[n:0] leads phase c ana_c[n:0] by 120°. The above example is merely illustrative of the sine wave output signal inputted by this application and is not intended to be limiting. The sine wave encoding parameters in this embodiment will be used to perform the subsequent first encoding operation.

[0047] In addition, this embodiment not only supports conventional sinusoidal output signals, but is also compatible with PWM mode to accommodate different output control requirements. To this end, the sinusoidal encoding parameters in this embodiment have been supplemented with a PWM period parameter (pwm_period[n:0]). pwm_period[n:0] represents the number of PWM modulation cycles, which is a system-configurable parameter. By multiplying the resulting sinusoidal output signal by the PWM period parameter, a sinusoidal output signal in PWM mode can be generated.

[0048] In this embodiment, among the various encoding parameters, the PWM encoding parameters are composed of a PWM angle offset parameter (angle_shift_pwm[n:0]) and a PWM line number modulation parameter (resolution_pwm[n:0]). The angle offset parameter represents the additional angle difference when converting the input angle when the PWM control encoding output is output, and the line number modulation parameter defines the number of cycles of electrical angle or mechanical angle in a physical rotation cycle of the motor. Both parameters are system configurable parameters with n+1 effective bits, corresponding to a maximum number of lines configurable in the input modulation system of 2. n+1 -1, which together ensures the precise output characteristics of PWM encoding and the flexibility of system control.

[0049] Finally, among the various encoding parameters, the ABZ encoding parameters are composed of the angle offset parameter (angle_shift_abz[n:0]) and the line modulation parameter (resolution_abz[n:0]). Among them, the angle offset parameter represents the additional angle difference when converting the input angle when the ABZ incremental encoding output is output, and the line modulation parameter defines the number of angle cycles in the motor's physical rotation cycle. Both parameters are system configurable parameters with n+1 effective bits, corresponding to the maximum number of lines that can be configured in the input modulation system is 2 n+1 -1.

[0050] In one embodiment of the present application, the computing resource control unit performs a corresponding first encoding operation on each sine wave encoding parameter in the encoding parameters according to the angle signal to be calculated, including: performing an angle offset operation and a line number modulation operation on the sine wave encoding parameter and the angle signal to be calculated to generate a sine wave angle modulation signal; generating a corresponding segment index value based on the sine wave angle modulation signal; and performing a shift operation on the sine wave angle modulation signal based on a preset reference angle to generate a residual angle value. The segment index value is input as an input signal to the lookup table module to read the corresponding sine wave parameter value. The sine wave parameter value and the residual angle value are input as input signals to the multiplication calculation module to calculate a sine wave increment value. The sine wave parameter value and the sine wave increment value are input as input signals into the addition calculation module to calculate and output a sine wave encoding signal; or a preset PWM periodic signal is received, the sine wave parameter value and the sine wave increment value are input as input signals into the addition calculation module to generate a sine wave encoding signal, and the sine wave encoding signal and the PWM periodic signal are input as input signals into the multiplication calculation module to calculate and output a PWM sine wave encoding signal; wherein the sine wave parameter value is a sine or cosine function value; and the lookup table module stores pre-calculated sine or cosine function values ​​corresponding to multiple angles.

[0051] The following sections describe the first encoding process in detail, focusing on sine wave encoding for phase A. It's important to note that the encoding process for phases B and C follows the same logic as for phase A, so this section uses phase A as an example. When phases B and C are configured for sine wave encoding output, the calculation formulas for their sine and cosine values ​​are the same as for phase A, and the specific details will not be repeated here.

[0052] Sine wave encoding for phase A involves first applying line-count modulation to the input angle value, then performing sine and cosine calculations to generate sine or cosine encoding values ​​for one or more phases. This encoding process operates in two modes: direct output mode and PWM mode. In direct output mode, the sine wave encoding directly outputs the sine or cosine encoding value. In PWM mode, this direct output is further modulated by multiplying it by a configurable PWM period number (pwm_period[n:0]), enabling finer signal control.

[0053] In this embodiment, the sine wave encoding parameter and the angle signal to be calculated are input as input signals into the addition calculation module to perform the angle offset operation. The process includes: performing the angle offset calculation of the A phase in the sine wave encoding operation according to Formula 1, inputting the angle signal to be calculated (angle_cal[n:0]) and the A phase angle offset parameter (angle_a_shift[n:0]) into the addition calculation module, completing the calculation through the adder therein, and outputting the shifted angle value angle_a_shifted[n:0].

[0054] angle_a_shifted[n:0]=angle_cal[n:0]+angle_a_shift[n:0] (Formula 1)

[0055] In this embodiment, the sine wave encoding parameters and the angle signal to be calculated are input as input signals to the multiplication calculation module to perform line number modulation. The process of generating a sine wave angle modulation signal is shown in Equation 2. The shifted angle value (angle_a_shifted[n:0]) and the A phase line number modulation parameter (resolution_ana_a[n:0]) are input to the multiplication calculation module, and the multiplier completes the calculation and outputs a sine wave angle modulation signal (angle_a_scaled[n:0]). The purpose of line number remodulation is to map the input 0-360° angle range into resolution_* periodically varying encoded outputs, where these can be ana_a, ana_b, ana_c, abz, or pwm. The value of resolution_* represents the number of remodulated lines. It is worth noting that the result of the n+1-bit multiplication by the n+1-bit multiplier is 2n+2 bits. The lower n+1 bits of the multiplier are actually used as the sine wave angle modulation signal angle_a_scaled[n:0].

[0056] angle_a_scaled[n:0]=angle_a_shifted[n:0]*resolution_ana_a[n:0] (Formula 2)

[0057] In this embodiment, based on the sine wave angle modulation signal, the process of generating the corresponding segment index value includes: calculating the r-bit sine and cosine search index sincos_index[r-1:0] according to formula 3, which can be directly obtained through the formula without consuming additional computing resources. This index generation method is based on the demand for efficient processing of angle information. By using bit mapping instead of traditional floating-point calculations, the hardware complexity and computing overhead can be significantly reduced. In this embodiment, the depth of the sine and cosine lookup table is 2 r , indicating that 2 r sine or cosine values. The index generation follows a specific mapping rule: the highest bit (r-1) of sincos_index corresponds to the nth bit of angle_a_scaled, the second highest bit (r-2) corresponds to the n-1th bit, and so on. The lowest bit (0) corresponds to the n-r+1th bit. This embodiment avoids complex trigonometric function operations by using a table lookup method.

[0058] sincos_index[r-1:0]=angle_a_scaled[n:n-r+1] (Formula 3)

[0059] In this embodiment, the sinusoidal angle modulation signal is subjected to angle shifting. Specifically, the shift operation is performed using a preset reference angle to generate a residual angle value. The n+1-bit angle remainder, sincos_remain[n:0], is calculated using Equation 4, where constant0[r-1:0] represents r constants of 0. This means that the upper r bits of sincos_remain[n:0] are set to zero, while the lower n-r+1 bits correspond to the corresponding lower bits of the modulation angle anagle_a_scaled.

[0060] sincos_remain[n:0]={constant0[r-1:0],angle_a_scaled[nr:0]} (Formula 4)

[0061] In this embodiment, the segment index value is input as an input signal into the lookup table module to read the corresponding sine wave parameter value as shown in Formula 5 and Formula 6. This step is directly obtained through the lookup table module without consuming additional computing resources. Formula 5 shows the calculation formula for generating the standard sine value corresponding to the lookup index of the front angle, where sin() is the standard sine calculation and Pi is the standard pi. The r-bit sincos_index[r-1:0] is obtained from Formula 3, and its value range is 0 to 2 r -1, when the system selects the n and r values, the 2 r-1 value can be determined. Formula 6 shows the calculation formula for generating the standard cosine value corresponding to the search index of the current angle. cos() is the standard sine calculation, and Pi is the standard pi. The r bit sincos_index[n:0] is obtained from Formula 3, and its value range is 0 to 2 r -1, when the system selects the n and r values, the 2 r -1 value is sufficient for determination.

[0062] sin_value_lut(sincos_index)=sin((sincos_index*2 n-r+1 / 2 n+1 )*2*Pi) (Formula 5)

[0063] cos_value_lut(sincos_index)=cos((sincos_index*2 n-r+1 / 2 n+1 )*2*Pi) (Formula 6)

[0064] The calculation formulas for generating the sine multiplication coefficient lookup table and the cosine multiplication coefficient lookup table are shown in Formula 7 and Formula 8. This step is directly obtained through the lookup table module, without consuming additional computing resources. After obtaining the sin or cos value of the corresponding angle, the slope value, sin_slop_lut or cos_slop_lut, is calculated by further calculating the sin or cos value adjacent to the current index and calculating the difference between the sin or cos values ​​of the adjacent indexes. This slope value is the corresponding sine wave parameter value.

[0065] sin_slop_lut(sincos_index)=sin_value_lut(sincos_index+1)-sin_value_lut(sincos_index)

[0066] (Formula 7)

[0067] cos_slop_lut(sincos_index)=cos_value_lut(sincos_index+1)-cos_value_lut(sincos_index)

[0068] (Formula 8)

[0069] In this embodiment, the sine wave parameter value and the remaining angle value are input as input signals into the multiplication calculation module, and the process of calculating the sine wave incremental value is shown in Formulas 9 and 10. Formula 9 represents the calculation formula for the sine incremental value sin_delta[n:0], which is multiplied by sincos_remain[n:0] and sin_slop_lut(sincos_index), and is completed by the multiplication calculation module. It should be noted that sin_delta[n:0] is the high-order n+1 bits of the output result of the multiplication calculation module. Formula 10 represents the calculation formula for the cosine incremental value cos_delta[n:0], which is multiplied by sincos_remain[n:0] and cos_slop_lut(sincos_index), and is completed by the multiplication calculation module. It should be noted that cos_delta[n:0] is the high-order n+1 bits of the output result of the multiplication calculation module.

[0070] sin_delta[n:0]=sincos_remain[n:0]*sin_slop_lut(sincos_index) (Formula 9)

[0071] cos_delta[n:0]=sincos_remain[n:0]*cos_slop_lut(sincos_index)(Formula 10)

[0072] In this embodiment, the sine wave parameter value and the sine wave increment value are input into the addition calculation module as input signals, and the process of calculating and outputting the sine wave encoding signal is shown in Formula 11 and Formula 12.

[0073] ana_asin[n:0]=sin_value_lut(sincos_index)+sin_delta[n:0] (Formula 11)

[0074] ana_acos[n:0]=cos_value_lut(sincos_index)+cos_delta[n:0] (Formula 12)

[0075] Furthermore, the sine wave encoding mode in this embodiment is also compatible with the PWM control mode. A preset PWM period signal is received, and the sine wave parameter value and the sine wave increment value are input as input signals to the addition calculation module to generate a sine wave encoding signal. The sine wave encoding signal and the PWM period signal are then input as input signals to the multiplication calculation module. The process of calculating and outputting the PWM sine wave encoding signal is shown in Equations 13 and 14. Equation 13 represents the final calculation formula for ana_a[n:0] when a sine-encoded PWM output is used. It is equal to the sine value ana_asin[n:0] multiplied by pwm_period[n:0], and is performed by the multiplier. Note that ana_apwm(sin)[n:0] takes the upper n+1 bits of the multiplier output. Formula 14 shows the final calculation formula of ana_a[n:0] when the cosine coded PWM output is used. It is equal to the cosine value ana_acos[n:0] multiplied by pwm_period[n:0], which is completed by the multiplier. It should be noted that ana_apwm(cos)[n:0] takes the high n+1 bits of the multiplier output result. In order to be compatible with the output control of PWM,

[0076] ana_apwm(sin)[n:0]=ana_asin[n:0]*pwm_period[n:0] (Formula 13)

[0077] ana_apwm(cos)[n:0]=ana_acos[n:0]*pwm_period[n:0] (Formula 14)

[0078] In one embodiment of the present application, the process of the computing resource control unit performing a corresponding second encoding operation on each PWM encoding parameter in the encoding parameters according to the angle signal to be calculated includes: performing an angle offset operation and a line number modulation operation on the PWM encoding parameter and the angle signal to be calculated to generate a PWM modulation signal; inputting the PWM modulation signal and a preset PWM cycle parameter as input signals into the multiplication calculation module to calculate a first PWM encoding signal; and inputting the preset PWM cycle parameter and the first PWM encoding signal as input signals into the addition calculation module to calculate a second PWM encoding signal.

[0079] The PWM encoding output in this embodiment refers to a direct PWM encoding mode, wherein the PWM encoding parameters include a PWM offset parameter, a PWM line number modulation parameter, and a PWM modulation period. The process of performing an angle offset operation and a line number modulation operation on the PWM encoding parameters and the angle signal to be calculated to generate a PWM modulation signal includes: as shown in Formula 15, using an addition calculation module to multiply the angle signal to be calculated and the PWM offset parameter to generate an offset-corrected angle signal. As shown in Formula 16, the offset-corrected angle signal and the PWM line number modulation parameter are input into a multiplication calculation module to generate a line number-modulated PWM signal. It should be noted that angle_pwm_scaled[n:0] takes the lower n+1 bits of the multiplier result.

[0080] angle_pwm_shifted[n:0]=angle_cal[n:0]+angle_pwm_shift[n:0](Formula 15)

[0081] angle_pwm_scaled[n:0]=angle_pwm_shifted[n:0]*resolution_pwm[n:0](Formula 16)

[0082] Furthermore, the line-modulated PWM signal and the PWM modulation period are input into the multiplication module, where the calculation process shown in Equation 17 is performed. This formula represents the direct PWM code value calculation formula for Phase A, which is performed by the multiplier. Note that pwm_a[n:0] takes the high-order n+1 bits of the multiplier result. Correspondingly, the calculation process for Phase B is shown in Equation 18. The Phase A PWM code signal and the PWM modulation period are input into the addition module to generate the Phase B PWM code signal.

[0083] pwm_a[n:0]=angle_pwm_scale[n:0]*pwm_period[n:0] (Formula 17)

[0084] pwm_b[n:0]=pwm_period[n:0]-angle_pwm_a[n:0] (Formula 18)

[0085] In one embodiment of the present application, the computing resource control unit time-shares the lookup table module, the multiplication calculation module, and the addition calculation module, performs a corresponding first encoding operation and a second encoding operation on each encoding parameter according to the angle signal to be calculated, and generates a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated. The process includes: in each preset clock cycle, when the computing resource control unit performs the first encoding operation, the second encoding operation, or the third angle quantization operation, simultaneously performing one or more of the following operations in each clock cycle: configuring the lookup table module to receive an input signal in the current clock cycle and directly output a read result corresponding to the input signal; configuring the addition calculation module to receive an input signal in the current clock cycle, perform an addition operation, and directly output a calculation result corresponding to the input signal; configuring the multiplication calculation module to receive an input signal in the current clock cycle, perform a multiplication operation, and store the calculation result corresponding to the input signal in a latch for output in the next clock cycle; and reading and outputting the multiplication calculation result stored in the latch in the previous clock cycle. The beneficial effect of this embodiment is that within each preset clock cycle, the computing resource control unit allocates the operation order of the lookup table, addition module, and multiplication module as needed, allowing each module to complete its corresponding operation in turn at different time slices. This allows for the coordinated processing and continuous output of multiple computing tasks, even with limited hardware resources, through efficient allocation and timing management, thereby improving overall resource utilization.

[0086] The following will introduce the process of the computing resource control unit in the above-mentioned time-sharing multiplexing of the lookup table module, the multiplication calculation module, and the addition calculation module through an embodiment. In this process, the sharing of the adder calculation unit and the multiplier calculation unit is realized, reducing the chip circuit area and power consumption overhead. The computing resource control unit completes multiple addition operations and multiplication operations in the three encoding operations by time-sharing multiplexing the addition calculation module and the multiplication calculation module. The computing resource control unit includes the following control process: the addition calculation module has an adder built in to perform addition operations, and the multiplication calculation module has a multiplier built in to perform multiplication operations.

[0087] When the system is reset, all output coding signals are cleared and the calculation status indication signal cal_idle is set to valid. After the reset signal is released, at the sth system cycle, enable_mode is configured to any output enable state through the system bus. After that, when a valid pulse appears in the cal_valid input cache unit at a certain system clock cycle, recorded as the tth system clock cycle, the calculation resource control unit latches the input signal angle_cal[n:0] of this system clock cycle and sets cal_idle to an invalid state at the t+1th system clock cycle. The calculation resource control unit starts calculation at the tth system clock cycle. Table 1 shows the coding mode and calculation type executed in each clock cycle in this embodiment:

[0088]

[0089] Table 1: Encoding patterns and types of computations performed in each clock cycle

[0090] In the t-th system clock cycle of this embodiment, when cal_valid is detected as being in the valid state, the inputs of the adder are updated to angle_cal[n:0] and angle_shift_a[n:0], and the calculation is completed and the result angle_a_shifted[n:0] is output in the same clock cycle. Similarly, in this clock cycle, i.e., the t-th system clock cycle, the two sets of inputs of the multiplier are updated to angle_a_shifted[n:0] and resolution_ana_a[n:0] from the adder, and the output multiplier result is recorded as mult_result[2n+1:0]. The computing resource control unit has a 2n+2-bit latch for the multiplier result. The latch value of this latch is updated in the t+1-th system clock cycle, and the updated value is the multiplier calculation result in the t-th system clock cycle. In other words, each latch latches the multiplier calculation result of the previous clock cycle.

[0091] In the t+1th system clock cycle of this embodiment, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the tth system clock cycle. The lower n+1 bits of mult_result[n:0] in mult_result[2n+1:0] are used as the result of angle_a_scaled[n:0]. The input of the adder remains unchanged during the t+1th system clock cycle. Also during this clock cycle, i.e., the t+1th system clock cycle, the two sets of inputs to the multiplier are updated to sincos_remain[n:0] and sin_slop_lut(sincos_index) (when configured for sine encoding) or cos_slop_lut(sincos_index) (when configured for cosine encoding). sincos_remain[n:0] and sin_slop_lut(sincos_index) are directly derived from Equation 3-8, without the need for additional calculation.

[0092] In the t+2th system clock cycle of this embodiment, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the t+1th system clock cycle. The upper n+1 bits of mult_result[2n+1:0] are taken as sin_delta[n:0] or cos_delta[n:0]. In this clock cycle, the input of the adder is changed to sin_value_lut(sincos_index) (when configured in sine encoding mode) or cos_value_lut(sincos_index) (when configured in cosine mode) and sin_delta[n:0]. In this clock cycle, i.e., the t+2th system clock cycle, a new adder result ana_asin[n:0] (when configured in sine mode) or ana_acos[n:0] (when configured in cosine mode) is generated. If the currently configured sine wave mode is direct sine wave encoding, ana_asin[n:0] (when configured in sine mode) or ana_acos[n:0] (when configured in cosine mode) for this cycle is the final ana_a[n:0] output. The multiplier input remains unchanged. If configured in sine wave PWM encoding mode, in this clock cycle (i.e., the t+2 system clock cycle), one of the two sets of multiplier inputs is updated to the adder operation result from this system clock cycle, ana_asin[n:0] (when configured in sine mode) or ana_acos[n:0] (when configured in cosine mode), and the other set is updated to pwm_peiod[n:0].

[0093] In this embodiment, during system clock cycle t+3, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation during system clock cycle t+2. If the currently configured sine wave mode is direct sine wave encoding, the latch value during this cycle is irrelevant. If the currently configured sine wave mode is sine wave PWM encoding, the upper n+1 bits of mult_result[2n+1:0] are used as the final sine wave PWM encoded output ana_a[n:0]. At this point, the sine wave encoding for phase A is generated. Calculation of the encoding associated with phase B begins during this cycle. The calculations from t+0 to t+2 are repeated during cycles t+3 to t+5, replacing the angle offset and line count remodulation parameters with the values ​​corresponding to phase B.

[0094] In the t+6th system cycle of this embodiment, similar to the t+3th cycle, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the t+5th system clock cycle. If the currently configured sine wave mode is direct sine wave encoding, the latch value in this cycle is irrelevant. If the currently configured sine wave mode is sine wave PWM encoding, the upper n+1 bits of mult_result[2n+1:0] are used as the final sine wave PWM encoded output ana_b[n:0]. At this point, the sine wave code for phase B has been generated. The calculation of the code associated with phase C begins in this cycle. The calculations from t+0 to t+2 are repeated from t+6 to t+8, replacing the angle offset and line count remodulation parameters with the values ​​corresponding to phase C.

[0095] In this embodiment, in system cycle t+9, similar to cycle t+3, the result latched by latch mult_result[2n+1:0] is the result of the multiplier operation in system clock cycle t+8. If the currently configured sine wave mode is direct sine wave encoding, the latch value in this cycle is irrelevant. If the currently configured sine wave mode is sine wave PWM encoding, the upper n+1 bits of mult_result[2n+1:0] are used as the final sine wave PWM encoded output ana_c[n:0]. At this point, the sine wave encoding for phase C is generated. If ABZ incremental encoding output is enabled in the current output mode, then in the t+9th system clock cycle, the input of the adder is updated to angle_cal[n:0] and angle_abz_shift[n:0], and in this clock cycle, that is, the t+9th system clock cycle, the result of the adder is generated, recorded as angle_abz_shifted[n:0], and also in this clock cycle, the two sets of inputs of the multiplier are updated to the current adder output result angle_abz_shifted[n:0] and the input parameter resolution_abz[n:0].

[0096] In the t+10th system clock cycle of this embodiment, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the t+9th system clock cycle. The upper n+3 bits of this result are taken as the target angle value angle_abz[n+2:0] required for the ABZ incremental encoding output. During this cycle, the angle_abz_valid connected to the output encoding control unit is set to the valid state (maintained for one cycle and set to the invalid state in the t+11th system clock cycle). If the current output encoding mode enables the PWM direct encoding mode, then in this clock cycle, i.e., the t+10th system clock cycle, the input of the adder is updated to angle_cal[n:0] and angle_pwm_shift[n:0], and the result of the adder is angle_pwm_shifter[n:0]. Also in this clock cycle, that is, the t+10th system clock cycle, the two sets of inputs of the multiplier are updated to the results angle_pwm_shifted[n:0] and resolution_pwm[n:0] from the adder.

[0097] In the t+11th system clock cycle of this embodiment, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the t+10th system clock cycle. The lower n+1 bits of mult_result[n:0] in mult_result[2n+1:0] are used as the result of angle_pwm_scaled[n:0]. The input of the adder remains unchanged during the t+11th system clock cycle. Also during this clock cycle, the two sets of inputs to the multiplier are updated to angle_pwm_scale[n:0] and pwm_period[n:0]. During this system clock cycle, the signal cal_idle output by the computing resource control unit to the input buffer unit is updated to the active state.

[0098] In the t+12th system clock cycle of this embodiment, the result latched by the latch mult_result[2n+1:0] is the result of the multiplier operation in the t+11th system clock cycle. The high-order n+1 bits of mult_result[2n+1:0] are used as the result of the A-phase PWM code output pwm_a[n:0]. During this cycle, the input of the adder is updated to the complement of pwm_period[n:0] and pwm_a[n:0] (subtraction operation). The adder result is obtained in this clock cycle, which is the B-phase PWM code output wm_b[n:0]. In the t+12th system clock cycle, if cal_valid of the input buffer unit is valid, the process jumps to step 1) to start a new round of calculation, and the output cal_idle of the computing resource control unit is updated to an invalid state. Otherwise, the process will stop at step 9), and the output cal_idle of the computing resource control unit will remain invalid.

[0099] The nine steps above represent the complete calculation flow when all outputs in all encoding modes are enabled simultaneously. The enable_mode input parameter allows flexible selection of the encoding mode to be enabled and further refines control over the outputs of phases A, B, and C in the sine wave encoding, allowing unnecessary calculation steps to be skipped as needed to save computation cycles and resources. Regardless of the selected encoding mode or output combination, efficient hardware resource utilization can be achieved by time-sharing the addition, multiplication, and lookup table modules.

[0100] The encoding output control unit 103 is configured to receive a third angle parameter from the computing resource control unit; and perform a third encoding operation based on the third angle parameter to generate a third encoded signal.

[0101] In one embodiment of the present application, the process of the computing resource control unit 102 performing the corresponding third encoding operation on the incremental encoding parameter in each of the encoding parameters according to the angle signal to be calculated includes: inputting the incremental encoding parameter and the angle signal to be calculated as input signals into the addition calculation module to perform angle offset operation and line number modulation operation, and generate an ABZ incremental modulation signal.

[0102] In this embodiment, the incremental encoding parameters include two orthogonal A-phase and B-phase signals, a Z-phase zero position signal, an ABZ offset parameter, and an ABZ line count modulation parameter. The line count described in the ABZ line count modulation parameter corresponds to the number of high and low level cycles of the A or B phase during each Z-phase cycle. In other words, when the modulation line count is resolution_abz, when the input angle changes from 0 to 360°, the Z-phase signal will have a high level cycle, while the A or B phase will have a high-low cycle of resolution_abz times. When the incremental encoder is enabled, the incremental target angle angle_abz[n+2:0] must be calculated.

[0103] Equation 19 shows the calculation process for the ABZ offset angle signal. The angle signal to be calculated and the ABZ offset parameter are input into the addition module to generate the offset-corrected ABZ angle signal. Equation 20 shows the ABZ line number modulation process. The offset-corrected ABZ angle signal and the ABZ offset parameter are input into the multiplication module to generate the line number-modulated ABZ delta-modulation signal. Note that the ABZ delta-modulation signal angle_abz[n+2:0] is the upper n+3 bits of the multiplier result.

[0104] angle_abz_shifted[n:0]=angle_cal[n:0]+angle_abz_shift[n:0](Formula 19)

[0105] angle_abz[n+2:0]=angle_abz_shifted[n:0]*resolution_abz[n:0] (Formula 20)

[0106] In one embodiment of the present application, the encoding output control unit 103 performs a third encoding operation based on the third angle parameter to generate a third encoding signal. The process includes: inverting the lowest bit of the ABZ incremental modulation signal and outputting an A-phase incremental signal based on the inversion result; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low. Performing an exclusive OR operation on the lowest two bits of the ABZ incremental modulation signal and outputting a B-phase incremental signal based on the operation result; if the levels of the lowest two bits are consistent, the output B-phase incremental signal is low; otherwise, the output B-phase incremental signal is high. Performing an equality check operation on all bit data of the ABZ incremental modulation signal and a preset ABZ zero-bit reference value; if they are equal, a high-level Z-phase incremental signal is output; if they are not equal, a low-level Z-phase incremental signal is output.

[0107] In this embodiment, the parameters input to the encoding output control unit 103 from the computing resource control unit 102 include: the ABZ incremental modulation signal angle_abz[n+2:0] and the angle validity indication signal angle_abz_valid, as well as the system operating clock and reset signals from the system bus system_bus; and multiple configurable parameters. These configurable parameters include the ABZ bit width (abz_width), the ABZ initial angle value (abz_angle_init[n+2:0]), and the ABZ zero position reference value (abz_angle_z[n+2:0]), all of which can be configured according to specific requirements via the system bus system_bus.

[0108] The configurable parameter ABZ bit width (abz_width) controls the minimum number of toggle cycles for the A-phase and B-phase signals output by the ABZ incremental encoder. This refers to the number of system clock cycles required for the output signals abz_a or abz_b to transition from a high-level to a low-level, or vice versa. The configurable parameter ABZ incremental modulation signal (abz_angle_init[n+2:0]) controls the initial value of the internal position manager of the ABZ incremental encoder. The configurable parameter ABZ zero reference value (abz_angle_z[n+2:0]) controls the angle corresponding to the Z-phase output abz_z of the ABZ incremental encoder. The outputs of the ABZ incremental encoder unit include: the incremental encoder A-phase output abz_a; the incremental encoder B-phase output abz_b; and the incremental encoder Z-phase output abz_z. These three output signals together constitute the standard ABZ incremental encoder signal.

[0109] Upon system reset, the internal angle abz_inner[n+2:0] of the encoding unit is reset to zero. After the system reset is released, the initial value of the internal angle is derived from the configurable ABZ incremental modulation signal (abz_angle_init[n+2:0]) on the system bus. During the encoding process, when the angle validity indicator (ABZ valid flag signal (angle_abz_valid) is valid, the ABZ encoding unit uses the ABZ position information (angle_abz[n+2:0]) of the current system clock cycle as the current target angle. If the current internal angle abz_inner[n+2:0] is less than the current target angle, the encoding unit increments abz_inner[n+2:0] by one every ABZ bit width (abz_width) system clock cycles. If the current internal angle abz_inner[n+2:0] is greater than the current target angle, the encoding unit decrements abz_inner[n+2:0] by one every ABZ bit width (abz_width) system clock cycles. If the two are equal, abz_inner[n+2:0] remains unchanged.

[0110] When the angle valid indication signal ABZ valid flag signal (angle_abz_valid) is valid, the ABZ incremental encoding unit performs the following encoding steps according to Formulas 21 to 23 within the system clock cycle corresponding to each ABZ bit width (abz_width):

[0111] abz_a=inv(abz_inner[0]) (Formula 21)

[0112] abz_b=abz_inner[0]⊕abz_inner[1] (Formula 22)

[0113] abz_z=abz_inner[n+2:0]==angle_abz_z[n+2:0] (Formula 23)

[0114] As shown in Equation 21, the least significant bit of the ABZ position information (i.e., the internal angle abz_inner[n+2:0]) is inverted, and the A-phase incremental signal abz_a is output based on the inverted value. Specifically, if the least significant bit is high, the output A-phase incremental signal is low; if the least significant bit is low, the output A-phase incremental signal is high.

[0115] As shown in Equation 22, an exclusive-OR operation is performed on the lowest two bits of the ABZ position information, and the B-phase incremental signal abz_b is output based on the result. Specifically, if the levels of the lowest two bits are consistent (i.e., both high or both low), the output B-phase incremental signal is low; if the levels of the lowest two bits are inconsistent, the output B-phase incremental signal is high.

[0116] As shown in Equation 23, the encoding unit determines whether all bits of the ABZ position information are consistent with the ABZ zero-position reference value (abz_angle_z[n+2:0]). If they are consistent, the output Z-phase incremental signal abz_z is high; if not, the output Z-phase incremental signal abz_z is low.

[0117] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first encoding operation and the second encoding operation are merely used to distinguish between different encoding operations and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the quantity or execution order, and that terms such as "first" and "second" do not necessarily define differences.

[0118] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" represent examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0119] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0120] Figure 4 Schematic diagram of the low-cost motor encoding method provided by the embodiment of the present application. Figure 4 As shown, the method includes the following steps:

[0121] S41: receiving an original angle signal and a calculation idle indication signal, caching the original angle signal, and when the calculation idle indication signal is valid, reading the cached original angle signal.

[0122] S42: Receive multiple coding parameters; time-share multiplex the lookup table module, the multiplication calculation module and the addition calculation module, perform corresponding first coding operations and second coding operations on each coding parameter according to the angle signal to be calculated, and generate a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated.

[0123] S43: Perform a third encoding operation based on the third angle parameter to generate a third encoded signal.

[0124] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0125] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0126] Figure 5 : is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 5 As shown, the electronic terminal includes: at least one processor 501, a memory 502, at least one network interface 503 and a user interface 505. The various components in the device are coupled together via a bus system 504. It is understood that the bus system 504 is used to achieve connection and communication between these components. In addition to including a data bus, the bus system 504 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as bus systems.

[0127] The user interface 505 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0128] It will be appreciated that the memory 502 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM) or a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0129] The memory 502 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 500. Examples of such data include: any executable program for operating on the electronic terminal 500, such as an operating system 5021 and an application 5022; the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The low-cost motor encoding method provided by the embodiment of the present invention can be included in the application 5022.

[0130] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 501 or by software instructions. The above processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 501 may be a microprocessor or any conventional processor. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium located in a memory. The processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0131] In an exemplary embodiment, the electronic terminal 500 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0132] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the low-cost motor encoding method of any embodiment shown in the above embodiments.

[0133] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code. When the program code runs on a computer, the computer executes the low-cost motor encoding method of any embodiment shown in the above embodiments.

[0134] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0135] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0136] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0138] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0139] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0140] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0141] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0142] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0143] In summary, the present application provides a low-cost motor encoding system, method, medium, program product and terminal, through a scheme in which an input cache unit, a computing resource control unit and an encoding output control unit cooperate with each other, wherein the input cache unit is responsible for receiving the original angle signal from the position management system and caching it. The computing resource control unit performs corresponding multiple encoding and angle quantization operations according to different types of encoding parameters and the angle signal to be calculated by time-sharing multiplexing its internal lookup table module, multiplication calculation module and addition calculation module. The encoding output control unit receives the angle quantization result and completes the final encoding signal. Through the present application, a single chip can support multiple encoding types, realize hardware resource optimization, system cost reduction, integration improvement and application flexibility enhancement, which not only simplifies the system structure and improves system reliability, but also significantly accelerates the product development process and market speed. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0144] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A low-cost motor encoding system, characterized in that, include: An input cache unit, wherein the input cache unit is communicatively connected to the location management system and the computing resource control unit respectively; for receiving an original angle signal from the position management system and a calculation idle indication signal from the calculation resource control unit; the input buffer unit buffers the original angle signal and, when the calculation idle indication signal is valid, sends the buffered angle signal to be calculated to the calculation resource control unit; A computing resource control unit, comprising a multiplication computing module, an addition computing module and a lookup table module; the computing resource control unit is communicatively connected to the encoding output control unit; Used to receive multiple coding parameters and the angle signal to be calculated; the computing resource control unit time-division multiplexes the lookup table module, the multiplication calculation module and the addition calculation module, performs a corresponding first encoding operation and a second encoding operation on each coding parameter according to the angle signal to be calculated, and generates a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated; when the multiplication calculation module, the addition calculation module and the lookup table module are in an idle state, sends the calculation idle indication signal to the input buffer unit; The encoding output control unit is configured to receive a third angle parameter from the computing resource control unit; and perform a third encoding operation based on the third angle parameter to generate a third encoded signal.

2. The low-cost motor encoding system according to claim 1, characterized in that: The process of the computing resource control unit time-division multiplexing the lookup table module, the multiplication calculation module, and the addition calculation module, performing a corresponding first encoding operation and a second encoding operation on each coding parameter according to the angle signal to be calculated, and generating a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated includes: In each preset clock cycle, when the computing resource control unit performs the first encoding operation, the second encoding operation, or the third angle quantization operation, one or more of the following operations are simultaneously performed in each clock cycle: Configuring the lookup table module to receive an input signal in a current clock cycle and directly output a read result corresponding to the input signal; Configuring the addition calculation module to receive an input signal in a current clock cycle, perform an addition operation, and directly output a calculation result corresponding to the input signal; Configuring the multiplication calculation module to receive an input signal in a current clock cycle, perform a multiplication operation, and store a calculation result corresponding to the input signal into a latch for output in a next clock cycle; Read and output the multiplication result stored in the latch of the previous clock cycle.

3. The low-cost motor encoding system according to claim 2, characterized in that: The process of the computing resource control unit performing a corresponding first encoding operation on a sine wave encoding parameter in each encoding parameter according to the angle signal to be calculated includes: Performing an angle offset operation and a line number modulation operation on the sine wave encoding parameter and the angle signal to be calculated to generate a sine wave angle modulation signal; Based on the sine wave angle modulation signal, generating a corresponding segment index value; performing a shift operation on the sine wave angle modulation signal based on a preset reference angle to generate a residual angle value; Inputting the segment index value as an input signal into the lookup table module to read the corresponding sine wave parameter value; Inputting the sine wave parameter value and the remaining angle value as input signals into the multiplication calculation module to calculate the sine wave increment value; Inputting the sine wave parameter value and the sine wave increment value as input signals into the addition calculation module to calculate and output a sine wave coded signal; or receiving a preset PWM period signal, inputting the sine wave parameter value and the sine wave increment value as input signals into the addition calculation module to generate a sine wave coded signal, inputting the sine wave coded signal and the PWM period signal as input signals into the multiplication calculation module to calculate and output a PWM sine wave coded signal; The sine wave parameter value is a sine or cosine function value; the lookup table module stores pre-calculated sine or cosine function values ​​corresponding to multiple angles.

4. The low-cost motor encoding system according to claim 2, characterized in that: The process of the computing resource control unit performing a corresponding second encoding operation on the PWM encoding parameter in each encoding parameter according to the angle signal to be calculated includes: Performing an angle offset operation and a line number modulation operation on the PWM encoding parameter and the angle signal to be calculated to generate a PWM modulation signal; Inputting the PWM modulation signal and the preset PWM period parameter as input signals into the multiplication calculation module to calculate and obtain a first PWM coded signal; The preset PWM cycle parameter and the first PWM coded signal are input as input signals into the addition calculation module to calculate and obtain a second PWM coded signal.

5. The low-cost motor encoding system according to claim 2, characterized in that: The process of the computing resource control unit performing a corresponding third encoding operation on each incremental encoding parameter in the encoding parameters according to the angle signal to be calculated includes: The incremental encoding parameter and the angle signal to be calculated are input as input signals into the addition calculation module to perform angle offset operation and line number modulation operation, and generate an ABZ incremental modulation signal.

6. The low-cost motor encoding system according to claim 5, characterized in that: The encoding output control unit performs a third encoding operation based on the third angle parameter to generate a third encoded signal, the process comprising: Invert the lowest bit data of the ABZ incremental modulation signal, and output the A-phase incremental signal according to the inversion result; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low; Performing an exclusive OR operation on the lowest two bits of the ABZ incremental modulation signal, and outputting a B-phase incremental signal according to the operation result; wherein if the levels of the lowest two bits are consistent, the output B-phase incremental signal is a low level; otherwise, the output B-phase incremental signal is a high level; An equality judgment operation is performed on all bit data of the ABZ incremental modulation signal and a preset ABZ zero position reference value. If they are equal, a high-level Z-phase incremental signal is output; if they are not equal, a low-level Z-phase incremental signal is output.

7. A low-cost motor encoding method, the method is applied to an encoder, characterized in that: The method comprises: receiving an original angle signal and a calculation idle indication signal, caching the original angle signal, and reading the cached original angle signal when the calculation idle indication signal is valid; receiving a plurality of coding parameters; time-division multiplexing the lookup table module, the multiplication calculation module, and the addition calculation module, performing a corresponding first coding operation and a second coding operation on each coding parameter according to the angle signal to be calculated, and generating a third angle parameter by performing a third angle quantization operation on the angle signal to be calculated; A third encoding operation is performed based on the third angle parameter to generate a third encoded signal.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the low-cost motor encoding method according to claim 7 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program codes, and when the computer program codes are run on a computer, the computer is enabled to implement the low-cost motor encoding method according to claim 7 .

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the low-cost motor encoding method according to claim 7.

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