Photoetching alignment structure, forming method of photoetching alignment structure and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and discloses a photoetching alignment structure, a forming method of the photoetching alignment structure and a semiconductor device. The photoetching alignment structure comprises a semiconductor substrate and an alignment mark positioned on the semiconductor substrate; the alignment identifier comprises a plurality of first identifiers arranged at intervals along a first direction and a plurality of second identifiers arranged at intervals along a second direction perpendicular to the first direction, and each first identifier comprises a plurality of first sub-identifiers arranged at intervals along the second direction; each second identifier comprises a plurality of second sub-identifiers which are arranged at intervals along the first direction; the alignment identifiers are obtained based on the definition of the first graphical layer and the second graphical layer of the semiconductor substrate, and the spacing distance between the adjacent first identifiers is obtained based on the definition of the second graphical layer of the semiconductor substrate; the process of forming the second patterned layer is before the process of forming the first patterned layer, and the alignment mark can not only contain alignment information of the next layer in two directions, but also simplify the forming process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a photolithography alignment structure, a method for forming the photolithography alignment structure, and a semiconductor device. Background Art

[0002] As a key process for determining the critical dimensions of devices in the semiconductor manufacturing process, photolithography has always been a research hotspot. Especially nowadays, with the continuous miniaturization of device size, the requirements for the photolithography accuracy of the photolithography process are becoming higher and higher.

[0003] In the photolithography process, multi-layer patterning is usually achieved based on various alignment marks on the wafer. Usually, when multiple layers of patterns need to be superimposed, the photolithography alignment of the latter layer is achieved based on the alignment marks of the previous layer. When the latter layer is a key layer, the photolithography alignment needs to provide information in both horizontal and vertical directions. However, an alignment mark in the previous layer can only provide information in one direction. Therefore, if you want to obtain information in two directions, you need to occupy more effective chip area to place alignment marks in different directions. At the same time, it also requires the detector to use more time to obtain the horizontal and vertical information of the alignment mark. Summary of the Invention

[0004] To solve the above technical problems, the present application discloses, on one hand, a photolithography alignment structure, which includes:

[0005] semiconductor substrates;

[0006] An alignment mark provided on the semiconductor substrate; the alignment mark includes a plurality of first marks arranged at intervals along a first direction, and a plurality of second marks arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks includes a plurality of first sub-markers arranged at intervals along the second direction; each of the second marks includes a plurality of second sub-markers arranged at intervals along the first direction; the alignment mark is obtained based on the definition of the first graphic layer and the second graphic layer of the semiconductor substrate; wherein the spacing distance between adjacent first marks is obtained based on the definition of the second graphic layer of the semiconductor substrate; the process of forming the second graphic layer is located before the process of forming the first graphic layer.

[0007] In an optional embodiment, the number of the first identifiers is the same as the number of the second identifiers;

[0008] An end portion of one of the first marks is adjacent to an end portion of a corresponding one of the second marks.

[0009] In an optional embodiment, the lengths of the plurality of first marks arranged along the first direction gradually increase or decrease in the second direction;

[0010] The lengths of the plurality of second marks arranged along the second direction gradually increase or decrease in the first direction.

[0011] In an optional embodiment, the distance between the end of the first mark and the end of the second mark adjacent to each other along the second direction is the width of at least one of the first sub-mark or the second sub-mark.

[0012] In an optional embodiment, the alignment mark includes a first mark area and a second mark area that are mirror-symmetrical along a first axis;

[0013] In the first identification area, the lengths of the plurality of first identifications arranged along the first direction gradually increase or decrease in the second direction; the lengths of the plurality of second identifications arranged along the second direction gradually increase or decrease in the first direction.

[0014] In an optional embodiment, the alignment mark includes a third identification area and a fourth identification area that are mirror-symmetrical along a second axis; the third identification area includes the first identification area and the second identification area; and the first axis is perpendicular to the second axis.

[0015] In an optional embodiment, the interval between adjacent first marks is equal to the interval between adjacent second marks;

[0016] The interval between adjacent first marks is 1.5 to 2.5 microns.

[0017] In an optional embodiment, in each of the first identifiers, the intervals between adjacent first sub-identifiers are equal, and the sizes of the multiple first sub-identifiers are equal.

[0018] In an optional embodiment, the spacing distance between adjacent first sub-markers is 100 to 200 nanometers;

[0019] The length of the first sub-marker is 0.75 to 1.25 microns;

[0020] The width of the first sub-marker is 20 to 40 nanometers.

[0021] In an optional embodiment, in each of the second identifiers, the intervals between adjacent second sub-identifiers are equal, and the sizes of the plurality of second sub-identifiers are equal.

[0022] In an optional embodiment, the spacing distance between adjacent second sub-markers is 100 to 200 nanometers;

[0023] The length of the second sub-marker is 20 to 25 microns;

[0024] The width of the second sub-mark is 20 to 40 nanometers.

[0025] In an optional embodiment, the semiconductor substrate includes an active area and a scribe area;

[0026] The effective area is used to form functional devices;

[0027] The lane area surrounds the active area;

[0028] The alignment mark is provided in the scribe area and / or the effective area.

[0029] In an optional embodiment, the first patterned layer is a metal wiring layer;

[0030] The second patterned layer is a metal line segmentation layer.

[0031] In another aspect, the present application discloses a method for forming a photolithography alignment structure, comprising:

[0032] Providing an initial semiconductor structure; the initial semiconductor structure comprises a semiconductor substrate, a first mask material layer, and a second mask material layer arranged in sequence from bottom to top;

[0033] forming a second patterned layer on the second mask material layer;

[0034] Based on the second patterned layer, patterning the second mask material layer to form a second mask on the first mask material layer;

[0035] The second patterned layer is removed, and the first mask material layer is sequentially etched and deposited to form an alignment mark on the semiconductor substrate; the alignment mark includes a plurality of first marks arranged at intervals along a first direction, and a plurality of second marks arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks includes a plurality of first sub-marks arranged at intervals along the second direction; and each of the second marks includes a plurality of second sub-marks arranged at intervals along the first direction.

[0036] In an optional embodiment, the etching and deposition processes are performed on the first mask material layer in sequence to form an alignment mark on the semiconductor substrate, including:

[0037] Based on the second mask, etching the first mask material layer to form a first mask on the second mask;

[0038] Based on the first mask, etching the semiconductor substrate to a preset depth to form a groove region on the semiconductor substrate;

[0039] A metal material is deposited in the groove area to obtain an alignment mark.

[0040] On the other hand, the present application discloses a semiconductor device, characterized in that it includes the above-mentioned photolithography alignment structure.

[0041] The photolithography alignment structure provided in an embodiment of the present application includes a semiconductor substrate and alignment marks provided on the semiconductor substrate; the alignment marks include a plurality of first marks spaced apart along a first direction and a plurality of second marks spaced apart along a second direction; the first direction is perpendicular to the second direction; each first mark includes a plurality of first sub-marks spaced apart along the second direction; and each second mark includes a plurality of second sub-marks spaced apart along the first direction. The alignment marks are not only simple in structure but also contain alignment information in both horizontal and vertical directions. The periodic arrangement of the marks can help detection equipment identify and obtain horizontal and vertical information more quickly and accurately. The alignment marks are defined based on the first and second patterned layers of the semiconductor substrate, and the spacing between adjacent first marks is defined based on the second patterned layer of the semiconductor substrate. The process of forming the second patterned layer is performed before the process of forming the first patterned layer. Since the first and second patterned layers are necessary steps in the process of forming a semiconductor device, integrating them with the preparation of the alignment marks can simplify the steps of the overall semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 is a schematic diagram of an exemplary existing alignment mark of the present application;

[0044] Figure 2 yes Figure 1 A partial schematic diagram of an existing alignment mark;

[0045] Figure 3 This is a diagram showing the positional relationship between a metal wiring layer and a contact hole in an exemplary semiconductor device of the present application;

[0046] Figure 4is a schematic diagram of an exemplary existing photolithography alignment structure of the present application;

[0047] Figure 5 is a schematic diagram of an exemplary photolithography alignment structure of the present application;

[0048] Figure 6 is a partial schematic diagram of an exemplary photolithography alignment structure provided with a second patterned layer of the present application;

[0049] Figure 7 is a partial schematic diagram of another exemplary photolithography alignment structure provided with a second patterned layer of the present application;

[0050] Figure 8 is a partial schematic diagram of an exemplary photolithography alignment structure of the present application;

[0051] Figure 9 is a top view of another exemplary photolithography alignment structure of the present application;

[0052] Figure 10 is a schematic flow chart of an exemplary method for forming a photolithography alignment structure of the present application;

[0053] Figure 11-17 This is a structural schematic diagram of an exemplary process of forming a photolithography alignment structure in the present application.

[0054] The following is a supplementary description of the accompanying drawings:

[0055] 1-semiconductor substrate; 101-active area; 102-scribing area; 2-alignment mark; 3-first mark; 301-first sub-mark; 4-second mark; 401-second sub-mark; 5-first graphic layer; 6-second graphic layer; 601-horizontal definition segment; 602-vertical definition segment; 7-third graphic layer; 8-first identification area; 9-second identification area; 10-third identification area; 11-fourth identification area; 12-first mask material layer; 13-second mask material layer; 14-first mask; 15-first material layer; 16-second material layer; 17-anti-reflective layer; 18-photoresist. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0057] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0058] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0059] See also Figure 1-2 , which shows an exemplary existing alignment mark of the present application and a partially enlarged view of the existing alignment mark. Specifically, Figure 2 yes Figure 1 A partial enlarged view of the dotted box area, from Figure 2It can be seen that the existing alignment mark includes a plurality of marks arranged periodically along the third direction and the fourth direction. The third direction may refer to the direction of the midline of the vertical direction (such as the y-axis direction) and the horizontal direction (such as the x-axis direction), and the fourth direction is mirror-symmetric to the third direction about the y-axis. The spacing distances between adjacent marks in these marks along the third direction are equal. The mark may include a plurality of L-shaped sub-markers connected in sequence. The L-shaped sub-marker includes a transverse segment and a longitudinal segment. The transverse segment is perpendicularly connected to the longitudinal segment. The ends of the transverse segments in the existing marks are all connected to a longitudinal segment, or it can be said that the ends of the longitudinal segments are all connected to a transverse segment, so that each mark is stepped. Since the transverse segment is perpendicular to the longitudinal segment, the multiple marks arranged contain information in the vertical and horizontal directions. The above-mentioned marks must not only consider the horizontal and vertical directions, but also the third direction and other information. The structural design is relatively complex, and in semiconductor devices, the shapes of the various layers of the structure are also different. Figure 2 Because of the circuit shape shown, the mark is a part that needs to be processed separately, making the semiconductor device processing more complicated.

[0060] In the embodiment of the present application, the vertical direction may refer to Figure 2 The y direction shown may also refer to the first direction below, and the horizontal direction may refer to Figure 2 The x direction shown may also refer to the second direction below.

[0061] With the continuous development of semiconductor technology, chip integrated circuits are becoming increasingly miniaturized and integrated. Various semiconductor devices, such as MOS transistors, are usually integrated into chips. According to the channel type, MOS transistors can be divided into P-channel MOS field-effect transistors (abbreviated as POMS) and N-channel MOS field-effect transistors (abbreviated as NOMS). In the chip manufacturing process, not only the manufacture of semiconductor devices therein is involved, but also how to connect the functional layers of these semiconductor devices with the solder balls of the chip. This is generally achieved through metal wiring layers. Specifically, the metal wiring layers set on the multi-layer structure are connected in sequence and then connected to the solder balls at the bottom of the chip. Since the multi-layer structure has a certain thickness, and the metal wiring layers are usually deployed on the surface of the layer, all these layers are electrically connected through contact holes (also called conductive vias) set in the layer to connect the metal wiring layers on the surface of each layer. Therefore, the position of these contact holes is very critical. They need to be connected to the corresponding metal wires in both horizontal and vertical directions. Otherwise, if there is a deviation, it will affect the electrical performance of the device and even cause failure.

[0062] See also Figure 3, which shows a positional relationship diagram of a metal wiring layer and a contact hole in an exemplary semiconductor device of the present application, specifically a positional relationship diagram of the metal wiring layer (i.e., the first patterned layer 5), the contact hole layer (i.e., the third patterned layer 7) and the metal line segmentation layer (i.e., the second patterned layer 6) from a top view. It can be seen that the positions of the contact holes in the contact hole layer are defined by the metal wiring layer and the metal line segmentation layer, respectively. Specifically, the vertical direction of the contact hole (i.e., the y-axis direction) is defined by the edge of the metal line segmentation layer, and the horizontal direction of the contact hole (i.e., the x-axis direction) is defined by the metal line in the metal wiring layer. However, the above-mentioned alignment mark 2 currently used is usually formed when the metal wiring layer is formed, which means that the existing alignment mark 2 can actually only provide accurate horizontal direction information of the contact hole in the third patterned layer 7, but cannot provide accurate vertical direction information. This requires additional processes and time to prepare the alignment mark 2 that can provide vertical direction information, making the process of the semiconductor device more complicated.

[0063] See also Figure 4 The semiconductor substrate 1 includes an effective area 101 and a scribe area 102; the effective area 101 is used to form functional devices; the scribe area 102 surrounds the effective area 101; and the alignment mark 2 is provided in the scribe area 102. The scribe area 102 is subsequently used to form a dividing line, thereby dividing multiple devices on the wafer into independent devices. Since the structure of the existing alignment mark 2 is not compatible with the process steps in the chip, its graphics are not compatible with the graphics in the chip, and it occupies a large area, it is usually provided in the scribe area 102 of the semiconductor substrate 1. The larger the area and number of the alignment mark 2, the smaller the area of ​​the effective area 101 in the semiconductor substrate 1. Therefore, the use of the existing alignment mark 2 also affects the effective area 101 of the semiconductor substrate 1.

[0064] It should be noted that although the above application only describes the third patterned layer 7 as the contact hole layer, it is not actually limited to the third patterned layer 7 as the contact hole layer. As long as the process sequence of the third patterned layer 7 in the molding is after the first patterned layer 5 and the second patterned layer 6, one of the problems to be solved by the present application is that the alignment position of the third patterned layer 7 is determined by the first patterned layer 5 and the second patterned layer 6, but the alignment mark 2 formed synchronously during the process of molding the first patterned layer 5 or the second patterned layer 6 can only provide one direction information, and thus another alignment mark 2 needs to be additionally involved, which not only increases the complexity of the process, but also occupies more effective area 101 of the chip.

[0065] See also Figure 5 and 6The present application provides a photolithography alignment structure, comprising: a semiconductor substrate 1; and alignment marks 2 provided on the semiconductor substrate 1; the alignment marks 2 comprising a plurality of first marks 3 spaced apart along a first direction, and a plurality of second marks 4 spaced apart along a second direction; the first direction being perpendicular to the second direction; each first mark 3 comprising a plurality of first sub-marks 301 spaced apart along the second direction; and each second mark 4 comprising a plurality of second sub-marks 401 spaced apart along the first direction; the alignment marks 2 being defined based on a first patterned layer 5 and a second patterned layer 6 of the semiconductor substrate 1; the spacing between adjacent first marks 3 being defined based on the second patterned layer 6 of the semiconductor substrate 1; and the process for forming the second patterned layer 6 being performed before the process for forming the first patterned layer 5. As such, the photolithography alignment structure not only has a simple structure and enables precise alignment of the next process layer, but is also compatible with the molding process steps of the original semiconductor device, resulting in higher overall molding efficiency.

[0066] In the embodiment of the present application, the first direction may specifically refer to the negative direction of the y-axis, and the second direction may refer to the positive direction of the x-axis.

[0067] In the embodiments of this application, please refer to Figure 3 The first patterned layer 5 can be a metal wiring layer, the second patterned layer 6 can be a metal wire cutting layer, and the subsequently processed third patterned layer 7 can be a contact hole layer. However, it should be understood that the third patterned layer 7 is not limited to the contact hole layer; any process located after the first patterned layer 5 and requiring alignment lithography in both horizontal and vertical directions is acceptable. This example is merely for the purpose of facilitating a better understanding of the technical solution of this application.

[0068] In an optional embodiment, in order to facilitate molding processing, the number of the first identifiers 3 is the same as the number of the second identifiers 4; the end of a first identifier 3 is adjacent to the end of a corresponding second identifier 4, each first identifier 3 includes a first end and a second end sequentially arranged along the second direction, and each second identifier 4 includes a third end and a fourth end sequentially arranged along the first direction. Optionally, the first end and the third end are free ends, and the second end is adjacent to the fourth end. Macroscopically, a first identifier 3 and a second identifier 4 form an L-shaped identifier. Optionally, the width of each first sub-identifier 301 in the first identifier 3 is used to provide horizontal position information of the contact hole in the third graphic layer 7, and the end of each first sub-identifier 301 in the first identifier 3 is used to provide vertical position information of the contact hole in the third graphic layer 7. The second identifier 4 defines another vertical information, which, in combination with the horizontal information provided by the first identifier 4, can facilitate the identifier detector to quickly and accurately locate the alignment identifier 2. Please refer to Figure 6The gray areas in the figure are all second graphic layer 6, which defines the two ends of the first mark 3, that is, defines the spacing distance between adjacent first marks 3. Specifically, corresponding to the alignment mark 2, the pattern of the second graphic layer 6 can include multiple blocking bars arranged along the first direction, each blocking bar includes a vertically connected horizontal definition segment 601 and a vertical definition segment 602. The horizontal definition segment 601 is used to define the end of the first mark 3 and is located between adjacent first marks 3. The vertical definition segment 602 can be located between adjacent second marks 4. Based on Figure 7 It can be further seen that the second patterned layer 6 (specifically, the lateral definition segment 601) is located between adjacent first marks 3. Since the second patterned layer 6 is formed before the first patterned layer 5, the first patterned layer 5 is deposited on the semiconductor substrate 1 in the presence of the second patterned layer 6. This causes the metal wires in the first patterned layer 5 to be cut off due to the presence of the second patterned layer 6. After removing the second patterned layer 6, the following structure can be formed: Figure 8 The structure shown. This ensures that the horizontal and vertical information of the third patterned layer 7 are defined based on the first and second patterned layers, respectively. This allows the use of alignment marks with simple structures to improve the photolithography accuracy of the third patterned layer 7. In another optional embodiment, the first marks 3 and the second marks 4 may be arranged such that each first mark 3 includes a first end and a second end sequentially arranged along the first direction, and each second mark 4 includes a third end and a fourth end sequentially arranged along the second direction. Optionally, the first end and the third end are free ends, and the second end and the fourth end are adjacent.

[0069] In another optional embodiment, the number of first identifications 3 can also be greater than the number of second identifications 4, because the interval between adjacent first identifications 3 is defined by the second graphic layer 6, which determines the vertical information of the third graphic layer 7, and the width of each first sub-identification 301 in the first identification 3 along the second direction determines the horizontal information of the third graphic layer 7, so the first identification 3 is a key identification, as long as its periodic number can ensure the precise positioning of the contact hole in the third graphic layer 7.

[0070] In the embodiment of the present application, the alignment mark 2 as a whole can be as follows Figure 5 The square shown in FIG. 1 is a square. In this case, the lengths of each pair of first marks 3 and second marks 4 are equal. The alignment mark 2 can also be a rectangle, a circle, a trapezoid, etc., which is not limited here.

[0071] In an optional embodiment, the spacing between adjacent first marks 3 is equal to the spacing between adjacent second marks 4; the spacing between adjacent first marks 3 is 1.5 to 2.5 microns. In an exemplary embodiment of the spacing between adjacent first marks 3, the spacing between adjacent first marks 3 can be 1.5 microns, 1.7 microns, 1.9 microns, 2.1 microns, 2.3 microns, or 2.5 microns. Similarly, the spacing between adjacent second marks 4 can be 1.5 microns, 1.7 microns, 1.9 microns, 2.1 microns, 2.3 microns, or 2.5 microns.

[0072] In an alternative embodiment, see Figure 5 , the distribution of the first identifiers 3 and the second identifiers 4 may be such that the lengths of the multiple first identifiers 3 arranged along the first direction in the second direction gradually increase, and the lengths of the multiple second identifiers 4 arranged along the second direction gradually increase. Optionally, the distribution of the first identifiers 3 and the second identifiers 4 may also be such that the lengths of the multiple first identifiers 3 arranged along the first direction in the second direction gradually increase, and the lengths of the multiple second identifiers 4 arranged along the second direction in the first direction gradually decrease. Optionally, the distribution of the first identifiers 3 and the second identifiers 4 may also be such that the lengths of the multiple first identifiers 3 arranged along the first direction in the second direction gradually decrease, and the lengths of the multiple second identifiers 4 arranged along the second direction in the first direction gradually increase. Optionally, the distribution of the first identifiers 3 and the second identifiers 4 may also be such that the lengths of the multiple first identifiers 3 arranged along the first direction in the second direction gradually decrease, and the lengths of the multiple second identifiers 4 arranged along the second direction in the first direction gradually decrease.

[0073] In another alternative embodiment, please refer to Figure 5The alignment mark 2 includes a first marking area 8 and a second marking area 9 that are mirror-symmetrical along a first axis AA. In the first marking area 8, the lengths of the multiple first markings 3 arranged along the first direction in the second direction gradually increase or decrease; and the lengths of the multiple second markings 4 arranged along the second direction gradually increase or decrease. Because the first marking area 8 and the second marking area 9 are mirror-symmetrical along the first axis AA, in the second marking area 9, the lengths of the multiple first markings 3 arranged along the first direction in the second direction gradually increase or decrease; and the lengths of the multiple second markings 4 arranged along the second direction gradually decrease or increase. For example, when in the first marking area 8, the lengths of the multiple first markings 3 arranged along the first direction in the second direction gradually increase, and the lengths of the multiple second markings 4 arranged along the second direction gradually increase, in the second marking area 9, the lengths of the multiple first markings 3 arranged along the first direction in the second direction gradually increase; and the lengths of the multiple second markings 4 arranged along the second direction gradually decrease.

[0074] In another optional embodiment, the alignment mark 2 includes a third identification area 10 and a fourth identification area 11 that are mirror-symmetrical along a second axis BB; the third identification area 10 includes the first identification area 8 and the second identification area 9; the first axis AA is perpendicular to the second axis BB. Optionally, the first axis AA is parallel to the first direction, and the second axis BB is parallel to the second direction. Continuing with the above example, when, in the first identification zone 8 of the third identification zone 10, the lengths of the plurality of first marks 3 arranged along the first direction in the second direction gradually increase, and the lengths of the plurality of second marks 4 arranged along the second direction gradually increase, and in the second identification zone 9, the lengths of the plurality of first marks 3 arranged along the first direction in the second direction gradually increase, and the lengths of the plurality of second marks 4 arranged along the second direction gradually decrease, in the first identification zone 8 of the fourth identification zone 11, the lengths of the plurality of first marks 3 arranged along the first direction in the second direction gradually decrease, and the lengths of the plurality of second marks 4 arranged along the second direction gradually increase, and in the second identification zone 9, the lengths of the plurality of first marks 3 arranged along the first direction in the second direction gradually decrease, and the lengths of the plurality of second marks 4 arranged along the second direction gradually decrease. Whether it is the first identification zone 8, the second identification zone 9, the third identification zone 10, or the fourth identification zone 11, they are all symmetrical structures, facilitating the molding, processing, detection, and identification of the alignment mark 2.

[0075] In an optional embodiment, in each of the first identifiers 3, the intervals between adjacent first sub-identifiers 301 are equal, and the sizes of the plurality of first sub-identifiers 301 are equal. Figure 6 , the multiple first sub-identifiers 301 periodically arranged along the second direction in each first identifier 3 can be long strips (such as rectangles), and can specifically be metal wires formed synchronously with the first patterned layer 5. It should be noted that in the actual processing process, positioning and process deviations are inevitable, so that the spacing distances between the multiple first sub-identifiers 301 in the same first identifier 3 are not completely consistent. Optionally, the spacing distance between adjacent first sub-identifiers 301 is 100 to 200 nanometers, and specifically the distance between the centers of two adjacent first sub-identifiers 301 can be determined as the spacing distance between the two. In an exemplary embodiment of the spacing distance between adjacent first sub-identifiers 301, the spacing distance between adjacent first sub-identifiers 301 can be 100 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, 180 nanometers or 200 nanometers. The length of the first sub-marker 301 is 0.75 to 1.25 microns, specifically, the length of the first sub-marker 301 along the first direction is 0.75 to 1.25 microns. In an exemplary embodiment of the length of the first sub-marker 301, the length of the first sub-marker 301 can be 0.75 microns, 0.8 microns, 0.85 microns, 0.9 microns, 0.95 microns, 1.0 microns, 1.05 microns, 1.1 microns, 1.15 microns, 1.2 microns, or 1.25 microns. The width of the first sub-marker 301 is 20 to 40 nanometers, specifically, the length of the first sub-marker 301 along the second direction is 20 to 40 nanometers. In an exemplary embodiment of the width of the first sub-marker 301, the width of the first sub-marker 301 can be 20 nanometers, 22 nanometers, 24 nanometers, 26 nanometers, 28 nanometers, 30 nanometers, 32 nanometers, 34 nanometers, 36 nanometers, 38 nanometers, or 40 nanometers.

[0076] In an optional embodiment, in each second identifier 4, the intervals between adjacent second sub-identifiers 401 are equal, and the sizes of the plurality of second sub-identifiers 401 are equal. Figure 6, the multiple second sub-identifiers 401 periodically arranged along the second direction in each second identifier 4 can be long strips (such as rectangles), and can specifically be metal wires formed synchronously with the first patterned layer 5. It should be noted that in the actual processing process, positioning and process deviations are inevitable, so that the spacing distances between the multiple second sub-identifiers 401 in the same second identifier 4 are not completely consistent. Optionally, the spacing distance between adjacent second sub-identifiers 401 is 100 to 200 nanometers, and specifically the distance between the centers of two adjacent second sub-identifiers 401 can be determined as the spacing distance between the two. In an exemplary embodiment of the spacing distance between adjacent second sub-identifiers 401, the spacing distance between adjacent second sub-identifiers 401 can be 100 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, 180 nanometers, or 200 nanometers. The length of the second sub-marker 401 is 20 to 25 microns, specifically referring to the length of the second sub-marker 401 along the first direction being 20 to 25 microns. In an exemplary embodiment of the length of the second sub-marker 401, the length of the second sub-marker 401 can be 20 microns, 21 microns, 22 microns, 23 microns, 24 microns, or 25 microns. The width of the first sub-marker 301 is 20 to 40 nanometers, specifically referring to the length of the second sub-marker 401 along the second direction being 20 to 40 nanometers. In an exemplary embodiment of the width of the second sub-marker 401, the width of the second sub-marker 401 can be 20 nanometers, 22 nanometers, 24 nanometers, 26 nanometers, 28 nanometers, 30 nanometers, 32 nanometers, 34 nanometers, 36 nanometers, 38 nanometers, or 40 nanometers.

[0077] In the embodiment of the present application, in order to facilitate molding processing and detection and identification of identification, the spacing distance between adjacent first sub-identifiers 301 in each first identification 3 is the same, and the spacing distance between adjacent second sub-identifiers 401 in each second identification 4 is the same. However, due to limitations of the processing technology, or according to actual positioning needs, the spacing distance between adjacent first sub-identifiers 301 of each first identification 3 may also be different, and the spacing distance between adjacent second sub-identifiers 401 in each second identification 4 may also be different.

[0078] In an optional embodiment, the distance between the end of the first mark 3 and the end of the second mark 4 adjacent to each other along the second direction is the width of at least one first sub-mark 301 or second sub-mark 401. Figure 6In the middle circular dotted box area, there is a gap area between the last first sub-identifier 301 of the first identifier 3 and the first second sub-identifier 401 of the corresponding second identifier 4. Specifically, the gap area can be the width of one or two first sub-identifiers 301, or the width of one or two second sub-identifiers 401. The specific number can be set as needed. In an exemplary end, the spacing distance between the end of the first identifier 3 and the end of the second identifier 4 adjacent to each other along the second direction can be 200 to 400 nanometers, such as 200 nanometers, 220 nanometers, 240 nanometers, 260 nanometers, 280 nanometers, 300 nanometers, 320 nanometers, 340 nanometers, 360 nanometers, 380 nanometers or 400 nanometers. Since the first mark 3 and the second mark 4 are formed into an L shape during the processing of the second graphic layer 6, it is easy to cause the end of the first mark 3 to be cut into a non-horizontal straight line at its corner, thereby affecting the subsequent positioning accuracy of the third graphic layer 7. Based on the design of the above structure, even if the end of the horizontal definition segment 601 of the second graphic layer 6 corresponding to the end of the first mark 3 is not a regular shape, it will not affect the accurate definition of the horizontal direction of the end of the first mark 3.

[0079] In an alternative embodiment, see Figure 9 The alignment mark 2 can be set in the scribe area 102 of the semiconductor substrate 1. Optionally, since the molding process of the alignment mark 2 is synchronized with the processing technology of the first patterned layer 5 and the second patterned layer 6 in the semiconductor device, and the patterns of the first patterned layer 5 and the second patterned layer 6 are also relatively similar, the alignment mark 2 can also be designed in the effective area 101 of the semiconductor substrate 1, and integrated with the patterns of the first patterned layer 5 and the second patterned layer 6 to be molded. For example, the local pattern of the first patterned layer 5 molded in the semiconductor substrate 1 is used as the alignment mark 2. Not only does it not occupy the area of ​​the effective area 101, it also saves the occupation of the scribe area 102, which can improve the utilization rate of the wafer. Optionally, as needed, the alignment mark 2 can be set in both the scribe area 102 and the effective area 101 of the semiconductor substrate 1.

[0080] The present application provides a specific embodiment of a photolithography alignment structure. The photolithography alignment structure includes a semiconductor substrate 1; and an alignment mark 2 provided on the semiconductor substrate 1; the alignment mark 2 includes a plurality of first marks 3 arranged at intervals along a first direction, and a plurality of second marks 4 arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks 3 includes a plurality of first sub-marks 301 arranged at intervals along the second direction; each of the second marks 4 includes a plurality of second sub-marks 401 arranged at intervals along the first direction; the alignment mark 2 is obtained based on the definition of the first graphic layer 5 of the semiconductor substrate 1, and the spacing distance between adjacent first marks 3 is obtained based on the definition of the second graphic layer 6 of the semiconductor substrate 1, and the process of forming the second graphic layer 6 is located before the process of forming the first graphic layer 5. The first graphic layer 5 can refer to a metal wiring layer, the second graphic layer 6 can refer to a metal wire cutting layer, and the subsequently processed third graphic layer 7 can refer to a contact hole layer. As Figure 5 As shown, the first direction may specifically refer to the negative direction of the y-axis, and the second direction may refer to the positive direction of the x-axis.

[0081] The number of the first marks 3 is the same as the number of the second marks 4. The end of one first mark 3 is adjacent to the end of a corresponding second mark 4. The interval between adjacent first marks 3 is equal to the interval between adjacent second marks 4.

[0082] The alignment mark 2 includes a third marking area 10 and a fourth marking area 11 that are mirror-symmetrical along a second axis BB. The third marking area 10 includes a first marking area 8 and a second marking area 9. The first axis AA is perpendicular to the second axis BB. The alignment mark 2 includes a first marking area 8 and a second marking area 9 that are mirror-symmetrical along the first axis AA. In the first marking area 8, the lengths of the multiple first markings 3 arranged along the first direction gradually increase in the second direction, and the lengths of the multiple second markings 4 arranged along the second direction gradually increase in the first direction. In each first mark 3, the spacing between adjacent first sub-marks 301 is equal, and the sizes of the multiple first sub-marks 301 are equal. In each second mark 4, the spacing between adjacent second sub-marks 401 is equal, and the sizes of the multiple second sub-marks 401 are equal. The spacing between adjacent first sub-marks 301 in each first mark 3 is the same, and the spacing between adjacent second sub-marks 401 in each second mark 4 is the same. Optionally, the distance between the ends of the adjacent first mark 3 and the second mark 4 along the second direction is the width of at least one first sub-mark 301 or second sub-mark 401. The semiconductor substrate 1 includes an active area 101 and a scribe area 102; the active area 101 is used to form functional devices; the scribe area 102 surrounds the active area 101; and the alignment mark 2 is provided in the scribe area 102. The scribe area 102 is subsequently used to form a separation line, thereby separating multiple devices on the wafer into independent devices. Optionally, the alignment mark 2 is provided in both the scribe area 102 and the active area 101 of the semiconductor substrate 1.

[0083] The embodiment of the present application designs the structure of the alignment mark 2 and cooperates with the original molding process sequence during the chip molding process, so that the molded alignment mark 2 can not only contain the alignment information of the next layer in two directions (i.e., horizontal and vertical directions), but also has the advantage of simplifying the molding process steps of the alignment mark 2.

[0084] See also Figure 10 , the present application discloses a method for forming a photolithography alignment structure, which comprises:

[0085] S1001: providing an initial semiconductor structure; the initial semiconductor structure comprises a semiconductor substrate 1, a first mask material layer 12, and a second mask material layer arranged in sequence from bottom to top.

[0086] In the embodiment of the present application, the structure of the semiconductor substrate 1 is different depending on the different device structures being formed, but ultimately an alignment mark 2 must be formed on the semiconductor substrate 1. Since the alignment mark 2 is synchronized with the original forming process steps of the semiconductor device, the alignment mark 2 is specifically defined based on the first patterned layer 5. Therefore, although this application mainly describes the forming process of the alignment mark 2, it is actually also the forming process of the first patterned layer 5 of the semiconductor device.

[0087] In an embodiment of the present application, the first mask material layer 12 can be a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbon, silicon nitride oxide, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxide; the second mask material layer can be a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbon, silicon nitride oxide, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxide, and their thickness is not limited here.

[0088] In the embodiment of the present application, the above-mentioned step S1001 may specifically include: providing a semiconductor substrate 1, and sequentially forming a first mask material layer 12 and a second mask material layer on the semiconductor substrate 1 by using a deposition process. The deposition process includes chemical vapor deposition (CVD) and physical vapor deposition (PVD). Specifically, chemical vapor deposition can be plasma enhanced chemical vapor deposition (PEC VIID), high-density plasma chemical vapor deposition (high-density plasma DDP-CVD), sub-atmospheric pressure chemical vapor deposition (SACD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD) or other types of chemical vapor deposition. Optionally, physical vapor deposition can be a sputtering device or other types of physical vapor deposition.

[0089] S1003: forming a second patterned layer 6 on the second mask material layer.

[0090] In the embodiment of the present application, step S1003 may specifically include: forming a first material layer 15 on the second mask material layer, coating a photoresist 18 on the first material layer 15, patterning the photoresist 18, performing ion implantation on the exposed area of ​​the first material layer 15 based on the patterned photoresist 18, removing the photoresist 18 and the area of ​​the first material layer 15 not subjected to ion implantation, so as to form a second patterned layer 6 on the second mask material layer, that is, obtaining the following: Figure 11 The structure shown. Optionally, in addition to the above-mentioned ion implantation method to pattern the first material layer 15, an etching method (such as dry etching or wet etching) can also be used, that is, after the above-mentioned patterning of the photoresist 18, the first material layer 15 can also be etched based on the patterned photoresist 18, and the photoresist 18 is removed to obtain the second patterned layer 6. Whether ion implantation or etching is used to pattern the first material layer 15 is mainly related to the other layer structures that need to be manufactured synchronously in this step during the actual chip processing. The chip usually includes a variety of semiconductor devices, and the types of these semiconductor devices may be different, so the processing type or order of each layer may be different. However, in order to simplify the chip processing process, the steps of different layers of more different devices will be implemented in one step as much as possible. Therefore, when other structures in the chip need to be ion implanted in this step, the method of patterning the first material layer 15 in the embodiment of the present application can be formed by material ion implantation.

[0091] In another optional embodiment, to improve the accuracy of patterning the first material layer 15, step S1003 may specifically include: forming the first material layer 15 on the second mask material layer, forming the second material layer 16 on the first material layer 15, coating a photoresist 18 on the second material layer 16, patterning the photoresist 18, etching the second material layer 16 based on the patterned photoresist 18, performing ion implantation on the exposed areas of the first material layer 15, removing the photoresist 18 and the areas of the first material layer 15 not subjected to ion implantation, thereby forming a second patterned layer 6 on the second mask material layer. Because the surface of the first material layer 15 is not very flat due to its material type or molding method, the photoresist 18 directly coated thereon has poor flatness, which affects the photolithography accuracy. However, by first forming the second material layer 16 on the first material layer 15 (for example, the second material layer 16 can be a spin-on organic carbon material SOC), the surface of the second material layer 16 is relatively flat, thereby improving the flatness of the photoresist 18 directly coated thereon.

[0092] In another optional embodiment, in order to further improve the accuracy of patterning the first material layer 15, step S1003 may specifically include: forming the first material layer 15 on the second mask material layer, sequentially forming the second material layer 16 on the first material layer 15, sequentially forming the anti-reflection layer 17 and the photoresist 18 on the second material layer 16, patterning the photoresist 18, and obtaining the following: Figure 12 The structure shown in FIG. 1 is a structure in which the anti-reflection layer 17 is patterned based on the patterned photoresist 18, and then the second material layer 16 is etched to obtain the structure shown in FIG. Figure 13 The structure shown in FIG. 1 is ion-implanted into the exposed area of ​​the first material layer 15 to obtain Figure 14 The structure shown in FIG. 1 is obtained by removing the photoresist 18 and the region in the first material layer 15 where ions are not implanted, so as to form a second patterned layer 6 on the second mask material layer. Figure 11 The structure shown.

[0093] The anti-reflective coating 17 (ARC) in the photolithography process is mainly used to reduce the light reflection that occurs during the photolithography process. During the photolithography process, if the wafer substrate is a reflective material such as glass or metal, there will be a strong light reflection problem. When light hits its surface, part of the light is reflected, and the other part penetrates the substrate and enters the bottom layer. The reflected light will return to the photoresist layer, which may cause overexposure of the photoresist layer and produce problems such as blurring and distortion. To avoid this situation, an anti-reflective layer 17 is needed. This is a special film that can absorb or interfere with reflected light, thereby reducing the impact of reflection.

[0094] In the embodiment of the present application, the first material layer 15 includes amorphous silicon (ie, a-Si).

[0095] In the embodiment of the present application, the ions implanted include P-type ions; the P-type ions may include boron ions, boron fluoride ions or indium ions.

[0096] In an embodiment of the present application, the method for removing the area in the first material layer 15 where ion implantation is not performed can be a wet etching process, using liquid chemical reagents (such as acid, alkali and solvent, etc.) to remove the area in the first material layer 15 where ion implantation is not performed.

[0097] In the embodiment of the present application, the second patterned layer 6 may specifically refer to a metal wire cutting layer. Figure 6The gray areas in the figure are all the second graphic layer 6, which defines the two ends of the first mark 3, that is, limits the spacing distance between adjacent first marks 3. Specifically, corresponding to the alignment mark 2, the pattern of the second graphic layer 6 can be a plurality of blocking bars arranged along the first direction, each blocking bar includes a vertically connected horizontal definition segment 601 and a vertical definition segment 602, the horizontal definition segment 601 is used to define the end of the first mark 3, and is located between adjacent first marks 3, and the vertical definition segment 602 can be located between adjacent second marks 4.

[0098] S1005 : Based on the second patterned layer 6 , patterning the second mask material layer to form a second mask on the first mask material layer 12 .

[0099] In an optional embodiment, step S1005 may specifically include: forming a second material layer 16 on the second patterned layer 6, coating a photoresist 18 on the second material layer 16, patterning the photoresist 18, patterning the second material layer 16 and the first mask material layer 12 in sequence, removing the photoresist 18 and the second material layer 16 to form a second mask on the first mask material layer 12, and obtaining the following: Figure 15 The structure shown.

[0100] In another optional embodiment, in order to improve the accuracy of patterning the first material layer 15, step S1005 may specifically include: forming a second material layer 16 on the second patterned layer 6, and sequentially forming an anti-reflection layer 17 and a photoresist 18 on the second material layer 16, to obtain Figure 16 The structure shown in FIG. 1 is patterned with photoresist 18 to obtain Figure 17 The structure shown in FIG. 1 is sequentially patterned with the second material layer 16 and the first mask material layer 12, and the photoresist 18, the anti-reflection layer 17 and the second material layer 16 are removed to form a second mask on the first mask material layer 12, to obtain the following structure: Figure 15 The anti-reflection layer 17 is designed to reduce the reflection of light at the interface. The refractive index of the anti-reflection coating can be designed to be between that of the glass and the photoresist layer, thereby minimizing the reflected light, that is, reducing the standing wave effect and improving the lithography accuracy.

[0101] In the embodiment of the present application, the width of the patterned photoresist 18 is less than or equal to the width of the lateral definition segment 601 in the second patterned layer 6 , thereby ensuring that the pattern of the second mask subsequently formed is defined by the second patterned layer 6 .

[0102] S1007 : removing the second patterned layer 6 , and sequentially performing etching and deposition processes on the first mask material layer 12 to form an alignment mark 2 on the semiconductor substrate 1 .

[0103] In an embodiment of the present application, the alignment mark 2 includes a plurality of first marks 3 arranged at intervals along a first direction, and a plurality of second marks 4 arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks 3 includes a plurality of first sub-markers 301 arranged at intervals along the second direction; each of the second marks 4 includes a plurality of second sub-markers 401 arranged at intervals along the first direction.

[0104] In an optional embodiment, step S1007 may specifically include: etching the first mask material layer 12 based on the second mask to form a first mask 14 on the second mask; etching the semiconductor substrate 1 to a predetermined depth based on the first mask 14 to form a recessed region in the semiconductor substrate 1; and depositing a metal material in the recessed region to form an alignment mark 2. Optionally, after depositing the metal material, the surface of the semiconductor substrate 1 may be polished to improve the surface flatness of the semiconductor substrate 1.

[0105] In the embodiment of the present application, the metal material may be at least one of aluminum, tungsten, chromium, titanium, copper, silver and gold.

[0106] The present application also discloses a semiconductor device, characterized by including the above-mentioned photolithography alignment structure. Specifically, the semiconductor device can be a transistor, such as a MOS transistor, and the photolithography alignment structure includes a semiconductor substrate 1 and an alignment mark 2 provided on the semiconductor substrate 1; the alignment mark 2 includes a plurality of first marks 3 arranged at intervals along a first direction, and a plurality of second marks 4 arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each first mark 3 includes a plurality of first sub-marks 301 arranged at intervals along the second direction; each second mark 4 includes a plurality of second sub-marks 401 arranged at intervals along the first direction; the alignment mark 2 is defined based on a first patterned layer 5 of the semiconductor substrate 1, and the spacing between adjacent first marks 3 is defined based on a second patterned layer 6 of the semiconductor substrate 1; the process of forming the second patterned layer 6 is performed before the process of forming the first patterned layer 5, so that the alignment mark 2 can not only include alignment information of the next layer in two directions (i.e., the first direction and the second direction), but also simplify the steps of forming the alignment mark 2.

[0107] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A photolithography alignment structure, characterized in that: include: semiconductor substrates; An alignment mark provided on the semiconductor substrate; the alignment mark includes a plurality of first marks arranged at intervals along a first direction, and a plurality of second marks arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks includes a plurality of first sub-markers arranged at intervals along the second direction; each of the second marks includes a plurality of second sub-markers arranged at intervals along the first direction; the alignment mark is obtained based on the definition of the first graphic layer and the second graphic layer of the semiconductor substrate; wherein the spacing distance between adjacent first marks is obtained based on the definition of the second graphic layer of the semiconductor substrate; the process of forming the second graphic layer is located before the process of forming the first graphic layer.

2. The photolithography alignment structure according to claim 1, wherein: The number of the first identifiers is the same as the number of the second identifiers; An end portion of one of the first marks is adjacent to an end portion of a corresponding one of the second marks.

3. The photolithography alignment structure according to claim 2, wherein: The lengths of the plurality of first marks arranged along the first direction gradually increase or decrease in the second direction; The lengths of the plurality of second marks arranged along the second direction gradually increase or decrease in the first direction.

4. The photolithography alignment structure according to claim 2, wherein: The distance between the end of the first mark and the end of the second mark adjacent to each other along the second direction is the width of at least one of the first sub-marker or the second sub-marker.

5. The photolithography alignment structure according to claim 2, wherein: The alignment mark includes a first mark area and a second mark area that are mirror-symmetrical along a first axis; In the first mark area, the lengths of the plurality of first marks arranged along the first direction gradually increase or decrease in the second direction; The lengths of the plurality of second marks arranged along the second direction gradually increase or decrease in the first direction.

6. The photolithography alignment structure according to claim 5, wherein: The alignment mark includes a third identification area and a fourth identification area that are mirror-symmetrical along a second axis; the third identification area includes the first identification area and the second identification area; and the first axis is perpendicular to the second axis.

7. The photolithography alignment structure according to claim 1, wherein: The distance between adjacent first marks is equal to the distance between adjacent second marks; The interval between adjacent first marks is 1.5 to 2.5 microns.

8. The photolithography alignment structure according to claim 7, wherein: In each of the first identifiers, the intervals between adjacent first sub-identifiers are equal, and the sizes of the plurality of first sub-identifiers are equal.

9. The photolithography alignment structure according to claim 8, wherein: The interval between adjacent first sub-identifiers is 100 to 200 nanometers; The length of the first sub-marker is 0.75 to 1.25 microns; The width of the first sub-marker is 20 to 40 nanometers.

10. The photolithography alignment structure according to claim 7, wherein: In each of the second identifiers, the intervals between adjacent second sub-identifiers are equal, and the sizes of the plurality of second sub-identifiers are equal.

11. The photolithography alignment structure according to claim 10, wherein: The spacing between adjacent second sub-identifiers is 100 to 200 nanometers; The length of the second sub-marker is 20 to 25 microns; The width of the second sub-mark is 20 to 40 nanometers.

12. The photolithography alignment structure according to claim 1, wherein: The semiconductor substrate includes an active area and a scribe area; The effective area is used to form functional devices; The lane area surrounds the active area; The alignment mark is provided in the scribe area and / or the effective area.

13. The photolithography alignment structure according to claim 1, wherein: The first patterned layer is a metal wiring layer; The second patterned layer is a metal line segmentation layer.

14. A method for forming a photolithography alignment structure, characterized in that: include: providing an initial semiconductor structure; The initial semiconductor structure includes a semiconductor substrate, a first mask material layer, and a second mask material layer arranged in sequence from bottom to top; forming a second patterned layer on the second mask material layer; Based on the second patterned layer, patterning the second mask material layer to form a second mask on the first mask material layer; The second patterned layer is removed, and the first mask material layer is sequentially etched and deposited to form an alignment mark on the semiconductor substrate; the alignment mark includes a plurality of first marks arranged at intervals along a first direction, and a plurality of second marks arranged at intervals along a second direction; the first direction is perpendicular to the second direction; each of the first marks includes a plurality of first sub-marks arranged at intervals along the second direction; and each of the second marks includes a plurality of second sub-marks arranged at intervals along the first direction.

15. The forming method according to claim 14, wherein: The etching and deposition processing are performed on the first mask material layer in sequence to form an alignment mark on the semiconductor substrate, including: Based on the second mask, etching the first mask material layer to form a first mask on the second mask; Based on the first mask, etching the semiconductor substrate to a preset depth to form a groove region on the semiconductor substrate; A metal material is deposited in the groove area to obtain an alignment mark.

16. A semiconductor device, characterized in that: The method comprises the photolithography alignment structure according to any one of claims 1 to 13.

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