Low dropout regulator (LDO) implementation circuit with ultra-low power consumption

Abstract

The invention discloses an ultra-low power consumption LDO circuit, which relates to the technical field of electronic circuits and comprises a low power consumption oscillating circuit, a high power consumption BG circuit, a sampling hold circuit, a low power consumption LDO module and a detection module. The output end of the low-power-consumption oscillation circuit is connected with the input ends of the high-power-consumption BG circuit and the sampling hold circuit. The output end of the high-power-consumption BG circuit is connected with the input end of the sampling hold circuit; the output end of the sampling hold circuit is connected with the input end of the low-power-consumption LDO module and the input end of the detection module. The output end of the low-power-consumption LDO module is connected with the input end of the external system and the input end of the detection module. The ultra-low power consumption design is realized by periodically starting the high-power-consumption BG, the BG current is increased, the transistor works in a saturation region, the precision is higher, the transistor is not easily influenced by interference, the anti-interference capability is stronger, and meanwhile, the resistance required by the design is greatly reduced; the ultra-low power consumption is realized, the precision of the power supply system is higher, and the LDO area is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an ultra-low power consumption LDO circuit. Background Art

[0002] Low-power chips are widely used in IoT node devices such as mobile terminals, wearable devices, and IoT sensors. These products, which rely on small batteries for power, urgently need to reduce system power consumption and enhance battery life. As a key component of power management systems, the performance of LDOs directly impacts the overall circuit performance. Power modules are typically required to have extremely low quiescent current in standby or light-load mode to extend battery life. For example, IoT devices often require a quiescent current below 1μA.

[0003] To minimize the LDO's quiescent current, transistors typically operate in the subthreshold region. This results in significant variations in BG voltage depending on factors such as process corners. The LDO output further amplifies these variations, degrading the performance of the chip's power system. Furthermore, achieving ultra-low power consumption typically requires a significant number of resistors, which increases the LDO and chip area, a disadvantage for small wearable devices. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an ultra-low power consumption LDO circuit.

[0005] The object of the present invention is achieved through the following technical solutions: The present invention discloses an ultra-low-power LDO circuit, comprising a low-power oscillator circuit, a high-power BG circuit, a sample-and-hold circuit, a low-power LDO module, and a detection module; the output end of the low-power oscillator circuit is respectively connected to the input ends of the high-power BG circuit and the sample-and-hold circuit, the low-power oscillator circuit is used to generate a periodic signal to turn on or off the high-power BG circuit; the output end of the high-power BG circuit is connected to the input end of the sample-and-hold circuit, the high-power BG circuit is used to generate a reference voltage; the output end of the sample-and-hold circuit is respectively connected to the input ends of the low-power LDO module and the detection module, and the output end of the low-power LDO module is respectively connected to the input end of an external system and the detection module; the sample-and-hold circuit stores the reference voltage and provides a reference signal VBG_SH to the low-power LDO module, the low-power LDO module generates an LDO output VDD based on the reference signal VBG_SH; the detection module is used to detect whether the reference signal VBG_SH, the LDO output VDD, and the chip power supply reach a preset threshold, and output a final total detection output signal POC to the external system.

[0006] Furthermore, the low-power oscillator circuit includes a low-power oscillator, the output end of the low-power oscillator is connected to the clock input pin of the first D flip-flop, the output pin of the first D flip-flop is respectively connected to the clock input pin of the second D flip-flop and the input end of the first frequency divider, the output end of the first frequency divider is connected to the input end of the first logic gate, the output end of the first logic gate is connected to the input end of the second logic gate, the output pin of the second D flip-flop is respectively connected to the clock input pin of the third D flip-flop and the input end of the second frequency divider, the output pin of the third D flip-flop is connected to the input end of the third frequency divider, the output ends of the second frequency divider and the third frequency divider are respectively connected to the input end of the third logic gate, the output end of the third logic gate is respectively connected to the high-power BG circuit and the input end of the second logic gate, the high-power BG enable signal EN_BG is generated by the third logic gate, the output end of the second logic gate is connected to the sample and hold circuit, and the sample and hold enable signal EN_BG_SH is generated by the second logic gate.

[0007] Preferably, the high-power consumption BG circuit includes an operational amplifier AMP, a first transistor Q1, and a second transistor Q2. The positive input terminal of the operational amplifier AMP is connected to the emitter of the first transistor Q1, the negative input terminal of the operational amplifier AMP is connected in sequence to the third resistor and the emitter of the second transistor Q2, the first resistor R1 is connected in parallel between the positive input terminal and the output terminal of the operational amplifier AMP, the second resistor R2 is connected in parallel between the negative input terminal and the output terminal of the operational amplifier AMP, and the operational amplifier AMP is also connected to the output terminal of the third logic gate.

[0008] Preferably, the sample-and-hold circuit includes a sampling switch S1 and a sampling capacitor C_SH, the input end of the sampling switch S1 is respectively connected to the output end of the operational amplifier AMP and the second logic gate, the output end of the sampling switch S1 is respectively connected to the sampling capacitor C_SH and the low-power LDO module, and a stable reference signal VBG_SH is output through the sampling capacitor C_SH.

[0009] Preferably, the high power consumption BG circuit is turned on once every N clock cycles, and the sampling switch S1 is turned on once every N clock cycles, wherein the turn-on time of turning on the high power consumption BG circuit once is greater than the turn-on time of turning on the sampling switch S1 once.

[0010] Preferably, the detection module includes a BG detection circuit, an LDO detection circuit and a power detection circuit. The BG detection circuit is used to detect the reference signal VBG_SH and generate a BG detection signal POC_BG. If the BG detection signal POC_BG reaches a first preset threshold, the first high level is output; the LDO detection circuit is used to detect the LDO output VDD and generate an LDO detection signal POC_VDD. If the LDO detection signal POC_VDD reaches a second preset threshold, the second high level is output; the power detection circuit is used to detect the chip power supply and generate a power detection signal POC_POWER. If the power detection signal POC_POWER reaches a third preset threshold, the third high level is output; if the first high level, the second high level and the third high level are output simultaneously, the final total detection output signal POC is a high level.

[0011] The beneficial effects of the present invention are: 1) Ultra-low power design is achieved by periodically turning on the high-power BG, which increases the BG current and makes the transistor operate in the saturation region, resulting in higher precision, less susceptible to interference, and stronger anti-interference ability. At the same time, the resistance required for the design is greatly reduced.

[0012] 2) While achieving ultra-low power consumption, the power system is more accurate and the LDO area is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a principle block diagram of an ultra-low power LDO circuit according to an embodiment of the present invention; Figure 2 This is a principle block diagram of implementing BG and sample-hold enabling according to an embodiment of the present invention; Figure 3 This is a waveform diagram of implementing BG and sample-hold enable according to an embodiment of the present invention; Figure 4 This is a principle block diagram of periodically opening BG and sampling and holding according to an embodiment of the present invention; Figure 5 This is a waveform diagram of periodically opening BG and sampling and holding according to an embodiment of the present invention; Figure 6 This is a waveform diagram of BG / LDO / power supply detection according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0015] The present invention discloses an ultra-low power consumption LDO circuit. The principle block diagram of the present invention is as follows: Figure 1 As shown, it includes a low-power oscillation circuit, a high-power BG circuit, a sampling and holding circuit, a low-power LDO module and a detection module; the output end of the low-power oscillation circuit is respectively connected to the input end of the high-power BG circuit and the sampling and holding circuit, and the low-power oscillation circuit is used to generate a periodic signal to turn on or off the high-power BG circuit; the output end of the high-power BG circuit is connected to the input end of the sampling and holding circuit, and the high-power BG circuit is used to generate a reference voltage; the output end of the sampling and holding circuit is respectively connected to the input end of the low-power LDO module and the detection module, and the output end of the low-power LDO module is respectively connected to the input end of the external system and the detection module; the sampling and holding circuit saves the reference voltage and provides a reference signal VBG_SH to the low-power LDO module, and the low-power LDO module generates an LDO output VDD based on the reference signal VBG_SH; the detection module is used to detect whether the reference signal VBG_SH, the LDO output VDD and the chip power supply reach a preset threshold, and output a final total detection output signal POC to the external system to inform the subsequent system whether the LDO output can be used.

[0016] Specifically, the principle block diagram for realizing BG and sample-hold enable is as follows: Figure 2 As shown, the low-power oscillator circuit includes a low-power oscillator, the output end of the low-power oscillator is connected to the clock input pin of the first D flip-flop, the output pin of the first D flip-flop is respectively connected to the clock input pin of the second D flip-flop and the input end of the first frequency divider, the output end of the first frequency divider is connected to the input end of the first logic gate, the output end of the first logic gate is connected to the input end of the second logic gate, the output pin of the second D flip-flop is respectively connected to the clock input pin of the third D flip-flop and the input end of the second frequency divider, the output pin of the third D flip-flop is connected to the input end of the third frequency divider, the output ends of the second frequency divider and the third frequency divider are respectively connected to the input end of the third logic gate, the output end of the third logic gate is respectively connected to the high-power BG circuit and the input end of the second logic gate, the high-power BG enable signal EN_BG is generated by the third logic gate, the output end of the second logic gate is connected to the sample and hold circuit, and the sample and hold enable signal EN_BG_SH is generated by the second logic gate.

[0017] For example, the waveform diagram for realizing BG and sample-hold enable is as follows: Figure 3As shown, taking n=8 as an example, the low-power oscillator generates a clock signal, the first frequency divider is a divide-by-2 output frequency divider, and generates a first frequency-divided signal F_DIV2, the second frequency divider is a divide-by-4 output frequency divider, and generates a second frequency-divided signal F_DIV4, and the third frequency divider is an divide-by-8 output frequency divider, and generates a third frequency-divided signal F_DIV8; the second frequency-divided signal F_DIV4 and the third frequency-divided signal F_DIV8 are logically "ANDed" through the third logic gate to generate a high-power BG enable signal EN_BG, which is output to the high-power BG circuit and the second logic gate; the first frequency-divided signal F_DIV2 is logically "noted" through the first logic gate to generate a negated signal F_DIV2_N; the high-power BG enable signal EN_BG and the negated signal F_DIV2_N are logically "ANDed" through the second logic gate to generate a sample-and-hold enable signal EN_BG_SH, which is output to the sample-and-hold circuit.

[0018] Specifically, the principle block diagram of periodically opening BG and sampling and holding is as follows Figure 4 As shown, the high-power consumption BG circuit includes an operational amplifier AMP, a first transistor Q1, and a second transistor Q2. The positive input terminal of the operational amplifier AMP is connected to the emitter of the first transistor Q1, the negative input terminal of the operational amplifier AMP is connected in sequence to the third resistor and the emitter of the second transistor Q2, the first resistor R1 is connected in parallel between the positive input terminal and the output terminal of the operational amplifier AMP, the second resistor R2 is connected in parallel between the negative input terminal and the output terminal of the operational amplifier AMP, and the operational amplifier AMP is also connected to the output terminal of the third logic gate.

[0019] Specifically, the sample-and-hold circuit includes a sampling switch S1 and a sampling capacitor C_SH. The input end of the sampling switch S1 is respectively connected to the output end of the operational amplifier AMP and the second logic gate. The output end of the sampling switch S1 is respectively connected to the sampling capacitor C_SH and the low-power LDO module. A stable reference signal VBG_SH is output through the sampling capacitor C_SH.

[0020] Specifically, the high power consumption BG circuit is turned on once every N clock cycles, and the sampling switch S1 is turned on once every N clock cycles, wherein the turn-on time of turning on the high power consumption BG circuit once is greater than the turn-on time of turning on the sampling switch S1 once.

[0021] For example, the waveform of periodically opening BG and sampling and holding is as follows: Figure 5 As shown, the low-power oscillator generates a clock signal, and generates a high-power BG enable signal EN_BG and a sampling and holding enable signal EN_BG_SH through a low-power oscillation circuit; the high-power BG is turned on once every N clock cycles. Figure 5 The open time is 2 clock cycles, and the average power consumption is 2 / N; the sampling switch S1 is opened once every N clock cycles. Figure 5 Its start-up time is 1 clock cycle, which is 1 clock cycle slower than the high-power BG. The purpose is to wait for the high-power BG circuit to complete startup and stabilize the output reference voltage VBG. The sampling and holding capacitor C_SH outputs a stable reference signal VBG_SH. Considering the influence of leakage and other consumption, the stored signal will gradually decrease. Therefore, sampling is performed once every N clock cycles to ensure signal accuracy.

[0022] For example, the waveform of BG / LDO / power supply detection is as follows: Figure 6 As shown, the detection module includes a BG detection circuit, an LDO detection circuit, and a power detection circuit. The BG detection circuit is used to detect the reference signal VBG_SH and generate a BG detection signal POC_BG. If the BG detection signal POC_BG reaches a first preset threshold, it outputs a first high level. The signal output by the sampling and holding circuit is given to the low-power LDO as a reference to generate the LDO output VDD. The LDO detection circuit is used to detect the LDO output VDD and generate an LDO detection signal POC_VDD. If the LDO detection signal POC_VDD reaches a second preset threshold, it outputs a second high level. The power detection circuit is used to detect the chip power supply and generate a power detection signal POC_POWER. If the power detection signal POC_POWER reaches a third preset threshold, it outputs a third high level. The detection module performs "AND" logic. If the first high level, the second high level, and the third high level are output simultaneously, the final total detection output signal POC is a high level, indicating that the power system is stable and can be used. The first preset threshold, the second preset threshold, and the third preset threshold are preset values ​​based on the actual working environment and are not limited to a specific value.

[0023] In summary, the present invention provides an ultra-low-power LDO implementation circuit, comprising a low-power oscillator circuit, a high-power BG circuit, a sample-and-hold circuit, a low-power LDO module, and a detection module. The low-power oscillator circuit generates a periodic signal for turning the high-power BG on and off. The sample-and-hold circuit stores the BG output and provides it to the low-power LDO module as a reference to generate a power output. Simultaneously, the circuit detects whether the BG / LDO / power supply reaches a predetermined value, ultimately informing the downstream system whether the LDO output can be used. To minimize the LDO's quiescent current, transistors in chips typically operate in the subthreshold region, resulting in significant BG voltage variations with process corners and other factors. The BG in this application utilizes a high-power design, resulting in higher stability and precision. This increases the BG current, reduces leakage and external interference (such as interference from IO negative voltage through substrate current on the BG), and enhances the anti-interference capabilities of the BG and circuits using the BG as a reference, such as power-up and power-down detection. Furthermore, by periodically turning on the high-power BG, this application eliminates the need for large resistors to achieve ultra-low power consumption, reducing the LDO and chip area, which is beneficial for small wearable devices.

[0024] This invention achieves ultra-low power consumption by periodically turning on a high-power BG. This allows for high BG current, saturation operation of the transistor, and improved precision. This reduces interference and significantly reduces the required resistance. While achieving ultra-low power consumption, the power supply system also achieves higher precision and a smaller LDO footprint.

[0025] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.

Claims

1. An ultra-low power LDO circuit, characterized in that: It includes a low-power oscillation circuit, a high-power BG circuit, a sampling and holding circuit, a low-power LDO module and a detection module; the output end of the low-power oscillation circuit is respectively connected to the input ends of the high-power BG circuit and the sampling and holding circuit, and the low-power oscillation circuit is used to generate a periodic signal to turn on or off the high-power BG circuit; the output end of the high-power BG circuit is connected to the input end of the sampling and holding circuit, and the high-power BG circuit is used to generate a reference voltage; the output end of the sampling and holding circuit is respectively connected to the input ends of the low-power LDO module and the detection module, and the output end of the low-power LDO module is respectively connected to the input end of the external system and the detection module; the sampling and holding circuit saves the reference voltage and provides a reference signal VBG_SH to the low-power LDO module, and the low-power LDO module generates an LDO output VDD based on the reference signal VBG_SH; the detection module is used to detect whether the reference signal VBG_SH, the LDO output VDD and the chip power supply reach a preset threshold, and output the final total detection output signal POC to the external system.

2. The ultra-low power LDO circuit according to claim 1, wherein: The low-power oscillator circuit includes a low-power oscillator, the output end of the low-power oscillator is connected to the clock input pin of the first D flip-flop, the output pin of the first D flip-flop is respectively connected to the clock input pin of the second D flip-flop and the input end of the first frequency divider, the output end of the first frequency divider is connected to the input end of the first logic gate, the output end of the first logic gate is connected to the input end of the second logic gate, the output pin of the second D flip-flop is respectively connected to the clock input pin of the third D flip-flop and the input end of the second frequency divider, the output pin of the third D flip-flop is connected to the input end of the third frequency divider, the output ends of the second frequency divider and the third frequency divider are respectively connected to the input ends of the third logic gate, the output end of the third logic gate is respectively connected to the high-power BG circuit and the input ends of the second logic gate, the high-power BG enable signal EN_BG is generated by the third logic gate, the output end of the second logic gate is connected to the sample and hold circuit, and the sample and hold enable signal EN_BG_SH is generated by the second logic gate.

3. The ultra-low power consumption LDO circuit according to claim 2, wherein: The high-power consumption BG circuit includes an operational amplifier AMP, a first transistor Q1, and a second transistor Q2. The positive input terminal of the operational amplifier AMP is connected to the emitter of the first transistor Q1, the negative input terminal of the operational amplifier AMP is connected in sequence to the third resistor and the emitter of the second transistor Q2, the first resistor R1 is connected in parallel between the positive input terminal and the output terminal of the operational amplifier AMP, the second resistor R2 is connected in parallel between the negative input terminal and the output terminal of the operational amplifier AMP, and the operational amplifier AMP is also connected to the output terminal of the third logic gate.

4. The ultra-low power consumption LDO circuit according to claim 3, wherein: The sample-and-hold circuit includes a sampling switch S1 and a sampling capacitor C_SH. The input end of the sampling switch S1 is respectively connected to the output end of the operational amplifier AMP and the second logic gate. The output end of the sampling switch S1 is respectively connected to the sampling capacitor C_SH and the low-power LDO module. A stable reference signal VBG_SH is output through the sampling capacitor C_SH.

5. The ultra-low power consumption LDO circuit according to claim 4, characterized in that: The high power consumption BG circuit is turned on once every N clock cycles, and the sampling switch S1 is turned on once every N clock cycles. The turn-on time of the high power consumption BG circuit is greater than the turn-on time of the sampling switch S1.

6. The ultra-low power consumption LDO circuit according to claim 4, characterized in that: The detection module includes a BG detection circuit, an LDO detection circuit and a power detection circuit. The BG detection circuit is used to detect the reference signal VBG_SH and generate a BG detection signal POC_BG. If the BG detection signal POC_BG reaches a first preset threshold, the first high level is output; the LDO detection circuit is used to detect the LDO output VDD and generate an LDO detection signal POC_VDD. If the LDO detection signal POC_VDD reaches a second preset threshold, the second high level is output; the power detection circuit is used to detect the chip power supply and generate a power detection signal POC_POWER. If the power detection signal POC_POWER reaches a third preset threshold, the third high level is output; if the first high level, the second high level and the third high level are output simultaneously, the final total detection output signal POC is a high level.

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