Chip and software reset structure and software reset method thereof
By designing the chip's software reset structure, including a reset control unit, a register access control unit, and a global reset control unit, the problem of the chip being unable to be globally reset is solved, achieving fast recovery and flexible operation.
Patent Information
- Application Number
- CN202510708792.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-19
AI Technical Summary
In the prior art, a chip cannot achieve a global reset of all functional modules through software reset.
A chip software reset structure is designed, including a reset control unit, a register access control unit and a global reset control unit. Through collaborative action, all functional units in the chip are reset. The reset control information is synchronized with the clock signal to ensure the flexibility and reliability of the reset process.
It achieves timely global reset of the chip and quickly restores it to normal working state, reduces error recovery time, and improves operational flexibility and maintainability.
Smart Images
Figure CN120669833A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip manufacturing, and in particular to a chip and a software reset structure and a software reset method thereof. Background Art
[0002] The reset circuit plays a vital role in the chip. It can ensure that the chip returns to its initial state under certain conditions, thereby ensuring the reliability and stability of the chip.
[0003] Resets typically include hardware resets and software resets. A hardware reset typically restores the entire chip to its initial state through on-chip power-on / off resets or by inputting a valid pulse width level to a chip pin. A software reset typically resets the chip's Intellectual Property (IP) or functional modules by configuring specified registers.
[0004] However, current chips cannot achieve a global reset of all functional modules in the chip when resetting through software. Summary of the Invention
[0005] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that all functional modules of the chip cannot be globally reset during software reset, and to provide a chip and its software reset structure and software reset method, and the software reset structure can configure the time when implementing the reset.
[0006] The present disclosure solves the above technical problems through the following technical solutions:
[0007] According to a first aspect of the present disclosure, a software reset structure of a chip is provided, the software reset structure comprising: a reset control unit, a register access control unit, and a global reset control unit connected in communication;
[0008] Wherein, the reset control unit is used to send a reset control signal;
[0009] The register access control unit is configured to receive the reset control signal and obtain reset control information based on the reset control signal; the reset control information includes a maximum reset time;
[0010] The maximum reset time is determined based on the time required for resetting the functional units in the chip;
[0011] The global reset control unit is used to reset all the functional units in the chip based on the reset control information.
[0012] Optionally, the reset control information further includes a reset start signal and a reset state signal; wherein the reset state signal includes a reset progress signal and a reset completion signal;
[0013] The global reset control unit includes a register unit and a reset completion unit connected in communication;
[0014] The register unit is used to store the reset start signal, set the reset state signal to the reset proceed signal, and send the reset start signal to the reset completion unit;
[0015] The reset completion unit is configured to receive the reset start signal, start the reset timing, obtain an actual reset duration, and in response to the actual reset duration reaching the maximum reset time, generate identification information and send the identification information to the register unit for storage;
[0016] The register unit is further configured to receive the identification information, and modify the reset state signal into the reset completion signal and output the signal.
[0017] Optionally, the global reset control unit further includes a signal synchronization unit;
[0018] The signal synchronization unit is communicatively connected with the register unit and the reset completion unit;
[0019] The signal synchronization unit is used to synchronize signals between the register unit and the reset completion unit.
[0020] Optionally, the register unit includes a first register, a second register, and a third register that are communicatively connected;
[0021] Wherein, the first register is used to store the maximum reset time;
[0022] The second register is used to store the reset start signal;
[0023] The third register is used to store the reset state signal of the chip during the reset process.
[0024] Optionally, the signal synchronization unit includes a multi-stage trigger.
[0025] Optionally, the reset completion unit includes a counter.
[0026] Optionally, the software reset structure further includes a clock control unit;
[0027] The clock control unit is communicatively connected to the reset control unit, the register access control unit and the global reset control unit respectively;
[0028] The clock control unit is used to generate a clock signal and synchronize the clock frequencies of the reset control unit, the register access control unit and the global reset control unit based on the clock signal.
[0029] According to a second aspect of the present disclosure, a chip software reset method is provided, the software reset method comprising:
[0030] Get reset control signal;
[0031] The reset control signal is sent to the software reset structure based on the first aspect of the present disclosure, and the functional modules in the chip are reset based on the software reset structure.
[0032] According to a third aspect of the present disclosure, a chip is provided, wherein the chip includes the software reset structure of the chip described in the first aspect of the present disclosure.
[0033] Optionally, the chip is applied in an integrated circuit or a microcontroller.
[0034] On the basis of conforming to the common sense in this field, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0035] The positive progress of this disclosure is:
[0036] In the software reset structure designed in this disclosure, the synergy between the reset control unit, register access control unit, and global reset control unit is achieved to trigger the software global reset in a timely manner, quickly restore the system to normal working state, and reduce error recovery time;
[0037] Furthermore, based on the register unit, signal synchronization unit and reset completion unit in the global reset control unit, the time required for the chip to complete the reset and the specific state of the chip during the reset process are obtained, thereby providing greater operational flexibility. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 This is a functional block diagram for accessing common clock reset registers;
[0039] Figure 2 This is a schematic diagram of the software reset structure of the chip in Example 1 of the present disclosure;
[0040] Figure 3 Schematic diagram of the structure of the global reset control unit in Example 1 of the present disclosure;
[0041] Figure 4 Schematic diagram of the structure of the register unit in embodiment 1 of the present disclosure;
[0042] Figure 5This is a functional block diagram of the software reset structure of the chip in Example 1 of the present disclosure;
[0043] Figure 6 This is a functional structure diagram of the global software reset control unit in Example 1 of the present disclosure;
[0044] Figure 7 This is the timing constraint diagram in Example 1 of the present disclosure;
[0045] Figure 8 This is a flowchart of the software reset method of the chip in Example 2 of the present disclosure. DETAILED DESCRIPTION
[0046] The present disclosure is further illustrated below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0047] In the embodiments of the present disclosure, prefixes such as "first" and "second" are used only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. In the embodiments of the present disclosure, the use of prefixes such as ordinal numbers to distinguish description objects does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitations should be constituted due to the use of such prefixes. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
[0048] In an ASIC (Application-Specific Integrated Circuit) or MCU (Microcontroller Unit) chip, the commonly used clock control, reset control, and register access control functional structures are as follows: Figure 1 shown.
[0049] The clock control unit CCU generates the clock signal required by the on-chip functional module IP and other logic based on the input reference clock REF_CLK; the reset control unit RCU generates the reset signal required by the on-chip functional module IP and other logic based on the input reference reset REF_RST.
[0050] The serial or parallel interface signals of the chip pins are converted into register access buses to implement read and write operations on the registers.
[0051] The source of the reference clock REF_CLK signal includes the IO (input / output) input pin or the on-chip clock oscillator.
[0052] The source of the reference reset REF_RST includes pin IO input, or the power-on / power-off reset module in the chip.
[0053] Register access interfaces typically include SPI, I2C, UART (a commonly used serial communication protocol for data transmission between microcontrollers and other devices), etc. On-chip register access buses typically include AMBA's APB or AHB, Wishbone, Avalon (a commonly used high-speed serial or parallel bus technology) or other custom buses.
[0054] The clock and reset control logic is generated according to the functional module IP or other logic requirements within the chip.
[0055] However, it is currently impossible to implement a global reset through software within an ASIC or MCU chip.
[0056] In view of this, the present disclosure provides a chip and its software reset structure and software reset method to achieve software global reset, which can realize the function of external hardware pin reset, thereby greatly improving the flexibility of the chip.
[0057] Example 1
[0058] like Figure 2 As shown, this embodiment provides a software reset structure of a chip, which includes: a reset control unit 100, a register access control unit 200 and a global reset control unit 300 that are communicatively connected;
[0059] The reset control unit 100 is used to send a reset control signal;
[0060] The register access control unit 200 is used to receive a reset control signal and obtain reset control information based on the reset control signal; the reset control information includes a maximum reset time;
[0061] The maximum reset time is determined based on the time required to reset the functional units in the chip.
[0062] The global reset control unit 300 is used to reset all functional units in the chip based on the reset control information.
[0063] The maximum reset time in this embodiment corresponds to the maximum time required for a functional module in the system to complete the reset, and then during the reset process, it is determined whether several functional modules in the chip have completed the reset based on the maximum reset time.
[0064] Through the synergy between the reset control unit, register access control unit and global reset control unit, the software global reset is triggered in time, the system is quickly restored to normal working state, and the error recovery time is reduced.
[0065] The reset control information in this embodiment also includes a reset start signal and a reset state signal; wherein the reset state signal includes a reset progress signal and a reset completion signal.
[0066] In a specific implementation, the reset progress signal can be set to 0 and the reset completion signal can be set to 1, so as to quickly determine whether the functional modules in the chip have completed the reset based on the output of the reset status signal, thereby improving recognition efficiency.
[0067] like Figure 3 As shown, the global reset control unit 300 includes a register unit 301 and a reset completion unit 302 that are communicatively connected;
[0068] The register unit 301 is used to store the reset start signal, set the reset state signal as a reset proceed signal, and send the reset start signal to the reset completion unit.
[0069] The reset completion unit 302 is configured to receive a reset start signal, start a reset timer, obtain an actual reset duration, and in response to the actual reset duration reaching a maximum reset time, generate identification information and send the identification information to the register unit for storage;
[0070] The register unit 301 is further configured to receive identification information, and modify the reset state signal into a reset completion signal and output the signal.
[0071] The present disclosure enables users to quickly obtain the actual status of a functional module in a chip when resetting it through the setting of a register unit, thereby improving the user experience.
[0072] like Figure 3 As shown, the global reset control unit in this embodiment further includes a signal synchronization unit 303;
[0073] The signal synchronization unit 303 is in communication with the register unit 301 and the reset completion unit 302;
[0074] The signal synchronization unit is used to synchronize signals between the register unit and the reset completion unit.
[0075] The present disclosure is based on the register unit, signal synchronization unit and reset completion unit in the global reset control unit to obtain the time required for the chip to complete the reset and the specific state of the chip during the reset process, thereby providing greater operational flexibility.
[0076] like Figure 4 As shown, the register unit 301 in this embodiment includes a first register 3011, a second register 3012 and a third register 3013 that are communicatively connected;
[0077] Wherein, the first register 3011 is used to store the maximum reset time;
[0078] The second register 3012 is used to store the reset start signal;
[0079] The third register 3013 is used to store the reset state signal of the chip during the reset process.
[0080] The signal synchronization unit in this embodiment includes a multi-stage trigger. In a specific implementation manner, the multi-stage trigger is a three-stage trigger.
[0081] The reset completion unit in this embodiment includes a counter.
[0082] By setting three registers and storing different states in different registers, modular design can be more easily implemented. Each register can be regarded as a module and is responsible for processing a specific task, which improves the flexibility and maintainability of the chip.
[0083] like Figure 2 As shown, the software reset structure further includes a clock control unit 400;
[0084] The clock control unit 400 is communicatively connected to the reset control unit 100 , the register access control unit 200 , and the global reset control unit 300 ;
[0085] The clock control unit 400 is used to generate a clock signal and synchronize the clock frequencies of the reset control unit, the register access control unit and the global reset control unit based on the clock signal.
[0086] The setting of the clock control unit ensures the synchronization and coordination of the reset operation, improves the overall flexibility, scalability and reliability, and achieves more precise control of the reset process based on the synchronization of the clock signal.
[0087] The software reset structure of the chip provided in this embodiment can not only complete the reset of all the functional units in the chip, but also reset some functional units in the chip. That is, the software reset structure of the chip provided in this embodiment adds the function of global reset of all functional units in the chip on the basis of the original IP reset or partial logic reset.
[0088] The following describes the implementation principle of the software reset structure of the chip in this embodiment with a specific implementation method:
[0089] The present disclosure is based on the existing clock control unit CCU, reset control unit RCU and register access control unit, and utilizes the existing reference clock REF_CLK, reference reset REF_RST signal and newly added control signals (including the clock sys_clk and reset sys_rst synchronized with the control signals). The software global reset control unit generates a signal soft_rst with configurable effective level time. The signal is logically operated with the REF_RST signal to generate a ref_rst_s signal. The ref_rst_s is used as a new reference reset and transmitted to the RCU unit to achieve the functional effect of global reset. The functional structure is as follows: Figure 5 shown.
[0090] If the chip reset is low active, soft_rst is low active. Figure 5 The arithmetic logic unit is AND (&) operation; if the chip reset is high valid, then soft_rst is high valid, Figure 5 The arithmetic logic unit is the OR (|) operation, and the original CCU and RCU functional logic remain unchanged. Figure 5 is implemented in the dotted box.
[0091] The following describes the detailed invention of the software global reset control unit:
[0092] The control unit consists of three modules, the structure is as follows Figure 6 As shown in the figure, module 1 completes the reset count maximum configuration, software reset initiation, and software reset completion status signal generation. These logics operate in the sys_clk clock domain. Module 2 synchronizes the cross-clock domain signals between modules 1 and 3. Module 3 begins counting upon receiving the reset initiation signal and stops counting when it reaches the maximum value configured in module 1. The soft_rst signal is asserted during the counting period and is inactive otherwise.
[0093] Three registers are defined in module 1. Register 1 represents the maximum count value. This signal is transmitted to module 3 after synchronization with module 2. The software reset time is calculated by multiplying this value (the maximum count value) by the reference clock REF_CLK period. Register 2 indicates the start of the count reset. This signal (the reset start signal) is transmitted to module 3 through module 2. Register 3 indicates the reset state. For example, a low level indicates the reset state, while a high level indicates reset completion. This signal (the reset state signal) is generated by module 3 and transmitted synchronously through module 2.
[0094] All logic in module 1 operates in the sys_clk clock domain. Because stable signal transmission is required, module 2 uses a multi-stage register approach for synchronization. The counter in module 3 can increment from 0 to the configured maximum value and then reset, or decrement from the configured maximum value to 0 and then stop. All logic in module 3 operates in the reference clock domain, REF_CLK.
[0095] During the chip software global reset, the reference clock REF_CLK and the reference reset REF_RST remain unchanged, and REF_RST is still in the non-reset state. Therefore, the counter of module 3 is not affected by the software global reset and can complete counting until the end.
[0096] To ensure that the maximum count value configured in the sys_clk clock domain can be registered in the REF_CLK clock domain, module 3 detects the rising edge of the count start signal in the REF_CLK clock domain and registers the configured maximum count value when this rising pulse is valid. Counting is then restarted on the clock cycle following the rising pulse, entering the chip software reset state. During a global chip software reset, although the maximum count value and start signal configured in module 1 are restored to their reset initial values, they have already been registered in module 3 and therefore have no impact on the counting logic.
[0097] There are usually two ways for users to determine whether the software reset is completed: one is to wait for a specified time after the configuration software reset is started, and the software reset is considered completed after the waiting is completed. To ensure reliability, the waiting time is usually longer than the software reset time. This method is simple and does not require additional chip design; the other is to read the software reset status through the pin serial or parallel interface. This method requires the design of the software global reset status signal; the present disclosure supports two modes.
[0098] The software reset status register is defined in module 1. This register is at the reset level during a software global reset. After the reset is complete, its value is consistent with the soft_rst signal in module 3, which is synchronized through module 2. The user can read the reset completion level of the software reset status register through the serial or parallel interface pin to indicate that the software reset is complete.
[0099] In summary, the present disclosure fully utilizes the existing reference clock REF_CLK and reference reset REF_RST of the chip, and designs a small amount of control logic to achieve the functional effect of hardware global reset, and the reset time can be accurately configured.
[0100] The software reset structure provided by the present disclosure can solve the problem of difficulty in resetting the hardware pins of the chip in an embedded application environment, and also meet the application requirements of accurately resetting the chip in the host computer by operating the ground machine.
[0101] An embodiment is selected below to describe the invention in detail.
[0102] The chip reset is set to be active at low level, the reset mechanism is asynchronous reset and synchronous cancel, and the on-chip register bit width is 32; the register access is the SPI interface, with input clock SCK, input chip select SSN, low active, input data MOSI, output data MISO, SPI is fixed in slave mode, and the on-chip register access is the APB bus.
[0103] Set the count maximum register to count_max, which is readable and writable, with an effective bit width of 32 and an initial reset value of 32'b0. Set the count start reset start register to count_start, which is readable and writable, with an effective bit width of 1 and an initial reset value of 1'b0, with 1'b1 being valid. The software global reset status register is softrst_state, which is read-only, with an effective bit width of 1 and an initial reset value of 1'b0. 1'b0 indicates reset in progress, and 1'b1 indicates reset completion.
[0104] Combined with the timing constraints Figure 7 Describe the design of the present disclosure.
[0105] Write 0xFFF to count_max in module 1 through SPI and APB; write 1'b1 to count_start in module 1 through SPI and APB, such as Figure 7 At time t1 and time t2, the signal count_max is synchronized to the REF_CLK clock domain through module 2 as count_max_1; the signal count_start is synchronized to the REF_CLK clock domain through module 2 as count_start_1, as shown in the following example: Figure 4 At time t3 and time t4.
[0106] In the REF_CLK clock domain, the rising edge of count_start_1 is obtained to generate count_start_2. When count_start_2 is valid, count_max_1 is latched as count_max_2, which is the maximum value of the count.
[0107] Since count_max_2 is only related to count_start_2 and REF_RST, count_max_2 will remain unchanged unless it is rewritten or REF_RST is valid, which ensures that counting proceeds normally during a software global reset. Figure 7 Before time t5, the X value of count_max_2 should be 32'b0 or the last written value.
[0108] In the REF_CLK clock domain, count_start_3 is generated according to count_start_2 register, and counting is started when count_start_3 is valid, that is, Figure 7At t6, count_s starts counting from 0 and stops counting when it reaches 0xFFF, which is count_max_2, at t8. The software reset signal soft_rst is valid during the counting period and invalid when the counting is finished. Figure 7 It can be seen that the software reset time period is from t6 to t8. If the maximum value of the configuration count is larger, the reset time is also longer, meeting the requirement of configurable reset time.
[0109] Since the chip is set to asynchronous reset, the soft_rst signal is valid. Figure 7 At time t6, the chip enters the software global reset state, count_max and count_start are restored to the reset initial value, and after the initial value is synchronized by module 2, count_max_1 and count_start_1 are also restored to the reset initial value. Figure 7 At the same time, the register signal softrst_state also returns to the reset initial value 1'b0 at t6, and continues until the software global reset is completed and the reset completion value 1'b1 of soft_rst is synchronized and then becomes 1'b1. Figure 7 t9 moment.
[0110] During a software global reset, all logic except the functions designed in this disclosure stops working. Although SCK, SSN, and MOSI have inputs, the reset level 1'b0 of softrst_state cannot be transmitted to MISO of the SPI. Therefore, it is agreed that MISO also outputs the reset level value 1'b0 during a software reset. After the chip completes the software global reset and works normally, the SPI interface can read the reset completion level 1'b1 of softrst_state. The user believes that the software global reset is complete and can enter the working mode.
[0111] In the software reset structure designed in the present disclosure, the synergy between the reset control unit, the register access control unit and the global reset control unit is used to trigger the software global reset in a timely manner, quickly restore the system to a normal working state, and reduce the error recovery time.
[0112] Example 2
[0113] like Figure 8 As shown, this embodiment provides a chip software reset method, the software reset method includes:
[0114] S11: Get reset control signal;
[0115] S12: Sending a reset control signal to the software reset structure, and completing the reset of the functional modules in the chip based on the software reset structure.
[0116] The software reset method designed in the present disclosure utilizes the synergy between the reset control unit, register access control unit, and global reset control unit in the software reset structure to trigger a global software reset in a timely manner, quickly restore the system to a normal working state, and reduce error recovery time.
[0117] Furthermore, based on the register unit, signal synchronization unit and reset completion unit in the global reset control unit, the time required for the chip to complete the reset and the specific state of the chip during the reset process are obtained, thereby providing greater operational flexibility.
[0118] Example 3
[0119] This embodiment provides a chip, which includes the software reset structure of the chip in Embodiment 1 of the present disclosure.
[0120] In a specific implementation, the chip is applied to an integrated circuit or a microcontroller.
[0121] In the chip designed in this disclosure, by leveraging the synergy between the reset control unit, register access control unit, and global reset control unit in the software reset structure, a software global reset is triggered in a timely manner, quickly restoring the system to normal working state and reducing error recovery time.
[0122] Furthermore, based on the register unit, signal synchronization unit and reset completion unit in the global reset control unit, the time required for the chip to complete the reset and the specific state of the chip during the reset process are obtained, thereby providing greater operational flexibility.
[0123] While specific embodiments of the present disclosure have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of protection of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications are intended to fall within the scope of protection of the present disclosure.
Claims
1. A chip software reset structure, characterized in that: The software reset structure includes: a reset control unit, a register access control unit and a global reset control unit connected in communication; Wherein, the reset control unit is used to send a reset control signal; The register access control unit is configured to receive the reset control signal and obtain reset control information based on the reset control signal; the reset control information includes a maximum reset time; The maximum reset time is determined based on the time required for resetting the functional units in the chip; The global reset control unit is used to reset all the functional units in the chip based on the reset control information.
2. The chip software reset structure according to claim 1, characterized in that: The reset control information further includes a reset start signal and a reset state signal; wherein the reset state signal includes a reset progress signal and a reset completion signal; The global reset control unit includes a register unit and a reset completion unit connected in communication; The register unit is used to store the reset start signal, set the reset state signal to the reset proceed signal, and send the reset start signal to the reset completion unit; The reset completion unit is configured to receive the reset start signal, start the reset timing, obtain an actual reset duration, and in response to the actual reset duration reaching the maximum reset time, generate identification information and send the identification information to the register unit for storage; The register unit is further configured to receive the identification information, and modify the reset state signal into the reset completion signal and output the signal.
3. The chip software reset structure according to claim 2, characterized in that: The global reset control unit also includes a signal synchronization unit; The signal synchronization unit is communicatively connected with the register unit and the reset completion unit; The signal synchronization unit is used to synchronize signals between the register unit and the reset completion unit.
4. The chip software reset structure according to claim 2, characterized in that: The register unit includes a first register, a second register and a third register that are communicatively connected; Wherein, the first register is used to store the maximum reset time; The second register is used to store the reset start signal; The third register is used to store the reset state signal of the chip during the reset process.
5. The chip software reset structure according to claim 3, characterized in that: The signal synchronization unit includes a multi-stage trigger.
6. The chip software reset structure according to claim 2, characterized in that: The reset completion unit includes a counter.
7. The software reset structure of a chip according to any one of claims 1 to 6, characterized in that: The software reset structure also includes a clock control unit; The clock control unit is communicatively connected to the reset control unit, the register access control unit and the global reset control unit respectively; The clock control unit is used to generate a clock signal and synchronize the clock frequencies of the reset control unit, the register access control unit and the global reset control unit based on the clock signal.
8. A chip software reset method, characterized in that: The software reset method includes: Get reset control signal; The reset control signal is sent to a software reset structure according to any one of claims 1 to 7, and the functional modules in the chip are reset based on the software reset structure.
9. A chip, characterized in that: The chip includes the software reset structure of the chip according to any one of claims 1 to 7.
10. The chip according to claim 9, characterized in that The chip is applied in an integrated circuit or a microcontroller.