Method for optimizing calculation performance of number-theory transformation based on index multiplexing

Abstract

The invention provides a number-theory transformation calculation performance optimization method based on index multiplexing, and mainly aims to improve the performance in large-scale data number-theory transformation operation and solve the calculation bottleneck caused by bit reverse-order replacement operation. According to the method, an optimization scheme based on index multiplexing is provided by optimizing a bit reverse order permutation algorithm and utilizing the parallel computing capability of a GPU (Graphics Processing Unit). The core of the method is that redundancy calculation is reduced by multiplexing data indexes, so that the efficiency of number theory transformation is improved. Aiming at the characteristics of the GPU, the execution efficiency is improved by executing a bit reverse order replacement task in parallel and utilizing a hardware acceleration instruction. The problem of low execution efficiency in the prior art is solved, and an effective solution is provided for number-theory transformation acceleration of large-scale data.

Description

Technical field:

[0001] The present invention discloses a method for optimizing the computing performance of number-theoretic transformation based on index reuse, relates to the optimization of the computing performance of number-theoretic transformation of large-scale data in high-performance computing, and belongs to the field of computer technology. Background technology:

[0002] As high-performance computing and privacy-preserving computing applications continue to expand, the computational overhead of number-theoretic transformations has become a performance bottleneck. During number-theoretic transformation operations, the bit-reversal permutation of large-scale data often becomes a performance bottleneck. GPUs offer powerful parallel computing capabilities and provide developers with a flexible and efficient programming interface, significantly reducing development complexity while offering high cost-effectiveness and universal applicability. This collaborative hardware-software acceleration solution, based on high-performance commercial hardware, has become a research hotspot in the field of hardware acceleration for number-theoretic transformations.

[0003] In recent years, researchers both domestically and internationally have been exploring ways to accelerate number-theoretic transformations using various hardware acceleration platforms, including GPUs, FPGAs, and DSAs. However, most acceleration solutions suffer from challenges such as high deployment difficulty and limited acceleration effectiveness. In high-throughput blockchain networks that process large volumes of transactions, such as cryptocurrencies and large-scale decentralized applications, the high parallel processing capabilities of GPUs can effectively reduce the computational time of number-theoretic transformations. Furthermore, GPUs, as a hardware platform widely used in real-world production environments, have been deployed on a large scale in data centers. Therefore, research on accelerating number-theoretic transformations based on commercial GPU hardware platforms has significant engineering value and practical significance.

[0004] The number-theoretic transformation algorithm can be further optimized using a divide-and-conquer approach. For a cardinality-2 number-theoretic transformation, each time the coefficients of the odd- and even-degree polynomials are separated, the process continues until only a single coefficient remains. However, this recursive process requires a large amount of memory when executed on a computer. Therefore, it is possible to first mimic the recursive process, splitting the coefficients within the original array and then merging the resulting values.

[0005] For the splitting process, the bit reversal permutation algorithm can be used to implement it; and for the merging process, the butterfly operation can be used to optimize it to require only O(1) additional space to complete.

[0006] In summary, bit reversal permutation is an essential component for efficient number theoretic transformation computations. Current CPUs perform bit reversal permutation operations inefficiently, severely impacting performance. This issue is particularly pronounced when processing large amounts of data. Therefore, accelerating the bit reversal permutation process is crucial, significantly reducing execution latency and ultimately accelerating number theoretic transformations. Summary of the invention:

[0007] The primary purpose of this invention is to alleviate performance bottlenecks in number-theoretic transformation computations. To address the low efficiency of large-scale data reordering operations during number-theoretic transformation operations, the present invention proposes a method for optimizing number-theoretic transformation computational performance based on index reuse. This method improves the computational performance of number-theoretic transformations by optimizing the computational process of the bit-reversal permutation algorithm in number-theoretic transformations. The method includes the following steps:

[0008] (1) Determine the input data size, input data storage location, allocate data space, create GPU threads, create computing flows and data communication transmission flows.

[0009] (2) Apply for the corresponding memory space according to the input data storage location, confirm whether the calculation results or data indexes can be reused according to the input data scale, select the optimal reuse method, update the stored data index, synchronize the calculation flow and data communication transmission flow, and output the current bit reverse permutation result.

[0010] (3) Based on the bit reversal permutation result in (2), generate the corresponding input data splitting result.

[0011] Wherein, step 1) comprises the following steps:

[0012] Step (1.1) determines the input data size. Check whether the data size is a power of 2. If it is not a power of 2, the input is invalid.

[0013] Step (1.2) determines the storage location of the input data. Based on the storage location of the input data, the memory space that needs to be allocated is determined, and whether data transmission is required.

[0014] Step (1.3) allocates data space. Based on the size of the input data, the corresponding host memory and device memory are allocated.

[0015] Step (1.4) creates GPU threads. Create a number of threads that matches the size of the input data, and each thread is responsible for completing the bit-reversal permutation of a pair of original input data.

[0016] Step (1.5) creates a computational flow and a data communication transport flow. The computational flow is responsible for completing the computation process on the GPU, and two data communication transport flows are created to complete the data transmission from the host to the device and from the device to the host, respectively.

[0017] Wherein, step 2) comprises the following steps:

[0018] Step (2.1) initializes an unordered dictionary that stores data indexes.

[0019] Step (2.2) selects the optimal reuse method. Based on the input data size, reuse is performed between number-theoretic transformations of the same size. For the same input data, previous computations can be reused directly, significantly reducing execution time. For different input data but the same size, bit-reversal indices can be shared between different computations to avoid recalculating the same bit-reversal indices.

[0020] Step (2.3) updates the stored data index and updates the calculated data index to the unordered dictionary for reuse in subsequent calculation processes.

[0021] Step (2.4) Stream synchronization: Use the stream synchronization mechanism to complete the synchronization between the calculation stream and the data communication transmission stream, ensure that all calculations and data communication transmissions are completed accurately, and output the current bit reversal permutation result.

[0022] Advantages of the present invention include:

[0023] The present invention proposes a method for optimizing the computational performance of number-theoretic transformations based on index reuse. Compared with the prior art, the advantages are:

[0024] In the existing number theory transformation calculation method, there are a lot of redundant calculations in the process of calculating bit reversal permutation, which cannot meet the calculation performance requirements of number theory transformation of large-scale data. The solution of using CPU for calculation has low execution efficiency due to the limitations of the CPU's own characteristics, and a large number of operations that can be executed in parallel can only be executed sequentially. In response to the above problems, the present invention proposes a method that can efficiently reuse data indexes to optimize the execution process of bit reversal permutation. This method is based on the idea of ​​index reuse and utilizes the characteristics of the multi-core processor of the GPU platform to let different threads be responsible for the calculation of different bit reversal index tasks. These threads run in parallel on the CUDA computing core of the GPU. With its multi-core architecture, the GPU can create a large number of threads at the same time, and each thread independently completes the bit reversal of a pair of input data. At the same time, the streaming multiprocessor (SM) inside the modern GPU integrates a dedicated fast bit reversal circuit. These circuits directly map the input bits to the output bits through hard wiring. The bit reversal operation can be completed in parallel at the hardware level without the need for sequential processing, which greatly improves the execution efficiency. Description of the drawings:

[0025] Figure 1 This is a schematic diagram of a number theory transformation computing performance optimization solution based on index reuse.

[0026] Figure 2 This is the flowchart of bit reverse permutation execution. Specific implementation method:

[0027] The present invention will be further described in detail below with reference to the accompanying drawings.

[0028] like Figure 1 The figure shows a schematic diagram of the method for optimizing the computing performance of number theory transformation based on index reuse proposed by the present invention. Figure 1 A new index-reuse approach is presented, which computes the data index offline before the number-theoretic transformation begins. Before each round of number-theoretic transformations, the pre-computed and stored data index replaces the tedious data reordering process, thus reducing the time overhead of data reordering.

[0029] like Figure 2 FIG. 1 shows the execution flow of the bit reverse permutation in the index multiplexing method proposed by the present invention.

[0030] Initially, the kernel checks whether the input data has previously been bit-reversed. If so, the result is read directly, skipping the bit-reversal operation. If this is the first time the input data is being bit-reversed, the kernel checks whether the data size is a power of 2. If not, the bit-reversal operation cannot be performed, and the input is considered invalid, resulting in an error message being displayed to the user. If the data size is a power of 2, the kernel checks whether the input data is already stored in GPU memory based on the relevant configuration information. If so, the bit-reversal kernel can be executed directly. If the input data is still in CPU memory, the kernel allocates appropriate GPU memory space based on the data size. The kernel then asynchronously transfers the input data to the GPU memory, executes the bit-reversal kernel, and finally transfers the bit-reversal result back to CPU memory. This process then requires CUDA stream synchronization. In CUDA, a stream is a queue for task execution. Through stream synchronization, we can ensure that the execution of tasks in one stream can be completed before another stream can continue. CUDA stream synchronization is mainly used to coordinate the execution of tasks in different streams, ensure the correctness of the computational process, and maximize the efficiency of parallel computing while ensuring order. Finally, the results of the bit-reversed permutation calculations are saved in the GPU memory for use with the next input data of the same size. The data structure used to store the calculation results is an unordered hash table, which ensures the lowest query and modification time complexity. The use of an unordered hash table to save the calculation results allows the next time the bit-reversed permutation is performed, for input data of the same data size, the data after the bit-reversed permutation can be directly returned, thus avoiding the need to rearrange the data and improving the computational efficiency of number theory transformations.

[0031] Finally, it should be noted that the present invention may also have many other application scenarios. Without departing from the spirit and essence of the present invention, technical personnel familiar with the field can make various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the present invention.

Claims

1. A method for optimizing the computational performance of number-theoretic transformation based on index reuse improves the computational performance of number-theoretic transformation by optimizing the computational process of the bit-reversal permutation algorithm in the number-theoretic transformation. The method is characterized by: The following steps are involved: Step (1) determines the input data size, input data storage location, allocates data space, creates GPU threads, creates computing flows and data communication transmission flows; Step (2) applies for corresponding memory space according to the input data storage location, confirms whether the calculation results or data indexes can be reused according to the input data scale, selects the optimal reuse method, updates the stored data indexes, synchronizes the calculation flow and the data communication transmission flow, and outputs the current bit reversal permutation result; Step (3) generates the corresponding input data splitting result based on the bit reversal permutation result in step (2).

2. The method according to claim 1, characterized in that The specific process of step (1) is as follows: Step (1.1) determines the input data size and determines whether the data size is a power of 2. If it is not a power of 2, it is an illegal input; Step (1.2) determines the storage location of the input data, and determines the memory space that needs to be allocated and whether data transmission is required based on the storage location of the input data; Step (1.3) allocates data space, and allocates corresponding host memory and device memory according to the data size of the input data; Step (1.4) creates GPU threads, with the number of threads matching the size of the input data. Each thread is responsible for completing the bit-reversal permutation of a pair of original input data. Step (1.5) creates a computing stream and a data communication transmission stream. The computing stream is responsible for completing the computing process on the GPU, and two data communication transmission streams are created to complete the data transmission from the host end to the device end and the data transmission from the device end to the host end respectively.

3. The method according to claim 1 or 2, characterized in that The specific process of step (2) is as follows: Step (2.1) initializes the unordered dictionary that stores data indexes; Step (2.2) selects the optimal reuse method. Based on the input data size, reuse is performed between number-theoretic transformations of the same data size. For the same input data, the previous calculation results are directly reused to significantly reduce the execution time. For different input data but the same data size, the bit-reversal index is shared between different calculations to avoid repeated calculation of the same bit-reversal index. Step (2.3) updates the stored data index and updates the calculated data index to the unordered dictionary so that it can be reused in subsequent calculation processes; Step (2.4) Stream synchronization: Use the stream synchronization mechanism to complete the synchronization between the calculation stream and the data communication transmission stream, ensure that all calculations and data communication transmissions are completed accurately, and output the current bit reversal permutation result.

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