Register renaming method, electronic device, readable medium and program product

Abstract

The invention provides a register renaming method, which comprises the following steps of: analyzing a current instruction to obtain a bit width and a serial number of a logic register; determining a target idle physical register table from the plurality of idle physical register tables according to the bit width of the logic register, and selecting a target physical register from the target idle physical register table; based on the serial number of the target physical register and the serial number of the logical register, establishing a mapping relation between the target physical register and the logical register, and storing the mapping relation between the target physical register and the logical register and the use bit of the target physical register in a renaming mapping table; and updating all idle physical register tables according to the mapping relationship between the target physical register and the logic register and the use bit of the target physical register. The invention further provides electronic equipment, a readable medium and a program product.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a register renaming method, electronic device, readable medium, and program product. Background Art

[0002] Register renaming is a key technology in computer architecture. By assigning multiple physical registers to logical registers, it can eliminate false dependencies between instructions and improve the execution bandwidth of pipelined instructions. However, current register renaming technology only supports one physical register corresponding to two logical registers. Furthermore, it only supports sharing physical registers between multiple instructions in the same cycle, resulting in a limited scope of use. Furthermore, different operands occupy the entire bit width of the physical register, reducing the utilization of the physical register and wasting resources. Summary of the Invention

[0003] The present disclosure provides a register renaming method, an electronic device, a readable medium, and a program product.

[0004] In a first aspect, an embodiment of the present disclosure provides a register renaming method, comprising:

[0005] Parse the current instruction to obtain the bit width and number of the logical register;

[0006] determining a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, and selecting a target physical register from the target free physical register table, wherein different free physical register tables manage free physical registers of different bit widths;

[0007] Establishing a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, and storing the mapping relationship between the target physical register and the logical register and a usage bit of the target physical register in a renaming mapping table, wherein the usage bit is used to indicate usage of a data segment in the physical register;

[0008] All the free physical register tables are updated according to the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register.

[0009] In a second aspect, an embodiment of the present disclosure provides a processor, including:

[0010] The decoding unit is used to parse the current instruction and obtain the bit width and number of the logical register;

[0011] A physical register, used to store the operation bits and calculation results of the current instruction;

[0012] A register renaming unit is configured to determine a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, select a target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register in a renaming mapping table, and update all the free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register.

[0013] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the register renaming method described in any one of the embodiments of the present disclosure is implemented.

[0014] In a fourth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the register renaming method described in any one of the embodiments of the present disclosure.

[0015] The register renaming method provided by the embodiments of the present disclosure parses a current instruction to obtain the bit width and number of a logical register; determines a target free physical register table from multiple free physical register tables based on the bit width of the logical register; selects a target physical register from the target free physical register table; stores a mapping relationship between the target physical register and the logical register, as well as a usage bit of the target physical register, in a renaming mapping table; and updates all free physical register tables based on the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register. Because different free physical register tables manage free physical registers of different bit widths, during register renaming, not only the mapping relationship between the target physical register and the logical register in the free physical register table is updated, but also the usage bit of the target physical register is updated. In this way, the remaining bit width of the target physical register can be used by other instructions in different beats, thereby achieving refined physical register allocation, avoiding physical register resource waste, and improving physical register usage efficiency. Furthermore, the probability of all physical registers being used can be reduced, reducing processor pipeline pauses caused by all physical registers being used, thereby improving processor pipeline execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings of the embodiments of the present disclosure:

[0017] Figure 1 A principle block diagram of a processor is provided for an embodiment of the present disclosure;

[0018] Figure 2 A flowchart of a register renaming method provided by an embodiment of the present disclosure;

[0019] Figure 3 A block diagram of a processor provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0022] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0023] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0024] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0026] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0027] Register renaming technology is a renaming technology based on the management of the Register Mapping Table (RAT) and the Free Register List. The RAT is used to store the mapping relationship between existing logical registers and physical registers, and the Free Register List is used to record which physical registers are free (available) so as to obtain the numbers of free physical registers when performing register renaming.

[0028] In a first aspect, an embodiment of the present disclosure provides a register renaming method, which is executed under a processor framework.

[0029] Figure 1 A block diagram of a processor is provided for an embodiment of the present disclosure. The processor includes:

[0030] Decode unit 1 is used to parse instructions, obtain operands and logical register encodings, and determine the bit width of the logical register based on the operands. For example, decode unit 1 parses instructions based on different instruction set architectures to obtain the bit width of the logical register and the encoding of the logical register.

[0031] Physical register 2 includes a data portion and a use bit portion. The data portion is used to temporarily store instruction operands and calculation results; the use bit portion is used to manage the state of the physical register. The bit width of the physical register can be designed based on the instruction set and is not limited in this embodiment.

[0032] For example, taking the fifth Reduced Instruction Set Computer (RISC-V) floating-point instruction set extension as an example, assuming that the bit width of the physical register supported by the processor is 128 bytes (bits), and the bit width of the data part in the physical register is [127:0], since the RISC-V floating-point calculation instructions support a minimum 16-bit operand width, four free physical register tables of 16-bit, 32-bit, 64-bit, and 128-bit can be provided, namely free physical register tables a, b, c, and d. Since the minimum supported operand bit width is 16-bit, the register bit width is 128 bits, and the used bit is 8 bits, each bit in the used bit represents the usage of the 16-bit data of the physical register. For example, the used bit of physical register P0 is 8'0000_1000, indicating that [63:48] of P0 has been used. When any physical register is allocated in any free physical register table, all free physical register tables are updated according to the used bit.

[0033] In some embodiments, according to the instruction set architecture and actual usage needs, multiple free register tables can be maintained simultaneously. When a free physical register table with a bit width that matches the bit width of the operand cannot be found, a physical register can be obtained from a free physical register table with a bit width greater than the operand, that is, a physical register is selected from a free physical register table that does not match the operand bit width. When a physical register is selected from a free physical register table that does not match the operand bit width, the width of the used bits of the physical register can be left unchanged or adjusted as needed. For example, an 8-bit used bit physical register supports a minimum 16-bit free physical register table. If there is only a free physical register table with a minimum bit width of 32 bits, the used bit physical register can be modified to 4 bits, with each bit representing the usage status of the 32-bit bit width of the physical register.

[0034] The register renaming unit 3 is configured to determine a target free physical register table according to the bit width of the operand, allocate physical registers, and determine a target physical register from the target free physical register table.

[0035] In some embodiments, the register renaming unit 3 includes:

[0036] The renaming mapping table 31 is used to record the mapping relationship between the logical register and the target idle physical register, as well as the usage bit of the target idle physical register.

[0037] The Architecture Register File (ARF) 32 maintains the numbers and use bits of target physical registers. When an instruction is committed (retired), the physical register table is partially freed based on the numbers and use bits of the target physical registers. Multiple free physical register tables are also updated, allowing the freed physical registers to be renamed.

[0038] The free physical register table 33 is used to record the number and usage status of the free physical registers. The embodiment of the present disclosure includes multiple free physical register tables 33, each of which stores free physical registers of corresponding bit width.

[0039] The instruction submission unit 4 is used to write the mapping relationship between the target physical register and the logical register corresponding to the instruction and the usage bit of the target physical register into the architecture register file 32 after the instruction is executed, and release the release information in the architecture register file 32. The release information includes the target physical register number and usage bit used by the previous instruction, so as to update the usage bit in the physical register 2 and the free physical register table 33.

[0040] Figure 2 A flow chart of a register renaming method provided by an embodiment of the present disclosure. Figure 2 As shown, a register renaming method provided by an embodiment of the present disclosure includes:

[0041] Step S201: parse the current instruction to obtain the bit width and number of the logical register.

[0042] Parse the current instruction and derive the bit width and number of the logic register from the current instruction.

[0043] In some embodiments, parsing the current instruction to obtain the bit width and number of the register includes: parsing the current instruction to obtain the operand of the current instruction and the number of the logical register; and determining the bit width of the logical register based on the operand.

[0044] The current instruction is parsed to obtain the operand of the current instruction and the number of the logic register, and then the bit width of the logic register is determined based on the operand.

[0045] For example, if the current instruction includes a first instruction 0 and a second instruction 1, the decoding unit parses the first instruction 0 and obtains that the encoding of the logical register (logical) is X5 and the bit width (dst_size) of the operand is 16 bits.

[0046] Marked as: first instruction 0 logical id = x5, dst_size is 16-bit;

[0047] The decoding unit parses the first instruction 1 and obtains that the encoding of the logical register is X6 and the bit width of the operand (dst_size) is 32 bits.

[0048] Marked as: second instruction 1 logical id = x6, dst_size is 32-bit.

[0049] Step S202 : determining a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, and selecting a target physical register from the target free physical register table.

[0050] Different idle physical register tables manage idle physical registers of different bit widths, that is, idle physical registers with the same bit width are placed in one idle physical register table for management.

[0051] The embodiment of the present disclosure determines a target free physical register table according to the bit width of the logical register, and then selects any physical register from the target free physical register table as the target physical register.

[0052] For example, the bit width of the first instruction 0 is 16-bit, and a physical register is obtained from the 16-bit free physical register table a as the target physical register. Assume that the target physical register is numbered P0, and the used bit USED-bit=8'h1(0000_0001).

[0053] The second instruction 1 has a 32-bit bit width and obtains a physical register from the 32-bit free physical register table b as the target physical register. Assume that the target physical register is numbered P2 and the used bit USED-bit=8'h3 (0000_0011).

[0054] Step S203 : establishing a mapping relationship between the target physical register and the logical register based on the target physical register number and the logical register number, and storing the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register in a renaming mapping table.

[0055] The usage bit is used to indicate the usage status of a data segment in a physical register. In the disclosed embodiment, when the usage bit is high, it indicates that the usage bit is in use. When the usage bit is not high, it indicates that the usage bit is not in use. The mapping relationship between the target physical register and the logical register, as well as the usage bit of the target physical register, can be referred to as the physical register usage information.

[0056] The renaming mapping table stores the mapping relationship between the target physical register and the logical register, as well as the used bit of the target physical register, for example: logical register X5->target physical register P0 (used-bit=8'h1) and logical register X6->target physical register P2 (used-bit=8'h3).

[0057] In the embodiment of the present disclosure, the number and usage bit of the target physical register are stored in the renaming mapping table, which helps subsequent source operands to find the corresponding target physical register.

[0058] Step S204 : updating all free physical register tables according to the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register.

[0059] When any physical register is allocated in any free physical register table, all existing free physical register tables are updated according to the usage bit of the physical register, and the target free physical register is cleared from the free physical register table, indicating that the target free physical register has been allocated and is no longer a free physical register and is in an unavailable state.

[0060] In some embodiments, determining a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register includes:

[0061] When a free physical register that matches the bit width of the logical register can be found in multiple free physical register tables, the free physical register that matches the bit width of the logical register is used as the target free physical register table.

[0062] If no free physical register matching the bit width of the logical register can be found in the plurality of free physical register tables, a target free physical register is selected from a free physical register table having a bit width greater than the bit width of the logical register.

[0063] For example, assuming that the bit width of the logical register is 64 bits, but there is no free physical register in the free physical register table corresponding to 64 bits, then the target free physical register can be selected from the free physical register table with a bit width of 128 bits.

[0064] In some embodiments, after updating all free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register, the method further includes: if the remaining bit width of the target physical register does not match the bit width of the free physical register table, removing the target physical register from the non-matching free physical register table and moving the target physical register into the free physical register table that matches the remaining bit width.

[0065] For example, assume the total bit width of the target physical register is 128 bits and the target physical register is in the 128-bit free physical register table. If the current instruction occupies 64 bits and the remaining bit width is 64 bits, then the target physical register is removed from the 128-bit free physical register table and added to the 67-bit free physical register table.

[0066] In some embodiments, when the current instruction is executed, the operation result of the current instruction is written into the physical register.

[0067] When the operation result of the current instruction is written into the physical register, data of the corresponding bit width is written according to the number and usage bits of the target physical register.

[0068] In some embodiments, when the current instruction is committed, the mapping relationship between the target physical register and the logical register corresponding to the current instruction and the usage bit of the target physical register are written into the architecture register.

[0069] In some embodiments, when the next instruction of the current instruction is submitted, the target free physical register table corresponding to the bit width of the target physical register is updated based on the number of the target physical register and the usage bit of the target physical register, that is, the mapping relationship between the target physical register and the logical register is released.

[0070] For example, the usage bit of the physical register P0 corresponding to the first instruction 0 is: P0 (1111_0011), and the usage bit of the physical register P2 corresponding to the second instruction 1 is: P2 (1111_1111). After the physical registers P0 and P2 are released, the usage bit of the physical register P0 is (1111_0010), and the usage bit of the physical register is P2 (1111_1100).

[0071] When the physical register is released, the physical register is updated according to the release information, that is, the free register table is recovered and updated according to the used bits of the physical register. After the update, the physical register P0 can appear in the free register tables with a bit width of 16-bit and 32-bit because it has 32 bits of free bits. The physical register P2 can appear in the free register tables of 16-bit, 32-bit and 64-bit because it has 64 bits of free bits.

[0072] The register renaming method provided by the embodiments of the present disclosure parses a current instruction to obtain the bit width and number of a logical register; determines a target free physical register table from multiple free physical register tables based on the bit width of the logical register; selects a target physical register from the target free physical register table; stores a mapping relationship between the target physical register and the logical register, as well as a usage bit of the target physical register, in a renaming mapping table; and updates all free physical register tables based on the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register. Because different free physical register tables manage free physical registers of different bit widths, during register renaming, not only the mapping relationship between the target physical register and the logical register in the free physical register table is updated, but also the usage bit of the target physical register is updated. In this way, the remaining bit width of the target physical register can be used by other instructions in different beats, thereby achieving refined physical register allocation, avoiding physical register resource waste, and improving physical register usage efficiency. Furthermore, the probability of all physical registers being used can be reduced, reducing processor pipeline pauses caused by all physical registers being used, thereby improving processor pipeline execution efficiency.

[0073] In a second aspect, an embodiment of the present disclosure provides a processor.

[0074] Figure 3 FIG. 1 shows a block diagram of a processor provided by an embodiment of the present disclosure. Figure 3 As shown, an embodiment of the present disclosure provides a processor including:

[0075] Decoding unit 1 is used to parse the current instruction and obtain the bit width and number of the logical register;

[0076] Physical register 2, used to store the operation bits and calculation results of the current instruction;

[0077] The register renaming unit 3 is configured to determine a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, select a target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register in a renaming mapping table, and update all the free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register.

[0078] In some embodiments, the processor further includes an instruction submitting unit 4 for writing a mapping relationship between a target physical register and a logical register corresponding to the current instruction and a usage bit of the target physical register into an architecture register file after the current instruction is executed.

[0079] It should be noted that the processor is also used to execute other steps of the register renaming method provided in the embodiment of the present disclosure, which will not be described here in order to save space.

[0080] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0081] An embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any register renaming method described in the above embodiments.

[0082] The embodiments of the present disclosure further provide a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements any register renaming method described in the above embodiments.

[0083] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0084] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0085] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0086] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0087] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A register renaming method, comprising: Parse the current instruction to obtain the bit width and number of the logical register; determining a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, and selecting a target physical register from the target free physical register table, wherein different free physical register tables manage free physical registers of different bit widths; Establishing a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, and storing the mapping relationship between the target physical register and the logical register and a usage bit of the target physical register in a renaming mapping table, wherein the usage bit is used to indicate usage of a data segment in the physical register; All the free physical register tables are updated according to the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register.

2. The method according to claim 1, wherein The current instruction is parsed to obtain the bit width and number of the register, including: Parsing the current instruction to obtain the operand of the current instruction and the number of the logical register; A bit width of the logical register is determined based on the operand.

3. The method according to claim 1, wherein Determining a target idle physical register table from a plurality of idle physical register tables according to the bit width of the logical register includes: If an idle physical register matching the bit width of the logical register can be found in the plurality of idle physical register tables, using the idle physical register matching the bit width of the logical register as the target idle physical register table; If no free physical register matching the bit width of the logical register can be found in the plurality of free physical register tables, the target free physical register is selected from a free physical register table having a bit width greater than the bit width of the logical register.

4. The method according to claim 1, wherein After updating all the free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register, the method further includes: When the remaining bit width of the target physical register does not match the bit width of the free physical register table, the target physical register is removed from the free physical register table that does not match, and the target physical register is moved into the free physical register table that matches the remaining bit width.

5. The method according to claim 1, wherein When the current instruction is executed, the operation result of the current instruction is written into the physical register.

6. The method according to claim 1, wherein When the current instruction is submitted, a mapping relationship between the target physical register and the logical register corresponding to the current instruction and a usage bit of the target physical register are written into an architecture register file.

7. The method according to claim 6, wherein: When the next instruction of the current instruction is submitted, a target free physical register table corresponding to the bit width of the target physical register is updated based on the number of the target physical register and the usage bit of the target physical register.

8. A processor comprising: The decoding unit is used to parse the current instruction and obtain the bit width and number of the logical register; A physical register, used to store the operation bits and calculation results of the current instruction; A register renaming unit is configured to determine a target free physical register table from a plurality of free physical register tables according to the bit width of the logical register, select a target physical register from the target free physical register table, establish a mapping relationship between the target physical register and the logical register based on the number of the target physical register and the number of the logical register, store the mapping relationship between the target physical register and the logical register, and the usage bit of the target physical register in a renaming mapping table, and update all the free physical register tables according to the mapping relationship between the target physical register and the logical register and the usage bit of the target physical register.

9. A computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the register renaming method according to any one of claims 1 to 7 is implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the register renaming method according to any one of claims 1 to 7 is implemented.

Images