Reordering scheduling method and related device

Abstract

The invention discloses a reordering scheduling method and a related device, which regenerates a BANK address of a control command, stores the control command according to a new BANK address, and reorders the control command by adopting an arbitration state machine, so that the transmission time of a read / write transaction can be reduced as much as possible, and compared with a traditional DDR controller, the reordering scheduling method and the related device have the advantages that the transmission time is shortened; compared with the prior art, the time for transmitting the data with the same size is shorter, that is, more data can be transmitted within the same time, so that the read-write transmission efficiency is improved, and the waste of bandwidth is greatly reduced.

Description

Technical Field

[0001] The present invention relates to a reordering scheduling method and related devices, and belongs to the field of DDR controllers. Background Art

[0002] Extensive research has been conducted on command reordering within DDR controllers (such as DDR3 controllers). Most methods assign commands to read and write buffers, with one command buffer allocated to each of the eight banks (a bank is a DDR SDRAM module). Due to the timing requirements of DDR read and write operations, most employ an open page strategy. For example, a buffer with a width of four commands eliminates the need for pre-charge and active operations when a new command enters the queue if it is assigned to the same bank and row as a previous command. This significantly reduces read and write cycles and data path bubbles, improving data transmission efficiency. However, these scheduling algorithms employ fair round-robin polling of the command buffers associated with each bank. If the system frequently reads and writes data from the same bank, round-robin arbitration wastes bandwidth, significantly reducing read and write efficiency. Summary of the Invention

[0003] The present invention provides a reordering scheduling method and related devices, which solve the problems disclosed in the background technology.

[0004] According to one aspect of the present application, a reordering scheduling method is provided, comprising: Receive and convert the format of externally sent information; the information includes control commands and data corresponding to the control commands, including column addresses, row addresses and initial bank addresses; Regenerate a new BANK address based on the column address and the initial BANK address; According to the type of the control command and the new bank address, the control command is added to the buffer queue of the corresponding buffer queue set A; wherein, the control commands of the same type and the same new bank address are placed in the same buffer queue; Using an arbitration state machine, all control commands in buffer queue set A are reordered into buffer queue set B; According to the reordering results in the buffer queue set B, control commands and corresponding data scheduling are performed.

[0005] Furthermore, if a control command crosses a row address boundary, the control command needs to be split into two control commands with different row addresses.

[0006] Furthermore, a new BANK address is regenerated according to the column address and the initial BANK address, including: XOR the initial BANK address with the lower three bits of the column address to obtain a new BANK address.

[0007] Furthermore, the control commands are divided into first control commands and second control commands according to their types. The buffer queue set A includes a buffer queue set A1 and a buffer queue set A2. The first control command is added to the buffer queue set A1, and the second control command is added to the buffer queue set A2. An arbitration state machine is used to reorder all control commands in buffer queue set A into buffer queue set B, including: If the state of the arbitration state machine is the first state, the buffer queues in the buffer queue set A1 are fairly polled, and N first control commands are sequentially sent to the buffer queues in the buffer queue set B for storage, and the state of the arbitration state machine is switched to the second state; If the state of the arbitration state machine is the second state, the buffer queues in the buffer queue set A2 are fairly polled, and N second control commands are sequentially sent to the buffer queues in the buffer queue set B for storage, and the state of the arbitration state machine is switched to the first state.

[0008] Furthermore, when the arbitration state machine is in the first state or the second state, if the number of control commands in the corresponding buffer queue is less than N, the arbitration state machine switches its state after all control commands are sent.

[0009] Furthermore, in the buffer queue of buffer queue set B, the last control command conflicts with a control command in the front. If the types of the two are inconsistent, an invalid empty command is added between the two control commands; if the types of the two are consistent, the Bank address is the same, and the row address is different, in the next command cycle after the previous control command leaves the buffer queue, the pre-charge corresponding to the previous control command is turned off. After the pre-charge cycle ends, a Bank row valid command is issued to activate the last control command, pre-charge command, and Bank row valid command.

[0010] Furthermore, in the buffer queue of buffer queue set B, if the types of the last two control commands are consistent, the new BANK addresses are consistent, and the row addresses are different, an invalid empty command is added between the last two control commands to control the delay to meet the requirements of control command-precharge command-Bank row valid command; among them, if the type of the last two control commands is S, then there is no S type control command in buffer queue set A.

[0011] According to another aspect of the present application, a reordering scheduling device is provided, comprising: The conversion module receives and converts the format of information sent from the outside; the information includes control commands and data corresponding to the control commands, and the data includes column addresses, row addresses and initial bank addresses; The regeneration module regenerates a new BANK address based on the column address and the initial BANK address; The buffer module adds the control command to the buffer queue of the corresponding buffer queue set A according to the type of the control command and the new bank address; wherein, control commands of the same type and the same new bank address are placed in the same buffer queue; The reordering module uses an arbitration state machine to reorder all control commands in the buffer queue set A into the buffer queue set B; The scheduling module performs control commands and corresponding data scheduling based on the reordering results in the buffer queue set B.

[0012] According to one aspect of the present application, a computer-readable storage medium is provided, which stores one or more programs, wherein the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device performs a reordering scheduling method.

[0013] According to one aspect of the present application, a computer device is provided, comprising one or more processors and one or more memories, wherein one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for executing a reordering scheduling method.

[0014] The beneficial effects achieved by the present invention are as follows: By regenerating the bank address of the control command, storing the control command according to the new bank address, and reordering the control command using an arbitration state machine, the present invention can minimize the transmission time of a read / write transaction. Compared with a traditional DDR controller, the time required to transmit data of the same size is less, that is, more data can be transmitted in the same time, thereby improving the read and write transmission efficiency and greatly reducing bandwidth waste. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a flow chart of the reordering scheduling method; Figure 2 Schematic diagram for regenerating a new BANK address; Figure 3 This is a flowchart for reordering; Figure 4 This is a first example diagram of the control command sorting control in the buffer queue set B; Figure 5 A second example diagram of the control command sorting control in the buffer queue set B; Figure 6 A schematic diagram of the conversion delay between various control commands; Figure 7 is a block diagram of a reordering scheduling device; Figure 8 A schematic diagram of the DDR controller structure. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is obvious that the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0017] Unless specifically stated otherwise, the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0018] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0019] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0020] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0021] It should be noted that like symbols and letters refer to like items in the following figures, so once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0022] See also Figure 1 , Figure 1 : is a flowchart of a reordering scheduling method provided by an embodiment of the present application. The reordering scheduling method can be executed by a DDR controller. The reordering scheduling method can at least include the following steps: Step 1: Receive and convert the format of information sent from the outside; the information includes a control command and data corresponding to the control command, and the data includes a column address, a row address and an initial BANK address.

[0023] It should be noted that, taking the DDR controller that executes this method as an example, the external information is mainly information sent from the user-side interface. The user-side interface generally adopts the AXI bus commonly used in today's bus systems. Therefore, in order to adapt to the DDR controller, the DDR controller will convert the format of the information after receiving it.

[0024] It should be noted that the control commands are divided into first control commands and second control commands according to their types. For example, the first control command is a write control command, and the second control command is a read control command.

[0025] Step 2: Regenerate a new BANK address based on the column address and the initial BANK address.

[0026] It should be noted that after obtaining the information after format conversion, further operations need to be performed according to address mapping, address alignment and address segmentation.

[0027] The address mapping is that the lower 2 bits of the AXI address represent the byte address, which needs to be set to 0. At the same time, the AXI address greater than the high bit of the DDR address is set to 0, and the ROW-Bank-Column (row address-Bank address-column address) mapping method is adopted, and as shown Figure 2 As shown, the initial BANK address is XORed with the lower three bits of the column address to obtain a new BANK address. Specifically, the 3-bit Bank address is XORed with the lower three bits of the column address. Compared with the traditional mapping method, this mapping method can make the Bank address change quickly while the row address remains almost unchanged.

[0028] Taking the DDR controller as an example, the above-mentioned operation of generating a new BANK address can minimize the probability of the high-order address being mapped to the row address during the AXI Burst operation. The probability of the lower three bits of the bank address and the column address changing is the same, which can maximize the ability of all banks (such as 8) to accept commands together without making one bank clock work while the other bank is idle. In addition, by doing so, the number of commands received by the bank (such as 8) within a period of time will not be too different, which will cause most of the subsequent command buffer queues and data buffer modules to be idle and waste resources.

[0029] Address alignment means that when the data bit width of AXI transmission is large, the mapped address needs to be shifted left. For example, if 64 bits (8 bytes) are transmitted at a time, the lower three bits of the mapped address need to be 0, and the upper bits after the left shift need to be 0. Address splitting means that if a control command crosses a row address boundary, the control command needs to be split into two control commands with different row addresses. For example, when an AXI Burst Transform crosses a Row boundary, an AXI burst transfer command needs to be split into two burst transfer commands with different row addresses. This is to eliminate the extra precharge (precharge), Active (row read and write valid), and recovery (read / write recovery) delays introduced by cross-row read and write in one command, which causes bandwidth waste.

[0030] Step 3: Add the control command to the buffer queue of the corresponding buffer queue set A according to the type of the control command and the new BANK address; control commands of the same type and the same new BANK address are placed in the same buffer queue.

[0031] It should be noted that the number of buffer queue sets A is consistent with the number of types of control commands, for example, including buffer queue set A1 and buffer queue set A2. The first control command is added to buffer queue set A1, and the second control command is added to buffer queue set A2. Specifically, the write control command is added to buffer queue set A1, and the read control command is added to buffer queue set A2.

[0032] It's important to note that the number of buffer queues is equivalent to the number of banks. Modern DIMMs typically operate with eight banks simultaneously to meet bus width requirements. Therefore, each buffer queue set A includes eight buffer queues, corresponding to Banks 0 through 7. Control commands of the same type and bank address can be placed into the same buffer queue based on type and bank address. The buffer queue depth can be designed to be four, so if all buffer queues are full, each buffer queue set A will hold a total of 32 control commands.

[0033] Step 4: Use the arbitration state machine to reorder all control commands in the buffer queue set A into the buffer queue set B.

[0034] In some embodiments, the specific process may be as follows: If the state of the arbitration state machine is the first state, the buffer queues in the buffer queue set A1 are fairly polled, and N first control commands are sent to the buffer queue storage in the buffer queue set B in sequence, and the state of the arbitration state machine is switched to the second state; if the state of the arbitration state machine is the second state, the buffer queues in the buffer queue set A2 are fairly polled, and N second control commands are sent to the buffer queue storage in the buffer queue set B in sequence, and the state of the arbitration state machine is switched to the first state; wherein, N can generally be 16.

[0035] When the state of the arbitration state machine is the first state or the second state, if the number of control commands concentrated in the corresponding buffer queue is less than N, the state of the arbitration state machine is switched after all control commands are sent.

[0036] Taking the read control command and write control command as an example, the above process can be found in Figure 3 The arbitration state machine starts in the idle state. When a control command enters the buffer queue, to avoid delays caused by frequent read and write cycles, the read and write control commands need to be sent separately. Only after one command is sent will the other command be sent. For example, a read control command is sent only after 16 consecutive write control commands are sent. If there are fewer than 16 write control commands, the read control command is sent only after all write control commands are sent. The method for sending control commands uses a fair polling arbitration method for each buffer queue, and determines whether to continue polling the queue based on the value of the command counter in the buffer queue.

[0037] It should be noted that when reordering control commands, timing requirements must also be considered. For example, according to the timing requirements of DDR, functions or commands such as pre-charge, active (Bank row valid), refresh, self-refresh, and power-down must be combined to achieve efficient reading and writing of DDR.

[0038] Therefore, in some embodiments, in the buffer queue of buffer queue set B, the last control command conflicts with a control command in the front row. If the types of the two are inconsistent, an invalid empty command (NOP) is added between the two control commands; if the types of the two are consistent, the Bank address is the same, and the row address is different, in the next command cycle after the previous control command leaves the buffer queue, the pre-charge corresponding to the previous control command is turned off. After the pre-charge cycle ends, a Bank row valid command is issued to activate the last control command, pre-charge command, and Bank row valid command.

[0039] It should be noted that when reordering, the Look Ahead function can be used, combined with auxiliary commands pre-charge and active and other commands to achieve efficient data transmission and improve reading and writing efficiency. Figure 4 For example, Figure 4In the left image, there is a conflict between two control commands (marked in red). After the last control command enters the buffer queue, it is found that it conflicts with a control command in front of it. At this time, it is necessary to calculate the number of commands between the two to calculate the delay. If the subsequent command is of other types, such as write control commands, it is necessary to add an invalid empty command (NOP) when the delay is not enough. Then, in the next command cycle after the previous conflicting control command leaves the queue, turn off (pre-charge) row1 of Bank0. After the pre-charge cycle is over, issue the Active command to activate row3 of Bank0. The pre-charge and active commands as auxiliary read and write commands will not affect the execution of other commands being read and written. When the write command of Bank0 row3 comes to the top of the queue, the delay of the active command has been met, and the write operation can be performed directly. As a result, there is no idle delay on the data line, so that data can be read and written continuously.

[0040] In some embodiments, in the buffer queue of buffer queue set B, if the types of the last two control commands are the same, the new BANK addresses are the same, and the row addresses are different, an invalid empty command is added between the last two control commands to control the delay to meet the requirements of control command-precharge command-Bank row valid command; among them, if the type of the last two control commands is S, then there is no S type control command in buffer queue set A.

[0041] by Figure 5 For example, when the last two write control commands are in different rows of the same bank, a NOP needs to be added between Bank0 row1 and Bank0 row3 to control the command delay to meet the write-pre_charge-active requirement.

[0042] When two different types of control commands are sequentially stored in the buffer queue of the buffer queue set B, if the new BANK addresses and row addresses of the two control commands are consistent, an invalid empty command and other control commands are added between the two control commands.

[0043] by Figure 5 For example, the write control command of Bank0 row1 and the read control command of Bank0 row1 are sequentially added to the buffer queue set B, and NOP, the read control command of Bank0 row2, the read control command of Bank0 row3, etc. are added between them.

[0044] After all write control commands are sent, continue to send read control commands, and use auxiliary commands to sort the control commands according to the parameter delay for each control command conversion in the DDR command. The timing delay control and conversion between each control command can be seen in Figure 6 , the timing parameters can be found in the table below.

[0045] Table 1 1GB MICRO DDR3-1600 11-11-11 sg-125 timing parameters

[0046] Step 5: According to the reordering result in the buffer queue set B, control commands and corresponding data scheduling are performed.

[0047] The above method optimizes the address mapping method. The lower two bits of the AXI address represent the byte address and need to be set to 0. At the same time, the high bit of the AXI address that is greater than the DDR address is set to 0. The ROW-Bank-Column (row address-Bank address-column address) mapping method is adopted, and the 3-bit Bank address is XORed with the lower three bits of the Col address. Compared with the traditional mapping method, the Bank address can be changed quickly while the Row address remains almost unchanged.

[0048] The above method splits an AXI Burst Transform command into two burst transfer commands with different row addresses when the AXI Burst Transform command crosses a row boundary. This eliminates the extra pre-charge, active, and recovery delays introduced by cross-row reads and writes in a single command, which wastes bandwidth.

[0049] The above method places the processed control commands and address signals into the corresponding buffer queues according to the read and write modes, and sorts the commands in the queues respectively. Then, the read / write commands are reassembled and re-sorted through the arbitration state machine. After a certain number of read or write commands are transmitted, the other command is transmitted. In the re-sorting process, because the control commands with the same bank address but different row addresses are in conflict, other commands need to be inserted between the conflicting control commands. The purpose is to use the delay between the original conflicting control commands to read and write other banks, reduce the conflict delay on the bus, and improve the transmission efficiency. In addition, since the first step adopts a new bank address XOR method, the subsequent 8 bank buffer queues for fair polling read / write can distribute the commands of a burst transfer transaction as evenly as possible to different banks. Most of these commands have the same row address. In the reordering process, when a read transaction is converted to a write transaction or a write transaction is converted to a read transaction, the read and write commands of the same bank are separated, and other read or write control commands are inserted in the middle to minimize the delay lost in the control command conversion process. For the delay process, NOP is used to fill the delay to prevent errors. Subsequent refresh and low-power mode commands are inserted into the DFI (DDR PHY Interface) interface protocol based on the original read and write commands after calculating a certain time through the timing counter, thereby reducing power consumption and improving performance.

[0050] The above method can minimize the transmission time of a read / write transaction by regenerating the bank address of the control command, storing the control command according to the new bank address, and reordering the control commands using an arbitration state machine. Compared with traditional DDR controllers, it takes less time to transmit data of the same size, that is, more data can be transmitted in the same amount of time, thereby improving read and write transmission efficiency and greatly reducing bandwidth waste.

[0051] Figure 7 is a block diagram of a reordering scheduling device provided in an embodiment of the present application. Figure 7 The embodiment is a virtual device that can be loaded and executed by a computer device. The computer device may include the above-mentioned DDR controller. The device may include a conversion module, a regeneration module, a buffer module, a reordering module, and a scheduling module. When used to execute the above-mentioned reordering scheduling method, it can: The conversion module receives and converts the format of information sent from the outside; the information includes control commands and data corresponding to the control commands, and the data includes column addresses, row addresses and initial bank addresses; The regeneration module regenerates a new BANK address based on the column address and the initial BANK address; The buffer module adds the control command to the buffer queue of the corresponding buffer queue set A according to the type of the control command and the new bank address; wherein, control commands of the same type and the same new bank address are placed in the same buffer queue; The reordering module uses an arbitration state machine to reorder all control commands in the buffer queue set A into the buffer queue set B; The scheduling module performs control commands and corresponding data scheduling based on the reordering results in the buffer queue set B.

[0052] To further illustrate the above method and apparatus, take the DDR controller as an example, see Figure 8The DDR controller includes AXI interface, command split (command split module), reorder1 (reorder module 1), reorder2 (reorder module 2), read data buffer (read data buffer module), write data buffer (write data buffer module), initialization (initialization module), refresh control (refresh control module), DFI Interface (DDRPHY interface module) The AXI interface acts as an AXI Slave, converting information from external users such as the CPU, Cache, or DMA into information that complies with DDR. That is, the AXI interface module can implement the functions of the above-mentioned conversion module.

[0053] Command split is used to perform address mapping, address alignment and address splitting operations, that is, command splie includes the functions of the above-mentioned regeneration module.

[0054] reorder1 (reordering module 1) and reorder2 (reordering module 2) implement the functions of the buffer module and the reordering module respectively.

[0055] The read data buffer (read data buffer module) synchronizes the data read from the DDR PHY interface with the DDR controller through the FIFO. If the DDR PHY data bit width is larger than the DDR controller interface data bit width, it needs to be converted from parallel to serial and then output through the AXI interface.

[0056] The write data buffer module matches the corresponding data buffer according to a maximum of 32 buffer commands to temporarily buffer the written data. It also generates a buffer ID based on the location of different data buffers and sends it to the Command Split module to combine it with the original command information into a new command. Later, in the DFI Interface (DDRPHY interface protocol), the corresponding data is found based on the buffer ID information and sent to the memory.

[0057] The Initialization module mainly controls the DDR power-on timing and register initialization timing, and completes the initialization by using the timer count delay control signal according to the DDR protocol requirements.

[0058] The main function of the refresh control module is that DDR SDRAM is a dynamic memory module that uses capacitor charging and discharging to complete read and write functions. Therefore, it needs to be refreshed regularly to prevent the stored information from changing due to capacitor power failure.

[0059] The DFI Interface (DDR PHY Interface) is an internationally standardized interface protocol between the DDR controller and the DDR PHY. When a refresh command is valid, it has the highest priority and is inserted at the top of the command queue, ensuring a fast refresh response. The specific power-up and refresh timing requirements are beyond the scope of this article and will not be discussed in depth.

[0060] The present application also discloses a computer-readable storage medium, which stores one or more programs. The one or more programs include instructions. When the instructions are executed by a computing device, the computing device executes the reordering scheduling method.

[0061] The present application also discloses a computer device comprising one or more processors and one or more memories, wherein one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for executing the reordering scheduling method.

[0062] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0063] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0064] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0066] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.

Claims

1. A reordering scheduling method, characterized in that: include: Receive and convert the format of externally sent information; the information includes control commands and data corresponding to the control commands, including column addresses, row addresses and initial bank addresses; Regenerate a new BANK address based on the column address and the initial BANK address; According to the type of the control command and the new bank address, the control command is added to the buffer queue of the corresponding buffer queue set A; wherein, the control commands of the same type and the same new bank address are placed in the same buffer queue; Using an arbitration state machine, all control commands in buffer queue set A are reordered into buffer queue set B; According to the reordering results in the buffer queue set B, control commands and corresponding data scheduling are performed.

2. The method according to claim 1, characterized in that If a control command crosses a row address boundary, the control command needs to be split into two control commands with different row addresses.

3. The method according to claim 1, characterized in that Regenerate a new bank address based on the column address and the initial bank address, including: XOR the initial BANK address with the lower three bits of the column address to obtain a new BANK address.

4. The method according to claim 1, wherein The control commands are divided into first control commands and second control commands according to their types. The buffer queue set A includes a buffer queue set A1 and a buffer queue set A2. The first control command is added to the buffer queue set A1, and the second control command is added to the buffer queue set A2. An arbitration state machine is used to reorder all control commands in buffer queue set A into buffer queue set B, including: If the state of the arbitration state machine is the first state, the buffer queues in the buffer queue set A1 are fairly polled, and N first control commands are sequentially sent to the buffer queues in the buffer queue set B for storage, and the state of the arbitration state machine is switched to the second state; If the state of the arbitration state machine is the second state, the buffer queues in the buffer queue set A2 are fairly polled, and N second control commands are sequentially sent to the buffer queues in the buffer queue set B for storage, and the state of the arbitration state machine is switched to the first state.

5. The method according to claim 4, characterized in that When the state of the arbitration state machine is the first state or the second state, if the number of control commands concentrated in the corresponding buffer queue is less than N, the state of the arbitration state machine is switched after all control commands are sent.

6. The method according to claim 4, characterized in that In the buffer queue of buffer queue set B, the last control command conflicts with a control command in the front row. If the types of the two control commands are inconsistent, an invalid empty command is added between the two control commands. If the two are of the same type, have the same Bank address but different row addresses, in the next command cycle after the previous control command leaves the buffer queue, the precharge corresponding to the previous control command is turned off. After the precharge cycle ends, a Bank row valid command is issued to activate the last control command, precharge command and Bank row valid command.

7. The method according to claim 4, characterized in that In the buffer queue of buffer queue set B, if the types of the last two control commands are the same, the new BANK addresses are the same, and the row addresses are different, an invalid empty command is added between the last two control commands to control the delay to meet the requirements of control command-precharge command-Bank row valid command; among them, if the type of the last two control commands is S, there is no S type control command in buffer queue set A.

8. A reordering scheduling device, characterized in that: include: The conversion module receives and converts the format of information sent from the outside; the information includes control commands and data corresponding to the control commands, and the data includes column addresses, row addresses and initial bank addresses; The regeneration module regenerates a new BANK address based on the column address and the initial BANK address; The buffer module adds the control command to the buffer queue of the corresponding buffer queue set A according to the type of the control command and the new bank address; wherein, control commands of the same type and the same new bank address are placed in the same buffer queue; The reordering module uses an arbitration state machine to reorder all control commands in the buffer queue set A into the buffer queue set B; The scheduling module performs control commands and corresponding data scheduling based on the reordering results in the buffer queue set B.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs include instructions. When the instructions are executed by a computing device, the computing device executes the method according to any one of claims 1 to 7.

10. A computer device, characterized in that: include: One or more processors, and one or more memories, one or more programs stored in the one or more memories and configured to be executed by the one or more processors, the one or more programs including instructions for executing any one of the methods of claims 1 to 7.

Images