A posit format-based processing-in-memory processor and processing method

Abstract

The application provides a processing method and a processing device based on a POSIT format, and the application can greatly reduce the calculation complexity during network training by using the improved POSIT data format, and the range of numerical representation is improved due to the reserved dynamic bit width feature, the accuracy of neural network training is ensured, and the technical problems that the low-precision training in the prior art supports floating-point or integer data format and does not support the POSIT data type are solved. In addition, a large number of optimization means are required to ensure the accuracy, the technical scheme is complex, the data format lacks flexibility, and the network parameters cannot be effectively represented.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage technology, and in particular to a POSIT-based in-memory processor and processing method. Background Technology

[0002] Traditional processors, employing the von Neumann architecture with its separation of computation and storage, experience frequent large-scale data movement during network training, leading to a significant increase in energy consumption and making it difficult to achieve a good balance between high throughput and low power consumption. Therefore, in-memory computing technology has emerged, which embeds computing functions directly into storage units, effectively reducing data movement and improving computational efficiency, becoming an important development direction for current AI chip architectures.

[0003] Low-precision training provides a solution for mobile and edge computing scenarios. It utilizes FP8 or even INT8 data formats for network training, significantly reducing computational complexity and memory bandwidth requirements. However, relevant optimization measures are needed to ensure network training accuracy.

[0004] IEEE 754 standard floating-point arithmetic plays a crucial role in current network training, with its large bit width format meeting the high-precision requirements of network training. While the POSIT data format offers more flexible numerical representation due to its dynamic regime, enabling the representation of a larger data range, its uncertain mantissa bit width makes it unsuitable for accelerating computation in in-memory computing architectures.

[0005] Therefore, this invention proposes an improved POSIT data format that truncates the last digit, making it suitable for in-memory computing architectures to accelerate computation and applicable to low-precision network training. Summary of the Invention

[0006] Based on the technical problems existing in the above-mentioned background technology, the present invention proposes a POSIT-based in-memory processor and processing method, and the technical solution adopted includes:

[0007] A processing method based on the POSIT format, the method comprising:

[0008] S1: Encode the neural network parameters according to the standard POSIT data format and divide them according to the base data block size;

[0009] S2: Calculate the dynamic dispersion of the mantissa of the neural network parameters within each baseline block and dynamically adjust the data block size;

[0010] S3: Extract the maximum exponent as the shared exponent according to the adjusted data block, align the exponents of the rest of the numbers to the shared exponent and shift the mantissas accordingly, and truncate the shifted mantissas: fill 0 to the low bits when the bit width is less than 6 bits, and keep the high 6 bits when the bit width is greater than or equal to 6 bits, to generate improved POSIT data;

[0011] S4: Store the improved POSIT data to a storage module integrated with a computing array;

[0012] S5: Obtain activation data, convert the activation data to improved POSIT data by using the steps S1-S3, and perform multiply-accumulate operation by using the computing array;

[0013] S6: Encode the multiply-accumulate result into a standard POSIT format and output.

[0014] Preferably, the S1 is performed according to the size of the reference data block, and includes:

[0015] When the dynamic dispersion degrees of a plurality of reference data blocks connected in series are all greater than the high dispersion super block triggering threshold, the plurality of reference data blocks are merged into a super block, and the super block is the minimum reference data block.

[0016] Preferably, the S2 dynamically adjusts the size of the data block, and specifically includes:

[0017] If the dynamic dispersion degree is greater, it indicates that the mantissas of the neural network parameters in each reference block are more dispersed, and the size of the data block is reduced;

[0018] If the dynamic dispersion degree is smaller, it indicates that the mantissas of the neural network parameters in each reference block are more concentrated, and the size of the data block is increased.

[0019] Preferably, the dynamic dispersion degree is obtained by the following method:

[0020] Obtain the variance and mean of the absolute values of the mantissas of the neural network parameters;

[0021] Obtain the logarithm of the number of the neural network parameters in each data block;

[0022] The dynamic dispersion degree is proportional to the variance, and inversely proportional to the mean and the logarithm of the number of the neural network parameters.

[0023] Preferably, the step of extracting the maximum exponent as the shared exponent in the S3 specifically includes:

[0024] Traverse the Regime domain and the exponent domain of all the neural network parameters in each adjusted data block, and calculate the actual exponent value of each neural network parameter;

[0025] Select the maximum actual exponent value as the shared exponent of a single adjusted data block.

[0026] Preferably, the remaining number of S3 is aligned to the shared exponent and the mantissa is shifted accordingly, specifically including:

[0027] For each neural network parameter, calculate the difference between the actual exponent and the shared exponent ;

[0028] If the difference is less than 0, then right shift the mantissa of the neural network parameter by bits;

[0029] If the difference is greater than 0, then left shift the mantissa of the neural network parameter by bits;

[0030] After shifting, if the mantissa exceeds the 6-bit width, use rounding and overflow saturation processing.

[0031] Preferably, S5 performs multiply-accumulate operations through a compute-in-memory array, specifically including:

[0032] The compute-in-memory array performs parallel multiplication operations on the improved POSIT data activation data and weight parameters based on the two's complement representation, wherein:

[0033] Each computing unit uses bit-level multiplication logic, and the activation data is input into the compute-in-memory array in bit serial mode, and the entire compute-in-memory array performs in-place multiplication operations synchronously;

[0034] The results of the in-place multiplication are added by the adder tree level by level to obtain the intermediate results of the 6-bit mantissa multiplication;

[0035] The intermediate results are accumulated in fixed-point number form, and the final accumulation result is output.

[0036] Preferably, S6 includes:

[0037] Based on the mantissa of the neural network parameter corresponding to the shared exponent and the accumulation result, reconstruct the standard POSIT data, Regime domain and exponent domain.

[0038] Preferably, the reconstruction of the standard POSIT data, Regime domain and exponent domain specifically includes:

[0039] The Regime domain is determined according to the numerical range of the shared exponent: if the shared exponent is positive, the Regime domain ends with consecutive 0; if it is negative, the Regime domain ends with consecutive 1, and the length is determined by the absolute value of the shared exponent;

[0040] The numerical value of the exponent domain is the shared exponent minus the offset corresponding to the Regime domain;

[0041] ​​The mantissa bits of the standard POSIT data directly adopt the high effective bits of the mantissa of the accumulation result, and the insufficient part is complemented with 0.

[0042] A memory-compute integrated processor based on a POSIT format, characterized in that the memory-compute integrated processor comprises:

[0043] Parameter coding and initial block division unit: coding the neural network parameters according to the standard POSIT data format, and dividing according to the reference data block size;

[0044] Dynamic dispersion calculation and block size adjustment unit: calculating the dynamic dispersion of the mantissa of the neural network parameters in each reference block, and dynamically adjusting the data block size;

[0045] Exponent alignment and mantissa truncation unit: extracting the maximum exponent as a shared exponent according to the adjusted data block, aligning the exponents of the remaining numbers to the shared exponent and shifting the mantissa accordingly, and truncating the shifted mantissa: when the bit width is less than 6 bits, the low bits are complemented with 0, and when the bit width is greater than or equal to 6 bits, the high 6 bits are reserved: generating improved POSIT data;

[0046] Memory-compute integrated storage unit: storing the improved POSIT data into the memory module of the memory-compute integrated processor;

[0047] Activation data processing and multiply-accumulate operation unit: obtaining activation data, converting the improved POSIT data by using the steps S1-S3, and performing multiply-accumulate operation through the memory-compute array;

[0048] Standard format reconstruction unit: coding the multiply-accumulate result into the standard POSIT format and outputting.

[0049] The improved POSIT data format can greatly reduce the computational complexity of network training, and due to the dynamic bit width feature, the range of numerical representation is improved, and the accuracy of neural network training is guaranteed.

[0050] The memory-compute integrated circuit based on the improved POSIT data format can store weight information in this format and perform multiply-accumulate acceleration in this format, greatly reducing the computational power consumption, further improving the energy efficiency of low-precision neural network training, and greatly reducing the training cost. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 The improved POSIT data of the present application;

[0052] Figure 2 The memory-compute integrated processor of the present application;

[0053] Figure 3The calculation process of encoding the multiply-accumulate result into a standard POSIT format output. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, it should be understood that the preferred embodiments described here are only used to illustrate and explain the present application, and are not used to limit the present application.

[0055] One embodiment of the present application is a processing method based on the POSIT format, the method comprising:

[0056] S1: encode the neural network parameters according to the standard POSIT data format, and divide them according to the reference data block size; the size of the reference data block is ;

[0057] S2: calculate the dynamic dispersion of the mantissa of the neural network parameters in each reference block, and dynamically adjust the data block size;

[0058] S3: according to the re-adjusted data block, extract the maximum exponent as the shared exponent, align the exponents of the remaining numbers to the shared exponent and shift the mantissa accordingly, and truncate the shifted mantissa: when the bit width is less than 6 bits, fill 0 in the low bits, and when the bit width is greater than or equal to 6 bits, keep the high 6 bits: generate improved POSIT data;

[0059] S4: store the improved POSIT data to the storage module of the storage-computing integrated module;

[0060] S5: obtain the activation data, convert it to improved POSIT data using steps S1-S3, and perform multiply-accumulate operation through the storage-computing array;

[0061] S6: encode the multiply-accumulate result into a standard POSIT format output.

[0062] The working principle and effect of the above technical solution are: first, encode the neural network parameters according to the standard POSIT format and divide them into reference data blocks, dynamically adjust the data block size by calculating the dynamic dispersion of the mantissa of the parameters in the block, so that the block size adapts to the parameter distribution characteristics; then, extract the maximum exponent as the shared exponent from the adjusted data block, align the exponents of the other parameters to the shared exponent and shift the mantissa accordingly, and then truncate or pad the mantissa to 6 bits, generate improved POSIT data to balance accuracy and efficiency; then, store the improved data into the storage-computing integrated storage module, and after executing the same conversion process on the activation data, use the parallel multipliers of the storage-computing array to perform low-precision multiply-accumulate operation on the activation data and the weight parameters; finally, reconstruct the Regime domain, exponent domain and mantissa bits from the operation result, encode it back to the standard POSIT format output, realize the whole process of low-precision optimization from parameter storage, calculation to result output;

[0063] The method improves the adaptability of parameter block to data distribution by dynamically adjusting the data block size, avoids the precision loss or low efficiency caused by fixed block size; by extracting the maximum index as the shared index and uniformly aligning the mantissa, the precision retention capability under low precision representation is improved, and the truncation error caused by too large index difference is avoided; the multiply-accumulate operation is performed in parallel using the computing-in-memory array, the throughput and energy efficiency ratio of neural network calculation are improved, and the energy consumption and delay of data movement in the traditional architecture are avoided; finally, the result is encoded into the standard POSIT format and output, the compatibility with the downstream system is improved, and the additional conversion overhead caused by inconsistent format is avoided, which improves the processing efficiency and resource utilization under the computing-in-memory architecture while ensuring the accuracy of neural network calculation.

[0064] In an embodiment of the present application, the S1 is divided according to the reference data block size, including:

[0065] When the dynamic dispersion degrees of a plurality of continuous reference data blocks are all greater than the high dispersion super block trigger threshold, the plurality of reference data blocks are merged into a super block, and the super block is the minimum reference data block.

[0066] The working principle and effect of the above technical solution are as follows: when dividing parameters according to the reference data block size, the dynamic dispersion degrees of adjacent reference data blocks are continuously monitored, when it is found that the dynamic dispersion degrees of three continuous reference data blocks all exceed the high dispersion super block trigger threshold, it is indicated that the mantissa distribution of the parameters in these blocks is highly dispersed, at this time, they are merged into a larger super block, and at the same time, in order to ensure the flexibility and precision of the processing in the super block, each subunit in the super block is still set to the minimum reference data block size;

[0067] By merging the reference data blocks with continuous high dynamic dispersion into a super block, the data block management efficiency of the high dispersion area is improved, and the frequent addressing and control overhead caused by a large number of small reference blocks is avoided; at the same time, the minimum reference data block is retained in the super block as a processing unit, the local precision control capability is improved, and the precision loss caused by the super block being too large is avoided, the number of blocks and the management complexity are reduced while ensuring the processing precision of the high dispersion parameters.

[0068] In an embodiment of the present application, the S2 dynamically adjusts the data block size, specifically including:

[0069] If the dynamic dispersion degree is larger, it indicates that the mantissa of the neural network parameters in each reference block is more dispersed, and the data block size is reduced;

[0070] If the dynamic dispersion degree is smaller, it indicates that the mantissa of the neural network parameters in each reference block is more concentrated, and the data block size is increased, and the S2 dynamically adjusts the data block size by the following formula:

[0071]

[0072] in, Indicates the preset minimum data block size ( =8); Indicates the preset maximum data block size ( =64), The weights represent the dynamic dispersion coefficients; for convolutional layers, α = 1.0, and for fully connected layers, α = 0.6. β represents the variance weighting coefficient, with β=0.5 for convolutional layers and β=0.3 for fully connected layers; D represents the dynamic dispersion. The variance of the mantissa of the parameters within the data block;

[0073] The working principle and effect of the above technical solution are as follows: In the calculation formula for adjusting the data block size, through... A nonlinear mapping is constructed to make the block size response to parameter variance exhibit a "slow in, steep out" characteristic. This nonlinear response is more consistent with the physical characteristics of in-memory computing architectures than linear scaling; that is, when parameter fluctuations are large, the accuracy loss caused by exponential sharing increases exponentially, requiring a nonlinear mechanism to quickly shrink the block size. Simultaneously, for The calculation results are rounded to match the physical structure of the storage array. Storage cells are usually organized in powers of 2 (8 / 16 / 32 / 64, etc.), and the discrete block size avoids the padding overhead during hardware alignment. As a volatility indicator, it directly reflects the physical characteristics of the parameter distribution:

[0074] High-variance regions require smaller blocks to reduce exponential sharing error.

[0075] Low variance regions allow for larger blocks to increase computational parallelism.

[0076] Traditional methods typically use fixed block sizes, which cannot adapt to changes in parameter distribution; threshold-based piecewise adjustment results in discontinuous responses and boundary effects; and global statistical characteristic adjustment ignores local fluctuation characteristics.

[0077] This formula achieves the coupling of the physical characteristics of parameter distribution with the in-memory computing architecture through continuous mapping of variance, nonlinear response, and hardware-friendly discretization.

[0078] In one embodiment of the present invention, the dynamic dispersion is obtained in the following manner:

[0079] Obtain the variance and mean of the absolute values ​​of the mantissas of the neural network parameters;

[0080] Get the logarithm of the number of neural network parameters within each data block;

[0081] The dynamic dispersion is proportional to the variance, inversely proportional to the mean and the logarithm of the number of neural network parameters, and the dynamic dispersion is obtained by the following formula:

[0082]

[0083] Wherein, The variance of the absolute value of the mantissa of the neural network parameter, The mean of the absolute value of the mantissa of the neural network parameter, Indicates the number of neural network parameters within each data block;

[0084] The working principle and effect of the above technical scheme are that in the calculation formula of the above dynamic dispersion D, And the product relationship of Form a nonlinear response, so that the D value shows differentiated sensitivity to data of different distribution patterns:

[0085] High dispersion data: σ² / μ² significantly increases, D rapidly rises, and the block size rapidly shrinks

[0086] Low dispersion data: σ² / μ² close to 1, D dominated by log (N), smooth adjustment of block size

[0087] Match the nonlinear response characteristics with the physical constraints of the memory-computing integrated architecture

[0088] The traditional data blocking method usually adopts: fixed block size: unable to adapt to parameter distribution changes

[0089] Threshold-based heuristic adjustment: ignores the inherent distribution characteristics of data

[0090] Global statistical property adjustment: ignores local fluctuation characteristics

[0091] And the formula realizes: automatic adaptation to different layers and different regional parameter characteristics, low computational complexity, adaptation to memory-computing integrated architecture, and maximum precision preservation under minimum computational overhead through the combination design of relative dispersion + block size compensation + nonlinear response.

[0092] In one embodiment of the present application, the maximum index in the S3 is extracted as a shared index, specifically comprising:

[0093] Traverse all neural network parameters in each adjusted data block in the Regime domain and the index domain, and calculate the actual index value of each neural network parameter;

[0094] Select the maximum actual index value as the shared index of a single adjusted data block.

[0095] For the i-th parameter in the data block, the actual exponent is

[0096] where s represents the sign bit (0 or 1) of the Regime domain, and r represents the number of continuous sign bits in the Regime domain, represents the 2-bit binary value (range 0~3) of the exponent domain;

[0097] The working principle and effects of the above technical solution are as follows: for each neural network parameter in the adjusted data block, the Regime domain and the exponent domain in the POSIT format are first parsed, the sign bit of the Regime domain is used to determine the positive or negative of the exponent, the number of continuous sign bits is combined to calculate the contribution value of the domain to the exponent, and then the binary value of the exponent domain is superimposed to obtain the actual exponent value of each parameter. Finally, the largest one is selected from the actual exponent values of all parameters as the shared exponent of the current data block, so as to ensure that the exponents of all parameters in the block can be aligned to the maximum exponent.

[0098] By unifying the exponent reference in the data block, the exponents of all parameters in the block are aligned to the maximum exponent, which can reduce the magnitude of the shift of the mantissa caused by the too large difference between the exponents, reduce the precision loss when the mantissa is truncated or zero-padded, and simplify the exponent processing logic of the multiply-accumulate operation in the storage and calculation array, avoid complex conversion between different exponents, improve the calculation efficiency, and ensure that all parameters will not cause the mantissa to overflow during the alignment process due to the lack of exponents, thereby improving the integrity of data representation in the low-precision (6-bit mantissa) scenario.

[0099] In an embodiment of the present application, the exponents of the remainders of the S3 are aligned to the shared exponent and the mantissa is shifted accordingly, specifically including:

[0100] For each neural network parameter, the difference between the actual exponent and the shared exponent is calculated .

[0101] If the difference is less than 0, the mantissa of the neural network parameter is right-shifted by bits;

[0102] If the difference is greater than 0, the mantissa of the neural network parameter is left-shifted by bits;

[0103] After the shift, if the mantissa exceeds the 6-bit width, rounding and overflow saturation processing are used.

[0104] ​​The working principle and effect of the above technical solution are: for each neural network parameter in the data block, first calculate the difference between its actual exponent and the shared exponent, if the difference is less than 0, it means that the magnitude of the value represented by the original exponent of the parameter is smaller, and the mantissa needs to be right shifted to increase the exponent, and the low bits generated by the right shift are discarded and may be retained more accurately by rounding; if the difference is greater than 0, it means that the magnitude of the value represented by the original exponent of the parameter is larger, and the mantissa needs to be left shifted to reduce the exponent, and the left shift may cause the mantissa to exceed 6 bits of width, at this time, the overflow saturation processing is triggered, that is, when the mantissa is shifted and exceeds 6 bits of width, the truncated low bits are judged, if the highest bit of the truncated part is 1, 1 is added to the lowest bit of the reserved 6-bit mantissa, if it is 0, it is directly discarded, for example: the mantissa of a certain parameter is 7 bits 1011001 after shifting, the lowest bit of the truncated part is 1, therefore the 6-bit mantissa after rounding is 101101; the overflow saturation processing is that when the mantissa is left shifted to cause the value to exceed the maximum range that can be represented by 6 bits, at this time, the carry is no longer continued, but the mantissa is fixed to the maximum value 111111 of 6 bits, to avoid the value representation error caused by overflow, for example: the mantissa of a certain parameter is 111111, because the exponent difference needs to be left shifted by 2 bits, the width is exceeded after shifting, and the saturation processing is triggered, and finally the mantissa remains 111111.

[0105] The present scheme can balance the precision and bit width limitation, and improve the stability of numerical value representation, and provide a format unified, precision controllable data basis for the efficient multiply-accumulate operation of the subsequent compute-in-memory array.

[0106] In an embodiment of the present application, the S5 performs multiply-accumulate operation through the compute-in-memory array, specifically comprising:

[0107] The compute-in-memory array performs parallel multiplication operation on the improved POSIT data activation data and weight parameters based on the binary complement representation method, wherein:

[0108] Each computing unit adopts bit-level multiplication logic, and the activation data is input into the compute-in-memory array in a bit serial manner, and the entire compute-in-memory array performs in-place multiplication operation synchronously;

[0109] The result of the in-place multiplication is added by the adder tree level by level to obtain the intermediate result of 6-bit mantissa multiplication;

[0110] The intermediate result is accumulated in the form of fixed-point number, and the final accumulation result is output.

[0111] The working principle and effects of the above technical solution are as follows: the memory-computing array adopts binary complement representation method to process the activation data and weight parameters of the improved POSIT format, each computing unit operates through bit-level multiplication logic, after the activation data is input into the memory-computing array in a bit serial manner, the entire array synchronously performs in-place multiplication operation on the activation data and the weight parameters, the bit-level results generated by the in-place multiplication are collected and added through the adder tree level by level to obtain the intermediate results of 6-bit mantissa multiplication, and the intermediate results are accumulated according to the representation rule of fixed-point numbers to finally output the accumulated results;

[0112] The bit-level multiplication logic and the bit serial input mode are adopted, the data throughput efficiency of the memory-computing array is improved, and the line resource waste during parallel input is avoided; the data is directly calculated in the storage unit through in-place multiplication operation, the data processing speed is improved, and the energy consumption and delay caused by frequent data transfer between the storage unit and the computing unit are avoided; the adder tree collects the results level by level, the integration efficiency of the intermediate results is improved, and the time overhead of serial accumulation is avoided; finally, the result accuracy is ensured by accumulating in the form of fixed-point numbers, while the parallelism and energy efficiency of the multiplication and accumulation operation are improved, the accuracy of neural network calculation is ensured, and the demand of the memory-computing integrated architecture for efficient and low-energy calculation is met.

[0113] In an embodiment of the present application, the reconstructed standard POSIT data, the Regime domain and the exponent domain specifically include:

[0114] The Regime domain is determined according to the value range of the shared exponent: if the shared exponent is positive, the Regime domain ends with consecutive 0; if the shared exponent is negative, the Regime domain ends with consecutive 1, and the length is determined by the absolute value of the shared exponent;

[0115] The value of the exponent domain is the shared exponent minus the offset corresponding to the Regime domain;

[0116] The mantissa bits of the standard POSIT data directly adopt the high effective bits of the accumulation result mantissa, and the insufficient part is supplemented with 0.

[0117] The working principle and effect of the technical scheme are as follows: when the standard POSIT data is reconstructed, first, the end feature of the Regime domain is determined according to the positive and negative of the shared index, the Regime domain ends with consecutive 0 when the shared index is positive, and ends with consecutive 1 when the shared index is negative, and the length of the Regime domain is determined according to the size of the absolute value of the shared index; then the value of the index domain is obtained by subtracting the offset corresponding to the Regime domain from the shared index; finally, the high significant bit of the tail of the multiplication and accumulation result is taken as the tail bit of the standard POSIT data, and 0 is filled in the low bit if the tail length is insufficient, so that the low-precision accumulation result is converted back to the standard POSIT format through the cooperation of the Regime domain, the index domain and the tail bit;

[0118] The accuracy of the standard POSIT format reconstruction is improved, the Regime domain dynamically adapts to the shared index range, the index domain realizes fine adjustment, and the range limitation of the single domain expression index is avoided; the result precision retention efficiency is improved, the tail bit adopts the high significant bit of the accumulation result and fills 0, and the information loss in the format conversion is avoided; the hardware implementation efficiency is improved, the mapping logic of the improved format to the standard format is simplified, and the energy consumption and complexity increase caused by the complex conversion are avoided.

[0119] An embodiment of the present application is a storage-computing integrated processor based on the POSIT format, characterized in that the storage-computing integrated processor comprises:

[0120] Parameter encoding and initial block division unit: encode the neural network parameters according to the standard POSIT data format, and divide them according to the reference data block size;

[0121] Dynamic dispersion calculation and block size adjustment unit: calculate the dynamic dispersion of the tail of the neural network parameters in each reference block, and dynamically adjust the data block size;

[0122] Exponent alignment and tail truncation unit: according to the re-adjusted data block, extract the maximum exponent as the shared index, align the exponents of the remaining numbers to the shared index and shift the tail accordingly, and truncate the shifted tail: fill 0 in the low bit when the bit width is less than 6 bits, and keep the high 6 bits when the bit width is greater than or equal to 6 bits, to generate improved POSIT data;

[0123] Storage-computing integrated storage unit: store the improved POSIT data into the storage module of the storage-computing integrated processor;

[0124] Activation data processing and multiplication and accumulation operation unit: obtain the activation data, convert it into improved POSIT data by using the steps S1-S3, and perform multiplication and accumulation operation through the storage-computing array;

[0125] Standard format reconstruction unit: encode the multiplication and accumulation result into the standard POSIT format and output.

[0126] The working principle and effects of the above technical solutions are:

[0127] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A processing method based on the POSIT format, characterized in that, The method includes: S1: Encode the neural network parameters according to the standard POSIT data format and divide them according to the reference data block size; and, the division according to the reference data block size in S1 includes: When the dynamic dispersion of several consecutive connected reference data blocks is greater than the high dispersion superblock trigger threshold, the several reference data blocks are merged into a superblock, and each sub-unit in the superblock is set to the minimum reference data block size. S2: Calculate the dynamic dispersion of the mantissa of the neural network parameters within each baseline block, and dynamically adjust the data block size; and the dynamic dispersion is obtained in the following way: Obtain the variance and mean of the absolute values ​​of the mantissas of the neural network parameters; Get the logarithm of the number of neural network parameters within each data block; The dynamic dispersion is directly proportional to the variance and inversely proportional to the logarithm of the mean and the number of neural network parameters; S3: Based on the readjusted data block, extract the maximum exponent as the shared exponent, align the exponents of the remaining numbers to the shared exponent and shift the mantissa accordingly, and truncate the shifted mantissa: pad the low bits with 0 when the bit width is <6 bits, and retain the high 6 bits when the bit width is ≥6 bits, to generate improved POSIT data. S4: Store the improved POSIT data into the storage module that integrates storage and computing; S5: Obtain activation data, convert it into improved POSIT data using steps S1-S3, and perform multiply-accumulate operations through the storage array; S6: Encode the multiplication-accumulation result into the standard POSIT format for output. Furthermore, S2 dynamically adjusts the data block size, specifically including: If the dynamic dispersion is greater, it means that the tails of the neural network parameters in each reference block are more dispersed, so the data block size should be reduced. If the dynamic dispersion is smaller, it means that the tails of the neural network parameters within each reference block are more concentrated, so the data block size should be increased.

2. The processing method based on POSIT format according to claim 1, characterized in that, The extraction of the maximum index as the shared index in S3 specifically includes: Iterate through the Regime field and exponent field of all neural network parameters in each adjusted data block, and calculate the actual exponent value of each neural network parameter. The largest actual index value is selected as the shared index for a single adjusted data block.

3. The processing method based on POSIT format according to claim 1, characterized in that, The exponents of the remainders of S3 are aligned to the shared exponent and the mantissas are shifted accordingly, specifically including: For each neural network parameter, calculate the difference between the actual exponent and the shared exponent. ; like When the value is less than 0, the mantissa of the neural network parameters is shifted to the right. Bit; like If the value is greater than 0, then the mantissa of the neural network parameters is shifted to the left. Bit; If the mantissa exceeds 6 bits after shifting, rounding and overflow saturation are used.

4. The processing method based on POSIT format according to claim 1, characterized in that, The S5 process of performing multiply-accumulate operations via the storage array specifically includes: The in-memory array, based on two's complement representation, performs parallel multiplication operations on the activation data and weight parameters of the improved POSIT data, where: Each computing unit uses bit-level multiplication logic. Activation data is fed into the storage array via bit serialization, and the entire storage array performs in-situ multiplication operations synchronously. The results of in-place multiplication are added step by step through the adder tree to obtain the intermediate result of 6-bit mantissa multiplication; The intermediate results are accumulated in the form of fixed-point numbers, and the final accumulated result is output.

5. The processing method based on POSIT format according to claim 1, characterized in that, S6 includes: Based on the tails of the neural network parameters corresponding to the shared exponent and the accumulated result, the standard POSIT data, Regime domain, and exponent domain are reconstructed.

6. The processing method based on POSIT format according to claim 5, characterized in that, The reconstructed standard's POSIT data, Regime field, and index field specifically include: The Regime field is determined by the range of the sharing exponent: if the sharing exponent is positive, the Regime field ends with consecutive 0s; if it is negative, the Regime field ends with consecutive 1s, and its length is determined by the absolute value of the sharing exponent. The value of the exponent field is the shared exponent minus the offset corresponding to the Regime field; The mantissa of standard POSIT data is directly taken from the most significant bit of the accumulated result, with any insufficient bits padded with 0.

7. A POSIT-based in-memory processor, characterized in that, The in-memory processor includes: Parameter encoding and initial block unit: The neural network parameters are encoded according to the standard POSIT data format and divided according to the reference data block size; and the parameter encoding and initial block unit, divided according to the reference data block size, includes: When the dynamic dispersion of several consecutive connected reference data blocks is greater than the high dispersion superblock trigger threshold, the several reference data blocks are merged into a superblock, and each sub-unit in the superblock is set to the minimum reference data block size. Dynamic Discreteness Calculation and Block Size Adjustment Unit: Calculates the dynamic discreteness of the mantissa of the neural network parameters within each baseline block and dynamically adjusts the data block size; and the dynamic discreteness is obtained in the following manner: Obtain the variance and mean of the absolute values ​​of the mantissas of the neural network parameters; Get the logarithm of the number of neural network parameters within each data block; The dynamic dispersion is directly proportional to the variance and inversely proportional to the logarithm of the mean and the number of neural network parameters; Exponent Alignment and Mantissa Truncation Unit: Based on the readjusted data block, the maximum exponent is extracted as the shared exponent, the exponents of the remaining numbers are aligned to the shared exponent and the mantissas are shifted accordingly, and the shifted mantissas are truncated: when the bit width is < 6 bits, the low bits are padded with 0, and when the bit width is ≥ 6 bits, the high 6 bits are retained to generate improved POSIT data; In-memory computing storage unit: Stores the improved POSIT data into the in-memory computing storage module; Activate the data processing and multiply-accumulate operation unit: acquire the activation data, convert it into improved POSIT data using steps S1-S3, and perform multiply-accumulate operations through the storage array; The standard format reconstruction unit encodes the multiplication-accumulation result into the standard POSIT format for output. Furthermore, the dynamic discreteness calculation and block size adjustment unit dynamically adjusts the data block size, specifically including: If the dynamic dispersion is greater, it means that the tails of the neural network parameters in each reference block are more dispersed, so the data block size should be reduced. If the dynamic dispersion is smaller, it means that the tails of the neural network parameters within each reference block are more concentrated, so the data block size should be increased.

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