digital signal processor

Abstract

The application discloses a kind of digital signal processors, comprising: the 0th kernel to the L-1 kernel, L is greater than or equal to 2 positive integer, the 0th kernel is used to arrange order from big to small according to preset base and decompose to-be-calculated data, obtain at least one level to-be-calculated sub-data after decomposition, wherein, each level to-be-calculated sub-data corresponds to different preset base, the data point number of the i level to-be-calculated sub-data is the integer power of its corresponding preset base, i is less than or equal to the positive integer, and it is the maximum level number of to-be-calculated sub-data;The 2nd kernel to the L-1 kernel is based on the preset base corresponding to to-be-calculated sub-data, and the fast Fourier transform calculation is carried out to to-be-calculated sub-data, to obtain the Fourier transform result of to-be-calculated data.The application has good applicability, and the calculation efficiency is higher.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology, and specifically relates to a digital signal processor. Background Technology

[0002] In radar signal processing systems, the Fast Fourier Transform (FFT) plays a core role in several key aspects of radar imaging. Both range and azimuth processing require converting signals to the frequency domain using FFT. Therefore, the speed of FFT processing is a crucial factor determining the performance of the signal processing unit.

[0003] With the development of digital electronics and large-scale integrated circuits, the computing power of various embedded signal processing chips is constantly improving. These chips mainly include Digital Signal Processors (DSPs), Field-Programmable Gate Arrays (FPGAs), and Graphics Processing Units (GPUs). GPUs have strong floating-point computing power, but their application areas are limited due to their large power consumption and size. FPGAs have abundant logic resources and can perform large-scale parallel computing of radar signal processing algorithms, but they are usually used for signal preprocessing, interface forwarding, and logic control. DSPs are widely used in Fourier transform processing due to their low power consumption and high computing power.

[0004] Currently, radix-2 and radix-4 FFTs are the mainstream in engineering applications. However, traditional radix-2 algorithms involve many multiplication operations and are time-consuming, while radix-4 algorithms require the signal length to be a power of 4 (e.g., 64, 256). Otherwise, zero-padding or truncation is needed to adjust the length, which introduces computational redundancy or signal distortion. Furthermore, the smaller the radix, the more times the data is split and the more frequent the synchronization, resulting in higher inter-core communication overhead and impacting the efficiency of multi-core computing. Summary of the Invention

[0005] This invention provides a digital signal processor that can solve the above-mentioned technical problems.

[0006] The digital signal processor provided in this embodiment of the invention includes: a 0th core to a (L-1)th core, where L is a positive integer greater than or equal to 2;

[0007] The 0th kernel is used to decompose the data to be calculated according to a preset base number from largest to smallest, to obtain at least one level of sub-data to be calculated; and to send the sub-data to be calculated to the second to L-1th kernels; wherein each level of sub-data to be calculated corresponds to a different preset base number, and the number of data points of the i-th level sub-data to be calculated is... For its corresponding preset base an integer power, where i is less than or equal to positive integers, The maximum level of the sub-data to be calculated is the radar echo signal;

[0008] The second to L-1 kernels are used to perform fast Fourier transform calculations on the sub-data to be calculated based on the preset cardinality corresponding to the sub-data to be calculated;

[0009] The 0th kernel is also used to read and integrate the Fourier transform results of the data to be calculated.

[0010] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: According to the digital signal processor provided by the present invention, by using multiple preset radixes to perform mixed-radix processing on the data to be calculated, higher-order radixes are preferentially used for Fourier transform, and the remaining data are then processed using smaller radixes; the butterfly unit corresponding to the higher-order radix can reduce the number of complex multiplication operations, thereby avoiding the computational redundancy and signal distortion problems caused by filling the remaining data with 0 when only higher-order radixes are used. At the same time, it can reduce the number of data partitioning and synchronization frequency, and improve computational efficiency. Attached Figure Description

[0011] Figure 1 A flowchart illustrating the implementation of a fast Fourier transform method based on DSP hybrid bases provided in this embodiment of the invention;

[0012] Figure 2 This is a schematic diagram of a scenario for performing a Fourier transform operation, provided as an embodiment of the present invention.

[0013] Figure 3 This is a pseudocode diagram illustrating the process of reordering Fourier transform results, provided as an embodiment of the present invention.

[0014] Figure 4 This is a schematic diagram of a DSP structure provided in an embodiment of the present invention. Detailed Implementation

[0015] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0016] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0017] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0018] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0019] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] The fast Fourier transform method based on DSP hybrid basis provided in this embodiment of the invention can be applied to DSPs, and this embodiment of the invention does not impose any restrictions on the specific model of the DSP.

[0023] Figure 1The diagram shown illustrates an implementation flowchart of a fast Fourier transform method based on a DSP hybrid basis, provided by an embodiment of the present invention. As an example and not a limitation, the method may include steps S101-S102, which are described below.

[0024] S101, decompose the data to be calculated according to the preset base number from largest to smallest, and obtain at least one level of sub-data to be calculated after decomposition.

[0025] For example, the data to be calculated can be radar echo signals.

[0026] In some embodiments, the data to be calculated can be decomposed according to a preset base from largest to smallest. The data to be calculated is decomposed into Level of sub-data to be calculated. It can be equal to the product of the number of data points in each sub-data set to be calculated, i.e. The i-th level sub-data to be computed can have Point data.

[0027] For example, the number of data points of the i-th level sub-data to be calculated It can be set to its corresponding preset base. Integer powers. For example, , It is an integer.

[0028] Optionally, The number of remaining data points in level i The largest integer power of N. The number of remaining data points in the i-th level can be the difference between N and the sum of the number of data points in the sub-data of the first i-1 levels, that is, the number of remaining data points in the i-th level is equal to N. .

[0029] For example, if N=2048, with the default bases being 8 and 2, it can be decomposed into: , , If according to To perform data decomposition, 3+2 data splits are required. If we follow... Data decomposition requires 2+5 data splits. To reduce the frequency of data synchronization and the number of data splits during FFT operations, the data can be divided into larger cardinality groups. .

[0030] In one possible implementation, since the number of range or azimuth points to be processed in a radar signal processing system is generally a power of 2, commonly used numbers are 1024, 2048, 4096 and 8192, the preset base number can include at least two of the following: 16, 8, 4, 2.

[0031] In one example, the data to be calculated can be divided into two levels of sub-data. In this case, 8 and 2 can be used as preset bases for mixed base operations.

[0032] S102, based on the preset cardinality corresponding to the sub-data to be calculated, perform fast Fourier transform calculation on the sub-data to be calculated to obtain the Fourier transform result of the data to be calculated.

[0033] In some embodiments, for the i-th level sub-data to be computed, a preset base can be used. Perform a discrete Fourier transform on the data to obtain the Fourier transform result of the sub-data at this level; finally, integrate the Fourier transform results of all sub-data to be calculated to obtain the Fourier transform result of the data to be calculated.

[0034] For example, the FFT can reduce the computational complexity of the Discrete Fourier Transform (DFT) from... Reduce to .

[0035] In one possible implementation, if there are two levels of sub-data to be computed, the mixed-basis FFT operation can be performed first. Point DFT calculation, and the results are compared with Multiply, then proceed. The point-wise DFT operation yields the Fourier transform result for each point.

[0036] For example, the Fourier transform result of each point of the data to be calculated can satisfy the following formula:

[0037]

[0038] in, For the data to be calculated Point Fourier transform result, It is the rotation factor, and , , , All are integers. , .

[0039] In one example, if the preset cardinality corresponding to the i-th level sub-data to be calculated is 2, the i-th level sub-data to be calculated can be bisected successively until each group of data after decomposition includes 2 data points. Then, DFT is performed on each group of 2 data points and the data is merged level by level to finally obtain the Fourier transform result of the i-th level sub-data to be calculated.

[0040] For example, the process of performing a Fourier transform on the sub-data to be calculated corresponding to 2 can be represented as:

[0041]

[0042] in, From 0 to positive integers, For the i-th level sub-data to be calculated, the first... Fourier transform results of point data For rotation factor, For the i-th level sub-data to be calculated, the first... The value of the point data.

[0043] Specifically, , It can be equal to , , .

[0044] Therefore, the Fourier transform result of each point of the sub-data to be calculated corresponding to 2 can satisfy the following formula:

[0045] .

[0046] Can be made separately Or let Perform a Fourier transform based on the following formula:

[0047]

[0048] in, ,

[0049] In one example, similarly, if the preset cardinality corresponding to the i-th level sub-data to be calculated is 4, the i-th level sub-data to be calculated can be divided into four parts successively until each group of data after decomposition includes 4 data points. Then, DFT is performed on each group of 4 data points and the data is merged level by level to finally obtain the Fourier transform result of the i-th level sub-data to be calculated.

[0050] For example, we can make them separately , , Or let The DFT of each group of 4 data points is performed using the following formula:

[0051]

[0052] in, The calculation method for the rotation factor is the same as in the above embodiments, except that... The values ​​can be different.

[0053] In one example, similarly, if the preset cardinality corresponding to the i-th level sub-data to be calculated is 8, the i-th level sub-data to be calculated can be divided into 8 parts successively until each group of data after decomposition includes 8 data points. Then, DFT is performed on each group of 8 data points and the data is merged level by level to finally obtain the Fourier transform result of the i-th level sub-data to be calculated.

[0054] For example, see Figure 2 For each group of 8 data points, after obtaining the value of each data point within the group, the rotation factor can be calculated according to the direction of the arrows in the figure, and multiplied with the calculated rotation factor to obtain the corresponding 8-point Fourier transform result.

[0055] According to the method provided by the present invention, by using multiple preset radixes to perform mixed-radix processing on the data to be calculated, higher-order radixes are preferentially used for Fourier transform, and the remaining data are then processed using smaller radixes. The butterfly unit corresponding to the higher-order radix can reduce the number of complex multiplication operations, thereby avoiding the computational redundancy and signal distortion problems caused by filling the remaining data with 0 when only using higher-order radixes. At the same time, it can reduce the number of data partitioning and synchronization frequency, and improve computational efficiency.

[0056] In some embodiments, the data to be computed and its Fourier transform results can be data sequences with the same number of points but in a different order. After the mixed-basis FFT operation, the output order of the computation results is shuffled, resulting in a disordered sequence of Fourier transform results for the data to be computed. The order of the Fourier transform results for the data to be computed can be integrated to determine their correspondence with the input data to be computed.

[0057] In one possible implementation, if the data to be computed is divided into two levels of sub-data to be computed, then the first sub-data in the output sequence... Point data can be the first The Fourier transform result of the data to be calculated, the first The data to be calculated and the first The point Fourier transform results correspond to this.

[0058] For example, if satisfy: Then its corresponding By adjusting the coefficients The result is obtained by performing the reverse operation. .

[0059] Specifically, The decomposition coefficients are... to It can be in Positive integers between to It can be in Positive integers between [a certain range].

[0060] For example, see Figure 3 The pseudocode shown assumes a preset base of 8 or 2. , , , , Then the input of the first A data to be computed can be represented by the following mixed 5-tuple:

[0061]

[0062] in, to In order to be in Positive integers between , In order to be in Positive integers between [a certain range].

[0063] right After performing reverse calculations on the mixed 5-tuple, we can obtain the calculated first tuple. Index of point Fourier transform results .

[0064] In one example, if for For positive integers in the range, the factorization coefficients can be calculated using the following formula:

[0065]

[0066] in, The number of data points to be calculated;

[0067] like for For positive integers in the range, the factorization coefficients can be calculated using the following formula:

[0068] .

[0069] For example, if , , , , , ,but Its inverse quintuple is Calculations yielded Therefore, the first The data to be calculated corresponds to the first Point Fourier transform result.

[0070] Figure 4 The diagram shown is a schematic representation of a DSP provided in an embodiment of the present invention. By way of example and not limitation, the DSP may include at least three cores, namely core 0 to core L-1, denoted as core 0 to core L-1 respectively.

[0071] In one possible implementation, kernel 0 can act as the master controller, used to decompose the data to be calculated in descending order of a preset cardinality, obtaining at least one level of sub-data to be calculated. Kernels 1 to L-1 can perform Fast Fourier Transform calculations on the sub-data to be calculated based on the preset cardinality corresponding to the sub-data to be calculated; kernel 0 can also synchronize the calculation results of kernels 1 to L-1 to obtain the Fourier Transform result of the data to be calculated.

[0072] For example, the DSP can be an 8-core fixed-point / floating-point high-performance DSP chip. Internally, it can use the SIMD instruction set, employing instructions such as CMPYSP and DOTP4SP.

[0073] Optionally, in addition to decomposing data, core 0 can also perform data input / output, task distribution and other operations to prevent the computing cores (cores 1-7) from being blocked by I / O tasks and ensure the continuity of data flow.

[0074] In one example, if the data to be calculated is divided into two levels of sub-data, cores 1-6 can be used to process the first level of sub-data, and core 7 can be used to process the second level of sub-data.

[0075] For example, if the preset radix includes 8 and 2, after the operation begins, core 0 can use L2 static random-access memory (SRAM) to move each group of 8 data points from DDR to cores 1-6, and each group of 2 data points from DDR to core 7. Cores 1-6 then begin radix-8 butterfly operations. After cores 1-6 finish processing, they raise the semaphore, and core 7 begins mantissa processing. Since the remaining radix-2 operation data is relatively small, single-core processing is sufficient.

[0076] In one possible implementation, the DSP can pre-calculate and store the possible rotation factors according to a preset base.

[0077] For example, a larger preset cardinality (e.g., 8) uses more rotation factors during calculation and can be stored in stages after pre-generation. A smaller preset cardinality (e.g., 2) uses fewer rotation factors during calculation and can be obtained through faster calculation.

[0078] In one example, the pre-generated rotation factor can be stored in L2SRAM in single-precision floating-point format and layered according to the FFT decomposition levels, with each layer including... One rotation factor.

[0079] For example, each set of twiddle factors can be packaged into four consecutive complex numbers, and a 256-bit data block can be loaded using the _amem8_f4 instruction during loading. The CMPYSP instruction can then be used to implement four-way parallel complex multiplication and addition. A double-buffered DMA strategy is also employed, using EDMA to prefetch the twiddle factors of the next level while calculating the current level.

[0080] According to the DSP provided by the present invention, by using multiple preset radixes to perform mixed-radix processing on the data to be calculated, higher-order radixes are preferentially used for Fourier transform, and the remaining data are then processed using smaller radixes. The butterfly unit corresponding to the higher-order radix can reduce the number of complex multiplication operations, thereby avoiding the computational redundancy and signal distortion problems caused by filling the remaining data with 0 when only using higher-order radixes. At the same time, it can reduce the number of data partitioning and synchronization frequency, and improve computational efficiency.

[0081] To better illustrate the beneficial effects of the present invention, the following simulation experiments were conducted:

[0082] For example, the preset base can be set to 8 and 2, and combined with optimization methods such as dual DMA buffer strategy and SIMD operation, and combined with the multi-core parallel hardware characteristics of C6678, simulation experiments can be carried out on TI's TMS320C6678 processor, and the correctness can be verified on the MATLAB platform.

[0083] For example, in order to verify the beneficial effects of the present invention, respectively in When the values ​​are 1024, 2048, 4096, and 8192, the present invention is compared with the TI official DSPF_sp_fftSPxSP (single core), and the experimental results are shown in Table 1 below.

[0084] Table 1. Performance of algorithms with different point counts (unit: ns)

[0085]

[0086] As shown in Table 1, compared with calling TI's official functions with a single core, the present invention can effectively reduce FFT processing time and improve computational efficiency.

[0087] Therefore, the method provided by this invention can significantly reduce computational complexity while ensuring the general applicability of sequence length through an adaptive factorization strategy. It adopts a phased hybrid radix architecture, that is, it performs high-order radix decomposition in the main calculation stage to compress the amount of computation, while for the remaining data segments that cannot be completely matched with high-order radix, it switches to low-order radix to complete the tail calculation. This hierarchical processing mechanism avoids the operational redundancy caused by the step-by-step iteration of low-order radix and overcomes the rigid constraint of pure high-order radix on sequence length, thereby achieving Pareto optimality between computational efficiency and flexibility.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

Claims

1. A digital signal processor, characterized in that, include: The 0th kernel to the (L-1)th kernel, where L is a positive integer greater than or equal to 2; The 0th kernel is used to decompose the data to be calculated according to a preset base number from largest to smallest, to obtain at least one level of sub-data to be calculated; and to send the sub-data to be calculated to the second to L-1th kernels; wherein each level of sub-data to be calculated corresponds to a different preset base number, and the number of data points of the i-th level sub-data to be calculated is... For its corresponding preset base an integer power, where i is less than or equal to positive integers, The maximum level of the sub-data to be calculated is the radar echo signal; The second to L-1 kernels are used to perform fast Fourier transform calculations on the sub-data to be calculated based on the preset cardinality corresponding to the sub-data to be calculated; The 0th kernel is also used to read and integrate the Fourier transform results of the data to be calculated.

2. The digital signal processor according to claim 1, characterized in that, The number of data points N of the data to be calculated is equal to the number of data points of each level of sub-data to be calculated. The product of , The number of remaining data points in level i The largest integer power of N, where the number of remaining data points in the i-th level is equal to the difference between N and the sum of the number of data points in the sub-data to be calculated in the first i-1 levels.

3. The digital signal processor according to claim 1, characterized in that, The preset base number includes at least two of the following: 16, 8, 4, and 2.

4. The digital signal processor according to claim 3, characterized in that, The data to be calculated is divided into two levels of sub-data to be calculated.

5. The digital signal processor according to claim 4, characterized in that, The preset base number for the first-level sub-data to be calculated is 8, and the preset base number for the second-level sub-data to be calculated is 2.

6. The digital signal processor according to claim 4, characterized in that, The Fourier transform result satisfies the following formula: in, For the data to be calculated Point Fourier transform result, It is the rotation factor, and , , , All are integers. , .

7. The digital signal processor according to claim 4, characterized in that, The data to be calculated and its Fourier transform result are data sequences with the same number of points, the first... The point to be calculated data is used to calculate the first point of the data to be calculated. Point Fourier transform result; Among them, if ,but , The decomposition coefficients are... to In order to be in Positive integers between to In order to be in Positive integers between [a certain range].

8. The digital signal processor according to claim 7, characterized in that, like for The positive integers between the given values ​​satisfy the following formula: in, The number of data points to be calculated; like for The positive integers between the given values ​​satisfy the following formula: 。

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