Multifunctional motor coding system and method, medium, program product and terminal

Abstract

The invention provides a multifunctional motor coding system and method, a medium, a program product and a terminal, and the method comprises the steps: obtaining an original angle signal through an input buffer unit, and transmitting the signal to a line number modulation unit when the calculation is idle; and flexible line number modulation is performed on the original angle signal according to a plurality of coding parameters through a multiplication and addition calculation module of the line number modulation unit, so that a plurality of high-precision analog signals are generated. The coding unit can carry out personalized coding on the analog signal according to different system bus parameters, such as an output mode, system configuration and a modulation period, and outputs a matched coded signal. According to the motor encoder, the diversity and the integration level of the motor encoder are remarkably improved, the complexity of various encoding circuits is effectively reduced through the shared computing unit, and the chip area is optimized. Compared with a traditional scheme, the circuit cost is greatly reduced while high precision is kept, and the operation efficiency is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a multifunctional motor encoding system, method, medium, program product and terminal. Background Art

[0002] Currently, a common solution to the problem of supporting multiple encoding types in motor encoders is to implement the encoding function using dedicated chips. Existing technologies typically design dedicated circuits for specific encoding types, using optical, magnetic, or inductive sensing methods to detect changes in the motor rotor's position. The chip then performs signal processing and encoding conversion. These dedicated chips can stably implement encoding functions, but generally only support a limited range of encoding formats. For example, some chips use optical detection to implement incremental encoding, which can accurately measure rotor angles, but lack flexible support for multiple encoding types.

[0003] Therefore, existing technologies have significant shortcomings in their compatibility with multiple encoding types. Dedicated circuits typically only support a few encoding types. Supporting more types requires designing multiple chips, which increases circuit area and costs. Existing solutions struggle to balance multi-encoding support with cost-effectiveness, especially in applications with strict size and cost requirements. Furthermore, the limited versatility of dedicated chips restricts the application and expansion of encoders in complex environments. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a multifunctional motor encoding system, method, medium, program product and terminal to solve the problem that existing chips have poor compatibility in supporting multiple encoding types, resulting in large circuit area, high cost and insufficient versatility, making it difficult to meet the needs of diversified and highly integrated applications.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a multifunctional motor encoding system, including: an input cache unit, which is communicatively connected to a position management system and a line number modulation unit respectively; used to receive an original angle signal from the position management system and a calculation idle indication signal from the line number modulation unit; the input cache unit caches the original angle signal, and when the calculation idle indication signal is valid, sends the cached angle signal to be calculated to the line number modulation unit; the line number modulation unit includes a multiplication calculation module and an addition calculation module; the line number modulation unit is communicatively connected to a first encoding unit, a second encoding unit and a third encoding unit respectively; used to receive a first encoding parameter, a second encoding parameter and / or a third encoding parameter, and perform a line number modulation operation on the original angle signal according to the first encoding parameter and / or the second encoding parameter and / or the third encoding parameter through a multiplication calculation module and an addition calculation module; wherein, when the first encoding parameter is used, a first analog signal, generating a second analog signal when the second encoding parameter is used, and generating a third analog signal when the third encoding parameter is used; a first encoding unit, the first encoding unit is communicatively connected to the system bus, and is used to receive the first analog signal from the line number modulation unit, and receive an output mode from the system bus; based on the output mode, encode the first analog signal to generate a first encoded signal; a second encoding unit, the second encoding unit is communicatively connected to the system bus, and is used to receive the second analog signal from the line number modulation unit, and receive a system configuration parameter from the system bus; based on the system configuration parameter, encode the second analog signal to generate a second encoded signal; a third encoding unit, the third encoding unit is communicatively connected to the system bus, and is used to receive the third analog signal from the line number modulation unit, and receive a modulation period parameter from the system bus; based on the modulation period parameter, encode the third analog signal to generate a third encoded signal.

[0006] In some embodiments of the first aspect of the present application, the line number modulation unit performs a line number modulation operation on the received first coding parameter to generate a first analog signal, and / or performs a line number modulation operation on the second coding parameter to generate a second analog signal, and / or performs a line number modulation operation on the third coding parameter to generate a third analog signal through a multiplication calculation module and an addition calculation module. The process includes: the line number modulation unit receives a coding mode control signal, and the coding mode control signal indicates to perform a line number modulation operation on one or more original angle signals of the first coding parameter, the second coding parameter, and the third coding parameter; when the line number modulation unit receives a valid original angle signal, the angle input signal is latched; within the current clock cycle, the angle offset is added to the original angle signal according to the first coding parameter and / or the second coding parameter and / or the third coding parameter through the addition calculation module to generate an addition result; the addition result is multiplied by the corresponding resolution parameter through the multiplication calculation module to generate a multiplication result, and the multiplication result is delayed to the next clock cycle for output through a latch; a preset number of bits is extracted from the multiplication result to generate a corresponding analog signal.

[0007] In some embodiments of the first aspect of the present application, the first coding signal includes an A-phase remodulation value, an A-phase valid flag signal, a B-phase remodulation value, a B-phase valid flag signal, a C-phase remodulation value, and a C-phase valid flag signal; the first coding unit encodes the first analog signal based on the output mode to generate a first coding signal. The process includes: performing the following steps when any one of the A-phase valid flag signal, the B-phase valid flag signal, and the C-phase valid flag signal is valid: when the output mode is a sinusoidal mode, calculating the sine value of the A-phase remodulation value to generate an A-phase coding value, calculating the sine value of the B-phase remodulation value to generate a B-phase coding value, and calculating the sine value of the C-phase remodulation value to generate a into a C-phase encoding value; when the output mode is a cosine mode, the cosine value of the A-phase remodulation value is calculated to generate an A-phase encoding value, the cosine value of the B-phase remodulation value is calculated to generate a B-phase encoding value, and the cosine value of the C-phase remodulation value is calculated to generate a C-phase encoding value; when the output mode is a sinusoidal full-wave rectification mode, the sine absolute value of the A-phase remodulation value is calculated to generate an A-phase encoding value, the sine absolute value of the B-phase remodulation value is calculated to generate a B-phase encoding value, and the sine absolute value of the C-phase remodulation value is calculated to generate a C-phase encoding value; when the output mode is a direct encoding mode, the A-phase remodulation value is output as the A-phase encoding value, the B-phase remodulation value is output as the B-phase encoding value, and the C-phase remodulation value is output as the C-phase encoding value.

[0008] In some embodiments of the first aspect of the present application, the second analog signal includes an ABZ valid flag signal and ABZ position information; the system configuration parameters include an ABZ bit width, an ABZ initial angle value, and an ABZ zero position reference value; the second encoding unit performs ABZ incremental encoding on the second analog signal based on the system configuration parameters to generate a second encoded signal. The process includes: when the ABZ valid flag signal is valid, in each system clock cycle corresponding to the ABZ bit width, performing the following steps: inverting the lowest bit data of the ABZ position information, and An A-phase incremental signal is output according to the inversion result; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low; an exclusive-OR operation is performed on the lowest two bits of the ABZ position information, and a B-phase incremental signal is output according to the operation result; if the levels of the lowest two bits are consistent, the output B-phase incremental signal is low; otherwise, the output B-phase incremental signal is high; if all bit data of the ABZ position information are consistent with the ABZ zero position reference value, the output Z-phase incremental signal is high; otherwise, the output Z-phase incremental signal is low.

[0009] In some embodiments of the first aspect of the present application, the third analog signal includes a PWM valid flag signal and PWM position information; based on the modulation cycle parameter, the third analog signal is encoded to generate a third encoded signal. The process includes: when the PWM valid flag signal is valid, the reverse PWM encoded signal of the forward PWM encoded signal is calculated according to the PWM position information and the modulation cycle parameter.

[0010] In some embodiments of the first aspect of the present application, the input cache unit includes multiple caches; the input cache unit also receives an angle update hysteresis threshold value, and the process of caching the original angle signal includes: when the input cache unit calculates the absolute difference between the original angle information received at the current moment and the original angle information last stored in the cache; if the absolute difference is greater than or equal to the angle update hysteresis threshold value, the original angle information received at the current moment is stored in the cache in a first-in-first-out manner; otherwise, the original angle information received at the current moment is discarded, and the original angle information at the next moment is continued to be received.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a multifunctional motor encoding method, which is applied to an encoder, and the method includes: receiving an original angle signal and a calculated idle indication signal; caching the original angle signal, and when the calculated idle indication signal is valid, receiving a first encoding parameter, a second encoding parameter and / or a third encoding parameter, and performing a line number modulation operation on the original angle signal according to the first encoding parameter and / or the second encoding parameter and / or the third encoding parameter; wherein, when the first encoding parameter is used, a first analog signal is generated, when the second encoding parameter is used, a second analog signal is generated, and when the third encoding parameter is used, a third analog signal is generated. analog signal; the process of generating a first analog signal when using the first coding parameter includes: receiving the first analog signal and an output mode; encoding the first analog signal based on the output mode to generate a first coded signal; the process of generating a second analog signal when using the second coding parameter includes: receiving the second analog signal and a system configuration parameter; encoding the second analog signal based on the system configuration parameter to generate a second coded signal; the process of generating a third analog signal when using the third coding parameter includes: receiving the third analog signal and a modulation period parameter; encoding the third analog signal based on the modulation period parameter to generate a third coded signal.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the multifunctional motor encoding method when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code is run on a computer, the computer implements the multifunctional motor encoding method.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the multifunctional motor encoding method.

[0015] As described above, the multifunctional motor encoding system, method, medium, program product and terminal of the present application have the following beneficial effects: the original angle signal is obtained through the input buffer unit, and the signal is transmitted to the line number modulation unit when the calculation is idle. Through the multiplication and addition calculation modules of the line number modulation unit, the original angle signal is flexibly modulated according to multiple encoding parameters to generate multiple high-precision analog signals. The encoding unit can personalize the analog signal according to different system bus parameters, such as output mode, system configuration and modulation period, and output a matching encoding signal. The present application significantly improves the diversity and integration of motor encoders, and effectively reduces the complexity of various encoding circuits by sharing the computing unit, thereby optimizing the chip area. Compared with traditional solutions, while maintaining high precision, the circuit cost is greatly reduced and the operating efficiency is significantly improved. Its outstanding technical advantages give it extremely broad application prospects in the fields of industrial automation, precision control, robotic systems, etc., and it represents an important innovation direction for motor encoding technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an embodiment of the multifunctional motor encoding system of the present application is shown.

[0017] Figure 2 A schematic diagram of the structure of the input buffer unit in one embodiment of the multifunctional motor encoding system of the present application is shown.

[0018] Figure 3 A schematic diagram of the structure of the line number modulation unit in one embodiment of the multifunctional motor encoding system of the present application is shown.

[0019] Figure 4 A schematic diagram of the structures of various encoding units in an embodiment of the multifunctional motor encoding system of the present application is shown.

[0020] Figure 5 A structural diagram of an embodiment of the multifunctional motor encoding method of the present application is shown.

[0021] Figure 6 A structural diagram of an embodiment of a multifunctional motor encoding terminal of the present application is shown. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0023] Before further explaining the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations:

[0024] <1> Sine wave encoding: A coding method based on sine and cosine wave signals, which is decoded by the phase and amplitude relationship to obtain angle or position information.

[0025] <2> ABZ incremental encoder: Outputs two pulse signals A and B with a phase difference of 90° to determine the rotation direction and incremental position, as well as a zero position reference signal of one pulse per revolution on the Z path.

[0026] <3> PWM encoding: An encoding method that transmits information by changing the width of a pulse signal, often used to adjust motor speed or power.

[0027] <4> Position management system: A system used to detect, control, and manage the location of objects, including components such as sensors, controllers, and actuators.

[0028] <5> Electrical angle: Indicates the angular relationship between the current or voltage phase in the motor winding and the motor's rotational position, used for motor control.

[0029] <6> Mechanical angle: The physical angle through which an object actually rotates or moves, usually measured in degrees.

[0030] <7> Three-phase quadrature output: Outputs three signals with a phase difference of 120°. This is commonly used for motor drive or position measurement to ensure that the signals are independent and evenly distributed.

[0031] <8> ABZ zero reference value: The position of one pulse of the Z signal per revolution in an ABZ encoder, used to determine the starting point of rotation or the absolute position reference.

[0032] To facilitate understanding of the embodiments of this application, first Figure 1 Detailed description. Figure 1 The following is a flow chart of a multifunctional motor encoding system 100 according to an embodiment of the present invention. The multifunctional motor encoding system 100 in this embodiment mainly includes an input buffer unit 101, a line number modulation unit 102, a first encoding unit 103, a second encoding unit 104, and a third encoding unit 105:

[0033] An input buffer unit 101 is communicatively connected to the position management system and the line number modulation unit respectively; it is used to receive the original angle signal from the position management system and the calculation idle indication signal from the line number modulation unit; the input buffer unit caches the original angle signal, and when the calculation idle indication signal is valid, sends the cached angle signal to be calculated to the line number modulation unit.

[0034] In one embodiment of the present application, the input buffer unit obtains the electrical angle or mechanical angle from the position management system of the microcontroller. This angle represents the position of the motor movement. The electrical angle in the motor rotational motion is periodically changing information. The present application creatively converts the input electrical signal of the same multi-bit digital signal into a sine wave encoding output, an incremental digital pulse (ABZ) output, and a PWM control output. These three types of encoding outputs share the input preprocessing module and time-share multiplex the computing unit, thereby saving hardware overhead and cost.

[0035] In one embodiment of the present application, the input cache unit communicates data with the position management system and the line number modulation unit. The input cache unit receives the original angle signal from the position management system and receives the calculation idle indication signal from the line number modulation unit. The input cache unit performs a cache operation on the received original angle signal. When the calculation idle indication signal is in a valid state, the input cache unit sends the cached angle signal to be calculated to the line number modulation unit. When the input cache unit is specifically implemented, its input end includes: a system bus, which carries a system working clock signal and a reset signal; an angle signal from the position management system, the bit width of the angle signal is n+1 bits, denoted as angle[n:0]; an angle signal valid indication signal angle_valid from the position management system; and a calculation idle indication signal cal_idle from the line number modulation unit.

[0036] The input buffer unit also receives configuration parameters, such as the angle update hysteresis threshold value angle_filter, which also has a bit width of n+1 bits. The output signals of the input buffer unit include: the angle signal to be calculated, angle_cal, which has a bit width of n+1 bits; and the angle calculation enable pulse signal cal_valid. The input buffer unit caches the input angle signal and outputs the angle signal to be calculated and the enable signal when calculation conditions are met.

[0037] In one embodiment of the present application, the input cache unit includes multiple caches; the input cache unit also receives an angle update hysteresis threshold value, and the process of caching the original angle signal includes: when the input cache unit calculates the absolute difference between the original angle information received at the current moment and the original angle information last stored in the cache; if the absolute difference is greater than or equal to the angle update hysteresis threshold value, the original angle information received at the current moment is stored in the cache in a first-in-first-out manner; otherwise, the original angle information received at the current moment is discarded, and the original angle information at the next moment is continued to be received.

[0038] In this embodiment, the input buffer unit includes multiple buffers and is used to receive an angle update hysteresis threshold value to cache the raw angle signal. The caching process includes: first, calculating the absolute difference between the raw angle information received at the current moment and the last piece of raw angle information stored in the buffer. When this difference is greater than or equal to the set angle update hysteresis threshold value, the raw angle information at the current moment is stored in the buffer on a first-in, first-out basis. If the difference is less than the threshold value, the raw angle information received at this moment is discarded, and the raw angle signal at the next moment is received. This mechanism ensures that only angle signals with significant changes are stored.

[0039] In this embodiment, the input buffer unit has x built-in data buffers, labeled BUF(1), BUF(2), ..., BUF(x). Each buffer can store n+1 bits of binary data. When the system bus (system_bus) is reset, the angle information stored in all data buffers is cleared, and the index to be output, BUF_INDEX, is initialized to 0. After the system reset is released and the operating clock is started, the input buffer unit begins normal operation.

[0040] For each operation cycle, if the angle signal valid indication signal (angle_valid) of the position management system is in a valid state, the input buffer unit calculates the absolute difference between the unsigned binary value of the current input angle signal angle[n:0] and the value in BUF(1). If the calculation result shows that the absolute difference between the two is less than the unsigned binary value of the corresponding angle_filter[n:0], the current input angle signal is discarded; otherwise, in the next clock cycle, the content of BUF(x) is updated to the value of BUF(x-1) in the current cycle, and so on, until BUF(1) is updated to the current input angle signal. The output index BUF_INDEX is incremented by 1 in sequence, and the value of BUF_INDEX is 0, 1, 2, and so on until x.

[0041] In the p+1th clock cycle, if the calculation idle indication signal (cal_idle) from the line number modulation unit is a valid signal and BUF_INDEX is not 0, an angle calculation enable pulse signal (cal_valid) lasting one clock cycle is generated, and the value in the data buffer pointed to by BUF_INDEX is output to angle_cal[n:0] of the line number modulation unit. After the operation, the value of BUF_INDEX will be subtracted by 1. In the same clock cycle, BUF_INDEX can be added by 1 and subtracted by 1 at the same time, thereby keeping its value unchanged. When the result of BUF_INDEX is equal to x in the pth clock cycle, the output state of the input buffer unit (BUF_FULL) becomes valid, thereby triggering an interrupt of the system processor to notify that the current input buffer is full. This means that the angle signal update frequency of the position management system exceeds the rate accepted by the present invention. In this case, the old angle information will be replaced by the new angle information, ensuring that the input buffer always stores the latest x sets of valid input angle information to ensure the real-time performance and accuracy of the system.

[0042] The line number modulation unit 102 includes a multiplication calculation module and an addition calculation module; the line number modulation unit is communicatively connected to the first coding unit, the second coding unit and the third coding unit respectively; it is used to receive the first coding parameter, the second coding parameter and / or the third coding parameter, and perform a line number modulation operation on the original angle signal according to the first coding parameter and / or the second coding parameter and / or the third coding parameter through the multiplication calculation module and the addition calculation module; wherein, when the first coding parameter is used, a first analog signal is generated, when the second coding parameter is used, a second analog signal is generated, and when the third coding parameter is used, a third analog signal is generated.

[0043] In this embodiment, the line number modulation unit includes angle offset and line number conversion. The input signals of the line number modulation unit include: 1.) the original angle signal (angle_cal[n:0]) includes n+1 bits of effective digits, indicating the electrical angle or mechanical angle; 2.) the angle_valid signal is used to indicate the validity of the input value, and the validity of the current input angle_cal[n:0] is defined by a high or low level state; 3.) the angle difference angle_shift_a[n:0] / angle_shift_b[n:0] / angle_shift_c[n:0] superimposed by the three groups of output signals ana_a[n:0] / ana_b[n:0] / ana_c[n:0] of the sine wave encoding, the effective digits are n+1 bits, and the angle difference can be configured as a parameter. For example, when the three groups of sine wave encoding outputs are desired to be three-phase orthogonal outputs, that is, the angle difference is 120°, the angle_shift_a[n:0] can be configured to be 0; the angle_shift_b can be configured to be (2 n+1 / 3)*2; angle_shift_c is 2 n+1 / 3, at this time, phase a ana_a[n:0] leads phase b ana_b[n:0] by 120°, and phase b ana_b[n:0] leads phase c ana_c[n:0] by 120°.

[0044] In addition, the signal input to the line number modulation unit also includes: 4.) the additional angle difference output by the ABZ incremental encoding (angle_shift_abz[n:0]), whose effective number of bits is n+1 bits and is a system-configurable parameter; 5.) the additional angle difference of the PWM control encoding (angle_shift_pwm[n:0]), whose effective number of bits is n+1 bits and is a system-configurable parameter. In order to achieve the flexibility of the line number, the signal input to the line number modulation unit also includes multiple re-modulation line number parameters, which include resolution_ana_a[k:0], resolution_ana_b[k:0], resolution_ana_c[k:0], resolution_abz[k:0] and resolution_pwm[k:0], whose effective number of bits is k+1 and corresponds to the line number configuration within the physical rotation cycle of the motor. The line number refers to the number of cycles of electrical angles or mechanical angles in a physical rotation cycle of a motor, and the effective number of bits is k+1, corresponding to the maximum configurable number of lines in the input modulation system of 2 k+1 -1, the remodulation line number parameter is also a system configurable parameter.

[0045] At the same time, the line number modulation unit also receives input signals from the system bus system_bus, which is used to transmit the system operating clock and reset signals, and provides an enable_mode signal to control the enable status of different encoding outputs. Through the system bus, software can dynamically modify the enable_mode signal to control the various outputs of the sine wave encoding, including the outputs of phase A, phase B, and phase C, as well as ABZ incremental encoding and PWM control output. By modifying the enable_mode signal, the line number modulation unit can flexibly adjust any combination of output signals during operation to meet different application requirements. Software can modify the enable_mode through the system bus to enable any one or more of the five output signals of the three encoding units mentioned above.

[0046] In one embodiment of the present application, when the line number modulation unit is in the reset state, all output coding signals are cleared, and the line number modulation unit sets the calculation idle indication signal (cal_idle) to valid and sends it to the input buffer unit. In the sth system cycle after the reset signal is released, the system bus controls the enable state of the output coding type by setting enable_mode. If a valid pulse appears in the calculation idle indication signal (cal_valid) of the input buffer unit in the tth system clock cycle, the line number modulation unit will latch the original angle signal (angle_cal[n:0]) at that moment. Then, in the t+1th system clock cycle, the calculation idle indication signal (cal_valid) is set to an invalid state, and the line number modulation unit starts calculation from the tth system clock cycle. This design ensures that the system can lock the data and start processing in time after receiving a valid input signal, thereby ensuring the timing accuracy and effectiveness of the data processing process.

[0047] In this embodiment, when enable_mode is set to enable five output enable groups, the addition and multiplication modules sequentially execute sine wave encoding, ABZ incremental encoding, and PWM control encoding line number modulation operations through time-division multiplexing. The following describes the steps for performing a complete line number modulation operation using these three encoding methods in this embodiment within system clock cycles t to t+5. Specifically, the steps include:

[0048] Step 1: Within t system clock cycles, upon detecting the cal_valid signal, the adder immediately updates its two n+1-bit inputs, angle_cal[n:0] and angle_shift_a[n:0], completing the calculation and outputting the result angle_add[n:0] in the same clock cycle. This addition result, along with the corresponding resolution resolution_ana_a[k:0], is then synchronously fed into the multiplier for the next step. Because multiplication is relatively complex and time-consuming, an n+1+k+1-bit latch, mult_result[n+k+1:0], is used to latch the multiplier's output angle_mult[n+k+1:0] to ensure data stability and address timing constraints. This latched value is updated to the multiplication result of cycle t in cycle t+1. This means the latch always stores the multiplication value from the previous cycle, enabling efficient pipeline processing.

[0049] Step 2: In the t+1 system clock cycle, the latch mult_result[n+k+1:0] latches the operation result of the multiplication calculation module in the t-th system clock cycle: (angle_cal[n:0]+angle_shift_a[n:0])×resolution_ana_a[k:0]. In the current clock cycle, the line number modulation unit performs the following operations: sets the angle_ana_a_valid signal to a valid state and maintains it for one system clock cycle; transmits the lower n+1 bits (mult_result[n:0]) in mult_result[n+k+1:0] as angle_ana_a[n:0] to the sine wave encoding unit (first encoding unit); updates the input values ​​of the adder and the multiplier, and updates the input of the adder to angle_cal[n:0] and angle_shift_b[n:0]; the adder generates a new calculation result angle_add[n:0]; and updates the two sets of inputs of the multiplier to the operation result of the adder in this cycle (angle_cal[n:0]+angle_shift_b[n:0]) and resolution_ana_b[k:0].

[0050] Step 3: In the t+2 system clock cycle, the latch mult_result[n+k+1:0] latches the operation result of the multiplication calculation module in the t+1 system clock cycle: (angle_cal[n:0]+angle_shift_b[n:0])×resolution_ana_b[k:0]. In the current clock cycle, the line number modulation unit performs the following operations: sets the angle_ana_b_valid signal to a valid state and maintains it for one system clock cycle; transmits the lower n+1 bits (mult_result[n:0]) in mult_result[n+k+1:0] as angle_ana_b[n:0] to the sine wave encoding unit (first encoding unit); updates the input values ​​of the adder and the multiplier, and updates the input of the adder to angle_cal[n:0] and angle_shift_c[n:0]; the adder generates a new calculation result angle_add[n:0]; and updates the two sets of inputs of the multiplier to the operation result of the adder in this cycle (angle_cal[n:0]+angle_shift_c[n:0]) and resolution_ana_c[k:0].

[0051] Step 4: In the t+3 system clock cycle, the latch mult_result[n+k+1:0] latches the operation result of the multiplication calculation module in the t+2 system clock cycle: (angle_cal[n:0]+angle_shift_c[n:0])×resolution_ana_c[k:0]. In the current clock cycle, the line number modulation unit performs the following operations: sets the angle_ana_c_valid signal to a valid state and maintains it for one system clock cycle; transmits the lower n+1 bits (mult_result[n:0]) in mult_result[n+k+1:0] as angle_ana_c[n:0] to the sine wave encoding unit (first encoding unit); updates the input values ​​of the adder and the multiplier, and updates the input of the adder to angle_cal[n:0] and angle_shift_abz[n:0]; the adder generates a new calculation result angle_add[n:0]; and updates the two sets of inputs of the multiplier to the operation results of the adder in this cycle (angle_cal[n:0]+angle_shift_abz[n:0]) and resolution_ana_abz[k:0].

[0052] Step 5: In the t+4 system clock cycles, the latch mult_result[n+k+1:0] latches the operation result of the multiplication calculation module in the t+3 system clock cycle: (angle_cal[n:0]+angle_shift_abz[n:0])×resolution_ana_abz[k:0]. In the current clock cycle, the line number modulation unit performs the following operations: the angle_ana_abz_valid signal is set to the valid state and maintained for one system clock cycle; the high n+3 bits of mult_result[n+k+1:k+1] in mult_result[n+k+1:0] are used as angle_abz[n+2:0] (the n+k+1 bit of mult_result corresponds to the n+3 bit of angle_abz, the n+k bit of mult_result corresponds to the n+2 bit of angle_abz, and so on). ltk-1 corresponds to the 0th bit of angle_abz) is transmitted to the ABZ encoding unit (the second encoding unit); the input values ​​of the adder and the multiplier are updated, and the input of the adder is updated to angle_cal[n:0] and angle_shift_pwm[n:0]; the adder generates a new calculation result angle_add[n:0]; the two sets of inputs of the multiplier are updated to the calculation result of the adder in this cycle (angle_cal[n:0]+angle_shift_pwm[n:0]) and resolution_ana_pwm[k:0].

[0053] Step 6: During system clock cycles t+5, the latch mult_result[n+k+1:0] latches the multiplication result of the multiplication module during system clock cycle t+4: (angle_cal[n:0] + angle_shift_pwm[n:0]) × resolution_ana_pwm[k:0]. During the current clock cycle, the line number modulation unit performs the following operations: The angle_ana_pwm_valid signal is set to the valid state for one system clock cycle; the lower n+1 bits (mult_result[n:0]) of mult_result[n+k+1:0] are transmitted to the PWM encoding unit (the third encoding unit) as angle_ana_pwm[n:0]; and during this clock cycle, i.e., system clock cycle t+5, if the cal_valid signal in the input buffer is valid, the process jumps to step 1 to start a new round of calculations, and the line number modulation unit's output cal_idle is updated to the invalid state. Otherwise, the process will stop at step 6, and the output cal_idle of the line number modulation unit will remain in an invalid state.

[0054] It should be noted that the embodiment in which enable_mode is set to enable all five outputs (angle_ana_a, angle_ana_b, angle_ana_c, angle_abz, and angle_pwm) is for illustrative purposes only and does not limit functionality. When enable_mode disables any of the above outputs, the line number modulation unit automatically skips the corresponding addition or multiplication calculation steps. Specifically, when enable_mode does not enable the calculation of angle_ana_a, in the tth system clock cycle, the adder inputs will be directly updated to angle_cal[n:0] and angle_shift_b[n:0]. During this clock cycle, the adder will generate a new result, angle_add[n:0]. At the same time, the two inputs of the multiplier will also be updated to the adder operation result of the current cycle: (angle_cal[n:0] + angle_shift_b[n:0]) × resolution_ana_b[k:0].

[0055] Similarly, in clock cycle t+4, the latch mult_result[n+k+1:0] will latch the multiplier calculation result from clock cycle t+3, namely (angle_cal[n:0] + angle_shift_pwm[n:0]) × resolution_pwm[k:0]. During this cycle, the line number modulation unit asserts angle_pwm_valid for one clock cycle and transmits the lower n+1 bits (mult_result[n:0]) of mult_result[n+k+1:0] to the PWM encoder unit as angle_pwm[n:0]. If cal_valid is valid in the input buffer, a new calculation cycle will be initiated in t system clock cycles, and the line number modulation unit's output cal_idle will be invalidated. Otherwise, the line number modulation unit's output cal_idle will remain invalid for t+4 system clock cycles. The above embodiments of the present application are only used to explain the present application and are not intended to limit the present application.

[0056] In one embodiment of the present application, the line modulation unit includes five sets of angle signals: one set is the A-phase remodulation angle angle_ana_a[n:0], the B-phase angle angle angle_ana_b[n:0], and the C-phase angle angle angle_ana_c[n:0], which are sent to the first encoding unit for sine wave encoding. Another set is the ABZ target angle angle_abz[n:0], which is sent to the second encoding unit for incremental encoding. A third set is the PWM control angle angle_pwm[n:0], which is sent to the third encoding unit for PWM control encoding.

[0057] In one embodiment of the present application, the output of the line number modulation unit further includes a calculation status indication signal cal_idle. This signal is used to indicate the calculation status of the line number modulation unit. The signal is valid after the calculation is completed and invalid when the calculation is in progress. The signal is connected to the input buffer unit.

[0058] In one embodiment of the present application, the addition module in the line number modulation unit is used to perform the addition operation of any two n+1-bit unsigned inputs, and its output is n+1 bits, denoted as angle_add[n:0]. The multiplication module is used to perform the unsigned multiplication operation of n+1 bits by k+1 bits, and its output is n+1+k+1 bits long, denoted as angle_mult[n+k+1:0].

[0059] In one embodiment of the present application, the line number modulation unit performs a line number modulation operation on the received first coding parameter to generate a first analog signal, and / or performs a line number modulation operation on the second coding parameter to generate a second analog signal, and / or performs a line number modulation operation on the third coding parameter to generate a third analog signal through a multiplication calculation module and an addition calculation module. The process includes: the line number modulation unit receives a coding mode control signal, and the coding mode control signal indicates to perform a line number modulation operation on one or more original angle signals of the first coding parameter, the second coding parameter, and the third coding parameter; when the line number modulation unit receives a valid original angle signal, it latches the angle input signal; in the current clock cycle, through the addition calculation module, according to the first coding parameter and / or the second coding parameter and / or the third coding parameter, performs angle offset addition on the original angle signal to generate an addition result; through the multiplication calculation module, multiplies the addition result with the corresponding resolution parameter to generate a multiplication result, and delays the multiplication result to the next clock cycle for output through a latch; extracts a preset number of bits from the multiplication result to generate a corresponding analog signal.

[0060] The first encoding unit 103 is communicatively connected to the system bus and is configured to receive the first analog signal from the line number modulation unit and the output mode from the system bus; and encode the first analog signal based on the output mode to generate a first encoded signal.

[0061] In one embodiment of the present application, the first coding signal includes an A-phase remodulation value, an A-phase valid flag signal, a B-phase remodulation value, a B-phase valid flag signal, a C-phase remodulation value, and a C-phase valid flag signal; the first coding unit encodes the first analog signal based on the output mode to generate a first coding signal. The process includes: performing the following steps when any one of the A-phase valid flag signal, the B-phase valid flag signal, and the C-phase valid flag signal is valid: when the output mode is a sine mode, calculating the sine value of the A-phase remodulation value to generate an A-phase coding value, calculating the sine value of the B-phase remodulation value to generate a B-phase coding value, and calculating the sine value of the C-phase remodulation value to generate a C-phase coding value. code value; when the output mode is the cosine mode, the cosine value of the A-phase remodulation value is calculated to generate the A-phase encoding value, the cosine value of the B-phase remodulation value is calculated to generate the B-phase encoding value, and the cosine value of the C-phase remodulation value is calculated to generate the C-phase encoding value; when the output mode is the sinusoidal full-wave rectification mode, the sine absolute value of the A-phase remodulation value is calculated to generate the A-phase encoding value, the sine absolute value of the B-phase remodulation value is calculated to generate the B-phase encoding value, and the sine absolute value of the C-phase remodulation value is calculated to generate the C-phase encoding value; when the output mode is the direct encoding mode, the A-phase remodulation value is output as the A-phase encoding value, the B-phase remodulation value is output as the B-phase encoding value, and the C-phase remodulation value is output as the C-phase encoding value.

[0062] In one embodiment of the present application, the first encoding unit is capable of performing sine wave encoding processing on the first analog signal based on the output mode to generate a first encoded signal. The first encoded signal includes an A-phase remodulation value, an A-phase valid flag signal, a B-phase remodulation value, a B-phase valid flag signal, a C-phase remodulation value, and a C-phase valid flag signal. These signals together constitute a complete three-phase signal system for accurately representing the encoded information. During the processing process, the first encoding unit will detect the status of the A-phase valid flag signal, the B-phase valid flag signal, and the C-phase valid flag signal. When any one of the signals is valid, the first encoding unit will perform the corresponding encoding operation according to the currently set output mode.

[0063] In an embodiment of the present invention, a first encoding unit is used to implement the aforementioned sine wave encoding function. This unit receives three-phase angle input values ​​and their valid flag signals from the line number modulation unit. Specifically, the inputs of the first encoding unit include: the A-phase remodulation value (angle_ana_a[n:0]), the B-phase remodulation value (angle_ana_b[n:0]), and the C-phase remodulation value (angle_ana_c[n:0]); the A-phase valid flag signal (angle_ana_a_valid[n:0]), the B-phase valid flag signal (angle_ana_b_valid[n:0]), and the C-phase valid flag signal (angle_ana_c_valid[n:0]).

[0064] The first encoding unit is also connected to the system bus system_bus, through which the system working clock and reset signal are obtained. The output mode of the first encoding unit is controlled by the configurable parameter ana_mode, which can be configured according to specific needs through the system bus system_bus. The first encoding unit outputs a three-phase encoding signal: ana_a[n:0] is the A-phase output, ana_b[n:0] is the B-phase output, and ana_c[n:0] is the C-phase output. To achieve the above functions, the first encoding unit has a built-in sine and cosine calculation unit that can calculate and output the corresponding sine and cosine values ​​according to the input phase angle values. The sine and cosine calculation unit is the core component for realizing multiple output modes, providing the system with flexible signal encoding capabilities.

[0065] In addition, the present invention provides a variety of output mode options to meet different application requirements. When the output mode is set to sine mode, the first encoding unit will calculate the sine values ​​of the A-phase remodulation value, the B-phase remodulation value, and the C-phase remodulation value, and generate corresponding A-phase encoding value, B-phase encoding value, and C-phase encoding value; when the output mode is set to cosine mode, the first encoding unit will calculate the cosine values ​​of the A-phase remodulation value, the B-phase remodulation value, and the C-phase remodulation value, and generate corresponding A-phase encoding value, B-phase encoding value, and C-phase encoding value; the cosine mode provides a waveform output that is 90 degrees out of phase with the sine mode; when the output When the mode is set to sinusoidal full-wave rectification mode, the first encoding unit will calculate the sine absolute values ​​of the A-phase remodulation value, the B-phase remodulation value and the C-phase remodulation value respectively, and generate the corresponding A-phase encoding value, B-phase encoding value and C-phase encoding value. In this mode, the output signal has only positive values; when the output mode is set to direct encoding mode, the first encoding unit directly outputs the A-phase remodulation value, the B-phase remodulation value and the C-phase remodulation value as the corresponding A-phase encoding value, the B-phase encoding value and the C-phase encoding value without performing any trigonometric function transformation.

[0066] Specifically, when the output mode is set to the sine mode, the input A-phase remodulation value (angle_ana_a[n:0]), B-phase remodulation value (angle_ana_b[n:0]) and C-phase remodulation value (angle_ana_c[n:0]) are input, and the operations shown in Formulas 1 to 3 are performed on the above three remodulation values ​​to calculate the corresponding sine values.

[0067] ana_a[n:0]=sin((angle_ana_a[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 1)

[0068] ana_b[n:0]=sin((angle_ana_b[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 2)

[0069] ana_c[n:0]=sin((angle_ana_c[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 3)

[0070] The sin function in formulas 1, 2, and 3 represents sine calculation. n+1 -1)) as an example, angle_ana_a[n:0] is an n+1-bit unsigned binary number, and its value range is 0 to 2 n+1 -1. By dividing the modulation angle by 2 n+1 -1, realizes the normalization of angle, which is done by mapping the input angle value proportionally to the range of 0 to 1. When measured from a physical perspective, (angle_ana_a[n:0] / (2 n+1 -1)) is 0 for 0° and 1 for 360°. The sine and cosine calculation unit calculates the angle according to the normalized input angle (angle_ana_a[n:0] / (2 n+1 -1)) to look up the table and get the corresponding sine value. At this time, sin((angle_ana_a[n:0] / (2 n+1 The output of -1))) is an n+1-bit binary signed number whose value range is from -1 to +1. Next, by multiplying by 2 n , the range of sine value is proportionally enlarged to -2 n to 2 n -1. Finally, add 2 n, map the value range of the final result ana_a[n:0] to 0 to 2 n+1 -1. At this point, the encoding conversion process of the sine value is completed.

[0071] Specifically, when the output mode is set to cosine mode, the input A-phase remodulation value (angle_ana_a[n:0]), B-phase remodulation value (angle_ana_b[n:0]) and C-phase remodulation value (angle_ana_c[n:0]) are input, and the operations shown in Formulas 4 to 6 are performed on the above three remodulation values ​​to calculate the corresponding cosine values.

[0072] ana_a[n:0]=cos((angle_ana_a[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 4)

[0073] ana_b[n:0]=cos((angle_ana_b[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 5)

[0074] ana_c[n:0]=cos((angle_ana_c[n:0] / (2 n+1 -1)))*2 n +2 n (Formula 6)

[0075] Among them, cos in formula 4, 5, and 6 represents cosine calculation, and * represents multiplication. Similar to formula 1, 2, and 3, the input angle is normalized first. The sine and cosine calculation unit calculates the angle according to the input (angle_ana_a[n:0] / (2 n+1 -1)) degrees and then look up the table to calculate the corresponding cosine value. n+1 The output is an n+1-bit binary signed number with a range of -1 to +1. The cosine value is proportionally enlarged to -2 by multiplying by 2n. n to 2 n -1, then +2 n , mapping the final ana_a[n:0] value range to 0 to 2 n+1 -1. Complete the cosine value encoding conversion.

[0076] Specifically, when the output mode is set to the sinusoidal full-wave rectification mode, the input A-phase remodulation value (angle_ana_a[n:0]), B-phase remodulation value (angle_ana_b[n:0]) and C-phase remodulation value (angle_ana_c[n:0]) are used, and the operations shown in Formulas 7 to 9 are performed on the above three remodulation values ​​to calculate the absolute value of the corresponding sinusoidal value and output the corresponding steamed wave or half wave.

[0077] ana_a[n:0] = |sin((angle_ana_a[n:0] / (2 n+1 -1)))|*2 n +2 n (Formula 7)

[0078] ana_b[n:0]=|sin((angle_ana_b[n:0] / (2 n+1 -1)))|*2 n +2 n (Formula 8)

[0079] ana_c[n:0]=|sin((angle_ana_c[n:0] / (2 n+1 -1)))|*2 n +2 n (Formula 9)

[0080] Formulas 7, 8, and 9 add an absolute value operation to the original sine value based on formulas 1, 2, and 3, that is, the absolute value operation is performed on the signed value of the sine output. Taking ana_a[n:0] as an example, the value range of ana_a[n:0] is mapped to 2 n to 2 n +1 -1, complete the sinusoidal full-wave rectification code conversion.

[0081] Specifically, when the output mode is set to direct encoding mode, each input angle value is directly used as the output phase value, as shown in Formulas 10 to 12.

[0082] ana_a[n:0]=angle_ana_a[n:0] (Formula 10)

[0083] ana_b[n:0]=angle_ana_b[n:0] (Formula 11)

[0084] ana_c[n:0]=angle_ana_c[n:0] (Formula 12)

[0085] The second encoding unit 104 is communicatively connected to the system bus, and is used to receive the second analog signal from the line number modulation unit and the system configuration parameters from the system bus; based on the system configuration parameters, the second analog signal is encoded to generate a second encoded signal.

[0086] In one embodiment of the present application, the second analog signal includes an ABZ valid flag signal and ABZ position information; the system configuration parameters include an ABZ bit width, an ABZ initial angle value, and an ABZ zero position reference value; the second encoding unit performs ABZ incremental encoding on the second analog signal based on the system configuration parameters to generate a second encoded signal. The process includes: when the ABZ valid flag signal is valid, in each system clock cycle corresponding to the ABZ bit width, performing the following steps: inverting the lowest bit data of the ABZ position information, and inverting the value according to the inverted value. The output A-phase incremental signal is output as a result of the value; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low; an exclusive OR operation is performed on the lowest two bits of the ABZ position information, and a B-phase incremental signal is output according to the operation result; if the levels of the lowest two bits are consistent, the output B-phase incremental signal is low; otherwise, the output B-phase incremental signal is high; if all bit data of the ABZ position information are consistent with the ABZ zero position reference value, the output Z-phase incremental signal is high; otherwise, the output Z-phase incremental signal is low.

[0087] In this embodiment, the second encoding unit is used to implement ABZ incremental encoding output. The second encoding unit receives multiple input signals and parameters and generates a standard ABZ incremental encoding output signal. It should be noted that ABZ incremental encoding is widely used in position and velocity measurement systems and can provide high-precision position and velocity information.

[0088] Specifically, the ABZ incremental encoder unit's inputs include: ABZ position information (angle_abz[n+2:0]) from the line number modulation unit; the ABZ valid flag (angle_abz_valid) from the line number modulation unit; the system bus (system_bus), which includes the system operating clock and reset signals; and multiple configurable parameters. These parameters include the ABZ bit width (abz_width), the ABZ initial angle value (abz_angle_init[n+2:0]), and the ABZ zero reference value (abz_angle_z[n+2:0]), all of which can be configured according to specific requirements via the system bus.

[0089] The configurable parameter ABZ bit width (abz_width) controls the minimum number of toggle cycles for the A-phase and B-phase signals output by the ABZ incremental encoder. This refers to the number of system clock cycles required for the output signals abz_a or abz_b to transition from a high-level to a low-level, or vice versa. The configurable parameter ABZ initial angle value (abz_angle_init[n+2:0]) controls the initial value of the internal position manager of the ABZ incremental encoder. The configurable parameter ABZ zero reference value (abz_angle_z[n+2:0]) controls the angle corresponding to the Z-phase output abz_z of the ABZ incremental encoder. The outputs of the ABZ incremental encoder unit include: the incremental encoder A-phase output abz_a; the incremental encoder B-phase output abz_b; and the incremental encoder Z-phase output abz_z. These three output signals together constitute the standard ABZ incremental encoder signal.

[0090] Upon system reset, the internal angle abz_inner[n+2:0] of the encoding unit is reset to zero. After the system reset is released, the initial value of the internal angle is derived from the configurable ABZ initial angle value (abz_angle_init[n+2:0]) parameter on the system bus. During the encoding process, when the angle validity indicator signal (angle_abz_valid) is valid, the ABZ encoding unit uses the ABZ position information (angle_abz[n+2:0]) of the current system clock cycle as the current target angle. If the current internal angle abz_inner[n+2:0] is less than the current target angle, the encoding unit increments abz_inner[n+2:0] every ABZ bit width (abz_width) system clock cycles. If the current internal angle abz_inner[n+2:0] is greater than the current target angle, the encoding unit decrements abz_inner[n+2:0] every ABZ bit width (abz_width) system clock cycles. If the two are equal, abz_inner[n+2:0] remains unchanged.

[0091] When the angle valid indication signal ABZ valid flag signal (angle_abz_valid) is valid, the ABZ incremental encoding unit performs the following encoding steps according to Formulas 13 to 15 in the system clock cycle corresponding to each ABZ bit width (abz_width):

[0092] abz_a=inv(abz_inner[0]) (Formula 13)

[0093] abz_b=abz_inner[0]⊕abz_inner[1] (Formula 14)

[0094] abz_z=abz_inner[n+2:0]==angle_abz_z[n+2:0] (Formula 15)

[0095] As shown in Equation 13, the least significant bit of the ABZ position information (i.e., the internal angle abz_inner[n+2:0]) is inverted, and the A-phase incremental signal abz_a is output based on the inverted value. Specifically, if the least significant bit is high, the output A-phase incremental signal is low; if the least significant bit is low, the output A-phase incremental signal is high.

[0096] As shown in Equation 14, an exclusive-OR operation is performed on the lowest two bits of the ABZ position information, and the B-phase incremental signal abz_b is output based on the result. Specifically, if the levels of the lowest two bits are consistent (i.e., both high or both low), the output B-phase incremental signal is low; if the levels of the lowest two bits are inconsistent, the output B-phase incremental signal is high.

[0097] As shown in Equation 15, the encoding unit determines whether all bits of the ABZ position information are consistent with the ABZ zero-position reference value (abz_angle_z[n+2:0]). If they are consistent, the output Z-phase incremental signal abz_z is high; if not, the output Z-phase incremental signal abz_z is low.

[0098] A third encoding unit 105 is communicatively connected to the system bus, and is used to receive the third analog signal from the line number modulation unit and the modulation cycle parameter from the system bus; based on the modulation cycle parameter, the third analog signal is encoded to generate a third encoded signal.

[0099] In one embodiment of the present application, the third analog signal includes a PWM valid flag signal and PWM position information; based on the modulation cycle parameter, the third analog signal is encoded to generate a third encoded signal. The process includes: when the PWM valid flag signal is valid, the reverse PWM encoded signal of the forward PWM encoded signal is calculated according to the PWM position information and the modulation cycle parameter.

[0100] In this embodiment, the third encoding unit is used to perform PWM control encoding. Its input signals include the PWM position information (angle_pwm) from the line modulation unit and its PWM valid flag signal (angle_pwm_valid), which is used to determine and provide the key to the current angle information. Furthermore, the input signal includes a fault indication signal (fault) for detecting system operational anomalies. The system bus (system_bus) provides the necessary operating clock and reset signals, and a configurable parameter (pwm_period) is used to set the modulation period parameter. This parameter can be configured based on the system bus requirements to accommodate different PWM encoding requirements.

[0101] Furthermore, under system reset conditions, the initial values ​​of the positive PWM output forward PWM code signal (pwm_p) and the negative PWM output reverse PWM code signal (pwm_n) are zero. After reset is released, if the angle valid indication signal angle_pwm_valid is valid in the g-th system clock cycle, the calculation process for the positive and negative outputs is shown in Equations 16 to 18.

[0102] pwm_cycle[2n+1:0]=angle_pwm[n:0]*pwm_period[n:0] (Formula 16)

[0103] pwm_p[n:0]=pwm_cycle[2n+1:n+1] (Formula 17)

[0104] pwm_n[n:0]=pwm_period[n:0]-pwm_p[n:0] (Formula 18)

[0105] In Equation 16, the PWM reference period (pwm_cycle[2n+1:0]) is the 2n+2-bit multiplication result of multiplying the n+1 PWM position information (angle_pwm) by the n+1 modulation period parameter (pwm_period). In Equation 17, the positive PWM code signal (pwm_p) is the high-order n+1 bits of the PWM reference period (pwm_cycle[2n+1:0]). In Equation 18, the negative PWM code signal (pwm_n) is the result of subtracting the positive PWM code signal (pwm_p) from the modulation period parameter (pwm_period).

[0106] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first coding unit and the second coding unit are merely used to distinguish between different coding units and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the number or execution order, and that terms such as "first" and "second" do not necessarily define differences.

[0107] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" represent examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0108] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0109] It should be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically as separate modules, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0110] Figure 5 FIG. 1 is a flow chart of a multifunctional motor encoding method provided in an embodiment of the present application. Figure 5 As shown, the method includes the following steps:

[0111] Step S51: receiving an original angle signal and calculating an idle indication signal.

[0112] Step S52: Cache the original angle signal, and when the calculated idle indication signal is valid, receive the first coding parameter, the second coding parameter and / or the third coding parameter, and perform a line number modulation operation on the original angle signal according to the first coding parameter and / or the second coding parameter and / or the third coding parameter; wherein, when the first coding parameter is used, a first analog signal is generated, when the second coding parameter is used, a second analog signal is generated, and when the third coding parameter is used, a third analog signal is generated.

[0113] Step S53: The process of generating the first analog signal using the first encoding parameter includes: receiving the first analog signal and an output mode; encoding the first analog signal based on the output mode to generate a first encoded signal.

[0114] Step S54: The process of generating the second analog signal using the second encoding parameter includes: receiving the second analog signal and the system configuration parameter; encoding the second analog signal based on the system configuration parameter to generate a second encoded signal.

[0115] Step S55: The process of generating a third analog signal using the third coding parameter includes: receiving the third analog signal and a modulation period parameter; and encoding the third analog signal based on the modulation period parameter to generate a third coded signal.

[0116] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above system embodiment, and for the sake of brevity, it will not be repeated here.

[0117] The content protected by this application is not limited to the method itself, but also covers a wide range of integrated circuit chips and related hardware systems that include this innovative encoding method. Specifically, the scope of protection of the present invention includes: microcontroller chips with built-in encoding methods, application-specific integrated circuits with line modulation units, motor control systems using the technology of the present invention, mechatronic products that apply this encoding method, and electronic systems and terminal products that include related hardware implementations. This application also protects computer programs related to the above-mentioned systems, computer-readable storage media, and software products that include this encoding method.

[0118] Figure 6 : is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 6As shown, the electronic terminal includes: at least one processor 601, a memory 602, at least one network interface 603 and a user interface 605. The various components in the device are coupled together through a bus system 604. It is understood that the bus system 604 is used to achieve connection and communication between these components. In addition to including a data bus, the bus system 604 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 6 Various buses are labeled as bus systems.

[0119] The user interface 605 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0120] It will be appreciated that the memory 602 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM) or a programmable read-only memory (PROM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0121] The memory 602 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 600. Examples of such data include: any executable program for operating on the electronic terminal 600, such as an operating system 6021 and an application 6022; the operating system 6021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 6022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The multifunctional motor encoding method provided in the embodiment of the present invention can be included in the application 6022.

[0122] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 601. Processor 601 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 601 or by software instructions. The above processor 601 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 601 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 601 can be a microprocessor or any conventional processor. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory. The processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0123] In an exemplary embodiment, the electronic terminal 600 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0124] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the multifunctional motor encoding method of any one of the embodiments shown above.

[0125] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code is run on a computer, the computer executes the multifunctional motor encoding method of any one of the embodiments shown above.

[0126] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0127] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0130] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0131] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0132] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0133] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0134] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0135] In summary, the present application provides a multifunctional motor encoding system, method, medium, program product, and terminal. The system obtains the original angle signal through an input buffer unit and transmits the signal to the line number modulation unit during idle time. The line number modulation unit's multiplication and addition calculation modules flexibly modulate the original angle signal according to multiple encoding parameters to generate multiple high-precision analog signals. The encoding unit can perform personalized encoding of the analog signal based on different system bus parameters, such as output mode, system configuration, and modulation period, and output a matching encoded signal. This application significantly improves the flexibility and integration of the motor encoder. It also effectively reduces circuit complexity and optimizes chip area by sharing the computing unit. Compared with traditional solutions, while maintaining high precision, circuit costs are significantly reduced and operational efficiency is significantly improved. Its outstanding technical advantages give it extremely broad application prospects in industrial automation, precision control, robotic systems, and other fields, representing an important innovation direction in motor encoding technology. Therefore, this application effectively overcomes the various shortcomings of the existing technology and has high industrial application value.

[0136] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A multifunctional motor encoding system, characterized in that: include: An input buffer unit, wherein the input buffer unit is communicatively connected to the position management system and the line number modulation unit respectively; for receiving an original angle signal from the position management system and a calculation idle indication signal from the line number modulation unit; the input buffer unit buffers the original angle signal and, when the calculation idle indication signal is valid, sends the buffered angle signal to be calculated to the line number modulation unit; A line number modulation unit, comprising a multiplication calculation module and an addition calculation module; the line number modulation unit is communicatively connected to the first encoding unit, the second encoding unit, and the third encoding unit respectively; and is configured to receive a first encoding parameter, a second encoding parameter, and / or a third encoding parameter, and perform a line number modulation operation on the original angle signal according to the first encoding parameter, the second encoding parameter, and / or the third encoding parameter via the multiplication calculation module and the addition calculation module; wherein a first analog signal is generated when the first encoding parameter is used, a second analog signal is generated when the second encoding parameter is used, and a third analog signal is generated when the third encoding parameter is used; a first encoding unit, the first encoding unit being communicatively connected to the system bus and configured to receive the first analog signal from the line number modulation unit and an output mode from the system bus; and encoding the first analog signal based on the output mode to generate a first encoded signal; a second encoding unit, the second encoding unit being communicatively connected to the system bus and configured to receive the second analog signal from the line number modulation unit and a system configuration parameter from the system bus; and encoding the second analog signal based on the system configuration parameter to generate a second encoded signal; A third encoding unit is communicatively connected to the system bus, and is used to receive the third analog signal from the line number modulation unit and the modulation cycle parameter from the system bus; based on the modulation cycle parameter, the third analog signal is encoded to generate a third encoded signal.

2. The multifunctional motor encoding system according to claim 1, characterized in that: The line number modulation unit performs a line number modulation operation on the received first coding parameter to generate a first analog signal, and / or performs a line number modulation operation on the second coding parameter to generate a second analog signal, and / or performs a line number modulation operation on the third coding parameter to generate a third analog signal through the multiplication calculation module and the addition calculation module, including: The line number modulation unit receives a coding mode control signal, wherein the coding mode control signal instructs to perform a line number modulation operation on one or more original angle signals among the first coding parameter, the second coding parameter, and the third coding parameter; latching the angle input signal when the line number modulation unit receives the valid original angle signal; In the current clock cycle, the addition calculation module performs angle offset addition on the original angle signal according to the first encoding parameter and / or the second encoding parameter and / or the third encoding parameter to generate an addition result; the multiplication calculation module multiplies the addition result with the corresponding resolution parameter to generate a multiplication result, and the multiplication result is delayed to the next clock cycle output through a latch; and a preset number of bits is extracted from the multiplication result to generate a corresponding analog signal.

3. The multifunctional motor encoding system according to claim 2, characterized in that: The first coded signal includes an A-phase remodulation value, an A-phase valid flag signal, a B-phase remodulation value, a B-phase valid flag signal, a C-phase remodulation value, and a C-phase valid flag signal; The process of the first encoding unit encoding the first analog signal based on the output mode to generate a first encoded signal includes: When any one of the A-phase valid flag signal, the B-phase valid flag signal, and the C-phase valid flag signal is valid, the following steps are performed: When the output mode is the sinusoidal mode, the sine value of the A-phase remodulation value is calculated to generate the A-phase encoding value, the sine value of the B-phase remodulation value is calculated to generate the B-phase encoding value, and the sine value of the C-phase remodulation value is calculated to generate the C-phase encoding value; When the output mode is the cosine mode, the cosine value of the A-phase remodulation value is calculated to generate the A-phase encoding value, the cosine value of the B-phase remodulation value is calculated to generate the B-phase encoding value, and the cosine value of the C-phase remodulation value is calculated to generate the C-phase encoding value; When the output mode is a sinusoidal full-wave rectification mode, the sine absolute value of the A-phase remodulation value is calculated to generate an A-phase encoding value, the sine absolute value of the B-phase remodulation value is calculated to generate a B-phase encoding value, and the sine absolute value of the C-phase remodulation value is calculated to generate a C-phase encoding value; When the output mode is the direct encoding mode, the output A-phase remodulation value is the A-phase encoding value, the output B-phase remodulation value is the B-phase encoding value, and the output C-phase remodulation value is the C-phase encoding value.

4. The multifunctional motor encoding system according to claim 2, characterized in that: The second analog signal includes an ABZ valid flag signal and ABZ position information; the system configuration parameters include an ABZ width, an ABZ initial angle value, and an ABZ zero position reference value; The process of the second encoding unit performing ABZ incremental encoding on the second analog signal based on the system configuration parameters to generate a second encoded signal includes: When the ABZ valid flag signal is valid, the following steps are performed in each system clock cycle corresponding to the ABZ bit width: Invert the lowest bit of the ABZ position information and output an A-phase incremental signal according to the inverted result; if the lowest bit is high, the output A-phase incremental signal is low; otherwise, the output A-phase incremental signal is low; Perform an exclusive OR operation on the lowest two bits of the ABZ position information, and output a B-phase incremental signal according to the operation result; if the levels of the lowest two bits are consistent, the output B-phase incremental signal is a low level; otherwise, the output B-phase incremental signal is a high level; If all bit data of the ABZ position information are consistent with the ABZ zero position reference value, the output Z-phase incremental signal is a high level; otherwise, the output Z-phase incremental signal is a low level.

5. The multifunctional motor encoding system according to claim 2, characterized in that: The third analog signal includes a PWM valid flag signal and PWM position information; and the process of encoding the third analog signal based on the modulation period parameter to generate a third encoded signal includes: When the PWM valid flag signal is valid, a reverse PWM coded signal of the forward PWM coded signal is calculated according to the PWM position information and the modulation period parameter.

6. The multifunctional motor encoding system according to claim 1, characterized in that: The input buffer unit includes a plurality of buffers; the input buffer unit also receives an angle update hysteresis threshold value, and the process of caching the original angle signal includes: When the input cache unit calculates the absolute difference between the original angle information received at the current moment and the original angle information last stored in the cache; if the absolute difference is greater than or equal to the angle update hysteresis threshold value, the original angle information received at the current moment is stored in the cache in a first-in-first-out manner; otherwise, the original angle information received at the current moment is discarded, and the original angle information of the next moment is continued to be received.

7. A multifunctional motor encoding method, the method being applied to an encoder, characterized in that: The method comprises: receiving a raw angle signal and calculating an idle indication signal; caching the original angle signal, and when the calculation idle indication signal is valid, receiving a first coding parameter, a second coding parameter, and / or a third coding parameter, and performing a line number modulation operation on the original angle signal according to the first coding parameter, the second coding parameter, and / or the third coding parameter; wherein a first analog signal is generated when the first coding parameter is used, a second analog signal is generated when the second coding parameter is used, and a third analog signal is generated when the third coding parameter is used; The process of generating a first analog signal using the first encoding parameter includes: receiving the first analog signal and an output mode; encoding the first analog signal based on the output mode to generate a first encoded signal; The process of generating the second analog signal when using the second encoding parameter includes: receiving the second analog signal and system configuration parameters; encoding the second analog signal based on the system configuration parameters to generate a second encoded signal; The process of generating a third analog signal when using the third encoding parameter includes: receiving the third analog signal and a modulation period parameter; and encoding the third analog signal based on the modulation period parameter to generate a third encoded signal.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the multifunctional motor encoding method according to claim 7 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program code, and when the computer program code is run on a computer, the computer is enabled to implement the multifunctional motor encoding method according to claim 7.

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the multifunctional motor encoding method according to claim 7.

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