Memory control method

Abstract

The invention provides a control method of a memory, which is applied to the memory with an open bit line architecture and at least comprises the following steps: when a sensing amplifier corresponding to a target activation word line enters a bias compensation stage, starting the target activation word line; and controlling the residual sensing amplifiers corresponding to the adjacent storage part of the storage part where the target activation word line is located to enter the bias compensation stage.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a method for controlling a memory. Background Art

[0002] Memory uses word lines and bit lines to control data reading, writing, and refreshing. During the data reading process, the sense amplifier needs to amplify the read data based on the voltage difference between the target bit line and the complementary bit line, thereby effectively obtaining the data stored in the memory cell. The target bit line refers to the bit line connected to the memory cell corresponding to the activated word line.

[0003] It is understandable that the voltage difference between the target bit line and the complementary bit line will have a significant impact on data amplification. When the voltage difference between the target bit line and the complementary bit line is less than the minimum voltage difference required by the sense amplifier for data amplification, the amplified data may contain errors. Summary of the Invention

[0004] The embodiments of the present application provide a memory control method, which is at least beneficial for optimizing the bias compensation of the memory.

[0005] According to some embodiments of the present application, an embodiment of the present application provides a memory control method, which is applied to a memory with an open bit line architecture and can at least include: when the sensing amplifier corresponding to the target activation word line enters the bias compensation stage, controlling the remaining sensing amplifiers corresponding to the adjacent storage parts of the storage part where the target activation word line is located to enter the bias compensation stage.

[0006] In some embodiments, the target activated word line has a corresponding complementary bit line located in the adjacent storage unit, and the other bit lines in the adjacent storage unit except the complementary bit line are in a floating state during the sensing amplification stage, and the sensing amplification stage is located after the bias compensation stage.

[0007] In some embodiments, the target activated word line has a corresponding complementary bit line located in the adjacent storage unit, and the other bit lines in the adjacent storage unit except the complementary bit line are in a floating state during the charge sharing stage, and the charge sharing stage is located between the sensing amplification stage and the bias compensation stage.

[0008] In some embodiments, the memory section where the target activated word line is located and the sense amplifiers corresponding to the adjacent memory section receive bias cancellation signals with the same timing, and during the bias compensation phase, the bias cancellation signals are in an enabled state.

[0009] In some embodiments, the sense amplifiers corresponding to the memory section where the target activated word line is located and the adjacent memory section receive the same bias cancellation signal.

[0010] In some embodiments, the sense amplifier includes: a first P-type amplifier tube, a second P-type amplifier tube, a first N-type amplifier tube, a second N-type amplifier tube, a first isolation tube, a second isolation tube, a first bias cancellation tube, and a second bias cancellation tube; wherein the first end of the first P-type amplifier tube and the first end of the second P-type amplifier tube are connected to a voltage node, the gate of the first P-type amplifier tube and the second end of the second P-type amplifier tube are connected to a first node, and the gate of the second P-type amplifier tube and the second end of the first P-type amplifier tube are connected to a second node; the first end of the first N-type amplifier tube and the first end of the second N-type amplifier tube are connected to a ground node, the second end of the first N-type amplifier tube is connected to the second node, and the second end of the second N-type amplifier tube is connected to a ground node. The first end of the first N-type amplifier transistor is connected to the first node, the gate of the first N-type amplifier transistor, the first end of the first bias cancellation transistor, and the first end of the first isolation transistor are connected to the bit line, the second end of the first bias cancellation transistor is connected to the second node, and the second end of the first isolation transistor is connected to the first node; the gate of the second N-type amplifier transistor, the first end of the second bias cancellation transistor, and the first end of the second isolation transistor are connected to the complementary bit line, the second end of the second bias cancellation transistor is connected to the first node, and the second end of the second isolation transistor is connected to the second node; the gate of the first bias cancellation transistor and the gate of the second bias cancellation transistor are used to receive the bias cancellation signal, and the gate of the first isolation transistor and the gate of the second isolation transistor are used to receive the isolation signal.

[0011] In some embodiments, the sense amplifier further includes: a first transmission tube and a second transmission tube, wherein the first end of the first transmission tube is used to receive a voltage signal, the second end is connected to the voltage node, and the gate is used to receive a first enable signal; the first end of the second transmission tube is used to receive a ground signal, the second end is connected to the ground node, and the gate is used to receive a second enable signal; the remaining sense amplifiers corresponding to the adjacent storage units receive the first enable signal and the second enable signal in an enabled state during the bias compensation phase, and receive the first enable signal and the second enable signal in a disabled state during other phases.

[0012] In some embodiments, the memory further includes a precharge circuit, which is used to provide a precharge voltage to the bit line and the complementary bit line based on a precharge signal, or to provide the precharge voltage to the first node and / or the second node based on the precharge signal.

[0013] In some embodiments, the precharge circuits corresponding to the storage unit where the target activated word line is located and the adjacent storage unit receive the same precharge signal.

[0014] In some embodiments, the timing of the precharge signal and the isolation signal received by any storage unit in the adjacent storage units is the same.

[0015] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0016] In the embodiment of the present disclosure, when the sensing amplifier corresponding to the target activation word line enters the bias compensation stage, the voltages of the bit line and the complementary bit line corresponding to the target activation word line will be pulled down by the ground voltage in the sensing amplifier. Since the complementary bit lines located in adjacent storage parts work at intervals, the remaining sensing amplifiers corresponding to the adjacent storage parts are controlled to enter the bias compensation stage, so that the voltages of the storage part where the target activation word line is located and all the bit lines in the adjacent storage parts are pulled down by the ground voltage in the sensing amplifier, which is beneficial to make the coupling environment of the bit line and the complementary bit line corresponding to the target activation word line the same, thereby ensuring that both the bit line and the complementary bit line can be effectively bias compensated. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0018] Figure 1 A schematic diagram of the structure of the memory provided in an embodiment of the present application;

[0019] Figure 2 A schematic structural diagram of a sense amplifier provided in one embodiment of the present application;

[0020] Figure 3 A schematic structural diagram of a sense amplifier and a pre-charge circuit provided in another embodiment of the present application;

[0021] Figure 4-5 This is a timing diagram of different storage units and corresponding sense amplifiers and pre-charging circuits provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0023] Figure 1 A schematic diagram of the structure of the memory provided in an embodiment of the present application.

[0024] refer to Figure 1, a memory control method is applied to a memory with an open bit line architecture, comprising: when the sensing amplifier corresponding to the target activation word line TWL enters the bias compensation stage, controlling the remaining sensing amplifiers corresponding to the adjacent storage parts of the storage part where the target activation word line is located to enter the bias compensation stage.

[0025] In the embodiment of the present disclosure, when the sensing amplifier corresponding to the target activation word line enters the bias compensation stage, the voltages of the bit line and the complementary bit line corresponding to the target activation word line will be pulled down by the ground voltage in the sensing amplifier. Since the complementary bit lines located in adjacent storage parts work at intervals, the remaining sensing amplifiers corresponding to the adjacent storage parts are controlled to enter the bias compensation stage, so that the voltages of the storage part where the target activation word line is located and all the bit lines in the adjacent storage parts are pulled down by the ground voltage in the sensing amplifier, which is beneficial to make the coupling environment of the bit line and the complementary bit line corresponding to the target activation word line the same, thereby ensuring that both the bit line and the complementary bit line can be effectively bias compensated.

[0026] The following is a more detailed description of the embodiments of the present application with reference to the accompanying drawings. Figure 1 , Figure 1 The diagram shows five memory sections A (first memory section A1 through fifth memory section A5) arranged along the direction in which the bit lines extend. Sense amplifiers SA are positioned between adjacent memory sections A, or rather, sense amplifiers SA are positioned on both sides of each memory section A. In other words, each set of sense amplifiers SA is used to amplify the bit lines in the memory sections A located on opposite sides. Each memory section A contains multiple word lines and multiple bit lines, arranged in a grid. Multiple memory cells arranged along the direction in which the word lines extend are connected to the same word line and to different bit lines, and multiple memory cells arranged along the direction in which the bit lines extend are connected to the same bit line and to different word lines. Therefore, the bit lines corresponding to each word line refer to all bit lines in the memory section in which the word line is located, and the word lines corresponding to each bit line refer to all word lines in the memory section in which the bit line is located. An open bitline architecture (Open-BL) means that two adjacent bit lines corresponding to the same word line are connected to sense amplifiers SA on different sides, allowing them to be sensed and amplified by the sense amplifiers SA on different sides.

[0027] It should be noted that all data lines connected to sense amplifiers in the storage unit are bit lines. However, for clarity and to emphasize the complementary relationship, in some scenarios, two bit lines connected to the same sense amplifier are referred to as a bit line and a complementary bit line. If there is a target active word line, the bit line in the storage unit where the target active word line is located is called a bit line, and the bit line corresponding to the target active word line and connected to the same sense amplifier is called a complementary bit line. The complementary bit line is usually located in the adjacent storage unit to the storage unit where the target active word line is located.

[0028] In addition, it should be noted that Figure 1 Taking the sensing amplifier SA and the storage unit A as an example, in this case, there is a spatially spaced arrangement relationship between the sensing amplifier SA and the storage unit A; in other embodiments, the sensing amplifier SA and the storage unit A may also be in different chips. However, no matter which distribution method is adopted, the basic definition of the open bit line structure will not change. The only adjustment that needs to be made is to modify the "sensing amplifiers on different sides" to "sensing amplifiers in different groups". The sensing amplifiers in different groups are used to connect different bit lines in the corresponding storage units, and the bit lines of adjacent different storage units are used as complementary bit lines for amplification. The "sensing amplifiers in different groups" and "sensing amplifiers on different sides" have the same logical relationship as the storage unit, and the only difference is that the positional relationship between the sensing amplifier and the storage unit is no longer restricted. It can be understood that in Figure 1 In the embodiment, a whole row SA connected to the bit lines of the first storage unit A1 and the second storage unit A2 is a group of sense amplifiers, and another whole row SA corresponding to the first storage unit A1 and the third storage unit A3 is another group of sense amplifiers. Figure 1 The illustrated embodiment is described as an example, but it is understood that it can also be applied to other embodiments.

[0029] Since the memory has an open bit line architecture, only half of the bit lines in the adjacent storage part of the storage part where the target activation word line is located are complementary bit lines corresponding to the target activation word line, and are pulled down by the ground voltage of the sensing amplifier corresponding to the target activation word line. If the sensing amplifier connected to the remaining bit lines does not work, the voltage of the remaining bit lines will not change in theory, or at least will not be pulled down by the ground node of the connected sensing amplifier. Since each bit line in the storage part where the target activated word line is located will be pulled down by the ground node of the connected sensing amplifier, each bit line has a tendency to decrease in voltage. However, the sensing amplifier corresponding to the target activated word line enters the bias elimination stage, which will only cause half of the bit lines in the adjacent storage part (i.e., complementary bit lines) to show a tendency to decrease in voltage. The voltage of the remaining half of the bit lines needs to be controlled by other sensing amplifiers. If the voltage of the remaining half of the bit lines is maintained at the pre-charge voltage, it will cause the voltage coupling environment of the bit line and the complementary bit line to be inconsistent, which will cause the voltage on the complementary bit line to be greater than the actual compensation voltage required at the end of the bias elimination stage, and also cause the voltage difference between the bit line and the complementary bit line to not meet the actual needs at the end of the subsequent charge compensation stage.

[0030] Further, in Figure 1In , since the target activation word line TWL is located in the first storage part A1, the sensing amplifier SA corresponding to the target activation word line TWL refers to the sensing amplifier SA located on the opposite sides of the first storage part A1, that is, the sensing amplifier between the first storage part A1 and the adjacent second storage part A2 and the third storage part A3. Since the sensing amplifiers between the first storage part A1 and the adjacent second storage part A2 and the third storage part A3 have entered the bias compensation stage based on the target activation word line TWL, the remaining sensing amplifiers corresponding to the adjacent storage parts (the second storage part A2 and the third storage part A3) refer to the sensing amplifier SA on the side of the second storage part A2 away from the first storage part A1, that is, the sensing amplifier SA between the second storage part A2 and the fourth storage part A4, and the sensing amplifier SA on the side of the third storage part A3 away from the first storage part A1, that is, the sensing amplifier SA between the third storage part A3 and the fifth storage part A5. In Figure 1 In FIG, the remaining sense amplifiers corresponding to adjacent storage parts are marked with red lines and fonts for easier understanding.

[0031] For simplicity, the bit lines in the storage section where the target active word line is located are defined as first-class bit lines. The first-class bit lines are used to read, write, or refresh data. The complementary bit lines connected to the same sense amplifier SA as the first-class bit lines are defined as second-class bit lines. The second-class bit lines are located in the adjacent storage section where the target active word line is located. The other bit lines in the storage section where the second-class bit lines are located are referred to as third-class bit lines. It can be understood that the purpose of this disclosure is to control the sense amplifiers connected to the third-class bit lines to enter the bias compensation phase, thereby ensuring that the coupling environment of the first-class bit lines and the second-class bit lines is the same.

[0032] Furthermore, for the sake of simplicity in expression, the storage unit where the target activation word line is located is defined as the target storage unit, the adjacent storage unit of the target storage unit is defined as the adjacent storage unit, the sensing amplifier between the target storage unit and the adjacent storage unit (i.e., the common corresponding or shared) is defined as the first type of sensing amplifier, and the remaining sensing amplifiers corresponding to the adjacent storage unit are defined as the second type of sensing amplifier, i.e. Figure 1 The sense amplifier is identified by red lines and font.

[0033] In some embodiments, the target active word line TWL has a corresponding complementary bit line (i.e., a second-type bit line) located in an adjacent storage unit. Bit lines other than the complementary bit line (i.e., a third-type bit line) in the adjacent storage unit are in a floating state during the sensing and amplification phase, which occurs after the bias compensation phase. A floating state refers to a state in which no voltage, such as a precharge voltage, is applied to the bit line. The potential of a floating bit line is easily affected by the potentials of surrounding bit lines, while having minimal coupling effects on surrounding bit lines, i.e., minimal impact on the amplitude of voltage changes on surrounding bit lines. By controlling the third-type bit line to be in a floating state during the sensing and amplification phase, the voltage coupling effects of the third-type bit line on the second-type bit line are reduced, thereby ensuring that the voltage on the second-type bit line can be compensated to the target voltage and shortening the time required to pull the voltage of the complementary bit line up to a high or low level.

[0034] It is understandable that if the third-type bit line remains at a precharge voltage, when the first-type sense amplifier enters the bias compensation phase, because the voltage of the third-type bit line is greater than the voltage of the second-type bit line after being pulled down, the ground voltage, due to the coupling effect of the third-type bit line, will pull down the voltage of the first-type bit line faster than the voltage of the second-type bit line. This results in different initial voltage states for the bit line and the complementary bit line before compensating for the mismatch of the sense amplifier transistors, and the bias compensation phase cannot achieve a good compensation effect. The ground voltage pulling down the bit line voltage and the complementary bit line voltage during the bias compensation phase is inherent. Only subsequently will the voltages on the bit line and the complementary bit line be adjusted based on factors such as threshold voltage mismatch between different N-type and / or P-type amplifier transistors. If this inherent phenomenon of the ground voltage pulling down the bit line voltage and the complementary bit line voltage results in a large voltage difference between the bit line and the complementary bit line, the subsequent bias compensation phase may not achieve the desired effect.

[0035] Data reading, writing, and refreshing all involve a sense amplification phase. Taking data reading as an example, it generally includes a bias compensation phase, a charge sharing phase, a sense amplification phase, and a precharge phase. The bias compensation phase is typically used to eliminate voltage imbalances caused by transistor threshold voltage mismatches within the sense amplifier (SA), as well as capacitance mismatches caused by differences in parasitic capacitance between the bit line and the complementary bit line. Taking the 1T1C structure, the smallest memory cell in a memory, as an example, the charge sharing phase occurs after the word line is activated (a high activation voltage is applied to the word line). The charge in the storage capacitor is shared with the charge on the first-class bit line through the access transistor, causing the voltage on the first-class bit line to be less than or greater than the static precharge voltage (or equilibrium voltage). Since the voltage on the complementary bit line is still at the precharge voltage at this time, a voltage difference forms between the first-class bit line and the complementary bit line. The sense amplification phase involves the sense amplifier amplifying the voltages on the first-class bit line and the complementary bit line based on this voltage difference, creating a low voltage and a high voltage with a large voltage difference, facilitating data reading. The precharge phase resets the voltages on the first-class bit line and the second-class bit line to the precharge voltage.

[0036] In some embodiments, the third-type bit lines are also in a floating state during the charge sharing phase, which occurs between the bias compensation phase and the sense amplification phase. Since the voltage of the third-type bit lines needs to be pulled down by the ground voltage of the corresponding sense amplifiers during the bias compensation phase, and the third-type bit lines need to be in a floating state during the sense amplification phase, controlling the third-type bit lines to be in a floating state during the charge sharing phase also simplifies timing control.

[0037] In some embodiments, the memory section where the target active word line is located (i.e., the target memory section) and the sense amplifiers corresponding to the adjacent memory section receive bias cancellation signals with the same timing. During the bias compensation phase, the bias cancellation signals are enabled. This helps ensure that all sense amplifiers (first-type sense amplifiers and second-type sense amplifiers) corresponding to the target memory section and the adjacent memory sections enter the bias compensation phase simultaneously.

[0038] In other embodiments, the second type of sensing amplifier may be controlled to enter the bias compensation stage before the first type of sensing amplifier, or the second type of sensing amplifier and the first type of sensing amplifier may be controlled to enter the bias compensation stage simultaneously. However, within a preset period before the second type of sensing amplifier enters the bias compensation stage, at least the third type of bit line is controlled to be in a floating state, or all the bit lines connected to the second type of sensing amplifier are controlled to be in a floating state.

[0039] In some embodiments, the sense amplifiers corresponding to the target storage unit and the adjacent storage unit receive the same offset cancellation signal. It is understood that the offset compensation signal with the same timing received by the sense amplifiers corresponding to the target storage unit and the adjacent storage unit can be the same offset cancellation signal, i.e., the same offset cancellation signal is generated and sent to the first type of sense amplifier and the second type of sense amplifier, respectively. Alternatively, different offset cancellation signals can be generated based on different devices, and then sent to the first type of sense amplifier and the second type of sense amplifier, respectively, so that the generated different offset signals have the same timing.

[0040] In some embodiments, reference Figure 2 The sense amplifier SA further includes an N-type amplifier pair (i.e., a first N-type amplifier tube N1 and a second N-type amplifier tube N2), a P-type amplifier pair (i.e., a first P-type amplifier tube P1 and a second P-type amplifier tube P2), a bias cancellation tube (a first bias cancellation tube Oc1 and a second bias cancellation tube Oc2), and an isolation tube (a first isolation tube Iso1 and a second isolation tube Iso2). The first end of the first P-type amplifier tube P1 and the first end of the second P-type amplifier tube P2 are connected to a voltage node PCS, which is used to receive a power supply signal Vcc. The gate of the first P-type amplifier tube P1 and the second end of the second P-type amplifier tube P2 are connected to a first node a, and the gate of the second P-type amplifier tube P2 and the second end of the first P-type amplifier tube P1 are connected to a second node b. The first end of the first N-type amplifier tube N1 and the first end of the second N-type amplifier tube N2 are connected to a ground node NCS, which is used to receive a ground voltage Vss. The second end of the N-type amplifier transistor N1 is connected to the second node b, and the second end of the second N-type amplifier transistor N2 is connected to the first node a. The gate of the first N-type amplifier transistor N1, the first end of the first bias cancellation transistor Oc1, and the first end of the first isolation transistor Iso1 are connected to the bit line BLA. The second end of the first bias cancellation transistor Oc1 is connected to the second node b, and the second end of the first isolation transistor Oc1 is connected to the first node a. The gate of the second N-type amplifier transistor N2, the first end of the second bias cancellation transistor Oc2, and the first end of the second isolation transistor Iso2 are connected to the complementary bit line BLB. The second end of the second bias cancellation transistor Oc1 is connected to the first node a, and the second end of the second isolation transistor Iso2 is connected to the second node b. The gates of the first bias cancellation transistor Oc1 and the second bias cancellation transistor Oc2 are used to receive the bias cancellation signal Oc, and the gates of the first isolation transistor Iso1 and the second isolation transistor Iso2 are used to receive the isolation signal Iso.

[0041] In some embodiments, continue to refer to Figure 2The sense amplifier SA further includes: a first transmission transistor TR1 and a second transmission transistor TR2, wherein the first end of the first transmission transistor TR1 is used to receive the power supply signal Vcc, the second end is connected to the voltage node PCS, and the gate is used to receive the first enable signal SapEn; the second end of the second transmission transistor TR2 is used to receive the ground voltage Vss, the second end is connected to the ground node NCS, and the gate is used to receive the second enable signal SanEn; the second type of sense amplifier receives the first enable signal SapEn and the second enable signal SanEn in the enabled state during the bias compensation phase, and receives the first enable signal SapEn and the second enable signal SanEn in the disabled state during other phases.

[0042] In some embodiments, reference Figure 2 and Figure 3 The memory also includes a precharge circuit PRE. Figure 2 In the embodiment shown, the precharge circuit PRE is provided inside the sense amplifier SA. The precharge circuit PRE provides a precharge voltage Vad2 to the first node a and the second node b based on the precharge signal PreEq, thereby indirectly adjusting the voltage of the bit line BLA and the complementary bit line BLB to the precharge voltage Vad2; or Figure 3 In the embodiment shown, the precharge circuit PRE is relatively independent of the sense amplifier circuit and is directly connected to the bit line BLA and the complementary bit line BLB. The precharge circuit PRE is used to directly provide the precharge voltage Vad2 to the bit line BLA and the complementary bit line BLB based on the precharge signal PreEq.

[0043] exist Figure 2 In the illustrated embodiment, the precharge circuit PRE includes a first precharge transistor PRE1 and a second precharge transistor PRE2. One end of the first precharge transistor PRE1 is used to receive a precharge voltage Vad2, and the second end is connected to one or both of the first node a and the second node b. The two ends of the second precharge transistor PRE are respectively connected to the first node a and the second node b. The gates of the first precharge transistor PRE1 and the second precharge transistor PRE2 are both used to receive a precharge signal PreEq. In other embodiments, the precharge circuit PRE includes only the first precharge transistor PRE1 and does not include the second precharge transistor PRE2. The first precharge transistor PRE1 is connected to one or both of the first node a and the second node b.

[0044] exist Figure 3In the illustrated embodiment, the pre-charge circuit PRE includes a first pre-charge sub-circuit PC1 and a second pre-charge sub-circuit PC2. The first pre-charge sub-circuit PC1 is directly connected to the bit line BLA and is used to provide a pre-charge voltage Vad2 to the bit line BLA based on a pre-charge signal PreEq. The second pre-charge sub-circuit PC2 is directly connected to the complementary bit line BLB and is used to provide a pre-charge voltage Vad2 to the complementary bit line BLB based on the pre-charge signal PreEq.

[0045] In some embodiments, the first pre-charge sub-circuit PC1 receives a first pre-charge signal and outputs a pre-charge voltage based on the first pre-charge signal, and the second pre-charge sub-circuit receives a second pre-charge signal and outputs a pre-charge voltage based on the second pre-charge signal. The first pre-charge signal and the second pre-charge signal are relatively independent, i.e., their timings can be different. The first pre-charge sub-circuit and the second pre-charge sub-circuit can operate independently, i.e., operate with different timings, or one can operate while the other does not. When the first pre-charge sub-circuit and the second pre-charge sub-circuit can operate independently, the first pre-charge sub-circuit PC1 or the second pre-charge sub-circuit PC2 connected to the third-type bit line can be disabled to place the third-type bit line in a floating state, while the second pre-charge sub-circuit PC2 or the first pre-charge sub-circuit PC1 connected to other bit lines connected to the same sense amplifier as the third-type bit line can be enabled to maintain their voltage at the pre-charge voltage.

[0046] In some embodiments, the precharge circuits PRE corresponding to the target storage unit and the adjacent storage unit receive the same precharge signal PreEq, which helps avoid directly or indirectly applying a precharge voltage to the bit line and the complementary bit line, causing the bit line and the complementary bit line to be in a floating state.

[0047] It is understandable that in Figure 2 In the embodiment shown, the precharge circuit PRE corresponding to the storage part refers to the precharge circuit PRE inside the sense amplifier SA corresponding to the storage part, which is used to indirectly and simultaneously adjust the voltages of the bit line BLA and the complementary bit line BLB to the precharge voltage Vad2; Figure 3 In the illustrated embodiment, the precharge circuit PRE corresponding to the storage section is connected to the sense amplifier SA corresponding to the storage section via a bit line and a complementary bit line. The precharge circuit PRE is configured to directly and simultaneously adjust the voltages of the bit line BLA and the complementary bit line BLB to the precharge voltage Vad2. In other embodiments, the voltage of either the bit line BLA or the complementary bit line BLB can also be directly adjusted to the precharge voltage.

[0048] In some embodiments, the timing of the pre-charge signal PreEq and the isolation signal Iso received by any storage unit in the adjacent storage units is the same. It is understandable that the storage unit can also be specially provided with a control circuit, which is used to adjust one or both of the pre-charge signal and the isolation signal corresponding to the adjacent storage unit based on the pre-charge signal corresponding to the target storage unit, so that the pre-charge signal and the isolation signal corresponding to the adjacent storage unit have the same timing as the pre-charge signal corresponding to the target storage unit. The control circuit can be relatively independent of the generation circuit of the pre-charge signal and the isolation signal corresponding to the storage unit, and the control circuit is directly connected to the signal line that transmits the pre-charge signal and the isolation signal, thereby adjusting the voltage of the pre-charge signal and the isolation signal.

[0049] Figure 4 A timing diagram of the target storage unit and its corresponding sense amplifier and pre-charge circuit provided in an embodiment of the present application; Figure 5 A timing diagram of an adjacent storage unit of a target storage unit and its corresponding sense amplifier and precharge circuit provided in an embodiment of the present application. Figure 4 and Figure 5 The corresponding pre-charge circuit can be Figure 2 or Figure 3 The structure shown. Based on Figure 4 and Figure 5 It can be seen that the timing sequence of the storage unit includes a precharge phase PCG, an offset compensation phase OC, a charge sharing phase CS, and a sensing and amplification phase Sensing. The period when the target active word line TWL has a target activation voltage is in the charge sharing phase CS and the sensing and amplification phase Sensing. Except for the target active word line TWL, other word lines WL in the same memory bank will not be activated during the same period. For the sense amplifier SA corresponding to the target active word line TWL, the first enable signal SapEn and the second enable signal SanEn are in an enabled state during the offset compensation phase OC and the sensing and amplification phase Sensing, the voltage of the voltage node PCS is pulled high, and the voltage of the ground node NCS is pulled low. Correspondingly, for the second type of sense amplifier, the first enable signal SapEn and the second enable signal SanEn are only in an enabled state during the offset compensation phase OC to control the sense amplifier SA to enter the offset compensation state, thereby pulling down the voltages of the connected bit line BLA and complementary bit line BLB.

[0050] exist Figure 4In the embodiment, for the first type of sense amplifier, the isolation signal Iso is in an enabled state in the sensing amplification phase Sensing, so as to amplify based on the voltage difference between the bit line and the complementary bit line, and transmit the amplified result to the bit line BLA and the complementary bit line BLB; the pre-charge signal PreEq is in an enabled state only in the pre-charge phase PCG, so as to directly or indirectly limit the voltage of the bit line and the complementary bit line to the pre-charge voltage Vad2; the difference between the bias compensation signal Oc and the pre-charge signal PreEq is that the bias compensation signal Oc is also in an enabled state in the bias compensation phase OC, so as to control the sense amplifier SA to enter the bias compensation phase.

[0051] exist Figure 5 In the figure, for the second type of sensing amplifier, the isolation signal Iso is in a disabled state during the sensing amplification stage Sensing, and the sensing amplifier SA does not need to perform the sensing amplification operation; the pre-charge signal PreEq is in an enabled state only during the pre-charge stage PCG, so that the bit line is in a floating state during the charge sharing stage CS and the sensing amplification stage Sensing, reducing the coupling effect on the complementary bit line corresponding to the target activated word line TWL, wherein the timing of the pre-charge signal PreEq is the same as the timing of the isolation signal Iso, and the same timing means that they are in an enabled state or a disabled state at the same time in any stage; the difference between the bias compensation signal Oc and the pre-charge signal PreEq is that the bias compensation signal Oc is also in an enabled state during the bias compensation stage OC, so as to control the sensing amplifier SA to enter the bias compensation stage.

[0052] In the embodiment of the present disclosure, when the sensing amplifier corresponding to the target activation word line enters the bias compensation stage, the voltages of the bit line and the complementary bit line corresponding to the target activation word line will be pulled down by the ground voltage in the sensing amplifier. Since the complementary bit lines located in adjacent storage parts work at intervals, the remaining sensing amplifiers corresponding to the adjacent storage parts are controlled to enter the bias compensation stage, so that the voltages of the storage part where the target activation word line is located and all the bit lines in the adjacent storage parts are pulled down by the ground voltage in the sensing amplifier, which is beneficial to make the coupling environment of the bit line and the complementary bit line corresponding to the target activation word line the same, thereby ensuring that both the bit line and the complementary bit line can be effectively bias compensated.

[0053] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A memory control method, applied to a memory with an open bit line architecture, characterized in that: include: When the sense amplifier corresponding to the target active word line enters the bias compensation phase, the remaining sense amplifiers corresponding to the adjacent storage sections of the storage section where the target active word line is located are controlled to enter the bias compensation phase.

2. The memory control method according to claim 1, wherein: The target active word line has a corresponding complementary bit line in the adjacent storage unit, and the bit lines in the adjacent storage unit except the complementary bit line are in a floating state during a sensing amplification stage, which is located after the bias compensation stage.

3. The memory control method according to claim 1, wherein: The target activated word line has a corresponding complementary bit line located in the adjacent storage unit, and the other bit lines in the adjacent storage unit except the complementary bit line are in a floating state during the charge sharing stage, and the charge sharing stage is located between the sensing amplification stage and the bias compensation stage.

4. The memory control method according to any one of claims 1 to 3, characterized in that: The memory section where the target active word line is located and the sense amplifiers corresponding to the adjacent memory sections receive bias cancellation signals with the same timing. During the bias compensation phase, the bias cancellation signals are in an enabled state.

5. The memory control method according to claim 4, wherein: The memory section where the target activated word line is located and the sense amplifiers corresponding to the adjacent memory sections receive the same bias cancellation signal.

6. The memory control method according to claim 4, wherein: The sense amplifier comprises: a first P-type amplifier tube, a second P-type amplifier tube, a first N-type amplifier tube, a second N-type amplifier tube, a first isolation tube, a second isolation tube, a first bias elimination tube, and a second bias elimination tube; wherein, The first end of the first P-type amplifier tube and the first end of the second P-type amplifier tube are connected to a voltage node, the gate of the first P-type amplifier tube and the second end of the second P-type amplifier tube are connected to a first node, and the gate of the second P-type amplifier tube and the second end of the first P-type amplifier tube are connected to a second node; The first end of the first N-type amplifier tube and the first end of the second N-type amplifier tube are connected to a ground node, the second end of the first N-type amplifier tube is connected to the second node, the second end of the second N-type amplifier tube is connected to the first node, the gate of the first N-type amplifier tube, the first end of the first bias cancellation tube, and the first end of the first isolation tube are connected to a bit line, the second end of the first bias cancellation tube is connected to the second node, and the second end of the first isolation tube is connected to the first node; The gate of the second N-type amplifier tube, the first end of the second bias cancellation tube and the first end of the second isolation tube are connected to the complementary bit line, the second end of the second bias cancellation tube is connected to the first node, and the second end of the second isolation tube is connected to the second node; The gate of the first bias cancellation transistor and the gate of the second bias cancellation transistor are used to receive the bias cancellation signal, and the gate of the first isolation transistor and the gate of the second isolation transistor are used to receive an isolation signal.

7. The memory control method according to claim 6, wherein: The sense amplifier further includes: a first transmission tube and a second transmission tube, wherein the first end of the first transmission tube is used to receive a voltage signal, the second end is connected to the voltage node, and the gate is used to receive a first enable signal; the second end of the second transmission tube is used to receive a ground signal, the second end is connected to the ground node, and the gate is used to receive a second enable signal; The remaining sense amplifiers corresponding to the adjacent storage parts receive the first enable signal and the second enable signal in an enabled state during the bias compensation phase, and receive the first enable signal and the second enable signal in a disabled state during other phases.

8. The memory control method according to claim 6, wherein: The memory further includes a precharge circuit configured to provide a precharge voltage to the bit line and the complementary bit line based on a precharge signal, or to provide the precharge voltage to the first node and / or the second node based on the precharge signal.

9. The memory control method according to claim 8, wherein: The precharge circuits corresponding to the storage unit where the target active word line is located and the adjacent storage unit receive the same precharge signal.

10. The memory control method according to claim 9, wherein: The timing of the precharge signal and the isolation signal received by any storage unit in the adjacent storage units is the same.

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