Memory device and memory system

Abstract

The invention provides a memory device and a memory system, which have high reliability and can operate at a high speed. A memory device according to an embodiment includes: a plurality of memory cells; a word line; and a controller; each of the plurality of memory cells is configured so as to be able to store a plurality of bit data in accordance with one state included in a plurality of states having different threshold voltages, and to read out the plurality of bit data at a read-out voltage corresponding to each state, and the word line is connected to the plurality of memory cells in common, and is configured so as to be able to read out the plurality of bit data at a read-out voltage corresponding to each state. The controller can read out the plurality of memory cells and distinguish the plurality of memory cells into a plurality of first memory cells corresponding to a high-state-side threshold voltage and at least one second memory cell corresponding to a low-state-side threshold voltage, and is configured so that the number of the second memory cells is not counted. And a counter that counts the number of the first memory cells, and performs a read operation for the plurality of memory cells using a read voltage shifted from the read voltage on the basis of the counting result.

Description

Technical Field

[0001] Embodiments relate to a memory device and a memory system. Background Art

[0002] A NAND-type flash memory capable of storing data in a nonvolatile manner is known. Summary of the Invention

[0003] Provided are a memory device and a memory system having high reliability and capable of high-speed operation.

[0004] A memory device of an embodiment comprises: a plurality of memory cells; a word line; and a controller; the plurality of memory cells are respectively configured to store a plurality of bit data according to a certain state among a plurality of states having different threshold voltages, and to read the plurality of bit data with a read voltage corresponding to each state, the word line being commonly connected to the plurality of memory cells, the controller being capable of reading the plurality of memory cells and distinguishing them into a plurality of first memory cells corresponding to a threshold voltage on a high state side, and at least one second memory cell corresponding to a threshold voltage on a low state side, the controller being configured to count the number of the first memory cells instead of the second memory cells, and to perform a read operation on the plurality of memory cells using a read voltage shifted from the read voltage based on a counting result. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a block diagram showing an example of the configuration of the memory system according to the first embodiment.

[0006] Figure 2 This is a block diagram showing an example of the hardware configuration of the memory controller included in the memory system according to the first embodiment.

[0007] Figure 3 This is a block diagram showing an example of the hardware configuration of a memory device included in the memory system according to the first embodiment.

[0008] Figure 4 This is a diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the first embodiment.

[0009] Figure 5 This is a diagram showing an example of the circuit configuration of a row decoder module included in the memory device according to the first embodiment.

[0010] Figure 6 This is a diagram showing an example of the circuit configuration of a sense amplifier module and a data register included in the memory device according to the first embodiment.

[0011] Figure 7 This is a schematic diagram showing an example of threshold voltage distribution and data allocation of memory cell transistors in the memory device according to the first embodiment.

[0012] Figure 8 This is a block diagram showing an example of the configuration of a voltage adjustment unit included in the memory device according to the first embodiment.

[0013] Figure 9 This is a schematic diagram showing an overview of Vth tracking.

[0014] Figure 10 (A) and (B) are schematic diagrams showing specific examples of settings in Vth tracking.

[0015] Figure 11 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device according to the first embodiment.

[0016] Figure 12 This is a schematic diagram showing an example of an on-chip trace instruction sequence in the memory device according to the first embodiment.

[0017] Figure 13 This is a schematic diagram showing an example of an on-chip trace operation waveform of the memory device according to the first embodiment.

[0018] Figure 14 This is a schematic diagram showing an overview of count targets in the on-chip trace of the memory device according to the first embodiment.

[0019] Figure 15 This is a graph showing an example of the correspondence between the count value and the shift value in the memory device according to the first embodiment.

[0020] Figure 16 This is a diagram showing a specific example of a shift value table used in on-chip tracing of the memory device according to the first embodiment.

[0021] Figure 17 This is a diagram showing a specific example of a lookup table used in on-chip tracing of the memory device according to the first embodiment.

[0022] Figure 18 This is a schematic diagram showing an example of an on-chip trace operation waveform of the memory device according to the first modification of the first embodiment.

[0023] Figure 19 This is a schematic diagram showing an example of an on-chip trace operation waveform of a memory device according to the second modification of the first embodiment.

[0024] Figure 20 This is a block diagram showing an example of the configuration of a voltage adjustment unit included in the memory device according to the second embodiment.

[0025] Figure 21 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device according to the second embodiment.

[0026] Figure 22 This is a schematic diagram showing an example of an on-chip trace operation waveform of the memory device according to the second embodiment.

[0027] Figure 23 This is a schematic diagram showing an overview of count targets in the on-chip trace of the memory device according to the second embodiment.

[0028] Figure 24 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device according to the third embodiment.

[0029] Figure 25 This is a schematic diagram showing an example of a command sequence for a read operation using an on-chip trace result in the memory device according to the third embodiment.

[0030] Figure 26 This is a schematic diagram showing an example of an operation waveform in a read operation using an on-chip trace result of the memory device according to the third embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, each embodiment will be described with reference to the drawings.

[0032] Each embodiment illustrates an apparatus or method for embodying the technical concept of the invention. The drawings are schematic or conceptual. Illustrations of components are omitted as appropriate. Components having substantially the same function and structure are denoted by the same reference numerals. Numerals, etc., attached to reference numerals are used to reference and distinguish similar components by the same reference numerals.

[0033] <1> First embodiment

[0034] The first embodiment relates to a memory system MS configured to determine an optimal shift value of a read voltage on-chip based on the number of memory cells within a specified range. The memory system MS of the first embodiment will be described in detail below.

[0035] <1-1> Structure

[0036] First, the configuration of the memory system MS according to the first embodiment will be described.

[0037] <1-1-1> Configuration of the Memory System MS

[0038] Figure 1 1 is a block diagram showing an example of the configuration of the memory system MS according to the first embodiment. Figure 1 As shown, the memory system MS can be connected to an external host device HD (also referred to as a host). The host device HD is an electronic device such as a personal computer, a portable information terminal, or a server. The memory system MS is a storage device such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 1 and at least one memory device 2.

[0039] The memory controller 1 is a semiconductor integrated circuit configured, for example, as an SoC (System on a Chip), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Array). The memory controller 1 manages and controls the memory device 2. The memory controller 1 is connected to the host device HD via a host bus HB. The memory controller 1 is connected to the memory device 2 via a memory bus MB. The memory controller 1 can control the memory device 2 based on commands received from the host device HD. For example, the memory controller 1 can control the memory device 2 to execute read, write, and erase operations.

[0040] The memory device 2 is, for example, a semiconductor memory device configured to store data in a nonvolatile manner. The memory device 2 is, for example, a NAND flash memory. In NAND flash memory, the unit for data reading and writing is called a page. The memory device 2 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is associated with one bit line BL and one word line WL. A column address is assigned to each bit line BL, and a page address is assigned to each word line WL.

[0041] <1-1-2> Hardware Configuration of Memory Controller 1

[0042] Figure 2 1 is a block diagram showing an example of the hardware configuration of the memory controller 1 included in the memory system MS according to the first embodiment. Figure 2As shown, the memory controller 1 includes, for example, a host interface circuit (host I / F) 10, a memory interface circuit (memory I / F) 11, a CPU (Central Processing Unit) 12, an ECC (Error Correction Code) circuit 13, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 15, and a buffer memory 16. The host I / F 10, the memory I / F 11, the CPU 12, the ECC circuit 13, the ROM 14, the RAM 15, and the buffer memory 16 may be connected to an internal bus.

[0043] The host I / F 10 controls the communication between the host device HD and the memory controller 1 in accordance with the interface specification. The host I / F 10 is connected to the host device HD via the host bus HB. The host I / F 10 supports, for example, SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe TM (PCI Express, Peripheral Component Interconnect Express), NVMe TM (Non-Volatile MemoryExpress TM , non-volatile memory fast access TM ) and other interface specifications.

[0044] The memory I / F 11 controls communication in accordance with the interface standard between the memory controller 1 and the memory device 2. The memory I / F 11 is connected to the memory device 2 via the memory bus MB. The memory I / F 11 supports interface standards such as Toggle DDR and ONFI (Open NAND Flash Interface).

[0045] The CPU 12 is a processor that controls the overall operation of the memory controller 1. In response to a write request received via the host I / F 10, the CPU 12 instructs the memory device 2 to write data via the memory I / F 11. In response to a read request received via the host I / F 10, the CPU 12 instructs the memory device 2 to read data via the memory I / F 11.

[0046] The ECC circuit 13 is a circuit that performs ECC processing. The ECC processing includes encoding and decoding of data. The ECC circuit 13 encodes data to be written to the memory device 2 and decodes data to be read from the memory device 2.

[0047] ROM14 is a non-volatile memory. ROM14 stores programs such as firmware. ROM14 is an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory) The CPU 12 executes firmware stored in the ROM 14 or the like to perform various processes.

[0048] The RAM 15 is a volatile memory and is used as a work area for the CPU 12. The RAM 15 is, for example, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0049] The buffer memory 16 is, for example, a volatile memory. The buffer memory 16 temporarily stores data received via the host I / F 10 or data received via the memory I / F 11. The buffer memory 16 is, for example, a DRAM or an SRAM. The buffer memory 16 may be mounted outside the memory controller 1.

[0050] <1-1-3> Hardware Configuration of Memory Device 2

[0051] Figure 3 1 is a block diagram showing an example of the configuration of the memory device 2 included in the memory system MS according to the first embodiment. Figure 3 As shown, the memory device 2 includes, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a register circuit 23, a sequencer 24, a standby / busy controller 25, a driver circuit 26, a row decoder module 27, a data register 28, a sense amplifier module 29, and a voltage regulator 30. Signals transmitted and received via the memory bus MB include, for example, input / output signals I / O0-I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a standby / busy signal RBn.

[0052] The memory cell array 20 is a collection of multiple memory cell transistors MT. The memory cell array 20 includes multiple blocks BLK0 to BLKn ("n" is an integer greater than or equal to 1). Blocks BLK are used, for example, as units for data erase operations. Each block BLK is assigned a block address. The memory cell array 20 is provided with multiple bit lines BL0 to BLm ("m" is an integer greater than or equal to 1) and multiple word lines WL (not shown).

[0053] The input / output circuit 21 controls the transmission and reception (input and output) of input / output signals I / O0-I / O7. The input / output signals I / O may include, for example, data DAT, status information, addresses, and commands. The input / output circuit 21 can input and output data DAT between the data register 28 and the memory controller 1. The input / output circuit 21 can output status information transmitted from the register circuit 23 to the memory controller 1. The input / output circuit 21 can also output addresses and commands transmitted from the memory controller 1 to the register circuit 23.

[0054] The logic controller 22 controls the input / output circuit 21 and sequencer 24 based on various control signals input from the memory controller 1. The logic controller 22 activates the memory device 2 based on the control signal CEn. Based on the control signals CLE and ALE, the logic controller 22 notifies the input / output circuit 21 that the input / output signals I / O received by the memory device 2 are commands and addresses, respectively. Based on the control signal WEn, the logic controller 22 instructs the input / output circuit 21 to receive the input / output signals I / O, and based on the control signal REn, instructs the input / output circuit 21 to transmit the input / output signals I / O. Based on the control signal WPn, the logic controller 22 places the memory device 2 in a protected state.

[0055] Register circuit 23 temporarily stores status, addresses, and instructions. Status is information indicating the operating state of memory device 2. This status is updated based on control by sequencer 24 and transmitted to memory controller 1 via input / output circuit 21. Addresses can include block addresses, page addresses, column addresses, and the like. Instructions include commands related to various operations of memory device 2.

[0056] The sequencer 24 is a controller that controls the overall operation of the memory device 2. Based on the instructions and addresses stored in the register circuit 23, the sequencer 24 performs read operations, write operations, and erase operations. Furthermore, the sequencer 24 can read multiple memory cell transistors MT and separate them into multiple memory cell transistors MT corresponding to a high-state threshold voltage and at least one memory cell transistor MT corresponding to a low-state threshold voltage. Furthermore, the sequencer 24 can perform on-chip tracking, which includes deriving a preferred shift value for the read voltage and performing a read operation using the derived shift value. Details of on-chip tracking are described below.

[0057] The standby / busy controller 25 generates a standby / busy signal RBn under the control of the sequencer 24. The standby / busy signal RBn notifies the memory controller 1 whether the memory device 2 is in the standby state or the busy state. The standby state indicates that the memory device 2 can accept commands from the memory controller 1, and is indicated by a high-level standby / busy signal RBn. The busy state indicates that the memory device 2 cannot accept commands from the memory controller 1, and is indicated by a low-level standby / busy signal RBn.

[0058] The driver circuit 26 generates voltages to be used in a read operation, a write operation, an erase operation, etc. The driver circuit 26 supplies the generated voltages to the row decoder module 27 or the sense amplifier module 29 .

[0059] The row decoder module 27 is a circuit used to select blocks BLK and supply voltages to wiring such as word lines WL. The row decoder module 27 includes multiple row decoders RD0 through RDn. Row decoders RD0 through RDn are associated with blocks BLK0 through BLKn, respectively. Each row decoder RD can select or deselect its associated block BLK based on the block address.

[0060] The data register 28 is a circuit that temporarily stores data DAT. The data register 28 is used, for example, to input and output data DAT between the input / output circuit 21 and the sense amplifier module 29. Furthermore, during on-chip tracking, the data register 28 outputs data read from the memory cell array 20 to the voltage adjustment unit 30. The data register 28 may also be referred to as a data latch, a page register, or a cache memory.

[0061] Sense amplifier module 29 is a circuit used to supply voltage to each bit line BL or read data. Sense amplifier module 29 includes multiple sense amplifier components SAU0 through SAUm. Sense amplifier components SAU0 through SAUm are associated with multiple bit lines BL0 through BLm, respectively. Each sense amplifier component SAU can determine the data read from the selected memory cell transistor MT based on the voltage of its associated bit line BL.

[0062] The voltage adjustment unit 30 has a function of determining a preferred shift value of the read voltage during on-chip tracking based on an instruction from the sequencer 24 and data DAT transferred from the data register 28. The detailed configuration of the voltage adjustment unit 30 will be described below.

[0063] In memory device 2, a group of memory cell array 20, row decoder module 27, and sense amplifier module 29 can also be referred to as a layer. A layer includes at least memory cell array 20. Memory device 2 can include multiple layers. Sequencer 24 can be configured to control each of the multiple layers.

[0064] Hereinafter, an example of a detailed circuit configuration of the memory cell array 20 , the row decoder module 27 , the data register 28 , and the sense amplifier module 29 will be described.

[0065] (1: Circuit Configuration of Memory Cell Array 20)

[0066] Figure 4 This is a diagram showing an example of the circuit configuration of the memory cell array 20 according to the first embodiment. Figure 4 FIG. 2 shows one of the plurality of blocks BLK included in the memory cell array 20. Figure 4 As shown, in a block BLK, multiple bit lines BL0 to BLm, multiple word lines WL0 to WL7, select gate lines SGD0 to SGD4, select gate line SGS, and source line SL are provided. Select gate lines SGD0 to SGD4 and SGS, as well as word lines WL0 to WL7, are provided for each block BLK. Bit lines BL0 to BLm are shared by multiple blocks BLK. Source line SL can be shared by multiple blocks BLK or provided for each block BLK.

[0067] For example, a block BLK includes five string units SU0-SU4. Each string unit SU includes multiple NAND strings NS. Each of these NAND strings NS is associated with a bit line BL0-BLm. That is, each bit line BL is shared by the NAND strings NS assigned the same column address across multiple blocks BLK. Each NAND string NS is connected between its associated bit line BL and a source line SL.

[0068] Each NAND string NS includes, for example, memory cell transistors MT0-MT7 and select transistors STD and STS. Each memory cell transistor MT is a memory cell having a control gate and a charge accumulation layer, and stores data in a non-volatile manner. The threshold voltage of the memory cell transistor MT can be changed based on, for example, the amount of charge injected into the charge accumulation layer. The memory cell transistor MT stores data corresponding to the threshold voltage. The select transistors STD and STS are used to select the string unit SU, respectively.

[0069] In each NAND string NS, the select transistor STD, memory cell transistors MT7 to MT0, and select transistor STS are connected in series. Specifically, the drain of the select transistor STD is connected to the bit line BL associated with it. The source of the select transistor STD is connected to the drain of the memory cell transistor MT7. The drain of the select transistor STS is connected to the source of the memory cell transistor MT0. The source of the select transistor STS is connected to the source line SL. The memory cell transistors MT0 to MT7 are connected in series between the select transistors STD and STS.

[0070] Select gate lines SGD0-SGD4 are associated with string units SU0-SU4, respectively. Each select gate line SGD is connected to the gates of the multiple select transistors STD included in the associated string unit SU. Select gate line SGS is connected to the gates of the multiple select transistors STS included in the associated block BLK. Word lines WL0-WL7 are connected to the control gates of the multiple memory cell transistors MT0-MT7 included in the associated block BLK.

[0071] In this specification, the collection of multiple memory cell transistors MT commonly connected to a word line WL within a string unit SU is referred to as a unit unit CU. In this specification, the collection of one bit of data stored by each of the multiple memory cell transistors MT included in the unit unit CU is referred to as page data. A unit unit CU can store two or more pages of data, depending on the number of bits of data stored by each memory cell transistor MT.

[0072] Furthermore, the memory cell array 20 may have circuit configurations other than those described above. For example, the number of string units SU included in each block BLK or the number of memory cell transistors MT and select transistors STD and STS included in each NAND string NS may be designed to be any number.

[0073] (2: Circuit Configuration of Row Decoder Module 27)

[0074] Figure 5 This is a diagram showing an example of the circuit configuration of the row decoder module 27 according to the first embodiment. Figure 5The connection relationship between the driver circuit 26 and the memory cell array 20 and the row decoder module 27, as well as the detailed circuit structure of one row decoder RD0 are shown. In addition, the circuit structure of the row decoders RD other than the row decoder RD0 is similar to that of the row decoder RD0. Figure 5 As shown, each row decoder RD is connected to signal lines CG0-CG7, SGDD0-SGDD4, SGSD, USGD, and USGS connected to the driver circuit 26. In addition, each row decoder RD is connected to word lines WL0-WL7 and select gate lines SGD0-SGD4 and SGS of the associated block BLK.

[0075] Row decoder RD0, for example, includes transistors TR0-TR19, transfer gate lines TG and bTG, and a block decoder BD. Transistors TR0-TR19 are each N-type high-voltage transistors. Transfer gate line TG is connected to the gates of transistors TR0-TR13. Transfer gate line bTG is connected to the gates of transistors TR14-TR19. The drains of transistors TR0-TR13 are connected to signal lines SGSD, CG0-CG7, and SGDD0-SGDD4, respectively. The sources of transistors TR0-TR13 are connected to select gate line SGS, word lines WL0-WL7, and select gate lines SGD0-SGD4 of block BLK0, respectively. The drain and source of transistor TR14 are connected to signal line USGS and select gate line SGS of block BLK0, respectively. The drains of transistors TR15-TR19 are connected to signal line USGD. The sources of transistors TR15-TR19 are connected to select gate lines SGD0-SGD4 of block BLK0, respectively.

[0076] The block decoder BD is a circuit that decodes the block address. Based on the decoded block address, the block decoder BD applies a high-level voltage to the transmission gate line TG and a low-level voltage to the transmission gate line bTG. Specifically, the block decoder BD of the selected block BLK applies a high-level voltage to the transmission gate line TG and a low-level voltage to the transmission gate line bTG. The block decoders BD of the unselected blocks BLK apply a low-level voltage to the transmission gate line TG and a high-level voltage to the transmission gate line bTG. Consequently, the voltages of the signal lines CG0 to CG7 are applied to the word lines WL0 to WL7 of the selected block BLK, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are applied to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, and the voltages of the signal lines USGD and USGS are applied to the select gate lines SGD and SGS of the unselected blocks BLK.

[0077] Furthermore, the row decoder module 27 may also have circuit configurations other than those described above. For example, the number of transistors TR included in the row decoder module 27 may be appropriately modified based on the number of wiring lines in each block BLK. Signal line CG is shared by multiple blocks BLK and is therefore also referred to as a global word line. Word line WL is provided for each block and is therefore also referred to as a local word line. Signal lines SGDD and SGSD are shared by multiple blocks BLK and are therefore also referred to as global transfer gate lines. Select gate lines SGD and SGS are provided for each block and are therefore also referred to as local transfer gate lines.

[0078] (3: Circuit Configuration of Sense Amplifier Module 29 and Data Register 28)

[0079] Figure 6 1 is a diagram showing an example of the circuit configuration of the sense amplifier module 29 and the data register 28 according to the first embodiment. Figure 6 As shown, each sense amplifier element SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, bus lines DBUS and LBUS, latch circuits SDL, ADL, BDL, CDL, and DDL, an operation unit OP, and a transistor T0. Data register 28 includes a plurality of latch circuits XDL0 through XDLm. Latch circuits XDL0 through XDLm are associated with sense amplifier elements SAU0 through SAUm, respectively. Latch circuits XDL0 through XDLm are connected to their associated sense amplifier elements SAU via bus line DBUS.

[0080] The bit line connection portion BLHU is a protection circuit that prevents a high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the sense amplifier portion SA. The bit line connection portion BLHU may also be configured to apply a predetermined voltage to unselected bit lines BL.

[0081] The sense amplifier unit SA is a circuit used to determine data based on the voltage of the bit line BL or to apply a voltage to the bit line BL. Each sense amplifier unit SA is connected to its associated bit line BL via a bit line connection unit BLHU. When the control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" bit data or "1" bit data based on the voltage of the associated bit line BL. The control signal STB is generated, for example, by the sequencer 24.

[0082] Each of the latch circuits SDL, ADL, BDL, CDL, and DDL can temporarily store data. The latch circuits SDL, ADL, BDL, CDL, and DDL and the sense amplifier unit SA are configured to be able to transmit and receive data via the bus line LBUS.

[0083] The operation unit OP performs various logic operations using data stored in the latch circuits SDL, ADL, BDL, CDL, and DDL. In addition, the sense amplifier element SAU may also include an operation circuit that performs various logic operations instead of the operation unit OP.

[0084] The transistor T0 of each sense amplifier assembly SAU controls signal transmission between the associated buses DBUS and LBUS. One end of the transistor T0 of each sense amplifier assembly SAU is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier assembly SAU is connected to the associated bus LBUS. A control signal DSW is input to the gate of the transistor T0 of each sense amplifier assembly. The control signal DSW is generated, for example, by the sequencer 24.

[0085] Each latch circuit XDL can temporarily store data. Each latch circuit XDL is configured to transmit and receive data to and from a sense amplifier assembly SAU associated with it via a bus DBUS. Each latch circuit XDL is used to input and output data DAT between the sense amplifier module 29 and the input / output circuit 21. Each latch circuit XDL can also be shared by multiple sense amplifier assemblies SAU.

[0086] Furthermore, the sense amplifier module 29 may have a circuit configuration other than that described above. For example, the number of latch circuits included in each sense amplifier unit SAU may be appropriately changed. The operation unit OP may also be omitted from the sense amplifier unit SAU.

[0087] <1-1-4> Threshold Voltage Distribution of Memory Cell Transistor MT

[0088] Figure 7 This is a diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistors MT in the memory system MS of the first embodiment. The vertical axis "NMTs" represents the number of memory cell transistors MT. The horizontal axis "Vth" represents the threshold voltage of the memory cell transistor MT. Figure 7 As shown, when each memory cell transistor MT stores 4 bits of data (4 bits / cell), for example, the threshold voltage distribution of the plurality of memory cell transistors MT forms 16 states. Since the data written to each unit cell CU is randomized, the memory cell transistors MT are roughly evenly distributed in the 16 states. In other words, the plurality of memory cell transistors MT can be read by the sequencer 24 and distinguished into a plurality of memory cell transistors MT corresponding to a threshold voltage on the high side and at least one memory cell transistor MT corresponding to a threshold voltage on the low side.

[0089] In this specification, these 16 states are referred to as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, in ascending order of threshold voltage. Each memory cell transistor MT in each of the S0 to S15 states is assigned a different 4-bit data. Furthermore, each memory cell transistor MT may store 2 bits, 3 bits, or 5 bits or more of data, or may be assigned data different from that described below. The operations described below can also be applied to situations where the memory cell transistor MT stores multiple bits of data.

[0090] The following shows an example of data allocation for memory cell transistors MT belonging to each of the 16 states. Furthermore, the 4-bit data stored in each memory cell transistor MT is also referred to as the most significant bit data, upper bit data, middle bit data, and lower bit data. Furthermore, a page of data consisting of the most significant bit data, upper bit data, middle bit data, and lower bit data stored by each of the plurality of memory cell transistors MT included in each unit unit CU is also referred to as the most significant page data, upper page data, middle page data, and lower page data, respectively.

[0091] S0 state: "1111 (most significant bit data / upper significant bit data / middle significant bit data / lower significant bit data)" data

[0092] S1 status: "0111" data

[0093] S2 status: "0011" data

[0094] S3 status: "1011" data

[0095] S4 status: "1001" data

[0096] S5 status: "1000" data

[0097] S6 status: "1010" data

[0098] S7 status: "0010" data

[0099] S8 status: "0110" data

[0100] S9 status: "0100" data

[0101] S10 status: "0000" data

[0102] S11 status: "0001" data

[0103] S12 status: "0101" data

[0104] S13 status: "1101" data

[0105] S14 status: "1100" data

[0106] S15 status: "1110" data

[0107] Read voltages are set between adjacent states. Specifically, read voltage R1 is set between the S0 and S1 states. Read voltage R2 is set between the S1 and S2 states. Similarly, read voltages R3 to R15 are set between adjacent states. That is, read voltage Rj ("j" is an integer between 1 and 15) is set between the S(j-1) and Sj states. Furthermore, read pass voltage VREAD is set to a voltage higher than the state with the highest threshold voltage (e.g., the S15 state).

[0108] A read voltage is applied to the word line WL selected for the read operation. The memory cell transistors MT included in the cell unit CU of the selected word line WL for the read operation are turned on when their threshold voltage is lower than the applied read voltage. A read pass voltage VREAD is applied to unselected word lines WL. The memory cell transistors MT connected to the word line WL to which the read pass voltage VREAD is applied remain turned on regardless of the stored data.

[0109] In application Figure 7 In the data allocation shown, lower page data is determined by a read operation using read voltages R5, R11, and R14. Middle page data is determined by a read operation using read voltages R4, R6, R9, and R15. Upper page data is determined by a read operation using read voltages R2, R8, R10, and R12. Uppermost page data is determined by a read operation using read voltages R1, R3, R7, and R13. In the page data read operation using multiple read voltages, arithmetic processing is appropriately performed within the sense amplifier unit SAU.

[0110] also, Figure 7 The data allocation shown is also called 3-4-4-4 encoding because the lower, middle, upper, and uppermost pages are read three, four, four, and four times, respectively. The uppermost bit data and the uppermost page can also be called the highest bit and the highest page, respectively.

[0111] <1-1-5> Configuration of Voltage Regulator 30

[0112] Figure 8 1 is a block diagram showing an example of the configuration of the voltage adjustment unit 30 included in the memory device 2 according to the first embodiment. Figure 8As shown, the voltage adjustment unit 30 includes, for example, a calculation circuit 31 , a counter 32 , a table selection unit 33 , a table storage register 34 , and a table number storage register 35 .

[0113] The arithmetic circuit 31 is a circuit capable of performing an exclusive OR (XOR) operation on the data received from the data register 28. Specifically, the arithmetic circuit 31 receives the result of the first read operation and the result of the second read operation from the data register 28. Next, the arithmetic circuit 31 performs an XOR operation on the result of the first read operation and the result of the second read operation. At this time, the arithmetic circuit 31 performs an XOR operation on the data determined by the same sense amplifier unit SAU. In addition, the arithmetic circuit 31 includes a reduction mechanism capable of performing a reduction process on the data received from the data register 28. The reduction mechanism reduces the amount of data received from the data register 28 through the reduction process. The amount of data reduction achieved through the reduction process is designed based on the performance of the counter 32. For example, when the counter 32 is an 8-bit counter, the reduction mechanism is configured to reduce the data received from the data register 28 to 1 / 16 through the reduction process.

[0114] The counter 32 receives the result of the XOR operation from the operation circuit 31 . The counter 32 then counts the number of “1” bit data included in the received result of the XOR operation and outputs the count result to the table selection unit 33 .

[0115] The table selection unit 33 uses the information in the lookup table 342 to select an index number in the shift value table 341 corresponding to the preferred shift value for the read voltage, based on the count result (count value) received from the counter 32. The table selection unit 33 then writes the selected index number to the table number storage register 35. Furthermore, the table selection unit 33 outputs the information corresponding to the selected index number in the shift value table 341 to the sequencer 24. The sequencer 24 can perform a read operation based on the information in the shift value table 341 received from the table selection unit 33.

[0116] Table storage register 34 stores a shift value table 341 and a lookup table 342. Shift value table 341 stores information related to the shift value of the read voltage for each of a plurality of index numbers. Lookup table 342 stores information associating the index numbers in shift value table 341 with the count results of counter 32. Values ​​in shift value table 341 and lookup table 342 are, for example, values ​​read from a designated ROM area in memory device 2.

[0117] The table number storage register 35 stores the index number of the shift value table 341 selected by the table selection unit 33. The table number storage register 35 can manage the index number for each specified group. For example, the table number storage register 35 can be configured so that the same index number is shared by each block BLK or each word line WL. The operation when the index number is shared will be described in the third embodiment.

[0118] Furthermore, the shift value table 341 or the lookup table 342 is created based on data obtained from, for example, a previously performed stress test. Furthermore, the created shift value table 341 and the lookup table 342 are set in a designated storage area (ROM area) of the memory cell array 20 before the memory device 2 is shipped. In the voltage adjustment unit 30, the reduction process performed by the reduction mechanism of the arithmetic circuit 31 can also be performed after performing the XOR operation. The reduction mechanism can also be omitted from the arithmetic circuit 31 of the voltage adjustment unit 30. In this case, the reduction process is performed by reducing the data transferred from the data register 28 to the arithmetic circuit 31 without using the arithmetic circuit 31. Furthermore, the reduction process can also be performed during reading. When the reduction process is performed during reading, the reading time can be shortened as the amount of data to be read decreases. This is not limited to this, and the memory device 2 of the first embodiment can be configured to perform the reduction process.

[0119] <1-2>Action

[0120] Next, the operation of the memory system MS according to the first embodiment will be described.

[0121] <1-2-1> Overview of Vth Tracking

[0122] First, let's explain the overview of Vth tracking. Vth tracking is the process of finding the valley positions of two adjacent states (hereinafter referred to as adjacent states) and estimating the optimal read voltage. The optimal read voltage is the read voltage value that minimizes the number of error bits (failed bits) during read operations. Vth tracking is also called a tracking operation. Figure 9 This is a schematic diagram showing the outline of Vth tracking. The vertical axis "NMTs" represents the number of memory cell transistors MT. The horizontal axis "Vth" represents the threshold voltage of the memory cell transistor MT. Figure 9 The vicinity of the valley position in the adjacent state and elements related to Vth tracking are shown.

[0123] like Figure 9As shown, in Vth tracking, multiple shift reads are first performed according to the setting of the pre-set read voltage. Each shift read is a read operation that specifies the amount of voltage shift from the starting read level. The number of times the shift read is performed corresponds to the number of sampling times. The number of sampling times in this example is 7. In addition, the location where sampling (shift read) is performed is represented as a sampling point. The shift amount is specified by a DAC (Digital Analog Converter) value, for example. In the multiple shift reads in Vth tracking, multiple read levels set at equal intervals are used. The interval between adjacent read levels corresponds to the sampling step size, which is equivalent to the voltage width between samples.

[0124] Next, the number of memory cell transistors MT that are turned on at each read level (hereinafter referred to as the number of turned-on cells) is counted, and the difference in the number of turned-on cells at two adjacent read levels is calculated. Then, a histogram of the number of turned-on cells obtained by counting is generated, and the point where the curve of the difference in the number of turned-on cells bulges downward, that is, the point where the difference in the number of turned-on cells becomes minimal, is extracted (minimum value detection). Then, the ratio of the two differences adjacent to the minimum point is calculated, and the voltage difference (potential difference) of the two read levels adjacent to the minimum point is internally divided by the calculated ratio (internal division ratio processing). The voltage thus obtained is estimated to be the preferred read voltage. The series of processes of Vth tracking can be performed on-chip using the memory device 2, for example, without passing through the memory controller 1.

[0125] Furthermore, to enable high-speed Vth tracking of the memory device 2, the number of sampling times is preferably small. During Vth tracking, the sampling start point, sampling step size, and number of sampling times can be adjusted through register settings. The register settings for Vth tracking are determined based on the results of prior stress evaluation using a representative memory device 2, for example. Figure 10 It is a schematic diagram showing a specific example of the setting in Vth tracking. Figure 10 (A) and (B) in FIG. 3 exemplify the case where the number of sampling times is 7 and the sampling step sizes are different in the setting of Vth tracking.

[0126] In the case of ensuring a larger sampling range with fewer sampling times, consider Figure 10 As shown in (A), the sampling step size is set to be larger ( Figure 10 (The sampling step size is larger than the sampling step size). In this case, the sampling range is more likely to include valley positions in adjacent states, making it possible to cope with changes in threshold voltage distribution under various pressures. On the other hand, the accuracy of the internal ratio processing may be reduced, resulting in a decrease in the accuracy of the estimated preferred read voltage.

[0127] On the other hand, in order to maintain the estimation accuracy of the preferred read voltage, it is considered that Figure 10As shown in (B), the sampling step size is set to be smaller ( Figure 10 (The sampling step size is small.) However, if the sampling step size is reduced, the sampling range becomes smaller, and the sampling range is more likely to not include the valley position of the adjacent state. In other words, with a small number of samples and a small sampling step size, it may not be possible to cope with the changes in the threshold voltage distribution under various pressures. In other words, it may not be possible to maintain tolerance to various pressures.

[0128] Therefore, in Vth tracking, a certain number of sampling times or more is necessary to achieve a balance between optimal read voltage estimation accuracy and maintaining stress tolerance. However, considering the time required to read data from the memory cell array 20 to the data register 28, there may be upper limits or combination constraints when setting the sampling step size and sampling times. For example, it is difficult to adjust the sampling times and sampling step size to a sufficient degree without changing the sampling range.

[0129] Therefore, it is desirable to achieve high-speed Vth tracking while maintaining both the estimation accuracy of the preferred read voltage and the stress tolerance. Therefore, the memory device 2 of the first embodiment performs on-chip tracking that can estimate the preferred read voltage with a small number of sampling times.

[0130] <1-2-2> On-chip tracking

[0131] During on-chip tracking, the memory device 2 of the first embodiment counts the number of memory cells in a state corresponding to a higher state (e.g., the S15 state) among multiple states, and based on the count result, performs a read operation on the multiple memory cells using a shifted read voltage. The details of on-chip tracking in the memory device 2 of the first embodiment are described below.

[0132] (1: On-chip trace processing flow)

[0133] Figure 11 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device 2 according to the first embodiment. When the memory device 2 according to the first embodiment receives the address of the page to be read and the instruction to execute on-chip trace from the memory controller 1, for example, Figure 11 A series of processing.

[0134] First, the memory device 2 performs RL1 read (step ST11). RL1 read is a read operation using read voltage RL1. RL1 read corresponds to single-state read of the first read point. Read voltage RL1 is set to overlap the highest state (e.g., S15 state), for example.

[0135] Next, memory device 2 performs an RL2 read (step ST12). The RL2 read is a read operation using read voltage RL2. The RL2 read corresponds to a single-state read at a second read point, which is different from the first read point. Read voltage RL2 is set, for example, to a voltage that overlaps with the highest state (e.g., the S15 state) and is higher than read voltage RL1.

[0136] Next, the memory device 2 performs an XOR operation on the result read out of RL1 and the result read out of RL2 (step ST13). In step ST13, the XOR operation using the result read out of RL1 and the result read out of RL2 is performed on each corresponding sense amplifier element SAU.

[0137] Next, the memory device 2 uses a reduction mechanism to count the number of "1" bits (the amount of "1"-bit data) in the XOR operation result (step ST14). The reduction mechanism adjusts the reduction amount so that a maximum of 255 bits is estimated, for example. Next, the counter 32 counts the number of "1" bits contained in the reduced XOR operation result. Furthermore, during the processing of step ST14, the counter 32 is controlled to prevent overflow. For example, if the counter 32 is an 8-bit counter, the count value is stopped at 255 counts.

[0138] Next, the memory device 2 selects a table number based on the count value and the lookup table 342 (step ST15 ). Specifically, the table selection unit 33 uses the lookup table 342 to select the table number (index number) of the shift value table 341 corresponding to the count value of step ST14 .

[0139] Next, the memory device 2 stores the selected table number in the table number storage register 35 (step ST16). In step ST16, if a table number associated with the same address is already stored in the table number storage register 35, the newly selected table number is overwritten.

[0140] Next, the memory device 2 performs a read operation using the shift value corresponding to the selected table number (step ST17). That is, the sequencer 24 derives the preferred read voltage to be used based on the shift value corresponding to the selected table number and performs a read operation using the preferred read voltage.

[0141] While the above description describes the use of shift value table 341 and lookup table 342 to determine the preferred shift value for the read voltage, this is not limiting. The memory device 2 of the first embodiment may also be configured to determine the shift value for the read voltage by performing a calculation using a linear equation, for example, using the count value in step ST14 as a variable. Alternatively, the XOR operation may be performed using the operation unit OP of each sense amplifier element SAU. In this case, the data obtained by the XOR operation is transferred to the data register 28 and, after being reduced, is output to the counter 32.

[0142] (2: Instruction sequence)

[0143] Figure 12 This is a schematic diagram showing an example of an instruction sequence of on-chip trace in the memory device 2 according to the first embodiment. Figure 12 , the input / output signal I / O and the standby / busy signal RBn when on-chip trace is executed are shown. Note that before the operation starts, the standby / busy signal RBn is "H" (high level: standby state).

[0144] like Figure 12 As shown, first, the memory controller 1 sends the instruction "xxh", the instruction "yyh", the instruction "00h", the address "ADD", and the instruction "30h" to the memory device 2 in sequence. The instruction "xxh" is an instruction that instructs the use of on-chip tracking. The instruction "yyh" is an instruction that instructs an action corresponding to a specific page. The instruction "yyh" changes according to the page to be read. The instruction "00h" is an instruction that instructs a read action. The address "ADD" can include information such as the block BLK, string component SU, and word line WL to be read. The address "ADD" can be sent through multiple cycles. The instruction "30h" is an instruction that instructs the memory device 2 to start a read action based on the instruction and address stored in the register circuit 23.

[0145] If the register circuit 23 stores the instruction "30h", the sequencer 24 changes the memory device 2 from the standby state (RBn="H") to the busy state (RBn="L" (low level: busy state)) and starts on-chip tracing. Figure 12 In FIG, the period during which on-chip tracing is performed is represented by tR.

[0146] When on-chip tracing is complete, the sequencer 24 switches the memory device 2 from the busy state to the standby state. Upon detecting the completion of the read operation based on a change in the standby / busy signal RBn, the memory controller 1 sequentially outputs the read results (data DAT) to the memory device 2 by, for example, switching the control signal REn.

[0147] (3: On-chip tracking waveform)

[0148] Figure 13 This is a schematic diagram showing an example of an operation waveform during on-chip tracing of the memory device 2 according to the first embodiment. Figure 13 , the voltage of the selected word line WLsel and the control signal STB are shown. Note that in the initial state before the operation begins, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). The following describes the case of performing on-chip tracking for the following bit pages.

[0149] like Figure 13 As shown, the period for performing on-chip tracking in the first embodiment includes three periods: P1, P2, and P3. Period P1 corresponds to a period during which a readout operation (sampling) is performed, collecting information for selecting a preferred shift value for the readout voltage. Period P2 corresponds to a period during which a preferred shift value for the readout voltage is selected based on the information collected during period P1. Period P3 corresponds to a period during which a readout operation is performed using a preferred readout voltage based on the preferred shift value for the readout voltage selected during period P2.

[0150] Specifically, during period P1, the sequencer 24 applies a read pass voltage VREAD (not shown) to the unselected word lines WL. Furthermore, the sequencer 24 applies a read voltage RL1 to the selected word line WLsel, thereby activating the control signal STB. The read result is then stored in any latch circuit of each sense amplifier element SAU ( Figure 11 Then, the sequencer 24 applies the read voltage RL2 to the selected word line WLsel, and makes the control signal STB effective. Then, the read result is stored in any latch circuit of each sense amplifier unit SAU ( Figure 11 Step ST12).

[0151] During period P2, the sequencer 24 controls the voltage adjustment unit 30 to select a preferred shift value ( Figure 11 Steps ST13 to ST16).

[0152] During period P3, sequencer 24 applies a read pass voltage VREAD (not shown) to unselected word lines WL. Sequencer 24 also sequentially applies preferred read voltages R5sft, R11sft, and R14sft to the selected word line WLsel. Control signal STB is asserted during each period in which preferred read voltages R5sft, R11sft, and R14sft are applied. Preferred read voltage R5sft is read voltage R5 obtained by applying a preferred shift value to a reference value of read voltage R5. Preferred read voltage R11sft is read voltage R11 obtained by applying a preferred shift value to a reference value of read voltage R11. Preferred read voltage R14sft is read voltage R14 obtained by applying a preferred shift value to a reference value of read voltage R14. Sequencer 24 determines the lower page data based on the read results using preferred read voltages R5sft, R11sft, and R14sft. Next, the sequencer 24 stores the determined data in the data register 28 .

[0153] The operations described above can also be performed in the same manner when executing on-chip tracing with another page selected.

[0154] (4: Overview of Counting Objects)

[0155] Figure 14 This is a schematic diagram showing an overview of count targets in on-chip tracing of the memory device 2 according to the first embodiment. Figure 14 The corresponding relationship between the S14 state and the S15 state in the threshold voltage distribution of the memory cell transistor MT, the result of RL1 reading, the result of RL2 reading, and the XOR operation result is shown. Figure 14 As shown, in this example, the read voltages RL1 and RL2 are set so as to overlap with the S15 state which is the highest state.

[0156] In RL1 reading, "1" bit data is read from memory cell transistors MT having a threshold voltage equal to or lower than read voltage RL1, and "0" bit data is read from memory cell transistors MT having a threshold voltage higher than read voltage RL1. In RL2 reading, "1" bit data is read from memory cell transistors MT having a threshold voltage equal to or lower than read voltage RL2, and "0" bit data is read from memory cell transistors MT having a threshold voltage higher than read voltage RL2.

[0157] As a result, the XOR operation result of the result read out by RL1 and the result read out by RL2 becomes "0" bit data in the memory cell transistor MT whose threshold voltage is lower than the read voltage RL1, becomes "1" bit data in the memory cell transistor MT whose threshold voltage is higher than the read voltage RL1 and lower than the read voltage RL2, and becomes "0" bit data in the memory cell transistor MT whose threshold voltage is higher than the read voltage RL2. Therefore, Figure 11 The counted objects in the process of step ST14 correspond to the number of memory cell transistors MT whose threshold voltage is higher than the read voltage RL1 and lower than the read voltage RL2 (the number of “1” bit data).

[0158] Furthermore, in the first embodiment, the number of memory cell transistors MT to be counted is less than the number corresponding to one page of data. Furthermore, for example, the width of the S15 state falls within a range slightly larger than 40 DAC. When the reduction mechanism reduces the 16 kilobytes of read data, including parity, to 1 / 16 and outputs it, the S15 state includes approximately 500 bits. In contrast, by setting the read voltage RL2 to a voltage value corresponding to the read voltage RL2 + 8 DAC, for example, it is expected that the count value will not exceed 255 bits. By appropriately setting the range of the read voltages RL1 and RL2 in this manner, it is possible to achieve optimal read voltage accuracy and increased on-chip tracking speed.

[0159] (5: Correspondence between counting results and shift values)

[0160] Figure 15 This is a graph showing an example of the correspondence between the count value and the shift value in the memory device 2 of the first embodiment. The vertical axis represents the preferred shift value of the read voltage. The horizontal axis represents Figure 11 The count value in the process of step ST14. Figure 15 The relationship between the count value and the shift value at each of the read voltages R4 , R6 , R9 , and R15 used in the read operation of the middle page data is shown. Figure 15 The graph shown is generated by applying pressure to a certain median page and repeatedly performing acquisition of the count value of the median page and querying of the optimal shift value.

[0161] In this example, an approximate straight line between the count value and the shift value is obtained for each of read voltages R4, R6, R9, and R15. The linear function corresponding to this approximate straight line is not limited to the median page; it can also be obtained for other pages. Thus, the relationship between the count value and the preferred shift value for the read voltage obtained in step S14 is obtained by approximating the linear function for each read voltage. Therefore, memory device 2 can derive the preferred shift value for each read voltage based on the count value.

[0162] Furthermore, to simplify the process of deriving the optimal shift value of the read voltage based on the count value, the memory device 2 of the first embodiment uses a shift value table 341 and a lookup table 342. Specific examples of the shift value table 341 and the lookup table 342 are described below.

[0163] (6: Specific Example of Shift Value Table 341)

[0164] Figure 16 This is a diagram showing a specific example of the shift value table 341 used in the on-chip trace of the memory device 2 according to the first embodiment. Figure 16 The corresponding relationship between the table number NTBL corresponding to the index value of the shift value table 341 and the shift value (DAC value) of the read voltage of each page is shown. In this example, the case where the common table number NTBL is used for each of the lower page data, the middle page data, the upper page data, and the uppermost page data is shown.

[0165] An example of the shift amount of each of the read voltages R5 , R11 , and R14 associated with the read operation of the lower page data is shown below.

[0166] Table No. NTBL: Shift amount of read voltage R5, R11, R14

[0167] 1:0, -4, -7

[0168] 2: -2, -6, -10

[0169] 3: -3, -8, -12

[0170] 4: -4, -10, -15

[0171] 5: -5, -12, -17

[0172] 6: -6, -14, -20

[0173] An example of the shift amounts of the read voltages R4 , R6 , R9 , and R15 associated with the read operation of the middle page data is shown below.

[0174] Table No. NTBL: Reading voltage shift amount of R4, R6, R9, R15

[0175] 1: -1, -2, -4, -9

[0176] 2: -2, -3, -5, -12

[0177] 3: -3, -5, -7, -15

[0178] 4: -4, -6, -9, -18

[0179] 5: -5, -7, -11, -21

[0180] 6: -6, -9, -12, -24

[0181] An example of the shift amounts of the read voltages R2 , R8 , R10 , and R12 associated with the read operation of the upper page data is shown below.

[0182] Table No. NTBL: Shift amount of read voltage R2, R8, R10, R12

[0183] 1:0, -3, -5, -6

[0184] 2:0, -4, -7, -8

[0185] 3:0, -6, -9, -10

[0186] 4: -1, -8, -11, -13

[0187] 5: -1, -9, -13, -15

[0188] 6: -2, -11, -14, -17

[0189] An example of the shift amounts of the read voltages R1 , R3 , R7 , and R13 associated with the read operation of the uppermost page data is shown below.

[0190] Table No. NTBL: Readout voltage shift amount of R1, R3, R7, R13

[0191] 1: -5, 0, -3, -4

[0192] 2: -5, -1, -4, -7

[0193] 3: -5, -2, -5, -9

[0194] 4: -6, -3, -7, -11

[0195] 5: -6, -4, -8, -14

[0196] 6: -6, -5, -9, -16

[0197] By using the shift value table 341 described above, the table selection unit 33 can obtain the preferred shift value of the read voltage corresponding to the table number NT BL. The shift value table 341 may also represent the shift value of the read voltage as a voltage value instead of a DAC value.

[0198] (7: Specific Example of Lookup Table 342)

[0199] Figure 17 This is a diagram showing a specific example of the lookup table 342 used for on-chip tracing of the memory device 2 according to the first embodiment. Figure 17 The correspondence between the count value NC of the counter 32 and the table number NTBL of the shift value table 341 is shown.

[0200] An example of the table number NTBL associated with the magnitude of the count value NC is shown below.

[0201] Size of count value NC: table number NTBL

[0202] NC<28:0

[0203] 28≦NC<66:1

[0204] 66≦NC<104:2

[0205] 104≦NC<142:3

[0206] 142≦NC<180:4

[0207] 180≦NC<218:5

[0208] 218≦NC:6

[0209] By using the lookup table 342 as described above, the table selection unit 33 can select the table number NTBL corresponding to the count value NC. In addition, the range of the count value NC assigned to the table number NTBL can be greater than Figure 17 The example shown is less segmented and can also be Figure 17 The example shown is further divided. The count value NC as a reference is based on the use of Figure 15 The evaluation results described are set appropriately.

[0210] <1-3> Effects of the First Embodiment

[0211] According to the first embodiment, it is possible to provide a memory device 2 and a memory system MS that have high reliability and can operate at high speed. The effects of the first embodiment will be described in detail below.

[0212] When reading data from NAND flash memory, the optimal read voltage for all blocks BLK and all word lines WL is set based on pre-test results, consistent with product shipping conditions. However, using only this read voltage for read operations (normal reads) is difficult to handle, for example, write / erase cycles, data retention, cross-temperature (cross temperature), and IR reflow stresses. When these stresses are applied to NAND flash memory, error bits increase, making error correction difficult using the ECC circuit 13 of the memory controller 1.

[0213] Vth tracking can derive the optimal read voltage for the aforementioned stress. Furthermore, the effect of stress on the read voltage tends to increase with increasing stress. Furthermore, by determining the optimal read voltage in the high state, memory device 2 can determine the read voltages in other states.

[0214] However, Vth tracking acquires sample data from multiple read operations and estimates the optimal read voltage shift value based on this acquired sample data before executing the final data read operation. Therefore, when performing Vth tracking, there is a concern that it may affect sequential and random read performance. In other words, increasing the speed of operation requires balancing the accuracy of estimating the read voltage shift value with maintaining stress tolerance while reducing the number of samples.

[0215] Therefore, the memory system MS of the first embodiment performs on-chip tracking that allows the optimal read voltage to be derived with a reduced number of sampling times. Specifically, to extract the memory cell to be counted, the memory device 2 performs two single-level reads (RL1 read and RL2 read). Next, the memory device 2 performs an XOR operation on the results of the two single-level reads and counts the number of "1" bits in the XOR operation by appropriately reducing the number of bits. The memory device 2 then selects the optimal shift value for the read voltage corresponding to the count result from the shift value table 341.

[0216] Thus, the memory device 2 can derive the optimal read voltage with two sampling cycles and perform a read operation using the optimal read voltage. Therefore, the first embodiment can provide a memory device 2 and a memory system MS that are highly reliable and capable of high-speed operation. Furthermore, the memory device 2 can estimate the low-state read voltage based on the results of on-chip tracing of the high-state side. As a result, the memory device 2 of the first embodiment can shorten the time required to estimate the optimal read voltage, thereby reducing power consumption.

[0217] Furthermore, in the memory device 2 of the first embodiment, the number of bits in the counter 32 may be limited to reduce hardware costs. Furthermore, if the number of bits counted by the counter 32 increases, the on-chip trace operation speed may decrease. In contrast, in the memory device 2 of the first embodiment, the number of bits counted by the counter 32 can be reduced by performing an XOR operation on the result read from RL1 and the result read from RL2.

[0218] Furthermore, the memory device 2 of the first embodiment can reduce the number of counted items by utilizing a reduction mechanism, thereby eliminating the restriction on the number of bits of the counter 32. Therefore, the memory device 2 of the first embodiment has high reliability and can operate at high speed, thereby reducing the manufacturing cost of the memory device 2.

[0219] <1-4> Modifications of the First Embodiment

[0220] The memory system MS of the first embodiment can be modified in various ways.

[0221] For example, the RL1 readout in step ST11 and the RL2 readout in step ST12 are each performed in the highest state (the S15 state in the case of 4 bits / cell) where the voltage transition amount is the largest under data retention pressure. However, when writing to the highest state, there is no need to worry about erroneous writing to a higher state, so there is a case where ΔVPGM is set larger than that of other states to perform high-speed writing. ΔVPGM corresponds to the difference in the voltage setting value of the write pulse for each program-verify loop in the write operation. Therefore, the threshold voltage width of the highest state after writing is larger than that of other states, and may not be suitable as the target of RL1 readout and RL2 readout. In this case, a state lower than the highest state (such as the S14 state or the S13 state) can also be set as the target of RL1 readout and RL2 readout.

[0222] Alternatively, the combination of steps ST11 and ST12 may be performed by a read operation using one type of read voltage. Figure 18 Schematic diagram showing an example of an on-chip trace operation waveform of the memory device 2 according to the first modification of the first embodiment. Figure 18 , the voltage of the selected word line WLsel and the control signal STB are shown. Note that in the initial state before the operation begins, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). The following describes the case of performing on-chip tracking for the following bit pages.

[0223] like Figure 18 As shown, the period for executing on-chip trace in the first modification of the first embodiment includes three periods P1, P2, and P3, similarly to the first embodiment. The operations in periods P2 and P3 in the first modification of the first embodiment are similar to those in the first embodiment.

[0224] During the period P1 of the first variation of the first embodiment, the sequencer 24 applies a read pass voltage VREAD (not shown) to the unselected word line WL. In addition, the sequencer 24 applies a read voltage RL3 to the selected word line WLsel. The read voltage RL3 is, for example, the same voltage as the read voltage RL2. Furthermore, while the read voltage RL3 is applied to the selected word line WLsel, the sequencer 24 activates the control signal STB twice at different timings. Thus, the two read results are stored in any latch circuit of each sense amplifier element SAU. This operation can obtain the same as the execution Figure 11 The results of both reading out RL1 in step ST11 and reading out RL2 in step ST12 are the same.

[0225] For example, when read voltage RL3 is applied to the selected word line WLsel, CR charges, causing the voltage of the selected word line WLsel to rise. The difference in the timing at which data is captured in the sense amplifier unit SAU is then converted into the voltage difference between read voltages RL1 and RL2. Thus, the memory device 2 in the first variation of the first embodiment can achieve the same read results as the read operation during period P1 of the first embodiment through a read operation using a single read voltage RL3. Alternatively, this read operation can be achieved by asserting control signal STB twice, after charging of the selected word line WLsel is completed, at different times during which the sense nodes included in the sense amplifier unit SA discharge.

[0226] The above-described operation can also be performed when on-chip tracking is performed with other pages selected. Thus, similar to the first embodiment, the memory device 2 of the first variation of the first embodiment can perform a read operation using the preferred shift value of the read voltage obtained by on-chip tracking, thereby improving the reliability of the memory device 2. Furthermore, the memory device 2 of the first variation of the first embodiment can shorten the time required for sampling compared to the first embodiment.

[0227] Furthermore, similar to the first embodiment, the memory device 2 according to the first variation of the first embodiment can also use a linear function with a count value as a variable, etc., instead of the lookup table 342, to calculate the shift value of the read voltage. Furthermore, if the memory device 2 according to the variation of the first embodiment is equipped with the same soft bit read as described above for the read operation, the read operation can be directly implemented using the circuit used for the soft bit read.

[0228] Furthermore, during on-chip tracking periods P1 and P3, the order in which the read voltages are applied may be from the higher voltage onward. Alternatively, the sequencer 24 may maintain the read voltage last applied during period P1 during period P2 and directly transition from that read voltage to the preferred read voltage during period P3. Figure 19 This is a schematic diagram showing an example of an on-chip trace operation waveform of the memory device 2 according to the second modification of the first embodiment. Figure 19 , the voltage of the selected word line WLsel and the control signal STB are shown. Note that in the initial state before the operation begins, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). The following describes the case of performing on-chip tracking for the following bit pages.

[0229] like Figure 19As shown, the period for performing on-chip tracking in the second variation of the first embodiment includes three periods, P1, P2, and P3, similar to the first embodiment. Furthermore, during period P1, the sequencer 24 sequentially applies read voltages RL2 and RL1 to the selected word line WLsel. During period P2, the voltage of the selected word line WLsel is maintained at read voltage RL1. Then, during period P3, the sequencer 24 transitions the voltage of the selected word line WLsel from read voltage RL1 to preferred read voltage R14sft. Subsequently, the preferred read voltages R11sft and R5sft are sequentially applied to the selected word line WLsel. In the second variation of the first embodiment, during each period in which the read voltage is applied, the control signal STB is asserted to read data, similar to the first embodiment.

[0230] The actions described above can also be performed in the same manner when performing on-chip tracking of other selected pages. Thus, the on-chip tracking of the memory device 2 of the second variation of the first embodiment can achieve the same effect as that of the first embodiment. Furthermore, the memory device 2 of the second variation of the first embodiment can shorten the time required for voltage control of the selected word line WLsel compared to the first embodiment, thereby shortening the time for on-chip tracking. In addition, the second variation of the first embodiment can also be combined with the first variation of the first embodiment. That is, during the on-chip tracking period P1 of the second variation of the first embodiment, the read operation using one read voltage can also be performed in the same manner as in the first variation of the first embodiment.

[0231] <2> Second embodiment

[0232] The second embodiment relates to a memory system MS configured to determine a preferred shift value of a read voltage based on the result of counting the number of memory cell transistors MT in a threshold region different from that of the first embodiment. The following details the memory system MS of the second embodiment, focusing primarily on the differences from the first embodiment.

[0233] <2-1>Composition

[0234] Figure 20 1 is a block diagram showing an example of the configuration of the voltage adjustment unit 30A included in the memory device 2 according to the second embodiment. Figure 20 As shown, the voltage adjustment unit 30A includes, for example, a counter 32A, a table selection unit 33, a table storage register 34, and a table number storage register 35. Specifically, the voltage adjustment unit 30A has a configuration similar to the voltage adjustment unit 30 of the first embodiment, except that the arithmetic circuit 31 is omitted and the counter 32 is replaced by a counter 32A.

[0235] Counter 32A receives data corresponding to the readout result from data register 28. Next, counter 32A counts the number of "0" bits contained in the received data. Counter 32A then outputs the count result to table selection unit 33. Counter 32A is configured, for example, to be able to count a larger number than counter 32 of the first embodiment. Counter 32 is, for example, a 9-bit counter. Furthermore, counter 32A includes a reduction mechanism capable of performing a reduction process on the data received from data register 28. The configuration of the reduction mechanism is the same as that of the first embodiment.

[0236] Furthermore, the shift value table 341 and the lookup table 342 stored in the table storage register 34 in the second embodiment each store information associating the count value of the "0" bit data obtained by the counter 32A with the preferred shift value of the read voltage. In the voltage adjustment unit 30A, the reduction mechanism can also be omitted from the counter 32A of the voltage adjustment unit 30A. In this case, the reduction process is performed by reducing the data transferred from the data register 28 to the counter 32A without using the counter 32A. Furthermore, the reduction process can also be performed during reading. When the reduction process is performed during reading, the reading time can be shortened as the amount of read data decreases. This is not limited to this, and the memory device 2 of the second embodiment only needs to be configured to be able to perform the reduction process. The other configurations of the memory system MS of the second embodiment are the same as those of the memory system MS of the first embodiment.

[0237] <2-2>Action

[0238] Hereinafter, the operation of the memory system MS according to the second embodiment will be described.

[0239] (1: On-chip trace processing flow)

[0240] Figure 21 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device of the second embodiment. When the memory device 2 of the second embodiment receives the address of the page to be read and the instruction to execute on-chip trace from the memory controller 1, for example, Figure 21 A series of processing.

[0241] First, the memory device 2 executes RL4 read (step ST21). RL4 read is a read operation using read voltage RL4. Read voltage RL4 is set to overlap the highest state (eg, S15 state), for example.

[0242] Next, the memory device 2 uses the reduction mechanism to count the number of "0" bits (the amount of "0" bit data) in the result read from RL4 (step ST22). The reduction mechanism adjusts the reduction amount so that, for example, a maximum of 511 bits is estimated. Next, the counter 32A counts the number of "0" bits contained in the reduced result read from RL4. Furthermore, during step ST22, the counter 32A is controlled to prevent overflow. For example, if the counter 32A is a 9-bit counter, the count value is stopped at 511 counts.

[0243] Next, similarly to the first embodiment, the memory device 2 selects a table number based on the count value and the lookup table 342 (step ST15 ).

[0244] Next, similarly to the first embodiment, the memory device 2 stores the selected table number in the table number storage register 35 (step ST16 ).

[0245] Next, similarly to the first embodiment, the memory device 2 executes a read operation using the shift value corresponding to the selected table number (step ST17 ).

[0246] Furthermore, in the above description, the preferred shift value of the read voltage is determined using the shift value table 341 and the lookup table 342. However, the present invention is not limited thereto. The memory device 2 of the second embodiment may also be configured to determine the shift value of the read voltage by performing a calculation using a linear equation or the like using the count value in step ST22 as a variable.

[0247] (2: On-chip tracking waveform)

[0248] Figure 22 This is a schematic diagram showing an example of an on-chip trace operation waveform of the memory device 2 according to the second embodiment. Figure 22 , the voltage of the selected word line WLsel and the control signal STB are shown. Note that in the initial state before the operation begins, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). The following describes the case of performing on-chip tracking for the following bit pages.

[0249] like Figure 22 As shown, the period for executing on-chip trace in the second embodiment includes three periods P1, P2, and P3, similarly to the first embodiment.

[0250] During period P1 of the second embodiment, the sequencer 24 applies a read pass voltage VREAD (not shown) to the unselected word lines WL. Furthermore, the sequencer 24 applies a read voltage RL4 to the selected word line WLsel. The read voltage RL4 is set to overlap with the highest state (e.g., S15 state), for example. Next, the sequencer 24 asserts the control signal STB while the read voltage RL4 is applied. The read result is then stored in any latch circuit of each sense amplifier element SAU ( Figure 21 Step ST21).

[0251] In the period P2 of the second embodiment, the sequencer 24 controls the voltage adjustment unit 30A to select a preferred shift value ( Figure 21 Steps ST22, ST15, and ST16).

[0252] During period P3 of the second embodiment, the sequencer 24 applies a read pass voltage VREAD (not shown) to unselected word lines WL. Furthermore, the sequencer 24 sequentially applies preferred read voltages R5sft, R11sft, and R14sft to the selected word line WLsel. During each period in which the preferred read voltages R5sft, R11sft, and R14sft are applied, the control signal STB is asserted. Next, the sequencer 24 determines the lower page data based on the read results using the preferred read voltages R5sft, R11sft, and R14sft. The sequencer 24 then stores the determined data in the data register 28.

[0253] The actions described above can also be performed in the same manner when performing on-chip tracking with other pages selected. In addition, the memory device 2 of the second embodiment can also use a linear function with a count value as a variable instead of the lookup table 342 to obtain the shift value of the read voltage by calculation. In addition, during each of the periods P1 and P3 of the on-chip tracking of the second embodiment, the order of applying the read voltage can be started from a higher voltage as described in the second variation of the first embodiment. In addition, the sequencer 24 can maintain the read voltage last applied during period P1 during period P2, and directly switch from the read voltage to the preferred read voltage during period P3. As a result, the memory device 2 of the second embodiment can shorten the on-chip tracking time, similar to the second variation of the first embodiment.

[0254] (3: Overview of Counting Processing)

[0255] Figure 23 This is a schematic diagram showing an overview of a counting process in on-chip trace of the memory device 2 according to the second embodiment. Figure 23The corresponding relationship between the S14 state and the S15 state in the threshold voltage distribution of the memory cell transistor MT and the result of the RL4 readout is shown. Figure 23 As shown, in this example, the read voltage RL4 is set so as to overlap with the S15 state which is the highest state.

[0256] In RL4 reading, "1" bit data is read from the memory cell transistor MT whose threshold voltage is lower than the read voltage RL4, and "0" bit data is read from the memory cell transistor MT whose threshold voltage is higher than the read voltage RL4. Figure 21 The count target in the process of step ST22 corresponds to the number of memory cell transistors MT having a threshold voltage higher than the read voltage RL4 (the number of “0” bit data).

[0257] Furthermore, in the second embodiment, the number of memory cell transistors MT to be counted is equal to or less than the number corresponding to one page of data. The threshold voltage width of the highest state after writing is larger than that of other states, making it unsuitable for RL4 reading. In this case, a state lower than the highest state (e.g., S14 or S13) can also be set as the target for RL4 reading. The rest of the operation of the memory system MS of the second embodiment is the same as that of the memory system MS of the first embodiment.

[0258] <2-3> Effects of the Second Embodiment

[0259] As described above, the memory device 2 of the second embodiment counts the number of "0" bits based on a single sampling result and derives the optimal read voltage based on the shift value table 341 and the lookup table 342. Consequently, the memory device 2 of the second embodiment can perform a read operation using the optimal read voltage. Therefore, similar to the first embodiment, the second embodiment can provide a memory device 2 and a memory system MS that are highly reliable and capable of high-speed operation.

[0260] <3> Third embodiment

[0261] The third embodiment relates to a memory system MS capable of performing a read operation using the on-chip trace results described in the first or second embodiment. The following details the memory system MS of the third embodiment, mainly focusing on differences from the first and second embodiments.

[0262] <3-1> Structure

[0263] The configuration of the memory system MS according to the third embodiment is the same as that of the memory system MS according to the first embodiment or the second embodiment.

[0264] <3-2>Action

[0265] Hereinafter, the operation of the memory system MS according to the third embodiment will be described.

[0266] (1: On-chip trace processing flow)

[0267] Figure 24 This is a flowchart showing an example of the processing flow of on-chip trace in the memory device 2 according to the third embodiment. When the memory device 2 according to the third embodiment receives the address of the page to be read and an instruction to execute a read operation using the result of on-chip trace from the memory controller 1, it starts Figure 24 A series of processing.

[0268] First, the memory device 2 reads the table number associated with the page to be read from the table number storage register 35 (step ST31). The table number read in step ST31 is a table number obtained from another page on the same word line WL or a table number obtained from the same block BLK.

[0269] Next, the memory device 2 reads out the shift value corresponding to the table number read out from the table number storage register 35 from the shift value table 341 (step ST32 ).

[0270] Next, the memory device 2 performs a read operation using the read shift value (step ST33). That is, the sequencer 24 derives a preferred read voltage to be used based on the shift value corresponding to the selected table number, and performs a read operation using the preferred read voltage.

[0271] Furthermore, while the above description describes the use of shift value table 341 and lookup table 342 to determine the preferred shift value for the read voltage, this is not limiting. The memory device 2 of the third embodiment may also be configured such that, when table number storage register 35 stores a count value instead of a table number, the shift value for the read voltage is determined by performing a calculation using a linear equation or the like using the count value as a variable. In this case, table number storage register 35 may also be configured to store the count value acquired in step ST14 or ST22.

[0272] (2: Instruction sequence)

[0273] Figure 25 This is a schematic diagram showing an example of a command sequence for a read operation using the result of on-chip trace in the memory device 2 according to the third embodiment. Figure 25 , the input / output signal I / O and the standby / busy signal RBn are shown when the read operation using the result of on-chip tracking is performed. In addition, before the operation starts, the standby / busy signal RBn is "H" (high level: standby state).

[0274] like Figure 25 As shown, first, the memory controller 1 sends command "zzh", command "yyh", command "00h", address "ADD", and command "30h" in sequence to the memory device 2. Command "zzh" is a command instructing to use the result of on-chip trace.

[0275] If the instruction "30h" is stored in the register circuit 23, the sequencer 24 changes the memory device 2 from the standby state (RBn="H") to the busy state (RBn="L" (low level: busy state)) and starts the read operation using the on-chip trace result. Figure 25 In FIG, the period during which the read operation using the result of on-chip tracking is performed is represented by tR.

[0276] When the read operation using the on-chip tracking results is completed, the sequencer 24 changes the memory device 2 from the busy state to the standby state. When the completion of the read operation is detected based on the change of the standby / busy signal RBn, the memory controller 1 sequentially outputs the read results (data DAT) to the memory device 2 by, for example, switching the control signal REn.

[0277] (3: Waveform of readout operation)

[0278] Figure 26 This is a schematic diagram showing an example of an operation waveform in a read operation using an on-chip trace result of the memory device according to the third embodiment. Figure 26 , the voltage of the selected word line WLsel and the control signal STB are shown. Note that in the initial state before the operation begins, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). The following describes the case of performing on-chip tracking for the following bit pages.

[0279] like Figure 26 As shown, the read operation using the on-chip tracking result only includes period P3. Specifically, in period P3 of the second embodiment, the sequencer 24 obtains the shift value ( ) of the read voltage obtained from the shift value table 341 based on the index number of the shift value table 341 stored in the table number storage register 35. Figure 24 Then, the sequencer 24 sets the preferred read voltages R5sft, R11sft, and R14sft obtained by applying the acquired shift values ​​of the read voltages, and performs the same operation as in the first embodiment. Figure 13 The read operation is similarly performed during the period P3 shown ( Figure 24 Step ST33).

[0280] The above-described operation can be similarly performed even when executing on-chip trace with another page selected. Other operations of the memory system MS according to the third embodiment are the same as those of the memory system MS according to the first or second embodiment.

[0281] <3-3> Effects of the Third Embodiment

[0282] The memory device 2 of the third embodiment derives the preferred read voltage of the page to be read based on the instruction from the memory controller 1, using the table number obtained in the associated page, etc. As a result, the memory device 2 of the third embodiment can perform a read operation using the preferred read voltage without performing, for example, Figure 13 Therefore, the third embodiment can provide a memory device 2 and a memory system MS that have high reliability and can operate at high speed, similarly to the first embodiment or the second embodiment.

[0283] <4>Other

[0284] In the memory controller 1 in the above embodiment, an MPU (Micro Processing Unit) may be used instead of the CPU 12. In addition, each of the processes described in the above embodiment may be executed by a dedicated hardware circuit, a processor executing a program (firmware), or a combination thereof.

[0285] The instruction sequence illustrated in the above embodiment is only an example. The page to be read can also be represented by the address ADD. Any number can be applied to "xxh", "yyh" and "zzh". The flowchart used for explanation in the above embodiment is only an example. Other processes can be added to the processes shown in the flowchart. In this specification, "connection" means electrical connection, and does not exclude the presence of other elements in between, for example. "Electrical connection" can also be interposed with an insulator, as long as it can operate in the same way as the case of electrical connection. Word lines WL, selection gate lines SGD and SGS, etc. can also be simply referred to as "wiring".

[0286] A high-level voltage is a voltage that turns on an N-type transistor with a gate voltage of that level applied thereto. A low-level voltage is a voltage that turns off an N-type transistor with a gate voltage of that level applied thereto. In this specification, the application of a voltage to a word line WL corresponds to the application of a voltage to the word line WL by the driver circuit 26 via the row decoder module 27. The application of voltage to other wirings also corresponds to the application of a voltage to the word line WL by the driver circuit 26 via the row decoder module 27, similarly to the word line WL. The voltage of each wiring can be estimated based on the voltage of the signal line connecting the driver circuit 26 and the row decoder module 27.

[0287] While some embodiments of the present invention have been described, these embodiments are provided for illustrative purposes only and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are encompassed by the invention recited in the claims and their equivalents.

[0288] [Explanation of Symbols]

[0289] 1: Memory controller

[0290] 2: Memory device

[0291] 10: Host interface circuit

[0292] 11: Memory interface circuit

[0293] 12:CPU

[0294] 13:ECC circuit

[0295] 14:ROM

[0296] 15: RAM

[0297] 16: Buffer memory

[0298] 20: Memory cell array

[0299] 21: Input and output circuits

[0300] 22:Logic Controller

[0301] 23: Register circuit

[0302] 24: Sequencer

[0303] 25: Standby / Busy Controller

[0304] 26: Driver circuit

[0305] 27: Row decoder module

[0306] 28: Data register

[0307] 29: Sense amplifier module

[0308] 30,30A: Voltage adjustment unit

[0309] 31: Operational Circuit

[0310] 32,32A: Counter

[0311] 33: Table selection unit

[0312] 34: Table save register

[0313] 35: Table number storage register

[0314] 341: Shift value table

[0315] 342: Lookup Table

[0316] BLK:Block

[0317] SU: String Components

[0318] NS:NAND string

[0319] BL: bit line

[0320] WL: Word Line

[0321] SGD, SGS: select gate line

[0322] CG, SGDD, SGSD, USGD, USGS: signal line

[0323] MT: Memory cell transistor

[0324] STD, STS: Select transistor

[0325] RD: Row Decoder

[0326] RL1, RL2, RL3, RL4: read voltage

[0327] SAU: Sense Amplifier Unit

[0328] SA: Sense Amplifier

[0329] T0,TR: transistor

[0330] P1, P2, P3: Period

[0331] SDL, ADL, BDL, CDL, DDL, XDL: latch circuits.

Claims

1. A memory device comprising: multiple storage units; word lines; and Controller; Each of the plurality of memory cells is configured to store a plurality of bits of data in accordance with a state among a plurality of states having different threshold voltages, and to read the plurality of bits of data using a read voltage corresponding to each state. The word line is commonly connected to the plurality of memory cells. The controller is capable of: The plurality of memory cells are read and divided into a plurality of first memory cells corresponding to a threshold voltage on a high state side and at least one second memory cell corresponding to a threshold voltage on a low state side, The controller is composed of: The number of the first memory cells is counted instead of the number of the second memory cells, and a read operation is performed on the plurality of memory cells using a read voltage shifted from the read voltage based on the count result.

2. The memory device according to claim 1, wherein The group of the plurality of memory cells stores multiple pages of data, and The number of the first storage units is equal to or smaller than the number corresponding to one page of the plurality of pages of data.

3. The memory device according to claim 1, wherein When the controller counts the number of the first storage units, Counting is performed while excluding a portion of the first storage cells having first bit values ​​based on a plurality of sampling results.

4. The memory device according to claim 3, further comprising: a counter for said counting, and The controller is further configured to control the counter so that it does not overflow during the counting.

5. The memory device according to claim 2, wherein The controller is further configured to execute a read operation on the second memory cell using a read voltage shifted from the read voltage based on the count result. The memory device according to claim 1 , wherein As the number of the first storage units, the result of an exclusive OR operation of two sampling results is used.

7. The memory device of claim 6, wherein The first memory cell includes a highest state among the plurality of states, and the two sampling results are acquired by a read operation using a read voltage set to overlap with the highest state.

8. The memory device of claim 6, wherein The two sampling results are acquired by a read operation using two different read voltages.

9. The memory device of claim 6, wherein The two sampling results are obtained by performing a data readout operation twice at different timings using one readout voltage.

10. The memory device of claim 1, wherein The number of the first storage unit is based on one sampling result. The memory device according to claim 10 , wherein The first memory cell includes a highest state among the plurality of states, and the one sampling result is acquired by a read operation using a read voltage set to overlap with the highest state.

12. The memory device according to claim 1, further comprising: The first storage circuit is configured to store a table associating the magnitude of the count result with the shift amount of the read voltage; and The controller is further configured to determine the shifted read voltage based on the table.

13. The memory device of claim 1, wherein The controller is further configured to determine the shifted read voltage using a relational expression between the magnitude of the count result and the shift amount of the read voltage.

14. The memory device of claim 1, wherein The controller is further configured to: count the number of the first memory cells based on receipt of a first command and an address; and perform a read operation on the plurality of memory cells using the shifted read voltage based on the count result.

15. The memory device according to claim 12, further comprising: The second storage circuit is configured to store an index number of the table corresponding to the count result.

16. The memory device of claim 15, wherein The controller is further configured to, when the second storage circuit stores the index number, read second page data different from the first page data used to obtain the index number using the shifted read voltage based on information on the shift value corresponding to the index number.

17. The memory device of claim 16, wherein The group of memory cells connected to the word line stores a plurality of pages of data including the first page of data and the second page of data.

18. The memory device of claim 16, wherein The controller is further configured to, upon receipt of a second command and an address, acquire the index number from the second storage circuit and execute a read operation of the second page data.

19. A memory system comprising: The memory device according to claim 14; and The memory controller is configured to issue the first command and transmit it to the memory device.

20. A memory system comprising: The memory device according to claim 18; and The memory controller is configured to issue the second command and transmit it to the memory device.

21. A memory device comprising: multiple storage units; word lines; and Controller; Each of the plurality of memory cells is configured to store a plurality of bits of data in accordance with a state among a plurality of states having different threshold voltages, and to read the plurality of bits of data using a read voltage corresponding to each state. The word line is commonly connected to the plurality of memory cells. The controller is capable of: The plurality of memory cells are read and divided into a plurality of first memory cells corresponding to a threshold voltage on a high state side and at least one second memory cell corresponding to a threshold voltage on a low state side, The controller is composed of: When counting the number of the first storage units, After counting by excluding a portion of the first storage unit having the first bit value based on a plurality of sampling results, A read operation is performed on the plurality of memory cells using a read voltage shifted from the read voltage based on a count result.

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