Semiconductor memory device and memory system

Abstract

The invention provides a semiconductor memory device and a memory system capable of improving the use efficiency of a bus. The semiconductor memory device includes a data storage unit, a data transfer circuit, and a control unit. The data storage unit temporarily stores data read from the memory cell array. The data transmission circuit is provided between the data storage unit and the pad unit, and transmits data stored in the data storage unit to the input / output pad. The data transfer circuit is provided with a blocking unit capable of blocking the supply of current to the data transfer circuit. The control unit blocks the supply of current to the data transfer circuit by means of the blocking unit when a prescribed time has elapsed since data transfer to the memory controller is not started from a point in time when the data is transferred to the data transfer circuit via the data holding unit from the memory cell array. The specified time can be changed.

Description

[0001] [Related Applications]

[0002] This application claims the benefit of priority from Japanese Patent Application No. 2024-044085 (filing date: March 19, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor storage device and a memory system. Background Art

[0004] As a semiconductor memory device, a NAND (Not-AND) type flash memory is well known. Summary of the Invention

[0005] According to an embodiment, a semiconductor memory device and a memory system capable of improving bus usage efficiency are provided.

[0006] The semiconductor memory device of the embodiment comprises: a memory cell array capable of storing data; a data storage unit for temporarily storing the data read from the memory cell array; a first terminal for sending the data to an external memory controller; a second terminal for receiving a read control signal sent by the memory controller; a first power supply voltage input terminal for receiving a first voltage; a second power supply voltage input terminal for receiving a second voltage lower than the first voltage; a data transmission circuit provided between the data storage unit and the first terminal for transmitting the data stored in the data storage unit to the second terminal. 1 terminal; a switching element capable of controlling connection or disconnection between the data transmission circuit and the first power supply voltage input terminal or the second power supply voltage input terminal; and a control unit that controls the data transmission circuit and the switching element. When the memory controller instructs the control unit to perform a first operation, the control unit causes the data transmission circuit to transfer the data stored in the data storage unit. When a specified time has passed after the data transmission circuit has transferred the data and the memory controller has not received the read control signal, the control unit disconnects the data transmission circuit from the first power supply voltage input terminal or the second power supply voltage input terminal via the switching element. The specified time can be changed according to an instruction from the memory controller.

[0007] A memory system according to an embodiment includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device in response to a request from a host computer. The memory controller outputs a recommended value for the designated time to the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram showing a schematic configuration of a memory system according to an embodiment.

[0009] Figure 2 This is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment.

[0010] Figure 3 This is a circuit diagram showing the configuration of a semiconductor memory device according to an embodiment.

[0011] Figure 4 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment.

[0012] Figure 5 : is a block diagram showing the configuration of a sense amplifier group according to an embodiment.

[0013] Figure 6 This is a diagram showing an example of threshold distribution of memory cell transistors.

[0014] Figure 7 This is a diagram showing changes in the potential of each wiring during a programming operation.

[0015] Figure 8 This is a diagram showing changes in the potential of each wiring during a read operation.

[0016] Figure 9 This is a diagram showing the configuration of a circuit for outputting data from a memory cell array to a memory controller in a memory system according to an embodiment.

[0017] Figure 10 This is a block diagram showing a configuration for supplying current to a storage unit and an input / output circuit according to an embodiment.

[0018] Figure 11 This is a diagram showing an example of transition of signals and the like transmitted and received between the semiconductor memory device and the memory controller according to the embodiment.

[0019] Figure 12 This is a diagram showing an example of transition of signals and the like transmitted and received between the semiconductor memory device and the memory controller according to the embodiment.

[0020] Figure 13 This is a diagram showing an example of transition of signals and the like transmitted and received between the semiconductor memory device and the memory controller according to the embodiment.

[0021] Figure 14 This is a diagram showing an example of transition of signals and the like transmitted and received between the semiconductor memory device and the memory controller according to the embodiment.

[0022] Figure 15 This is a timing chart showing an example of the operation of the memory system according to the embodiment.

[0023] Figure 16 This is a block diagram showing a schematic configuration for supplying current to a storage unit and an input / output circuit according to a modified example of the embodiment.

[0024] Figure 17 This is a timing chart showing an operation example of a memory system according to another embodiment. DETAILED DESCRIPTION

[0025] In the following, the embodiments are described with reference to the drawings. To facilitate understanding, identical components are denoted by identical reference numerals in the drawings as much as possible, and duplicate descriptions are omitted.

[0026] 1. Implementation Method

[0027] A semiconductor storage device according to an embodiment will be described. The semiconductor storage device according to this embodiment is a nonvolatile storage device configured as a NAND flash memory.

[0028] 1.1 Memory System Structure

[0029] First, the configuration of the memory system according to this embodiment will be described.

[0030] like Figure 1 As shown, the memory system 3 of this embodiment includes a memory controller 1 and semiconductor memory devices 2a through 2d. Semiconductor memory devices 2a through 2d are nonvolatile memory devices configured as NAND flash memories. The memory system 3 can be connected to a host 4. The host 4 is, for example, an electronic device such as a personal computer or a portable terminal.

[0031] The memory controller 1 controls data writing to the semiconductor memory devices 2a to 2d in response to a write request from the host 4 . The memory controller 1 also controls data output from the semiconductor memory devices 2a to 2d in response to a read request from the host 4 .

[0032] Between the memory controller 1 and the semiconductor memory devices 2a~2d, the chip enable signal / CE, ready-busy signal R / B, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protection signal / WP, signal DQ<7:0>, and data select signals DQS, / DQS are received and sent.

[0033] The chip enable signal / CE is used to enable semiconductor memory devices 2a-2d. The ready-busy signal R / B is used to indicate whether semiconductor memory devices 2a-2d are in the ready or busy state. The "ready state" indicates that they are accepting external commands. The "busy state" indicates that they are not accepting external commands.

[0034] like Figure 1 As shown, chip enable signal / CE is sent individually to each of a plurality of semiconductor memory devices 2a to 2d. Figure 1 In the example, a number is added at the end of " / CE0" to distinguish the chip enable signals / CE from each other.

[0035] Likewise, ready-busy signals R / B are individually transmitted from each of the plurality of semiconductor memory devices 2a to 2d. Figure 1 In the example, a number is added to the end, such as "R / B0", to distinguish each ready-busy signal R / B from each other.

[0036] Signals other than the chip enable signal / CE and the ready-busy signal R / B (such as the command latch enable signal CLE) are transmitted and received between the memory controller 1 and the semiconductor memory devices 2a-2d via a signal line common to the plurality of semiconductor memory devices 2a-2d. The memory controller 1 uses the individual chip enable signals / CE to specify the semiconductor memory devices 2a-2d with which to communicate.

[0037] The command latch enable signal CLE indicates that the signal DQ<7:0> is a command. The address latch enable signal ALE indicates that the signal DQ<7:0> is an address. The write enable signal / WE is used to load received signals into the semiconductor memory devices 2a-2d. It is activated whenever a command, address, or data is received by the memory controller 1. The memory controller 1 instructs the semiconductor memory devices 2a-2d to load the signal DQ<7:0> while the / WE signal is at "L (low)" level.

[0038] Read enable signals / RE and RE are signals used by memory controller 1 to instruct semiconductor memory devices 2a to 2d to output data to memory controller 1. Read enable signals RE and / RE are used, for example, to control the timing of the operation of semiconductor memory devices 2a to 2d when outputting signal DQ<7:0>. Write protect signal / WP is a signal used to instruct semiconductor memory devices 2a to 2d to prohibit data writing and erasing. Signal DQ<7:0> is the entity of data sent and received between semiconductor memory devices 2a to 2d and memory controller 1, and includes instructions, addresses, and data. Data strobe signals DQS and / DQS are signals used to control the input and output timing of signal DQ<7:0>.

[0039] The memory controller 1 includes a RAM (Random Access Memory) 11 , a processor 12 , a host interface 13 , an ECC (Error Check and Correction) circuit 14 , and a memory interface 15 . These are interconnected via an internal bus 16 .

[0040] Host interface 13 outputs requests and user data (write data) received from host 4 to internal bus 16. Host interface 13 also transmits user data read from semiconductor memory devices 2a to 2d and responses from processor 12 to the host.

[0041] The memory interface 15 controls a process of writing user data and the like into the semiconductor memory devices 2 a to 2 d and a process of reading user data and the like from the semiconductor memory devices 2 a to 2 d in accordance with an instruction from the processor 12 .

[0042] The processor 12 generally controls the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Microprocessor Unit), or the like. Upon receiving a request from the host 4 via the host interface 13, the processor 12 performs control in accordance with the request. For example, in response to a request from the host 4, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor memory devices 2a-2d. Furthermore, in response to a request from the host 4, the processor 12 instructs the memory interface 15 to read user data and parity from the semiconductor memory devices 2a-2d.

[0043] The processor 12 determines the storage area (memory area) on the semiconductor memory devices 2a to 2d for the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for the data of the page unit (page data) which is the write unit. Hereinafter, the user data stored in one page of the semiconductor memory devices 2a to 2d is also referred to as "group data". The group data is generally encoded and stored in the semiconductor memory devices 2a to 2d in the form of codewords. Encoding is not required in this embodiment. The memory controller 1 may also store the group data in the semiconductor memory devices 2a to 2d without encoding. Figure 1 is shown as an example of an encoding configuration. When the memory controller 1 does not perform encoding, the page data and the group data are identical. Furthermore, one codeword can be generated from one group data, or one codeword can be generated from divided data obtained by dividing the group data. Furthermore, one codeword can be generated using multiple group data.

[0044] The processor 12 determines the memory area of ​​the semiconductor memory devices 2a to 2d to which the data is to be written for each set of data. Physical addresses are assigned to the memory areas of the semiconductor memory devices 2a to 2d. The processor 12 uses the physical addresses to manage the memory areas to which the data is to be written. The processor 12 specifies the determined memory area (physical address) and instructs the memory interface 15 to write the user data to the semiconductor memory devices 2a to 2d. The processor 12 manages the correspondence between the logical address of the user data (the logical address managed by the host 4) and the physical address. When the processor 12 receives a read request containing a logical address from the host 4, it specifies the physical address corresponding to the logical address, and specifies the physical address to instruct the memory interface 15 to read the user data.

[0045] The ECC circuit 14 generates a code word by encoding the user data stored in the RAM 11. In addition, the ECC circuit 14 decodes the code word read from the semiconductor memory devices 2a to 2d.

[0046] The RAM 11 temporarily stores user data received from the host 4 before being stored in the semiconductor memory devices 2a to 2d, or temporarily stores data read from the semiconductor memory devices 2a to 2d before being sent to the host 4. The RAM 11 is, for example, a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0047] Figure 1 2 shows a configuration example in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Furthermore, the ECC circuit 14 may be built into the semiconductor memory devices 2a to 2d. Figure 1 The specific configuration and arrangement of each element shown are not particularly limited.

[0048] When a write request is received from the host 4, Figure 1 The memory system 3 operates as follows. The processor 12 temporarily stores data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory devices 2a to 2d.

[0049] When a read request is received from the host 4, Figure 1The memory system 3 operates as follows. Memory interface 15 inputs codewords read from semiconductor memory devices 2a to 2d to ECC circuit 14. ECC circuit 14 decodes the input codewords and stores the decoded data in RAM 11. Processor 12 transmits the data stored in RAM 11 to host 4 via host interface 13.

[0050] 1.2 Schematic Structure of a Semiconductor Memory Device

[0051] Next, the schematic configuration of semiconductor memory devices 2a to 2d will be described. Since semiconductor memory devices 2a to 2d have the same configuration, the configuration of semiconductor memory device 2a will be described below as a representative.

[0052] like Figure 2 As shown, the semiconductor storage device 2a has two planes PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generating circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0053] Plane PL1 includes a memory cell array 110, sense amplifiers 120, and a row decoder 130. Plane PL2 includes a memory cell array 210, sense amplifiers 220, and a row decoder 230. The configuration of plane PL1 is identical to that of plane PL2. Specifically, the configuration of memory cell array 110 is identical to that of memory cell array 210, the configuration of sense amplifiers 120 is identical to that of sense amplifiers 220, and the configuration of row decoder 130 is identical to that of row decoder 230. The number of planes provided in semiconductor memory device 2a may be two as in this embodiment, but may also be one, or may be three or more.

[0054] The memory cell arrays 110 and 210 are used to store data. Each of the memory cell arrays 110 and 210 includes a plurality of memory cell transistors associated with word lines and bit lines.

[0055] Row decoders 130 and 230 are circuits composed of a group of switches that apply voltages to the multiple word lines of memory cell arrays 110 and 210. Row decoders 130 and 230 receive a block address and a row address from register 42, select a block based on the block address, and select a word line based on the row address. Row decoders 130 and 230 switch the switch states so that the voltage from voltage generator circuit 43 is applied to the selected word line. The operation of row decoder 230 is controlled by sequencer 41.

[0056] Sense amplifiers 120 and 220 are circuits for adjusting the voltage applied to the bit lines of memory cell arrays 110 and 210, or the voltage of the read bit lines, and converting it into data. When reading data, sense amplifiers 120 and 220 acquire data read from the memory cell transistors in memory cell arrays 110 and 210 to the bit lines and transmit the acquired read data to input / output circuit 21. When writing data, sense amplifiers 120 and 220 transmit data written via the bit lines to the memory cell transistors. The operation of sense amplifiers 120 and 220 is controlled by sequencer 41.

[0057] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1. The input / output circuit 21 transfers the commands and addresses contained in the signals DQ<7:0> to the register 42. Furthermore, the input / output circuit 21 transmits and receives write data and read data with the sense amplifiers 120 and 220. The input / output circuit 21 functions both as an "input circuit" for receiving commands and the like from the memory controller 1 and as an "output circuit" for outputting data to the memory controller 1. Alternatively, the input and output circuits may be formed of separate circuits.

[0058] The logic control circuit 22 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals / RE and RE, and a write protect signal / WP from the memory controller 1. Furthermore, the logic control circuit 22 transmits a ready-busy signal R / B to the memory controller 1 to notify the outside of the status of the semiconductor memory device 2a.

[0059] The input / output circuit 21 and the logic control circuit 22 are circuits configured to input and output signals to and from the memory controller 1. That is, the input / output circuit 21 and the logic control circuit 22 are provided as interface circuits of the semiconductor memory device 2a.

[0060] The sequencer 41 controls the operation of various components, such as the planes PL1 and PL2 and the voltage generation circuit 43, based on control signals input from the memory controller 1 to the semiconductor memory device 2a. The sequencer 41 controls the operation of the memory cell arrays 110 and 210, among others. In this embodiment, the sequencer 41 is an example of a control unit of the semiconductor memory device 2a. Furthermore, both the sequencer 41 and the logic control circuit 22 can be considered control units.

[0061] The sequencer 41 includes a feature register 41a. The feature register 41a stores the operating parameters of the semiconductor memory device 2a. The operating parameters can be set by the SetFeature action described below.

[0062] Registers 42 include a command register 42a, an address register 42b, and a status register 42c. Command register 42a temporarily stores commands. Address register 42b temporarily stores addresses. Status register 42c stores status information indicating the status of semiconductor memory device 2a. More specifically, status register 42c stores status information indicating the status of planes PL1 and PL2. This status information is output from input / output circuit 21 to memory controller 1 in the form of a status signal in response to a request from memory controller 1.

[0063] The voltage generation circuit 43 generates the voltages required for writing, reading, and erasing data in the memory cell arrays 110 and 210, respectively, in response to instructions from the sequencer 41. These voltages include, for example, voltages applied to the multiple word lines and multiple bit lines of the memory cell arrays 110 and 210. The voltage generation circuit 43 can apply voltages individually to each word line, bit line, etc., so that planes PL1 and PL2 can operate in parallel with each other.

[0064] The input / output pad group 31 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the input / output circuit 21. Each terminal is provided separately for the signal DQ<7:0> and the data strobe signals DQS and / DQS. In this embodiment, the input / output pad group 31 is an example of a pad portion.

[0065] The logic control pad group 32 is provided with a plurality of terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is provided separately for each of the chip enable signal / CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signals / RE, RE, the write protect signal / WP, and the ready-busy signal R / B.

[0066] The power input terminal group 33 is provided with a plurality of terminals for receiving the application of various voltages required for the operation of the semiconductor memory device 2a. The voltages applied to each terminal include the power supply voltage VCC, VCCQ, VPP, and the ground voltage VSS. The power supply voltage VCC is a circuit power supply voltage applied externally as an operating power supply, for example, a voltage of approximately 2.5V. The power supply voltage VCC is used to generate the internal power supply voltage of the semiconductor memory device 2a, namely the voltage VDD. The power supply voltage VDD is, for example, a voltage of approximately 1.5V. The power supply voltage VCCQ is a power supply voltage lower than the power supply voltage VCC, for example, a voltage of 1.2V. The power supply voltage VCCQ is the input and output power supply voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2a.

[0067] 1.3 Circuit Structure of Memory Cell Array

[0068] Next, the circuit configuration of the memory cell array 110 will be described.

[0069] like Figure 3 As shown, the memory cell array 110 is composed of a plurality of blocks BLK. Figure 3 Only one of the multiple blocks BLK is shown in FIG. The configuration of the other blocks BLK in the memory cell array 110 is also similar to that in FIG. Figure 3 The shown configuration is the same.

[0070] like Figure 3 As shown, the block BLK includes, for example, four string groups SU (SU0-SU3). In addition, each string group SU includes a plurality of NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0-MT7) and selection transistors ST1 and ST2.

[0071] The memory cell transistor MT is connected in series between the selection transistor ST1 and the selection transistor ST2. The memory cell transistor MT7 on one end is connected to the source of the selection transistor ST1, and the memory cell transistor MT0 on the other end is connected to the drain of the selection transistor ST2.

[0072] The gates of the select transistors ST1 in each of the string groups SU0-SU3 are commonly connected to select gate lines SGD0-SGD3, respectively. The gates of the select transistors ST2 are commonly connected to the same select gate line SGS across multiple string groups SU within the same block BLK. The gates of the memory cell transistors MT0-MT7 within the same block BLK are commonly connected to word lines WL0-WL7, respectively. That is, while word lines WL0-WL7 and select gate line SGS are common across multiple string groups SU0-SU3 within the same block BLK, select gate line SGD is individually provided for each string group SU0-SU3, even within the same block BLK.

[0073] The memory cell array 110 is provided with m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS included in a string group SU. The drain of each select transistor ST1 in the NAND string NS is connected to the corresponding bit line BL. The source of each select transistor ST2 in the NAND string NS is connected to a source line SL. The source line SL is common to the sources of the multiple select transistors ST2 in the block BLK.

[0074] The data stored in multiple memory cell transistors MT within the same block BLK is erased at once. Meanwhile, data is read and written at once for multiple memory cell transistors MT connected to a single word line WL and belonging to a single string group SU. Each memory cell can store three bits of data, including an upper-order bit, a mid-order bit, and a lower-order bit.

[0075] That is, the semiconductor memory device 2a of this embodiment uses a TLC (Triple Level Cell) method, in which one memory cell transistor MT stores three bits of data, as a method for writing data into the memory cell transistor MT. Alternatively, an MLC (Multi-Level Cell) method, in which one memory cell transistor MT stores two bits of data, may be used as a method for writing data into the memory cell transistor MT. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0076] In the following description, a set of 1-bit data stored in a plurality of memory cell transistors MT connected to one word line WL and belonging to one string unit SU is referred to as a "page." Figure 3 In FIG. 1 , a symbol “MG” is attached to one of the sets including the plurality of memory cell transistors MT.

[0077] As in this embodiment, when one memory cell transistor MT stores three bits of data, a set of multiple memory cell transistors MT connected to a common word line WL within a string group SU can store three pages of data. Hereinafter, a page containing a set of lower-order bit data will be referred to as a "lower-order page," and the data on the lower-order page will be referred to as "lower-order page data." Similarly, a page containing a set of mid-order bit data will be referred to as a "mid-order page," and the data on the mid-order page will be referred to as "mid-order page data." A page containing a set of upper-order bit data will be referred to as an "upper-order page," and the data on the upper-order page will be referred to as "upper-order page data."

[0078] 1.4 Cross-sectional structure of a semiconductor memory device

[0079] Next, the memory cell array 110 and its peripheral structures will be described.

[0080] like Figure 4 As shown, in the memory cell array 110, a plurality of NAND strings NS are formed on the conductive layer 320. The conductive layer 320 is also called a buried source line (BSL), which is equivalent to Figure 3 The source line SL is shown.

[0081] Multiple wiring layers 333 functioning as select gate lines SGS, multiple wiring layers 332 functioning as word lines WL, and multiple wiring layers 331 functioning as select gate lines SGD are stacked above the conductive layer 320. An insulating layer (not shown) is disposed between the stacked wiring layers 333, 332, and 331.

[0082] A plurality of memory holes 334 are formed in the memory cell array 110. The memory holes 334 are holes that penetrate the wiring layers 333, 332, and 331, and the insulating layer (not shown) therebetween, in the vertical direction, and reach the conductive layer 320. A blocking insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the sides of the memory holes 334, and a conductive pillar 338 is embedded within them. The conductive pillar 338, for example, comprises polysilicon and functions as a region forming a channel when the memory cell transistor MT and the select transistors ST1 and ST2 included in the NAND string NS operate. Thus, a pillar-shaped structure comprising the blocking insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is formed within the memory hole 334.

[0083] The portions of the columnar body formed inside the memory hole 334 that intersect the stacked wiring layers 333, 332, and 331 function as transistors. The portion of the transistor that intersects the wiring layer 331 among these multiple transistors functions as a selection transistor ST1. The portion of the transistor that intersects the wiring layer 332 among the multiple transistors functions as a memory cell transistor MT (MT0 to MT7). The portion of the transistor that intersects the wiring layer 333 among the multiple transistors functions as a selection transistor ST2. With this configuration, the columnar body formed inside each memory hole 334 functions as a selection transistor ST1. Figure 3 The NAND string NS shown in the figure functions as follows: The conductive pillar 338 located inside the pillar functions as a channel for the memory cell transistor MT and the select transistors ST1 and ST2.

[0084] A wiring layer functioning as a bit line BL is formed above the conductive column 338. A contact plug 339 is formed at the upper end of the conductive column 338 to connect the conductive column 338 and the bit line BL.

[0085] and Figure 4 The same composition as shown is along Figure 4 There are multiple ones arranged in the depth direction of the paper. Figure 4 A set of multiple NAND strings NS arranged in a row in the depth direction of the paper forms a string group SU.

[0086] In the semiconductor memory device 2a of this embodiment, a peripheral circuit PER is provided below the memory cell array 110, that is, between the memory cell array 110 and the semiconductor substrate 300. The peripheral circuit PER is provided to implement operations such as writing, reading, and erasing data in the memory cell array 110. Figure 2 The sense amplifier 120, the row decoder 130, and the voltage generating circuit 43 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors, RC (Resistor-Capacitor) circuits, and the like. Figure 4 In the illustrated example, the transistor TR formed on the semiconductor substrate 300 is electrically connected to the bit line BL located above the memory cell array 110 via a contact 924 .

[0087] 1.5 Structure of Sense Amplifier

[0088] Next, the circuit configuration of the sense amplifier 120 will be described.

[0089] The sense amplifier 120 includes a plurality of sense amplifier groups respectively associated with the plurality of bit lines BL. Figure 5The circuit configuration of one of the sense amplifier groups SAU is shown in FIG.

[0090] like Figure 5 As shown, the sense amplifier unit SAU includes a sense amplifier unit SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier unit SA and latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS so as to be able to transmit and receive data to and from each other.

[0091] During a read operation, for example, the sense amplifier unit SA senses data read from the corresponding bit line BL and determines whether the read data is "0" or "1." The sense amplifier unit SA includes, for example, a p-channel MOS (Metal Oxide Semiconductor) transistor, namely transistor TR1; n-channel MOS transistors, namely transistors TR2 to TR9; and a capacitor C10.

[0092] One end of transistor TR1 is connected to a power supply line, and the other end of transistor TR1 is connected to transistor TR2. The gate of transistor TR1 is connected to node INV within latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end of transistor TR2 is connected to node COM. Signal BLX is input to the gate of transistor TR2. One end of transistor TR3 is connected to node COM, and the other end of transistor TR3 is connected to transistor TR4. Signal BLC is input to the gate of transistor TR3. Transistor TR4 is a high-voltage-resistant MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. Signal BLS is input to the gate of transistor TR4.

[0093] One end of transistor TR5 is connected to node COM, and the other end of transistor TR5 is connected to node SRC. The gate of transistor TR5 is connected to node INV. One end of transistor TR6 is connected between transistor TR1 and transistor TR2, and the other end of transistor TR6 is connected to node SEN. Signal HLL is input to the gate of transistor TR6. One end of transistor TR7 is connected to node SEN, and the other end of transistor TR7 is connected to node COM. Signal XXL is input to the gate of transistor TR7.

[0094] One end of transistor TR8 is grounded, and the other end of transistor TR8 is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end of transistor TR9 is connected to bus line LBUS. Signal STB is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. Clock CLK is input to the other end of capacitor C10.

[0095] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequencer 41. Furthermore, a power supply line connected to one end of transistor TR1 is applied with, for example, voltage VDD, which is an internal power supply voltage of semiconductor memory device 2a, and a node SRC is applied with, for example, voltage VSS, which is a ground voltage of semiconductor memory device 2a.

[0096] Latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store read data. Latch circuit XDL is connected to input / output circuit 21 and is used to input / output data between sense amplifier group SAU and input / output circuit 21. Read data is stored in latch circuit XDL so that it can be output from input / output circuit 21 to memory controller 1. For example, data read by sense amplifier group SAU is stored in any one of latch circuits ADL, BDL, and CDL, then transferred to latch circuit XDL and output from latch circuit XDL to input / output circuit 21. Furthermore, data input from memory controller 1 to input / output circuit 21 is transferred from input / output circuit 21 to latch circuit XDL, and then from latch circuit XDL to any one of latch circuits ADL, BDL, and CDL. In this embodiment, latch circuit XDL is an example of a data storage unit.

[0097] Latch circuit SDL includes, for example, inverters IV11 and IV12, and n-channel MOS transistors, namely, transistors TR13 and TR14. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end of transistor TR13 is connected to bus line LBUS. Signal STI is input to the gate of transistor TR13. One end of transistor TR14 is connected to node LAT, and the other end of transistor TR14 is connected to bus line LBUS. Signal STL is input to the gate of transistor TR14. For example, the data stored in node LAT corresponds to the data stored in latch circuit SDL. Furthermore, the data stored in node INV corresponds to the inverse of the data stored in node LAT. The circuit configuration of latch circuits ADL, BDL, CDL, and XDL is similar to that of latch circuit SDL, and therefore their description will be omitted.

[0098] 1.6 Threshold Distribution of Memory Cell Transistors

[0099] Next, the threshold distribution of the memory cell transistor MT will be described.

[0100] Figure 6Schematically shows the threshold distribution of the memory cell transistor MT. Figure 6 The middle graph shows the correspondence between the threshold voltage of the memory cell transistor MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0101] When the TLC method is adopted as in this embodiment, a plurality of memory cell transistors MT are as follows. Figure 6 As shown in the middle section of , 8 threshold distributions are formed. These 8 threshold distributions (write levels) are called "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level in the order of threshold voltage from low to high. Figure 6 The table in the upper row shows an example of 3-bit data allocated to each level of the threshold voltage.

[0102] In this manner, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is allocated corresponding to each candidate level as described above.

[0103] A read voltage used in a read operation is set between adjacent threshold distributions. The "read voltage" refers to the voltage applied to the word line WL connected to the memory cell transistor MT to be read, that is, the selected word line, during the read operation. During the read operation, data is determined based on the result of the determination of whether the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage. For example, Figure 6 As schematically shown in the lower diagram of FIG, read voltage VrA, which determines whether the threshold voltage of memory cell transistor MT is included in either the "ER" level or the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. Other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are also set in the same manner as read voltage VrA.

[0104] The read pass voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage in the highest threshold distribution (eg, "G" level). The memory cell transistor MT having the read pass voltage VPASS_READ applied to the gate is turned on regardless of stored data.

[0105] When the data allocation described above is applied, during a read operation, a page of data for lower-order bits (lower-order page data) can be determined by reading using read voltages VrA and VrE. A page of data for middle-order bits (middle-order page data) can be determined by reading using read voltages VrB, VrD, and VrF. A page of data for upper-order bits (upper-order page data) can be determined by reading using read voltages VrC and VrG.

[0106] 1.7 Programming Operation of Semiconductor Memory Devices

[0107] Next, the programming operation of semiconductor memory device 2a will be described. Hereinafter, an example in which the programming operation targets plane PL1 will be described, and the same applies to plane PL2.

[0108] Figure 7 Indicates the potential change of each wiring during the programming operation. During the programming operation, the sense amplifier 120 changes the potential of each bit line BL according to the programming data. An "L" level, such as the ground voltage VSS (0V), is applied to the bit line BL connected to the memory cell transistor MT that is the programming target (the threshold voltage of which should be increased). An "H" level, such as 2.5V, is applied to the bit line BL connected to the memory cell transistor MT that is not the programming target (the threshold voltage of which should be maintained). The former bit line BL is Figure 7 The latter bit line BL is marked as "BL(0)". Figure 7 It is marked as “BL(1)” in the figure.

[0109] The row decoder 130 selects any block BLK as the target for the write operation, and thus selects any string group SU. More specifically, the voltage generating circuit 43 applies, for example, 5V to the select gate line SGD (selection gate line SGDsel) in the selected string group SU via the row decoder 130. This turns on the select transistor ST1. Meanwhile, the voltage generating circuit 43 applies, for example, voltage VSS to the select gate line SGS via the row decoder 130. This turns off the select transistor ST2.

[0110] Furthermore, a voltage of, for example, 5V is applied from the voltage generating circuit 43 via the row decoder 130 to the select gate line SGD (non-select select gate line SGDusel) of the non-selected string groups SU in the selected block BLK. This turns on the select transistor ST1. Furthermore, the select gate line SGS is commonly connected to the string groups SU included in each block BLK. Therefore, the select transistor ST2 is also turned off in the non-selected string groups SU.

[0111] Furthermore, the voltage VSS, for example, is applied to the selection gate line SGD and the selection gate line SGS in the non-selected block BLK from the voltage generating circuit 43 via the row decoder 130. As a result, the selection transistors ST1 and ST2 are turned off.

[0112] The source line SL is set to a potential higher than that of the select gate line SGS. This potential is, for example, 1V.

[0113] Thereafter, the potential of the selection gate line SGDsel in the selection block BLK is set to, for example, 2.5V. This potential is a voltage that can turn on the selection transistor ST1 corresponding to the bit line BL(0) assigned 0V in the example, and turn off the selection transistor ST1 corresponding to the bit line BL(1) assigned 2.5V. Thus, in the selection string group SU, the selection transistor ST1 corresponding to the bit line BL(0) is turned on, and the selection transistor ST1 corresponding to the bit line BL(1) assigned 2.5V is turned off. On the other hand, the potential of the non-selection selection gate line SGDusel is set to, for example, voltage VSS. Thus, in the non-selection string group SU, the selection transistor ST1 is turned off regardless of the potentials of the bit line BL(0) and the bit line BL(1).

[0114] Furthermore, the row decoder 130 selects any word line WL in the selected block BLK as the target of the write operation. A voltage VPGM, for example, is applied from the voltage generating circuit 43 via the row decoder 130 to the word line WL (selected word line WLsel) that is the target of the write operation. Meanwhile, a voltage VPASS_PGM, for example, is applied from the voltage generating circuit 43 via the row decoder 130 to the other word lines WL (unselected word line WLusel). The voltage VPGM is a high voltage used to inject electrons into the charge storage layer 336 through tunneling. The voltage VPASS_PGM is a voltage sufficient to turn on the memory cell transistor MT connected to the word line WL while not changing the threshold voltage. The voltage VPGM is a voltage higher than VPASS_PGM.

[0115] In the NAND string NS corresponding to the bit line BL(0) to be programmed, the select transistor ST1 is turned on. Consequently, the channel potential of the memory cell transistor MT connected to the selected word line WLsel becomes 0 V. The potential difference between the control gate and the channel increases, which in turn injects electrons into the charge storage layer 336, raising the threshold voltage of the memory cell transistor MT.

[0116] In the NAND string NS corresponding to the bit line BL(1) not being programmed, the select transistor ST1 is turned off. Consequently, the channel of the memory cell transistor MT connected to the selected word line WLsel is electrically floating, and the channel potential is raised to approximately voltage VPGM through capacitive coupling with the word line WL and the like. The potential difference between the control gate and the channel decreases, and as a result, electrons are not injected into the charge storage layer 336, thereby maintaining the threshold voltage of the memory cell transistor MT. Specifically, the higher the threshold distribution level shifts, the less the threshold voltage fluctuates.

[0117] 1.8 Reading Operation of Semiconductor Memory Device

[0118] Next, the read operation of semiconductor memory device 2a will be described. The following example describes the case where the read operation targets plane PL1, and the same applies to plane PL2. The verify operation performed after the program operation is the same as the read operation described below.

[0119] Figure 8 Indicates the potential change of each wiring during the read operation. In the read operation, the NAND string NS including the memory cell transistor MT to be read is selected. Alternatively, the string group SU including the page to be read is selected.

[0120] First, 5V is applied, for example, to the selection gate line SGDsel, the non-selection selection gate line SGDusel, and the selection gate line SGS from the voltage generating circuit 43 via the row decoder 130. As a result, the selection transistor ST1 and the selection transistor ST2 included in the selection block BLK are turned on. In addition, the read pass voltage VPASS_READ is applied, for example, to the selection word line WLsel and the non-selection word line from the voltage generating circuit 43 via the row decoder 130. The read pass voltage VPASS_READ is a voltage of such a degree that the memory cell transistor MT can be turned on regardless of the threshold voltage of the memory cell transistor MT and does not change the threshold voltage. As a result, current is conducted in all NAND strings NS included in the selection block BLK, regardless of whether the string group SU is selected or the non-selection string group SU.

[0121] Next, a read voltage Vr such as VrA is applied from the voltage generating circuit 43 via the row decoder 130 to the word line WL (selected word line WLsel) connected to the memory cell transistor MT to be read. A read pass voltage VPASS_READ is applied to other word lines (unselected word lines WLusel).

[0122] Furthermore, the voltages applied to the selected select gate line SGDsel and the select gate line SGS are maintained, and a voltage VSS, for example, is applied to the unselected select gate line SGDusel from the voltage generating circuit 43 via the row decoder 130. Consequently, the select transistors ST1 included in the selected string group SU remain in the on state, while the select transistors ST1 included in the unselected string group SU are turned off. Furthermore, the select transistors ST2 included in the selected block BLK are turned on in both the selected string group SU and the unselected string group SU.

[0123] As a result, in the NAND strings NS included in the unselected string group SU, at least the select transistor ST1 is turned off, and thus no current path is formed. On the other hand, the NAND strings NS included in the selected string group SU form or do not form a current path depending on the relationship between the read voltage Vr applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0124] The sense amplifier 120 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 120 reads data based on the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT, which is the target of the read operation, is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data reading can be performed based not on the current flowing through the bit line BL but on the temporal change in the potential of the bit line BL. In this latter case, the bit line BL is precharged to a specified potential.

[0125] The verification operation is performed in the same manner as the read operation. In the verification operation, a verification voltage such as VfyA is applied from the voltage generating circuit 43 via the row decoder 130 to the word line WL connected to the memory cell transistor MT to be verified.

[0126] In addition, the operation of applying a voltage of 5 V to the selected select gate line SGDsel and the unselected select gate line SGDusel in the initial stage of the programming operation may be omitted. Similarly, the operation of applying a voltage of 5 V to the unselected select gate line SGDusel and applying the read pass voltage VPASS_READ to the selected word line WLsel in the initial stage of the read operation (verification operation) may be omitted.

[0127] 1.9 Specific Configuration for Outputting Data from a Semiconductor Memory Device

[0128] Next, a specific configuration for outputting data from the semiconductor storage device 2 a to the memory controller 1 will be described. Figure 9 1 is a diagram schematically showing a configuration along a path from the memory cell array 110 to the input / output pad group 31 in the semiconductor memory device 2 a .

[0129] like Figure 9 As shown, the sense amplifier 120 includes Figure 5The sense amplifier group SAU, multiple latch circuits XDL, and multiplexer 121 are shown. Data read from the memory cell array 110 is sent from the sense amplifier group SAU to the latch circuits XDL for temporary storage, and then transferred to the first storage unit 510 via the multiplexer 121. The multiplexer 121 and the first storage unit 510 are connected via a first data bus 501 comprising, for example, 128 wires. The number of wires included in the first data bus 501 is not limited to 128. The number of wires included in the first data bus 501 is smaller than the number of wires connecting the multiple latch circuits XDL and the multiplexer 121. The multiplexer 121 sequentially transfers the data sent from the multiple latch circuits XDL to the first storage unit 510 via the first data bus 501.

[0130] The first storage unit 510 is a FIFO circuit configured to store a plurality of data read from the memory cell array 110, that is, to perform a so-called "first in, first out (FIFO)" operation. The first storage unit 510 temporarily stores a plurality of data transmitted from the multiplexer 121 and outputs the data to the input / output circuit 21 in order of the data input first. The first storage unit 510 and the input / output circuit 21 are connected via, for example, a second data bus 502 including 16 signal lines. In addition, the number of wiring lines included in the second data bus 502 is not limited to 16. After the data input from the first storage unit 510 to the input / output circuit 21 is temporarily stored by the second storage unit 520, it is output to the outside as the signal DQ<7:0> from the input / output pad group 31.

[0131] The input / output circuit 21 includes a second storage unit 520, a write indicator generating circuit 541, a read indicator generating circuit 542, a multiplexer 531, and a driver 532. The circuit comprising the second storage unit 520, the write indicator generating circuit 541, the read indicator generating circuit 542, the multiplexer 531, and the driver 532 is provided individually for each of the eight pads of the input / output pad group 31, namely, the eight pads corresponding to the signal DQ<7:0>. In other words, the input / output circuit 21 includes eight second storage units 520 and eight multiplexers 531, each of which is provided. Figure 9 Among these, only those connected to the DQ<0> pad are shown, and the others are omitted.

[0132] Second storage unit 520 receives data sent from first storage unit 510 and stores multiple data items. Second storage unit 520 is divided into a portion for storing even-numbered data and a portion for storing odd-numbered data. The former portion is hereinafter referred to as "second storage unit 521." The latter portion is hereinafter referred to as "second storage unit 522."

[0133] Like the first storage unit 510, the second storage unit 520 is a FIFO circuit configured to perform a first-in, first-out (FIFO) operation. After temporarily receiving data input from the first storage unit 510, the second storage unit 520 outputs the data to the DQ<0> pad in the order in which the data was input. This data is then output alternately by the second storage unit 521 and the second storage unit 522 via the multiplexer 531 and the driver 532.

[0134] The write pointer generation circuit 541 is a circuit for generating a write pointer Wptr. The write pointer Wptr is an indicator indicating a storage position (write position) when the second storage unit 520 stores data sent from the first storage unit 510 .

[0135] The read pointer generation circuit 542 generates a read pointer Rptr. The read pointer Rptr indicates the storage position (read position) of data in the second storage unit 520 when data is sent from the second storage unit 520 to the driver 532.

[0136] A pair of circuits including a write indicator generation circuit 541 and a read indicator generation circuit 542 are provided for each of the second storage unit 521 and the second storage unit 522 . Figure 9 Only the write index generation circuit 541 and the read index generation circuit 542 provided for the second storage unit 522 are shown in the figure, and the write index generation circuit 541 and the read index generation circuit 542 provided for the second storage unit 521 are omitted from the figure.

[0137] The sequencer 41 controls the transmission of data from the first storage unit 510 to the second storage unit 520 and the transmission of data from the second storage unit 520 to the multiplexer 531 .

[0138] Specifically, the sequencer 41 controls the operation of the first storage unit 510 and the write pointer generation circuit 541 by sending the clock signal CLK1 to the first storage unit 510 and the write pointer generation circuit 541, respectively. The clock signal CLK1 is a signal that specifies the timing for the second storage unit 520 to take in data. The write pointer generation circuit 541 generates a write pointer Wptr based on the input clock signal CLK1. The write pointer Wptr is incremented by the write pointer generation circuit 541 when the clock signal CLK1 rises from the "L" level to the "H" level. As the write pointer Wptr is incremented, the storage position (write position) of the data in the second storage unit 520 is sequentially switched when the second storage unit 520 stores the data taken in from the first storage unit 510.

[0139] Furthermore, the sequencer 41 controls the operation of the readout indicator generation circuit 542 and the multiplexer 531 by sending the clock signal CLK2 to the readout indicator generation circuit 542 and the multiplexer 531, respectively. The sequencer 41 generates the clock signal CLK2 based on the readout enable signal / RE input from the memory controller 1. The readout indicator generation circuit 542 generates the readout indicator Rptr based on the input clock signal CLK2. The readout indicator Rptr is incremented by the readout indicator generation circuit 542 at the timing when the clock signal CLK2 rises from the "L" level to the "H" level. As the readout indicator Rptr increments, the storage location (readout location) of the data in the second storage unit 520 is sequentially switched when the data is sent from the second storage unit 520 to the driver 532. This implements the "first-in, first-out" operation of the second storage unit 520.

[0140] The multiplexer 531 alternately receives even data input from the second storage unit 521 and odd data input from the second storage unit 522 , and outputs the data to the driver 532 .

[0141] Furthermore, the first storage unit 510 and the input / output circuit 21 are configured using transistors with a lower threshold voltage than, for example, the transistors used in the sense amplifier 120, for high-speed operation. In this embodiment, the first storage unit 510 and the input / output circuit 21 are an example of a data transmission circuit provided between the latch circuit XDL and the input / output pad group 31.

[0142] Figure 10 2 is a block diagram showing a configuration for supplying current to the first storage unit 510 and the input / output circuit 21. Figure 10 Only the portion corresponding to the DQ<0> pad is shown in the figure, and the other portions are omitted.

[0143] like Figure 10 As shown, the power supply voltage input terminals of the first storage unit 510 and the input / output circuit 21 are connected to the VCCQ pad 60<0> via the wiring 61. The VCCQ pad 60<0> is included in Figure 2 In the power input terminal group 33 shown, the VCCQ pad 60 <0> functions as a first power voltage input terminal and supplies the power voltage VCCQ to the first storage unit 510 and the input / output circuit 21 via the wiring 61 .

[0144] The ground voltage input terminal of the first storage unit 510 is connected to the VSS pad 62<0> via the wiring 63a and the wiring 64. The ground voltage input terminal of the input / output circuit 21 is connected to the VSS pad 62<0> via the wiring 63b and the wiring 64. The VSS pad 62<0> functions as the second power supply voltage input terminal. The VSS pad 62<0> is included in Figure 2 In the power input terminal group 33 shown, the VSS pad 62 <0> applies the ground voltage VSS to the first storage unit 510 and the input / output circuit 21 via the wirings 63 a and 63 b and the wiring 64 .

[0145] Transistors 65a and 65b, which function as foot switches, are provided on wirings 63a and 63b, respectively. When transistors 65a and 65b are in the on state, current is supplied to the first storage unit 510 and the input / output circuit 21, enabling operation of the first storage unit 510 and the input / output circuit 21. When transistors 65a and 65b are in the off state, current supply to the first storage unit 510 and the input / output circuit 21 is stopped. This can, for example, reduce the standby current of the first storage unit 510 and the input / output circuit 21. Transistors 65a and 65b are controlled by a control signal FSW_enable sent from the sequencer 41. Transistors 65a and 65b are provided between the ground voltage input terminals of the first storage unit 510 and the input / output circuit 21 and wiring 64 connected to the VSS pad 62<0>, controlling the connection or disconnection between the first storage unit 510 and the input / output circuit 21 and the VSS pad 62<0>. In this embodiment, transistors 65a and 65b are examples of a blocking unit and a switching element capable of blocking the current supply to the first storage unit 510 and the input / output circuit 21. Transistors 65a and 65b, serving as blocking units and switching elements, may also be provided between the power supply voltage input terminals of the first storage unit 510 and the input / output circuit 21 and the wiring 61 connected to the VCCQ pad 60<0>. In this case, transistors 65a and 65b function as read switches, controlling the connection and disconnection between the first storage unit 510 and the input / output circuit 21 and the VCCQ pad 60<0>.

[0146] 1.10 Reading Operation of Semiconductor Memory Device

[0147] Next, a description will be given of specific signal reception and transmission during a read operation between the semiconductor memory device 2a and the memory controller 1. The following description will focus on an example where the read operation targets plane PL1, but the same applies to plane PL2.

[0148] like Figure 11 As shown, during the read operation, first, when the memory controller 1 switches the chip enable signal / CE0 corresponding to the semiconductor memory device 2a from the "H" level to the "L" level at time t10, the semiconductor memory device 2a transitions to the enabled state. As a result, the semiconductor memory device 2a becomes capable of receiving signals from the memory controller 1. In addition, at this time, the sequencer 41 Figure 10The transistors 65 a and 65 b shown are switched from an off state to an on state to supply current to the first storage unit 510 and the input / output circuit 21 , thereby driving the first storage unit 510 and the input / output circuit 21 , respectively.

[0149] Next, the memory controller 1 sequentially inputs a signal including "00h," a plurality of "ADDs," and "30h" as signals DQ<7:0> to the semiconductor memory device 2a. "00h" is a command for executing a data read operation from the memory cell array 110. "ADD" is a signal that specifies the address from which data is to be read. "30h" is a command for starting a read operation. Figure 10 Here, t11 represents the time when the memory controller 1 starts inputting the signal DQ<7:0> to the semiconductor memory device 2a. Hereinafter, a signal including "00h", a plurality of "ADDs", and "30h" is also referred to as a "read operation command set CSr".

[0150] After time t11, memory controller 1 begins toggling write enable signal / WE. As described above, write enable signal / WE is a signal for receiving data from memory controller 1 to semiconductor memory device 2a. Write enable signal / WE alternately switches (toggles) between an "H" level and an "L" level. The thus-toggled write enable signal / WE serves as an "input signal" for receiving data.

[0151] When "00h" and "30h" are included in the input signals DQ<7:0>, the memory controller 1 switches the command latch enable signal CLE from "L" to "H" to fetch "00h" and "30h" as commands into the semiconductor memory device 2a. Furthermore, when multiple "ADD"s are included in the input signals DQ<7:0>, the memory controller 1 switches the address latch enable signal ALE from "L" to "H" to fetch the multiple "ADD"s as address information for data readout into the semiconductor memory device 2a. The address information fetched by the semiconductor memory device 2a is stored in register 42. The address information includes a block address and a row address.

[0152] Figure 10In FIG, t12 represents the time when "30h" is loaded into the semiconductor memory device 2a. After time t12, internal operations in the semiconductor memory device 2a begin. Specifically, the sequencer 41 activates the row decoder 130 based on the address information of the data read source stored in the register 42. The row decoder 130 receives the address information from the register 42, selects a block of the memory cell array 110 based on the block address included in the address information, and selects the word line WL based on the row address included in the address information. Furthermore, the row decoder 130 switches the switch state of the switch group so that the voltage from the voltage generating circuit 43 is applied to the selected word line WL. Thus, preparations for reading data from the memory cell array 110 are completed. Subsequently, the sense amplifier 120 obtains the data read from the memory cell transistor MT of the memory cell array 110 to the bit line BL and temporarily stores it in the latch circuit XDL. In addition, the read data temporarily stored by the latch circuit XDL is transmitted to the first storage unit 510 and the input / output circuit 21. The preparation for outputting data from the semiconductor storage device 2 a to the memory controller 1 is completed as described above. Figure 11 Here, tR represents the time reserved for the internal operation of the semiconductor memory device 2a. That is, at time t13, which is a specified time tR after time t12, the semiconductor memory device 2a is ready to output data to the memory controller 1. The specified time tR is, for example, 50 μsec to 100 μsec.

[0153] At time t14, a specified time after time t13, memory controller 1 begins toggling read enable signal / RE. As described above, read enable signal / RE is a signal used by memory controller 1 to instruct semiconductor memory device 2a to output data to memory controller 1. It is input to input / output pad group 31 of semiconductor memory device 2a. After time t13, read enable signal / RE alternately switches (toggles) between "H" and "L" levels. The thus-toggled read enable signal / RE serves as a "read control signal" for instructing data output.

[0154] Whenever the read enable signal / RE is switched (i.e., whenever each read control signal is input), the semiconductor memory device 2a outputs data as the signal DQ<7:0> from the input / output pad group 31 and switches the data selection signal DQS between the "H" level and the "L" level. Figure 11 In FIG, data output as the signal DQ<7:0> is respectively indicated as “D.” Furthermore, the timing at which the initial data is output and the data strobe signal DQS is switched is indicated as time t15. Figure 11 In FIG. 1 , arrows indicate the corresponding relationship between the switching of the read enable signal / RE input from the memory controller 1 and the switching of the data strobe signal DQS output from the semiconductor memory device 2 a .

[0155] The output of read data from the semiconductor memory device 2a is performed by dividing one data into even data including even bits and odd data including odd bits and outputting them alternately. Figure 11 Each data indicated as "D" in the figure is data to be output as either even data or odd data.

[0156] Let's say, Figure 1 As shown, when a plurality of semiconductor memory devices 2a to 2d are present in a memory system 3, the memory controller 1 may, for example, instruct a designated semiconductor memory device 2a to read data and before obtaining data from the designated semiconductor memory device 2a, instruct another semiconductor memory device 2b to read data in an interrupt manner. For example, in the case where the memory controller 1 and the semiconductor memory device 2a are connected as shown in FIG. Figure 11 In the case of receiving the signal as shown, the data read operation instructed to the semiconductor memory device 2a is completed at time t12, but the memory controller 1 needs to wait from time t12 to time t13 until the internal operation of the semiconductor memory device 2a is completed. During this period, if the memory controller 1 instructs another semiconductor memory device 2b to perform a specified operation, as shown in FIG. Figure 12 As shown, memory controller 1 switches chip enable signal / CE0 from "L" level to "H" level at a predetermined time t20 after time t12. Furthermore, memory controller 1 switches chip enable signal / CE1 of another semiconductor memory device 2b from "H" level to "L" level, thereby enabling semiconductor memory device 2b and instructing semiconductor memory device 2b to perform a predetermined operation.

[0157] exist Figure 12 In the case shown, if current continues to flow through the first storage unit 510 and the input / output circuit 21 after time t13 until data starts to be output from the semiconductor memory device 2a to the memory controller 1, the standby current increases. In particular, since the first storage unit 510 and the input / output circuit 21 use transistors with a low threshold voltage to increase their operation speed, there is a concern that the standby current is likely to increase.

[0158] Therefore, after the sequencer 41 of this embodiment completes the internal operation of the semiconductor memory device 2a at time t13, when the specified time tS has passed from time t13, the read enable signal / RE is not switched (the read control signal is not input) and the chip enable signal / CE0 is not at the "L" level, that is, when the semiconductor memory device 2a is not in the enabled state, the sequencer 41 of this embodiment will Figure 10The transistors 65a and 65b shown are switched to an off state by the control signal FSW_enable. Consequently, at time t21, the current supply to the first storage unit 510 and the input / output circuit 21 is stopped. Therefore, after time t21, the standby current of the first storage unit 510 and the input / output circuit 21 is reduced. The specified time tS will be referred to as "wait time tS" below. After time t21, the semiconductor memory device 2a enters a state of waiting to output data to the memory controller 1. "Wait time tS" can be considered to be the time during which the semiconductor memory device 2a maintains a data output waiting state to the memory controller 1 after the read data temporarily stored by the latch circuit XDL is transferred to the first storage unit 510 and the input / output circuit 21. After transferring data to the first storage unit 510 and the input / output circuit 21, the semiconductor memory device 2a of this embodiment outputs data to the memory controller 1 using the first storage unit 510 and the input / output circuit 21 if the read enable signal / RE is switched (the read control signal is input) during the "wait time tS". If the read enable signal / RE is not switched (the read control signal is not input) until the "wait time tS" expires, the current supply to the first storage unit 510 and the input / output circuit 21 is stopped. Alternatively, data output from the semiconductor memory device 2a to the memory controller 1 may be instructed by methods other than switching the read enable signals / RE and RE (the input of the read control signal). In this case, after transferring data to the first storage unit 510 and the input / output circuit 21, the semiconductor memory device 2a of this embodiment stops supplying current to the first storage unit 510 and the input / output circuit 21 if data output is not performed until the "wait time tS" expires.

[0159] When the current supply to the first storage unit 510 and the input / output circuit 21 is stopped at time t21 (when the data output wait state is not maintained), the data transferred from the sense amplifier 120 to the first storage unit 510 and the input / output circuit 21 is erased. Therefore, when the semiconductor memory device 2a subsequently outputs data to the memory controller 1, the memory controller 1 needs to input a data output operation command to the semiconductor memory device 2a.

[0160] Specifically, if Figure 12 As shown, when the memory controller 1 causes the semiconductor memory device 2a to output data at time t22 after time t21, it first switches the chip enable signal / CE0 from "H" level to "L" level. As a result, the semiconductor memory device 2a becomes enabled. At this time, the sequencer 41 uses the control signal FSW_enable to enable the semiconductor memory device 2a. Figure 10The transistors 65 a and 65 b shown are switched from an off state to an on state, thereby supplying current to the first storage unit 510 and the input / output circuit 21 , thereby driving the first storage unit 510 and the input / output circuit 21 , respectively.

[0161] Next, the memory controller 1 sequentially inputs a signal including "05h," multiple "ADDs," and "E0h" as signals DQ<7:0> to the semiconductor memory device 2a. "05h" is a command for causing the memory cell array 110 to output data. "ADD" is a signal that specifies the address from which data is to be read. "E0h" is a command for starting a read operation. Figure 12 Here, t23 indicates the time when the memory controller 1 starts inputting the signal DQ<7:0> to the semiconductor memory device 2a. Hereinafter, a signal including "05h", a plurality of "ADDs", and "E0h" is also referred to as "data output operation command set CSd".

[0162] After time t23, the memory controller 1 starts to trigger the write enable signal / WE. In addition, the memory controller 1 activates the command latch enable signal CLE and the address latch enable signal ALE as shown in FIG1. Figure 12 As shown, the semiconductor memory device 2a switches between the "H" level and the "L" level, and "05h" and "E0h" are read as commands into the semiconductor memory device 2a. A plurality of "ADD" are also read as address information of the data read source into the semiconductor memory device 2a. The address information read into the semiconductor memory device 2a is stored in the register 42.

[0163] Figure 12 In the figure, t24 represents the time when "E0h" is taken into the semiconductor memory device 2a. After the specified time tWHR2 from the time t24 to the time t25, the memory controller 1 starts to trigger the read enable signal / RE. The specified time tWHR2 is the time to prepare for transferring the read data temporarily stored in the latch circuit XDL to the first storage unit 510 and the input / output circuit 21 so that the semiconductor memory device 2a can output the data to the memory controller 1. After the time t25, the memory controller 1 starts to trigger the read enable signal / RE. Figure 12 As shown, the read enable signal / RE and the data strobe signal DQS are switched between the "H" level and the "L" level, respectively. As a result, the semiconductor memory device 2a outputs the data as the signal DQ<7:0> to the memory controller 1.

[0164] As described above, in the semiconductor memory device 2a of this embodiment, when the current supply to the first storage unit 510 and the input / output circuit 21 is temporarily stopped at time t21, the data output command set CSd must be re-input to the semiconductor memory device 2a as the signal DQ<7:0>. While the data output command set CSd is being input from the memory controller 1 to the semiconductor memory device 2a, other operations, such as data input / output operations, cannot be performed on the other semiconductor memory devices 2b to 2d. This degrades the bus usage efficiency of the semiconductor memory device 2a.

[0165] On the other hand, Figure 12 When the current supply to the first storage unit 510 and the input / output circuit 21 is stopped at time t21 after the waiting time tS has elapsed from time t13 shown in the figure, the read data can continue to be stored in the first storage unit 510 and the input / output circuit 21. In this case, data can be output from the semiconductor memory device 2a to the memory controller 1 without inputting the data output operation command set CSd from the memory controller 1 to the semiconductor memory device 2a. However, if the current supply to the first storage unit 510 and the input / output circuit 21 is not stopped, there is a concern that the waiting current may increase.

[0166] Therefore, in the semiconductor memory device 2a of this embodiment, the Figure 12 The timing for stopping the current supply to the first storage unit 510 and the input / output circuit 21 can be changed after time t13, based on the wait time tS shown. In other words, the semiconductor memory device 2a of this embodiment is configured so that after the read data temporarily stored in the latch circuit XDL by the read operation is transferred to the first storage unit 510 and the input / output circuit 21, the wait time tS for maintaining the data output wait state to the memory controller 1 can be changed according to an instruction from the memory controller 1. Next, the configuration of the semiconductor memory device 2a of this embodiment will be described.

[0167] In the semiconductor memory device 2a of this embodiment, Figure 2 The characteristic register 41a shown stores a set value ta of the latency tS. The memory controller 1 can store the set value ta of the latency tS in the characteristic register 41a by inputting a signal DQ<7:0> including a set characteristic instruction to the semiconductor memory device 2a.

[0168] Specifically, the memory controller 1 performs a SetFeature action when storing the set value ta of the waiting time tS in the feature register 41a. Figure 13The signals DQ<7:0> shown as "CMD," "C_ADD," and "F_ADD" are input to the semiconductor memory device 2a. "CMD" is a command for instructing the semiconductor memory device 2a to perform a characteristic setting operation. The characteristic setting operation causes the characteristic register 41a to store the operation parameters indicated as characteristic data. "C_ADD" is an address (characteristic address) indicating the operation parameters to be set by the characteristic setting operation. In other words, "C_ADD" is an address (characteristic address) indicating the location in the characteristic register 41a where the operation parameters indicated as characteristic data should be stored. "F_ADD" is the address of the characteristic register 41a where the characteristic data D0 to D3 should be stored. The characteristic data D0 to D3 are set values ​​ta for the waiting time tS. For example, data input by a user operating the host 4 is used as the characteristic data D0 to D3. That is, in the memory system 3 of this embodiment, the waiting time tS can be set to an arbitrary value by the user operating the host 4.

[0169] The memory controller 1 inputs the signal DQ<7:0> including "CMD", "C_ADD" and "F_ADD" to the semiconductor memory device 2a, and then respectively turns on the write enable signal / WE, the command latch enable signal CLE and the address latch enable signal ALE. Figure 13 As shown, the switching between the “H” level and the “L” level is performed, and “CMD” is taken into the semiconductor memory device 2 a as a command, and “C_ADD” and “F_ADD” are taken into the semiconductor memory device 2 a as addresses.

[0170] Figure 13 In the figure, t30 represents the time when "F_ADD" is taken into the semiconductor memory device 2a. After time t31, which is a specified time after time t30, the characteristic data D0 to D3 are transmitted from the memory controller 1 to the semiconductor memory device 2a using the data strobe signals DQS and / DQS. That is, after time t31, the memory controller 1 inputs the signal DQ<7:0> containing the characteristic data D0 to D3 to the semiconductor memory device 2a and switches the data strobe signal DQS between the "H" level and the "L" level. As a result, the characteristic data D0 to D3 are sequentially taken into the semiconductor memory device 2a in synchronization with the rising edge of the data strobe signals DQS and / DQS and stored in the characteristic register 41a. As a result, the set value ta of the wait time tS is stored in the characteristic register 41a.

[0171] The set value ta can be any time such as a time longer than the specified time tR, a time longer than the data output period of one page, or a minimum time that can input a command to another semiconductor memory device. Figure 12The case where the initial value tb is long, that is, the case where the relationship of "ta>tb" is established between the initial value tb and the set value ta will be described as an example.

[0172] When the memory controller 1 instructs the semiconductor storage device 2 a to perform a read operation, the memory controller 1 can change the waiting time tS from the initial value tb to the set value ta by inputting a signal DQ<7:0> including a prefix command.

[0173] For example, the memory controller 1 is Figure 14 When the instruction set CSr for inputting the read operation is used as the signal DQ<7:0>, "xxh" is added before "00h". "xxh" is a prefix instruction for indicating that the set value ta stored in the characteristic register 41a is used as the waiting time tS. Figure 14 As shown in FIG. 1 , when the signal DQ<7:0> including "xxh" is input to the semiconductor memory device 2a, the sequencer 41 of the semiconductor memory device 2a uses the setting value ta stored in the characteristic register 41a as the waiting time tS according to the prefix instruction xxh. Figure 14 As shown in FIG. 1 , the waiting time tS is changed from the initial value tb to the set value ta. Therefore, the sequencer 41 of the semiconductor memory device 2a does not change the waiting time tS from the initial value tb to the set value ta until the set value ta is exceeded from the time t13. Figure 10 The transistors 65a and 65b shown in FIG. 1 are switched to an OFF state so that the first storage unit 510 and the input / output circuit 21 continue to operate. Figure 14 As shown, at time t40, which is before time t13 by a set value ta, when memory controller 1 switches chip enable signal / CE0 from an "H" level to an "L" level in order to output data from semiconductor memory device 2a, memory controller 1 can immediately read data as signals DQ<7:0> from semiconductor memory device 2a after time t40. Specifically, memory controller 1 can output data as signals DQ<7:0> by switching read enable signal / RE and data strobe signal DQS between an "H" level and an "L" level, respectively, after time t41, which is a predetermined time period after time t40. Figure 14 The operation of the semiconductor memory device 2a shown is similar to that of Figure 12 As is clear from the comparison of the operations shown, it is not necessary to input the instruction set CSd for the data output operation to the semiconductor memory device 2a, thereby improving the bus usage efficiency of the semiconductor memory device 2a.

[0174] In addition, the memory controller 1 does not use the set value ta stored in the characteristic register 41a as the waiting time tS. Figure 12As shown in FIG. 1 , when the instruction set CSr for the read operation is input to the semiconductor memory device 2a as the signal DQ<7:0>, the prefix instruction xxh is not input. Therefore, when the instruction set CSr for the read operation does not include the prefix instruction xxh, the sequencer 41 of the semiconductor memory device 2a sets the waiting time tS to the initial value tb. In this case, Figure 12 As shown, at time t21 after the initial value tb has passed from time t13, when the chip enable signal / CE0 maintains the "H" level, the sequencer 41 Figure 10 The transistors 65a and 65b shown are switched to an OFF state by the control signal FSW_enable, stopping the current supply to the first storage unit 510 and the input / output circuit 21. Therefore, after time t21, the standby current of the first storage unit 510 and the input / output circuit 21 is reduced.

[0175] Furthermore, the set value ta of the waiting time tS can be set individually for each of the semiconductor storage devices 2a to 2d. This allows setting the optimal set value ta of the waiting time tS corresponding to the process variations of each of the semiconductor storage devices 2a to 2d.

[0176] 1.11 Operation Example of Semiconductor Memory Device

[0177] Next, an operation example of the semiconductor memory device 2a of this embodiment will be described. Note that the operations of the other semiconductor memory devices 2b to 2d are basically the same.

[0178] like Figure 15 As shown, in the semiconductor memory device 2a of this embodiment, when the memory controller 1 is Figure 13 As shown, when a characteristic setting operation is requested of semiconductor memory device 2a (step S10), semiconductor memory device 2a sets a set value ta of waiting time tS by characteristic setting (step S20).

[0179] Afterwards, if Figure 15 As shown, when the memory controller 1 sends a command for executing a data read operation to the semiconductor memory device 2a (step S11), and the semiconductor memory device 2a receives the read command (step S21), the semiconductor memory device 2a determines whether the read command is accompanied by a prefix command xxh (step S22). If the read command is accompanied by a prefix command xxh (step S22: Yes), the semiconductor memory device 2a turns off the transistors 65a and 65b at a point in time when the set value ta has passed after the internal operation for reading data from the memory cell array 110 is completed (step S23).

[0180] On the other hand, in the semiconductor memory device 2a, when the prefix instruction xxh is not attached to the read instruction (step S22: No), the transistors 65a and 65b are turned off at a point in time after the initial value tb has passed after the internal operation for reading data from the memory cell array 110 is completed (step S24).

[0181] 1.12 Functions and Effects of the Semiconductor Memory Device of This Embodiment

[0182] As described above, the semiconductor memory device 2a includes a memory cell array 110, a latch circuit XDL (data storage unit), an input / output pad group 31 (pad unit), a first storage unit 510 (data transmission circuit), an input / output circuit 21 (data transmission circuit), and a sequencer 41 (control unit). The latch circuit XDL temporarily stores data read from the memory cell array 110. The input / output pad group 31 transmits and receives signals to and from the memory controller 1. The first storage unit 510 and the input / output circuit 21 are provided between the latch circuit XDL and the input / output pad group 31, and transfer the data stored in the latch circuit XDL to the input / output pad group 31. The sequencer 41 controls the first storage unit 510 and the input / output circuit 21. Transistors 65a and 65b (blocking unit) capable of blocking current supply to the first storage unit 510 and the input / output circuit 21 are provided. When the sequencer 41 does not start transmitting data to the memory controller 1 at the time when data is transmitted from the memory cell array 110 via the latch circuit XDL to the first storage unit 510 and the input / output circuit 21, and a waiting time tS (specified time) has elapsed, the current supply to the first storage unit 510 and the input / output circuit 21 is blocked via transistors 65a and 65b. The waiting time tS can be changed.

[0183] According to this configuration, the waiting time tS can be changed according to the operating state of the semiconductor memory device 2a. Therefore, for example, if it takes a certain period of time for the memory controller 1 to instruct the semiconductor memory device 2a to perform a read operation and to instruct the output of the read data, a longer waiting time tS can be set. In this case, even in the case of Figure 14 As shown, after the read operation of the semiconductor memory device 2a is started at time t10, the read operation is temporarily suspended at time t20, and then at time t40 the semiconductor memory device 2a is caused to output data to the memory controller 1. Instead of inputting the data output operation instruction set CSd to the semiconductor memory device 2a, the read enable signal / RE can be switched (a read control signal is input to the semiconductor memory device 2a). This improves the bus usage efficiency of the semiconductor memory device 2a.

[0184] The transistors 65 a and 65 b are provided on the wirings 63 a and 63 b for applying a ground voltage to the first storage unit 510 and the input / output circuit 21 .

[0185] According to this configuration, by turning off the transistors 65 a and 65 b , it is possible to easily block the current supply to the first storage unit 510 and the input / output circuit 21 .

[0186] The semiconductor memory device 2a further includes a characteristic register 41a that stores a set value ta of the latency tS. The sequencer 41 reads the set value ta of the latency tS from the characteristic register 41a.

[0187] According to this configuration, the waiting time tS can be easily changed from the initial value tb to the set value ta.

[0188] In the semiconductor memory device 2 a , the set value ta of the latency tS stored in the characteristics register 41 a can be updated based on a signal transmitted from the memory controller 1 .

[0189] According to this configuration, the set value ta of the waiting time tS can be set to an arbitrary value, thereby improving convenience.

[0190] Furthermore, the sequencer 41 changes the waiting time tS from the initial value tb to the set value ta in accordance with the prefix command xxh sent from the memory controller 1 .

[0191] With this configuration, the memory controller 1 can easily instruct the semiconductor memory device 2a to switch the wait time tS between the initial value tb and the set value ta. Therefore, for example, if the memory controller 1 instructs the semiconductor memory device 2a to immediately output data after instructing it to perform a read operation, the wait time tS can be maintained at the initial value tb. Consequently, if, for example, the semiconductor memory device 2a temporarily stores read data in the latch circuit XDL and then unexpectedly delays data output, this can prevent the transistor 65a, which functions as the foot switch of the input / output circuit 21, and the transistor 65b, which functions as the foot switch of the first storage unit 510, from being unexpectedly left on for an extended period, thereby increasing power consumption.

[0192] The setting value ta of the waiting time tS can be set by the user.

[0193] According to this configuration, the user can arbitrarily set the setting value ta of the waiting time tS, thereby improving convenience.

[0194] 1.13 Variations of the Memory System of the Embodiment

[0195] Next, a modification example of the memory system 3 according to the embodiment will be described.

[0196] like Figure 16 As shown, the semiconductor memory device 2a of this variation further includes a monitor circuit 23. The monitor circuit 23 monitors the operating state of the semiconductor memory device 2a and acquires monitor information thereof. The monitor information includes, for example, information on signals transmitted between the memory controller 1 and the semiconductor memory device 2a, information on the current consumption of the semiconductor memory device 2a, and information on the temperature of the semiconductor memory device 2a. The monitor circuit 23 outputs the acquired monitor information to the sequencer 41. In this variation, the monitor circuit 23 is an example of a monitoring unit.

[0197] The sequencer 41 calculates a set value ta for the wait time tS based on the monitor information output from the monitor circuit 23. For example, the sequencer 41 calculates, as a recommended value tc, the wait time tS at which the memory controller 1 can output data without issuing a data output command set CSd based on the monitor information. Furthermore, the sequencer 41 calculates, as a recommended value tc, the wait time tS that optimizes the current consumption and temperature of the semiconductor memory device 2a based on the monitor information.

[0198] Furthermore, the sequencer 41 outputs the recommended value tc of the waiting time tS to the memory controller 1 in response to a request from the memory controller 1. In this case, if the memory controller 1 transmits the recommended value tc of the waiting time tS to the host 4 in response to a request from the host 4, the host 4 can output the recommended value tc of the waiting time tS to the user.

[0199] According to this configuration, the user can set the set value ta with reference to the recommended value tc of the waiting time tS output from the host computer 4 , thereby improving convenience.

[0200] Alternatively, the sequencer 41 may store the calculated recommended value tc of the latency tS as a set value ta in the characteristics register 41a. This configuration allows the set value ta of the latency tS to be automatically set in the semiconductor memory device 2a, eliminating the need for the memory controller 1 to input the set value ta of the latency tS to the semiconductor memory device 2a.

[0201] 2 Another embodiment

[0202] The present invention is not limited to the specific examples described above.

[0203] For example, multiple set values ​​ta for the wait time tS may be stored in the characteristics register 41a of a single semiconductor memory device 2a. In this case, the memory controller 1 can use the prefix instruction xxh to indicate which of the multiple set values ​​ta to use as the wait time tS, thereby changing the wait time tS according to the operating status of the semiconductor memory device 2a. In this manner, the wait time tS can be selected from the multiple set values ​​ta.

[0204] The set value ta of the waiting time tS may be pre-stored in a designated register of the sequencer 41. In this case, the sequencer 41 may set the waiting time tS to either the set value ta or the initial value tb stored in the designated register, for example, according to the operating status of the semiconductor memory device 2a.

[0205] The waiting time tS can also be set to an infinite time. Thus, the semiconductor memory device 2a can realize the following operation: for example, after temporarily storing the data read from the memory cell array 110 in the latch circuit XDL, the current supply to the first storage unit 510 and the input / output circuit 21 is not blocked, regardless of whether the read enable signal / RE (the presence or absence of the read control signal) is switched by the memory controller 1. In other words, the data output waiting state is not terminated.

[0206] The sequencer 41 can also determine the Figure 14 After the time t42 of the waiting time tS shown, a predetermined time has elapsed. If the predetermined time has elapsed, for example, the current supply to the sense amplifier group SAU is blocked. This can further reduce the waiting current of the semiconductor memory device 2a.

[0207] In the semiconductor storage device 2a of the embodiment, it is possible to Figure 15 As shown in FIG. 1 , the prefix instruction xxh is given to switch the waiting time tS to either the initial value tb or the set value ta, but the switching method of the waiting time tS is not limited to this. For example, in the semiconductor memory device 2a, the waiting time tS can also be switched to either the initial value tb or the set value ta by setting characteristics. For example, when the waiting time tS is set to the initial value tb, as shown in FIG. Figure 17 As shown in FIG. 1 , when the memory controller 1 sends a read command to the semiconductor memory device 2a (step S30), and the semiconductor memory device 2a receives the read command (step S40), the semiconductor memory device 2a turns off the transistors 65a and 65b at a time when the initial value tb has passed after the internal operation for reading data from the memory cell array 110 is completed (step S41). Figure 13As shown, when a characteristic setting operation is requested for semiconductor memory device 2a (step S31), semiconductor memory device 2a switches the waiting time tS to a set value ta by performing the characteristic setting operation (step S42). Thereafter, when memory controller 1 sends a read command to semiconductor memory device 2a (step S32), and semiconductor memory device 2a receives the read command (step S43), semiconductor memory device 2a turns off transistors 65a and 65b at a point in time after the set value ta has elapsed after the internal operation for reading data from memory cell array 110 is completed (step S44). Furthermore, if waiting time tS is subsequently restored to its initial value tb, memory controller 1 can switch the waiting time from the set value ta to the initial value tb by performing the characteristic setting operation. The operation of the other semiconductor memory devices 2b to 2d is basically similar.

[0208] In the semiconductor device 2a of the embodiment, the timing for turning off transistors 65a and 65b can be appropriately changed. For example, in the semiconductor device 2a of the embodiment, after receiving a read instruction set CSr from the memory controller 1, an internal operation for reading data is performed. Subsequently, data is output to the memory controller 1 based on a data output instruction set CSd received from the memory controller 1. In this case, the semiconductor device 2a can also turn off transistors 65a and 65b when a wait time tS has elapsed since the input of the data output instruction set CSd, i.e., the input of a signal including "05h," multiple "ADD," and "E0h," without starting data transfer to the memory controller 1. By applying the configuration of the embodiment to this type of semiconductor memory device 2a, the wait time tS can be changed based on instructions from the memory controller 1. In other words, the semiconductor device 2a of the embodiment is configured to, after a read action or a data output action as a first action is instructed by the memory controller 1 (after an instruction set CSr for the read action or an instruction set CSd for the data output action is input), be able to change the waiting time tS for maintaining the data output waiting state of the read data temporarily stored by the latch circuit XDL to be transferred to the first storage unit 510 and the input-output circuit 21 according to the instruction of the memory controller 1.

[0209] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0210]

Explanation of symbols

[0211] XDL: Latch circuit (data storage unit)

[0212] 1: Memory controller

[0213] 2a-2d: Semiconductor memory devices

[0214] 3: Memory system

[0215] 4: Host

[0216] 21: Input and output circuit (data transmission circuit)

[0217] 23: Monitor circuit (monitoring unit)

[0218] 31: Input and output pad group (pad part)

[0219] 41: Sequencer (control unit)

[0220] 41a: Feature register

[0221] 65a, 65b: transistors (blocking portion, switching element)

[0222] 110: Memory cell array

[0223] 510: First storage unit (data transmission circuit, storage device).

Claims

1. A semiconductor memory device comprising: a memory cell array capable of storing data; a data storage unit that temporarily stores the data read from the memory cell array; The first terminal is provided for transmitting the data to an external memory controller; The second terminal is configured to receive a read control signal sent by the memory controller; A first power supply voltage input terminal is provided for receiving a first voltage; a second power supply voltage input terminal configured to receive a second voltage lower than the first voltage; a data transmission circuit, provided between the data storage unit and the first terminal, for transmitting the data stored in the data storage unit to the first terminal; a switch element capable of controlling connection or disconnection between the data transmission circuit and the first power supply voltage input terminal or the second power supply voltage input terminal; as well as a control unit, controlling the data transmission circuit and the switching element; and The control unit, When a first operation is instructed from the memory controller, the data transfer circuit is caused to transfer the data stored in the data storage unit. When a predetermined time has passed since the data was transferred from the data transfer circuit without receiving the read control signal from the memory controller, the data transfer circuit is disconnected from the first power supply voltage input terminal or the second power supply voltage input terminal by the switching element. The designated time can be changed according to an instruction from the memory controller. 2 . The semiconductor memory device according to claim 1 , wherein the switching element is provided between the data transmission circuit and the second power supply voltage input terminal.

3. The semiconductor memory device according to claim 1, further comprising a register storing a setting value of the specified time. The control unit reads the set value of the designated time from the register. 4 . The semiconductor memory device according to claim 3 , wherein the set value of the designated time stored in the register is updated according to the instruction from the memory controller. 5 . The semiconductor memory device according to claim 1 , wherein the designated time is changeable between an initial value and a set value settable by a user.

6. The semiconductor memory device according to claim 1, further comprising a register for storing a plurality of setting values ​​for the specified time. The designated time can be selected from the plurality of set values. 7 . The semiconductor memory device according to claim 1 , wherein the control unit changes the designated time in accordance with a designated command sent from the memory controller.

8. The semiconductor memory device according to claim 1, wherein the data transmission circuit includes an input-output circuit. The input / output circuit can transmit the data to the memory controller via the first terminal.

9. The semiconductor memory device according to claim 1, wherein the data transmission circuit comprises a FIFO circuit, The FIFO circuit performs a first-in-first-out operation based on the data transferred from the data storage unit.

10. The semiconductor memory device according to claim 1, further comprising a monitoring unit for monitoring an operating state of the data transmission circuit. The control unit calculates a recommended value of the designated time according to an operating state of the data transmission circuit. 11 . The semiconductor memory device according to claim 10 , wherein the control section outputs the recommended value to the memory controller.

12. The semiconductor memory device according to claim 1, wherein the first operation is a read operation. The control unit, When the read operation is instructed by the memory controller, the data is read from the memory cell array and stored in the data storage unit, and the data transmission circuit is caused to transmit the data stored in the data storage unit. When the data transmission circuit does not receive the read control signal from the memory controller and the specified time elapses after transmitting the data, the switching element disconnects the data transmission circuit from the first power supply voltage input terminal or the second power supply voltage input terminal.

13. The semiconductor memory device according to claim 1, wherein the first operation is a data output operation. The control unit, When the data output operation is instructed by the memory controller, the data transmission circuit is caused to transmit the data stored in the data storage unit. When the data transmission circuit does not receive the read control signal from the memory controller and the specified time elapses after transmitting the data, the switching element disconnects the data transmission circuit from the first power supply voltage input terminal or the second power supply voltage input terminal.

14. A memory system comprising: The semiconductor memory device according to claim 11; and a memory controller for controlling the semiconductor memory device according to a request from a host; The memory controller outputs the recommended value to the host.

15. A semiconductor memory device comprising: a memory cell array capable of storing data; The first terminal is provided for transmitting the data to an external memory controller; A first power supply voltage input terminal is provided for receiving a first voltage; a second power supply voltage input terminal configured to receive a second voltage lower than the first voltage; a data transmission circuit, provided between the memory cell array and the first terminal, for transmitting the data to the first terminal; a switch element capable of controlling connection or disconnection between the data transmission circuit and the first power supply voltage input terminal or the second power supply voltage input terminal; as well as a control unit, configured to control the data transmission circuit and the switch element; The control unit, After the data is transferred to the data transmission circuit, if the data is not output from the data transmission circuit to the memory controller within a predetermined time, the data transmission circuit is disconnected from the first power supply voltage input terminal or the second power supply voltage input terminal by the switching element. The designated time can be changed according to an instruction of the memory controller.

16. The semiconductor memory device according to claim 15, further comprising a register storing a setting value of the specified time. The control unit reads the set value of the designated time from the register, The set value of the designated time stored in the register is updated according to the instruction from the memory controller.

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