Semiconductor memory device

Abstract

The semiconductor storage device of the embodiment includes a substrate, a plurality of conductor layers, and a plurality of pillars MP. The substrate includes a first region MA1 and a second region HA, and a plurality of block regions BLK. The plurality of conductor layers have a plurality of step portions that do not overlap with the conductor layer of the upper layer in each region in which the second region overlaps with the plurality of block regions. The plurality of pillars MP is provided in each of the plurality of block regions, penetrating the plurality of conductor layers. The second region HA includes a first sub-region US and a second sub-region LS arranged in a first direction. The first sub-region US includes a first ladder structure in which a plurality of first step portions are stepped up or down in a direction toward the first region. The second sub-region LS includes a second ladder structure in which a plurality of second step portions are stepped up or down in a direction away from the first region, and a first pattern RPL provided continuously with any one of the plurality of conductor layers.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2020-156710 (Filing Date: September 17, 2020). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments relate to a semiconductor memory device. BACKGROUND

[0004] A NAND (Not-And) type flash memory capable of nonvolatile storage of data is known. SUMMARY

[0005] Embodiments provide a semiconductor memory device capable of improving yield and reducing chip area.

[0006] A semiconductor memory device of an embodiment includes a substrate, a plurality of conductor layers, a plurality of pillars, and a plurality of contacts. The substrate includes a first region, a second region, and a plurality of block regions. The first region and the second region are arranged in a first direction. The plurality of block regions are each provided extending in the first direction. The plurality of block regions are arranged in a second direction intersecting the first direction. The plurality of conductor layers are each divided in each of the plurality of block regions. The plurality of conductor layers are arranged and separated from each other in a third direction intersecting the first direction and the second direction, respectively. The plurality of conductor layers have a plurality of step portions. The plurality of step portions are each provided not to overlap with a conductor layer of an upper layer in each region in which the second region overlaps with the plurality of block regions. The plurality of pillars are provided in each of the plurality of block regions. The plurality of pillars each penetrate the plurality of conductor layers. A portion in which the pillar and the conductor layer intersect functions as a memory cell. In each of the plurality of block regions, the plurality of contacts are each provided on the plurality of step portions. The second region includes a first sub-region and a second sub-region arranged in the first direction. The first sub-region includes a first ladder structure including a configuration in which a plurality of first step portions included in the plurality of step portions are escalated or descended in a direction along the first direction and toward the first region. The second sub-region includes a second ladder structure and a first pattern. The second ladder structure includes a configuration in which a plurality of second step portions included in the plurality of step portions are escalated or descended in a direction along the first direction and away from the first region. The first pattern is provided continuously with any one of the plurality of conductor layers. The first pattern is arranged between the first ladder structure and the second ladder structure. At least one contact is arranged between a step portion of the conductor layer provided continuously with the first pattern and the first pattern. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1is a block diagram showing an example of the overall configuration of a semiconductor storage device according to the embodiment.

[0008] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in the semiconductor storage device according to the embodiment.

[0009] Figure 3 is a plan view showing an example of the planar layout of a memory cell array provided in the semiconductor storage device according to the embodiment.

[0010] Figure 4 is a plan view showing an example of the detailed planar layout in a memory region of a memory cell array provided in the semiconductor storage device according to the embodiment.

[0011] Figure 5 is an example of the cross-sectional configuration in a memory region of a memory cell array provided in the semiconductor storage device according to the embodiment, and is a cross-sectional view along the V-V line of FIG. 8. Figure 4

[0012] Figure 6 is an example of the cross-sectional configuration of a memory pillar in the semiconductor storage device according to the embodiment, and is a cross-sectional view along the VI- VI line of FIG. 10. Figure 5

[0013] Figure 7 is a plan view showing an example of the detailed planar layout in a lead-out region of a memory cell array provided in the semiconductor storage device according to the embodiment.

[0014] Figure 8 is an example of the cross-sectional configuration in a lead-out region of a memory cell array in the semiconductor storage device according to the embodiment, and is a cross-sectional view along the VIII-VIII line of FIG. 14. Figure 7

[0015] Figure 9 is an example of the cross-sectional configuration in a lead-out region of a memory cell array in the semiconductor storage device according to the embodiment, and is a cross-sectional view along the IX-IX line of FIG. 15. Figure 7

[0016] Figure 10 is a flowchart showing an example of the manufacturing method of the semiconductor storage device according to the embodiment.

[0017] Figure 11 is a cross-sectional view showing an example of the cross-sectional configuration at the manufacturing intermediate stage of the semiconductor storage device according to the embodiment.

[0018] Figure 12 is a plan view showing an example of the planar layout at the manufacturing intermediate stage of the semiconductor storage device according to the embodiment.

[0019] ​​​​Figure 13 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment, and is along the XIII-XIII line of Figure 12

[0020] Figure 14 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0021] Figure 15 is a plan view of an example of a plan layout at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0022] Figure 16 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0023] Figure 17 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0024] Figure 18 is a plan view of an example of a plan layout at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0025] Figure 19 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0026] Figure 20 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0027] Figure 21 is a plan view of an example of a plan layout at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0028] Figure 22 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment, and is along the XXII-XXII line of Figure 21

[0029] Figure 23 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0030] Figure 24 is a cross-sectional view of an example of a cross-sectional structure at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0031] Figure 25 is a plan view of an example of a plan layout at a manufacturing intermediate of the semiconductor storage device of the embodiment.

[0032] Figure 26 ​​This is an example of a cross-sectional structure of a semiconductor memory device in the middle of manufacturing a comparative example of the embodiment, and Figure 25 A cross-sectional view taken along line XXVI-XXVI.

[0033] Figure 27 It is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to a first modification of the embodiment.

[0034] Figure 28 This is an example of a cross-sectional structure in a lead-out region of a memory cell array included in a semiconductor memory device according to a first variation of the embodiment, and is shown along Figure 27 A cross-sectional view taken along line XXVIII-XXVIII.

[0035] Figure 29 It is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to a second modification of the embodiment.

[0036] Figure 30 It is a plan view showing an example of a planar layout in a lead-out region of a memory cell array included in a semiconductor memory device according to a third modification of the embodiment.

[0037] Figure 31 This is an example of a cross-sectional structure in a lead-out region of a memory cell array included in a semiconductor memory device according to a third variation of the embodiment, and is shown along Figure 30 Cross-sectional view of line XXXI-XXXI.

[0038] Figure 32 It is a plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to a fourth variation of the embodiment. DETAILED DESCRIPTION

[0039] The following describes the embodiments with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for realizing the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of the drawings may not necessarily be the same as those of the actual objects. The technical concept of the present invention is not determined by the shape, structure, or arrangement of the components.

[0040] In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The numerals following the characters constituting the reference numerals are used to distinguish components having the same configuration from each other, identified by reference numerals containing the same characters. Where it is not necessary to distinguish components denoted by reference numerals containing the same characters, these components are identified by reference numerals consisting solely of the characters.

[0041] [Implementation Method]

[0042] The following describes the semiconductor storage device 1 of the embodiment.

[0043] [1] Configuration of semiconductor storage device 1

[0044] [1-1] Overall configuration of semiconductor storage device 1

[0045] Figure 1 A configuration example of the semiconductor storage device 1 of the embodiment is shown. The semiconductor storage device 1 is a NAND-type flash memory capable of nonvolatile storage of data, and is capable of being controlled by an external memory controller 2. As shown in FIG. 1, the semiconductor storage device 1 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16. Figure 1

[0046] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of one or more). The block BLK is a collection of a plurality of memory cells capable of nonvolatile storage of data, and is used as a unit of erasure of data, for example. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with one bit line and one word line, for example. The detailed configuration of the memory cell array 10 will be described later.

[0047] The instruction register 11 holds an instruction CMD received by the semiconductor storage device 1 from the memory controller 2. The instruction CMD includes, for example, a command for causing the sequencer 13 to perform a readout operation, a write operation, an erasure operation, and the like.

[0048] The address register 12 holds address information ADD received by the semiconductor storage device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. The block address BAd, the page address PAd, and the column address CAd are used for selection of the block BLK, the word line, and the bit line, respectively, for example.

[0049] The sequencer 13 controls the operation of the entire semiconductor storage device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, and the like, based on the instruction CMD held in the instruction register 11, to perform a readout operation, a write operation, an erasure operation, and the like.

[0050] The driver module 14 generates voltages used for a readout operation, a write operation, an erasure operation, and the like. Furthermore, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line, based on the page address PAd held in the address register 12, for example.

[0051] ​The row decoder module 15 selects a corresponding block BLK in the memory cell array 10 based on the block address BAd held in the address register 12. Also, the row decoder module 15, for example, transmits a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0052] The sense amplifier module 16 applies a required voltage to each bit line in accordance with the write data DAT received from the memory controller 2 in a write operation. In addition, the sense amplifier module 16 determines data stored in the memory cell based on the voltage of the bit line in a read operation, and transmits the determination result as read data DAT to the memory controller 2.

[0053] The semiconductor storage device 1 and the memory controller 2 described above can be combined to constitute one semiconductor device. As such a semiconductor device, for example, a memory card such as an SD card or an SSD (solid state drive) can be cited. TM

[0054] [1-2] Circuit configuration of memory cell array 10

[0055] Figure 2 An example of the circuit configuration of the memory cell array 10 included in the semiconductor storage device 1 according to the embodiment is shown, which shows one of the plurality of blocks BLK included in the memory cell array 10. As shown in the drawing, the block BLK includes, for example, five string units SU0 to SU4. Figure 2

[0056] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer of one or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge accumulation layer, and nonvolatilely holds data. The selection transistors ST1 and ST2 are each used for selection of the string unit SU at the time of various operations.

[0057] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of the selection transistor ST2 is connected to the source line SL.

[0058] ​​In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. The gates of the plurality of selection transistors ST1 in the string unit SU0 are connected to the selection gate line SGD0. The gates of the plurality of selection transistors ST1 in the string unit SU1 are connected to the selection gate line SGD1. The gates of the plurality of selection transistors ST1 in the string unit SU2 are connected to the selection gate line SGD2. The gates of the plurality of selection transistors ST1 in the string unit SU3 are connected to the selection gate line SGD3. The gates of the plurality of selection transistors ST1 in the string unit SU4 are connected to the selection gate line SGD4. The gates of the plurality of selection transistors ST2 are connected to the selection gate line SGS.

[0059] Different column addresses are assigned to the bit lines BL0 to BLm, respectively. The NAND strings NS assigned with the same column address among the plurality of blocks BLK share each bit line BL. Each block BLK is provided with the word lines WL0 to WL7. The source lines SL are shared among the plurality of blocks BLK, for example.

[0060] A set of the plurality of memory cell transistors MT connected to the common word line WL in 1 string unit SU is referred to as a cell unit CU, for example. The storage capacity of the cell unit CU including the memory cell transistors MT storing 1 bit of data, respectively, is defined as "1 page of data", for example. The cell unit CU can have a storage capacity of 2 pages of data or more depending on the number of bits of data stored by the memory cell transistors MT.

[0061] Furthermore, the circuit configuration of the memory cell array 10 provided in the semiconductor storage device 1 of the embodiment is not limited to the configuration described above. The number of string units SU included in each block BLK, or the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be any number, for example.

[0062] [1-3] Configuration of Memory Cell Array 10

[0063] Hereinafter, an example of the configuration of the memory cell array 10 provided in the semiconductor storage device 1 of the embodiment will be described. Furthermore, in the drawings referred to below, the X direction corresponds to the direction of extension of the word lines WL, the Y direction corresponds to the direction of extension of the bit lines BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate 20 used for formation of the semiconductor storage device 1. Hatching is appropriately added in plan view for reference. The hatching added in plan view is not necessarily associated with the material or characteristics of the constituent elements to which the hatching is added. The illustration of the configuration is appropriately omitted in sectional view for reference. The configuration shown in each drawing is appropriately simplified for representation.

[0064] [1-3-1] Planar Layout of Memory Cell Array 10

[0065] Figure 3 FIG. 1 shows a planar layout of the memory cell array 10 included in the semiconductor storage device 1 according to the embodiment. The planar layout of the memory cell array 10 is shown in correspondence with eight blocks BLK0 to BLK7. As shown in FIG. 1, the memory cell array 10 includes a plurality of slits SLT and a plurality of slits SHE. In addition, the planar layout of the memory cell array 10 is divided into a memory area MA1 and a memory area MA2 and a lead-out area HA, for example, in the X direction. The memory areas MA1 and MA2 each include a plurality of NAND strings NS for storing data. The lead-out area HA is disposed between the memory areas MA1 and MA2, and is used for disposing contacts and the like that are paired with the laminated wiring of the memory cell array 10. Figure 3

[0066] The plurality of slits SLT each has a portion extending in the X direction, and is arranged in the Y direction. Each of the plurality of slits SLT crosses the memory areas MA1 and MA2 and the lead-out area HA in the X direction. In addition, the slit SLT has a configuration in which an insulator or a plate-shaped contact is embedded inside, for example, and separates the adjacent wiring (e.g., the word lines WL0 to WL7 and the select gate lines SGD and SGS) across the slit SLT. In this example, the regions separated by the plurality of slits SLT each correspond to one block BLK. In this specification, the slits SLT arranged in the odd-numbered positions in the Y direction are referred to as "SLTo", and the slits SLT arranged in the even-numbered positions are referred to as "SLTe".

[0067] The plurality of slits SHE is disposed in both of the memory areas MA1 and MA2. The plurality of slits SHE corresponding to the memory area MA1 is each disposed so as to cross the memory area MA1, and is arranged in the Y direction. The plurality of slits SHE corresponding to the memory area MA2 is each disposed so as to cross the memory area MA2, and is arranged in the Y direction. In this example, four slits SHE are each disposed between adjacent slits SLT. The slit SHE has a configuration in which an insulator is embedded inside. The slit SHE separates the adjacent wiring across the slit SHE, and separates at least the select gate line SGD. In this example, the regions separated by the slits SLT and SHE each correspond to one string unit SU.

[0068] The lead-out area HA includes a plurality of lead-out portions HP arranged in the Y direction. One lead-out portion HP is disposed every two blocks BLK. In other words, each lead-out portion HP is disposed in the lead-out area HA in a region between two slits SLTo adjacent in the Y direction, and is separated by one slit SLTe. Each lead-out portion HP includes a contact region US and a contact region LS arranged in the X direction. The contact region US includes a stepped configuration corresponding to the wiring disposed on the upper side among the laminated wiring. The contact region LS includes a stepped configuration corresponding to the wiring disposed on the lower side among the laminated wiring.

[0069] ​For example, the plurality of contact regions US included in the lead-out region HA are arranged in the Y direction. Similarly, the plurality of contact regions LS included in the lead-out region HA are arranged in the Y direction. Not limited thereto, the contact regions US of one lead-out portion HP and the contact regions LS of the other lead-out portion HP can be adjacent to each other in the Y direction. In other words, in the lead-out region HA, the contact regions US and LS can be alternately arranged in the Y direction.

[0070] The laminated wiring is electrically connected in a region on the side opposite to the Y direction at which the two block regions constituting one group meet, between the storage regions MA1 and MA2, bypassing the lead-out portion HP. Specifically, in the block BLK0, the lead-out portion HP is arranged on the side of the block BLK1, and the laminated wiring in the storage region MA1 and the laminated wiring in the storage region MA2 are continuously provided through the slit SLTo adjacent to the block BLK0 and the lead-out portion HP. On the other hand, in the block BLK1, the lead-out portion HP is arranged on the side of the block BLK0, and the laminated wiring in the storage region MA1 and the laminated wiring in the storage region MA2 are continuously provided through the slit SLTo adjacent to the block BLK1 and the lead-out portion HP.

[0071] The storage cell array 10 is arranged in the Y direction Figure 3 The layout of the storage cell array 10 included in the semiconductor storage device 1 of the embodiment is not limited to the above-described layout. For example, the number of slits SHE arranged between the adjacent slits SLT can be designed to be any number. The number of string units SU formed between the adjacent slits SLT can be changed based on the number of slits SHE arranged between the adjacent slits SLT. A region including a contact of a through laminated wiring can be provided in each of the storage region MA and the lead-out region HA.

[0072] [1-3-2] Configuration in the storage region MA of the storage cell array 10

[0073] (Planar layout in the storage region MA of the storage cell array 10)

[0074] Figure 4 An example of a detailed planar layout in the storage region MA of the storage cell array 10 included in the semiconductor storage device 1 of the embodiment is shown, which shows a region including one block BLK (i.e., string units SU0 to SU4). As Figure 4 In the storage region MA, the storage cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each slit SLT includes a contact LI and a spacer SP.

[0075] Each of the memory pillars MP functions as, for example, 1 NAND string NS. The plurality of memory pillars MP are arranged in a staggered manner of, for example, 24 columns in the region between the adjacent 2 slits SLT. Also, for example, the 5th column memory pillar MP, the 10th column memory pillar MP, the 15th column memory pillar MP, and the 20th column memory pillar MP, and the like each of which overlaps 1 slit SHE are counted from the paper surface side.

[0076] The plurality of bit lines BL each have a portion extending in the Y direction and are arranged in the X direction. Each of the bit lines BL is arranged to overlap at least 1 memory pillar MP in each string unit SU. In this example, 2 bit lines BL are arranged to overlap 1 memory pillar MP. One of the plurality of bit lines BL overlapping the memory pillar MP and the memory pillar MP are electrically connected via a contact CV.

[0077] For example, the contact CV between the memory pillar MP and the bit line BL in contact with the slit SHE is omitted. In other words, the contact CV between the memory pillar MP and the bit line BL in contact with the different 2 selection gate lines SGD is omitted. The number and arrangement of the memory pillars MP or the slits SHE between the adjacent slits SLT are not limited to those used in this example. Figure 4 The configuration described can be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0078] The contact LI is a conductor having a portion extending in the X direction. The spacer SP is an insulator provided on the side surface of the contact LI. The contacts LI are separated by the spacers SP. The contact LI and the conductors (for example, the word lines WL0 to WL7 and the selection gate lines SGD and SGS) adjacent to the contact LI in the Y direction are separated and insulated by the spacer SP.

[0079] (Cross-sectional configuration in the memory region MA of the memory cell array 10)

[0080] Figure 5 An example of a cross-sectional configuration in the memory region MA of the memory cell array 10 of the semiconductor storage device 1 according to the embodiment is shown, which shows a cross section along the V-V line of Figure 4 As shown in Figure 5 , the memory cell array 10 further includes a semiconductor substrate 20, conductor layers 21 to 25, and insulator layers 30 to 34.

[0081] Specifically, the semiconductor substrate 20 has the insulator layer 30 provided thereon. Although not shown, the insulator layer 30 includes, for example, a circuit corresponding to the row decoder module 15 or the sense amplifier module 16, or the like.

[0082] A conductive layer 21 is provided on the insulating layer 30. The conductive layer 21 is formed in a plate shape extending along the XY plane, for example, and serves as the source line SL. The conductive layer 21 includes, for example, silicon doped with phosphorus.

[0083] An insulating layer 31 is provided on the conductive layer 21. A conductive layer 22 is provided on the insulating layer 31. The conductive layer 22 is formed into a plate shape extending along the XY plane, for example, and serves as a select gate line SGS. The conductive layer 22 contains, for example, tungsten.

[0084] Insulator layers 32 and conductive layers 23 are alternately stacked on the conductive layer 22. The conductive layers 23 are formed, for example, in a plate shape extending along the XY plane. The stacked conductive layers 23 are used as word lines WL0 to WL7 in order from the semiconductor substrate 20 side. The conductive layers 23 are made of tungsten, for example.

[0085] An insulating layer 33 is provided on the uppermost conductive layer 23. A conductive layer 24 is provided on the insulating layer 33. The conductive layer 24 is formed into a plate shape extending along the XY plane, for example, and serves as a selection gate line SGD. The conductive layer 24 contains tungsten, for example.

[0086] An insulator layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulator layer 34. The conductive layer 25 is formed, for example, into a linear shape extending in the Y direction and serves as a bit line BL. Specifically, in a region (not shown), multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 comprises, for example, copper.

[0087] Each memory pillar MP extends along the Z direction, penetrating the insulating layers 31-33 and the conductive layers 22-24. The bottom of the memory pillar MP contacts the conductive layer 21. The portion where the memory pillar MP intersects the conductive layer 22 functions as the select transistor ST2. The portion where the memory pillar MP intersects one conductive layer 23 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects the conductive layer 24 functions as the select transistor ST1.

[0088] In addition, each memory column MP includes, for example, a core component 40, a semiconductor layer 41, and a laminated film 42. The core component 40 is extended along the Z direction. For example, the upper end of the core component 40 is included in a layer higher than the conductive layer 24, and the lower end of the core component 40 reaches the conductive layer 21. The semiconductor layer 41 covers the periphery of the core component 40. In the lower part of the memory column MP, a portion of the semiconductor layer 41 is in contact with the conductive layer 21. The laminated film 42 covers the side and bottom surfaces of the semiconductor layer 41, except for the portion where the semiconductor layer 41 is in contact with the conductive layer 21. The core component 40 includes, for example, an insulator such as silicon oxide. The semiconductor layer 41 includes, for example, silicon.

[0089] A contact CV is provided on the semiconductor layer 41 in the memory pillar MP. In the illustrated region, two contacts CV corresponding to two memory pillars MP among the six memory pillars MP are illustrated. In the memory region MA, the memory pillars MP not overlapping the slit SHE and not connected to the contact CV are connected to the contact CV in a region not illustrated.

[0090] The contact CV is contacted with one of the conductive layers 25, that is, one bit line BL. In each space of the one conductive layer 25 separated by the slits SLT and SHE, one contact CV is connected. That is, each conductive layer 25 is electrically connected to the memory pillar MP provided between the adjacent slits SLT and SHE and the memory pillar MP provided between the adjacent two slits SHE.

[0091] The slit SLT has, for example, a portion provided along the XZ plane, which separates the conductive layers 22 to 24. The contact LI in the slit SLT is provided along the slit SLT. A part of the upper end of the contact LI is in contact with the insulator layer 34. The lower end of the contact LI is in contact with the conductive layer 21. The contact LI is used, for example, as a part of the source line SL. The spacer SP is provided at least between the contact LI and the conductive layers 22 to 24. The contact LI and the conductive layers 22 to 24 are separated and insulated by the spacer SP.

[0092] The slit SHE has, for example, a portion provided along the XZ plane, which separates at least the conductive layer 24. The upper end of the slit SHE is in contact with the insulator layer 34. The lower end of the slit SHE is in contact with the insulator layer 33. The slit SHE contains, for example, an insulator such as silicon oxide. The upper end of the slit SHE can or can not be aligned with the upper end of the slit SLT. In addition, the upper end of the slit SHE can or can not be aligned with the upper end of the memory pillar MP.

[0093] Figure 6 An example of the cross-sectional configuration of the memory pillar MP in the semiconductor storage device 1 according to the embodiment is illustrated, which shows a cross-section along the VI-VI line of FIG. 1. More specifically, Figure 5 the cross-sectional configuration of the memory pillar MP in the layer parallel to the surface of the semiconductor substrate 20 and containing the conductive layer 23 is illustrated in FIG. 2. As Figure 6 illustrated in FIG. 2, the laminated film 42 contains, for example, a tunnel insulating film 43, an insulating film 44, and a barrier insulating film 45. Figure 6

[0094] ​In the cross section including the conductive layer 23, the core component 40 is provided at the center of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core component 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The barrier insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 23 surrounds the side surface of the barrier insulating film 45. The tunnel insulating film 43 and the barrier insulating film 45 each include, for example, silicon oxide. The insulating film 44 includes, for example, silicon nitride.

[0095] In each of the memory pillars MP described above, the semiconductor layer 41 is used as a channel (current path) of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 44 is used as a charge accumulation layer of the memory cell transistors MT. The semiconductor memory device 1 can cause the bit line BL and the contact LI to flow a current via the memory pillar MP by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0096] [1-3-3] Configuration of the Draw-out Area HA of the Memory Cell Array 10

[0097] Hereinafter, the configuration of the draw-out area HA of the memory cell array 10 included in the semiconductor memory device 1 according to the embodiment will be described. Hereinafter, the block BLK of the even number of bits is referred to as "BLKe", and the block BLK of the odd number of bits is referred to as "BLKo".

[0098] (Planar Layout of the Draw-out Area HA of the Memory Cell Array 10)

[0099] Figure 7 An example of a detailed planar layout of the draw-out area HA of the memory cell array 10 included in the semiconductor memory device 1 according to the embodiment is shown, which corresponds to the adjacent blocks BLK0 (BLKe) and BLK1 (BLKo). In addition, a part of the memory area MA1 and MA2 near the draw-out area HA is also shown. As shown in the drawing, in the draw-out area HA, the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD each have a portion (terrace portion) that does not overlap with the wiring layer (conductive layer) of the upper layer. Figure 7 Figure 7 As shown in the drawing, in the draw-out area HA, the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD each have a portion (terrace portion) that does not overlap with the wiring layer (conductive layer) of the upper layer.

[0100] The shape of the portion of the draw-out area HA that does not overlap with the wiring layer of the upper layer is similar to a step, a terrace, a rimstone, or the like. Specifically, a step difference is provided between the selection gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, between the word line WL6 and the word line WL7, and between the word line WL7 and the selection gate line SGD. Furthermore, the draw-out portion HP includes the terrace portion of the selection gate line SGS and the terrace portion of each of the word lines WL0 to WL7.​

[0101] Specifically, the contact area LS includes a plurality of stepped portions corresponding to the select gate line SGS and the word lines WL0 to WL2 arranged on the lower layer side in the multilayer wiring. The contact area US includes a plurality of stepped portions corresponding to the word lines WL3 to WL7 arranged on the upper layer side in the multilayer wiring. Further, these stepped portions are arranged in the order of the word line WL7, the word line WL6, the word line WL5, the word line WL4, the word line WL3, the select gate line SGS, the word line WL0, the word line WL1, and the word line WL2 along the X direction.

[0102] That is, in the contact area US, the stepped configuration formed by the stepped portions of the word lines WL7, WL6, WL5, WL4, and WL3 in the multilayer wiring has a configuration that is upgraded in the direction along the X direction and toward the memory area MA1. In other words, in the contact area US, the stepped configuration formed by the stepped portions of the word lines WL7, WL6, WL5, WL4, and WL3 in the multilayer wiring has a configuration that is downgraded in the direction along the X direction and toward the memory area MA2. On the other hand, in the contact area LS, the stepped configuration formed by the stepped portions of the select gate line SGS, the word lines WL0, WL1, and WL2 in the multilayer wiring has a configuration that is upgraded in the direction along the X direction and toward the memory area MA2. In other words, in the contact area LS, the stepped configuration formed by the stepped portions of the select gate line SGS, the word lines WL0, WL1, and WL2 in the multilayer wiring has a configuration that is downgraded in the direction along the X direction and toward the memory area MA1.

[0103] In addition, in the lead-out area HA, the memory cell array 10 includes a plurality of contacts CC. The plurality of contacts CC are respectively arranged on the stepped portions of the select gate line SGS, the word lines WL0 to WL7, and the select gate lines SGD0 to SGD4 in each block BLK. The plurality of contacts CC arranged in the lead-out portion HP and arranged in the area of one block BLK are arranged, for example, on one straight line. These contacts do not necessarily need to be arranged on one straight line, and can be arranged staggered up and down.

[0104] The multilayer wiring connected to the NAND string NS is electrically connected to the row decoder module 15 via the associated contact CC. The connection between the contact CC and the row decoder module 15 can be made via a contact that penetrates the multilayer wiring in the lead-out area HA, or can be made via a contact arranged in an area outside the memory cell array 10. The area in which the contact that penetrates the multilayer wiring is arranged can also be arranged in the memory area MA. The contact CC in the lead-out portion HP and the contact outside the lead-out portion HP can be connected to the row decoder module 15 via different paths.

[0105] In the present example, a portion of the step difference (step portion) of the stacked wiring arranged in the lead-out portion HP in the X direction is provided with the contact CC. Further, the stacked wiring arranged in the lead-out portion HP also has a step difference in the Y direction. This portion, for example, is not provided with the contact CC, and is also referred to as a "dummy step structure". The dummy step structure is a structure that is formed incidentally during the manufacturing process of the semiconductor storage device 1. For example, the portion of the lead-out portion HP corresponding to the block BLK0 (BLKe) and the portion corresponding to the block BLK1 (BLKo) have a structure that is symmetrical in the Y direction with the slit SLTe as a reference.

[0106] Further, in the semiconductor storage device 1 of the embodiment, the contact region US includes the reference pattern RPU, and the contact region LS includes the reference pattern RPL. The reference pattern RPU is adjacent to the reference pattern RPL in the X direction. The reference pattern RPU is used to manage the position of the step structure arranged in the contact region US during the manufacturing steps of the semiconductor storage device 1. The reference pattern RPL is used to manage the position of the step structure arranged in the contact region LS during the manufacturing steps of the semiconductor storage device 1. The reference patterns RPU and RPL are each divided by the slit SLTe that divides the lead-out portion HP in the vicinity of the center in the Y direction.

[0107] The reference pattern RPU is arranged in any of the wirings above the lowermost wiring (for example, the word line WL3) in the contact region US. In the present example, the word line WL4 has the reference pattern RPU. In this case, in each block BLK, the contact CC connected to the lowermost wiring in the contact region US is surrounded by the step portion of the word line WL4, the reference pattern RPU arranged continuously with the step portion of the word line WL4, and the slit SLTe that divides the lead-out portion HP. In other words, at least one contact CC is arranged between the step portion of the word line WL4 and the reference pattern RPU.

[0108] The reference pattern RPL is arranged in any of the wirings above the lowermost wiring (for example, the select gate line SGS) in the contact region LS. In the present example, the word line WL0 has the reference pattern RPL. In this case, in each block BLK, the contact CC connected to the lowermost wiring in the contact region LS is surrounded by the step portion of the word line WL0, the reference pattern RPL arranged continuously with the step portion of the word line WL0, and the slit SLTe that divides the lead-out portion HP. In other words, at least one contact CC is arranged between the step portion of the word line WL0 and the reference pattern RPL.

[0109] The portion of the contact region LS between the reference pattern RPL and the contact region US corresponds to a step portion of the lowermost wiring (e.g., the select gate line SGS) in the contact region LS. The interface portion of the contact regions US and LS and the reference patterns RPU and RPL are each separately arranged and cross the region between the reference patterns RPU and RPL.

[0110] (Cross-sectional configuration in the lead-out region HA of the memory cell array 10)

[0111] Figure 8 is a cross-sectional view along the VIII-VIII line of Figure 7 , showing an example of the cross-sectional configuration in the lead-out region HA of the memory cell array 10 included in the semiconductor storage device 1 of the embodiment. In addition, Figure 8 A portion of the memory regions MA1 and MA2 near the lead-out region HA is also shown in Figure 8 As shown in

[0112] Specifically, the contact region US includes a stepped configuration corresponding to the word lines WL3 to WL7. The contact region LS includes a stepped configuration corresponding to the select gate line SGS and the word lines WL0 to WL2. The stepped configuration provided in the contact region US and the stepped configuration provided in the contact region LS have, for example, a configuration symmetrical in the X direction, except for the difference in height. The height of the stepped configuration in the contact region US is higher than the height of the stepped configuration in the contact region LS. In this example, the stepped configuration in the contact region LS is lower than the stepped configuration in the contact region US, and the difference between the two is equivalent to the height of the four insulator layers 32 and the conductive layer 23.

[0113] In addition, in the lead-out region HA, the memory cell array 10 includes a plurality of conductive layers 26. A plurality of contacts CC are provided on the step portions of the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD, respectively. One conductive layer 26 is provided on each of the contacts CC. As a result, each of the conductive layers 22 to 24 and the associated conductive layer 26 are electrically connected via the contacts CC. The conductive layer 26 is included, for example, in a layer at the same height as the conductive layer 25.

[0114] The taper shape of the stacked structure including the word lines WL0 to WL3 arranged at the boundary portion of the contact regions US and LS is similar to the taper shape of the stacked structure including the word lines WL4 to WL7 arranged at the storage region MA2 side of the contact region LS. The reason is that, in the manufacturing steps of the semiconductor memory device 1, the etching process of every 4 sets of the conductor layers 23 and the insulator layers 32 is performed comprehensively with the contact region LS as the target. Details of this process will be described later. Hereinafter, the stepped structure arranged in the contact region US is also referred to as "upper stepped portion", and the stepped structure arranged in the contact region LS is also referred to as "lower stepped portion".

[0115] Figure 9 is a cross-sectional view along the IX-IX line of Figure 7 , showing an example of the cross-sectional structure in the lead-out region HA of the memory cell array 10 provided in the semiconductor memory device 1 of the embodiment. In addition, Figure 9 the reference pattern RPU including the contact region US. As Figure 9 indicated, the memory cell array 10 has a stepped structure ascending to both sides in the Y direction in the lead-out portion HP.

[0116] Specifically, in the region corresponding to the block BLK0 (BLKe), the plurality of conductor layers 23 of the stacked structure has a stepped structure ascending toward the slit SLTo adjoining the block BLK0. Similarly, in the region corresponding to the block BLK1 (BLKo), the plurality of conductor layers 23 of the stacked structure has a stepped structure ascending toward the slit SLTo adjoining the block BLK1. Further, the stepped structure in the Y direction in the region corresponding to the block BLK0 and the stepped structure in the Y direction in the region corresponding to the block BLK1 have a symmetrical configuration in the Y direction.

[0117] The slit SLTe between the blocks BLK0 and BLK1 divides the conductor layers 22 and 23 in the lead-out portion HP. In addition, this slit SLTe also divides the reference pattern RPU. That is, the reference pattern RPU has a portion continuously arranged with the conductor layer 23 corresponding to the word line WL4 within the block BLK0, and a portion continuously arranged with the conductor layer 23 corresponding to the word line WL4 within the block BLK1. Similarly, although not shown, the reference pattern RPL has a portion continuously arranged with the conductor layer 23 corresponding to the word line WL0 within the block BLK0, and a portion continuously arranged with the conductor layer 23 corresponding to the word line WL0 within the block BLK1.

[0118] Further, in this example, the width in the Y direction of the landing portion in the stepped structure in the Y direction is substantially equal to the width in the X direction of the landing portion in the stepped structure in the X direction. For example, the width in the Y direction of the landing portion in the Y direction in the word line WL5 is substantially equal to the width in the X direction of the landing portion in the X direction in the word line WL5. Further, in the semiconductor storage device 1 of the embodiment, the stepped structure formed in the lead-out portion HP can also be another structure. The memory cell array 10 can include at least the reference patterns RPU and RPL in the lead-out portion HP.

[0119] [2] Method of manufacturing semiconductor storage device 1

[0120] Figure 10 An example of a flowchart of a method of manufacturing the semiconductor storage device 1 of the embodiment. Figures 11-24 Each of the following drawings represents an example of a planar layout or a cross-sectional structure at an intermediate stage of manufacturing the semiconductor storage device 1 of the embodiment. The plan view used in the description of the manufacturing method shows the same region as Figure 7 The cross-sectional view used in the description of the manufacturing method shows the same region as Figure 8 or Figure 9 Hereinafter, an example of manufacturing steps related to the formation of the laminated wiring of the memory cell array 10 in the semiconductor storage device 1 of the embodiment will be described with appropriate reference to Figure 10 , as shown in Figure 10 In the manufacturing steps of the semiconductor storage device 1 of the embodiment, the processes of steps S10 to S20 are sequentially performed.

[0121] In the process of step S10, as shown in Figure 11 , a sacrificial member and an insulator layer are alternately laminated. In brief, on the semiconductor substrate 20, an insulator layer 30 including a circuit (not shown) corresponding to the row decoder module 15 and the like is formed. Then, on the insulator layer 30, a conductor layer 21 is formed. On the conductor layer 21, an insulator layer 31 and a sacrificial member 50 are sequentially formed. On the sacrificial member 50, a sacrificial member 51 and an insulator layer 32 are alternately formed. On the sacrificial member 51 of the uppermost layer, an insulator layer 33 and a sacrificial member 52 are sequentially formed. The sacrificial member 50 is associated with the selection gate line SGS. The sacrificial member 51 is associated with the word line WL. The sacrificial member 52 is associated with the selection gate line SGD. Further, in this example, after the process of step S10, a portion of each of the insulator layer 33 and the sacrificial member 52 is removed within the lead-out region HA.

[0122] In the process of step S11, as shown in Figure 12As shown, a mask REG1 for forming the reference pattern is formed. The mask REG1 includes opening portions H1, H2, and H3 that are separated from each other. The opening portion H1 overlaps with a region where a step portion of the lowermost conductive layer in the upper side stepped portion (for example, a step portion of the word line WL3) is to be formed. The opening portion H2 overlaps with a region where a step portion of the lowermost conductive layer in the lower side stepped portion (for example, a step portion of the select gate line SGS) is to be formed. The opening portion H3 is disposed between the opening portions H1 and H2, and between a region where the reference pattern RPU is to be formed and a region where the reference pattern RPL is to be formed. Further, a width of the mask REG1 in the X direction between the opening portions H1 and H3, and a width of the mask REG1 in the X direction between the opening portions H2 and H3 are each designed to be 2 times or less of a width of the step portion of the conductive layer 23 in the X direction. As shown, the upper surface of the uppermost sacrificial member 51 is exposed at the bottom of each of the opening portions H1, H2, and H3. Figure 13

[0123] In the processing of step S12, as shown, a convex portion for forming the reference pattern is formed by an etching process using the mask REG1. The etching process is, for example, RIE (Reactive Ion Etching) having anisotropy. In the etching process, for example, the set of the sacrificial members 51 and the insulator layer 32 are removed. The convex portion disposed between the opening portions H1 and H3 corresponds to the reference pattern RPU. The convex portion disposed between the opening portions H2 and H3 corresponds to the reference pattern RPL. Figure 14

[0124] In the processing of step S13, a stepped structure is formed by repeatedly performing a refinement process and an etching process. Specifically, first, a refinement process is performed on the mask REG1, and the mask REG1 is processed into a shape as shown. In the refinement process, an isotropic etching is performed, which is set to increase a selectivity ratio of a material used for the mask REG1. In addition, the refinement process is performed in such a manner that etching in a planar direction is performed to a degree corresponding to the width of one step portion. In this way, the opening portions H1, H2, and H3 are merged to form one large opening portion H4. Then, by using an anisotropic etching process of the mask REG1, the set of the sacrificial members 51 and the insulator layer 32 are removed, and a structure as shown is formed. Figure 15 Figure 16 Figure 17 If such refinement and etching processes are repeatedly performed, a structure as shown is formed. After the structure corresponding to the upper side stepped portion is completed, the mask REG1 is removed.

[0125] In the processing of step S14, as shown, a convex portion for forming the reference pattern is formed by an etching process using the mask REG2. The etching process is, for example, RIE (Reactive Ion Etching) having anisotropy. In the etching process, for example, the set of the sacrificial members 51 and the insulator layer 32 are removed. The convex portion disposed between the opening portions H1 and H3 corresponds to the reference pattern RPU. The convex portion disposed between the opening portions H2 and H3 corresponds to the reference pattern RPL. Figure 18 ​​​​As shown, a mask REG2 for multistage processing is formed. The mask REG2 includes an opening portion H5. The opening portion H5 overlaps with a region corresponding to the landing region LS. That is, the opening portion H5 overlaps with a portion corresponding to the reference pattern RPL. On the other hand, the mask REG2 covers a region corresponding to the landing region US including the reference pattern RPU within the lead-out portion HP.

[0126] In the processing of step S15, as shown, a lower side step portion is formed by using the multistage processing using the mask REG2. The "multistage processing" indicates a processing of removing a plurality of sets of the sacrificial member 51 and the insulator layer 32 by anisotropic etching. In this example, the etching processing of four sets of the sacrificial member 51 and the insulator layer 32 is performed using the mask REG2. Thereby, a configuration corresponding to the lower side step portion and the reference pattern RPL is formed within the landing region LS. Then, the mask REG2 is removed. Figure 19 In the processing of step S16, as shown, a processing conversion difference accompanying the processing of step S15 is measured. In this specification, the "processing conversion difference" corresponds to a dimension indicating a change of a step configuration generated accompanying the multistage processing. In the measurement of the processing conversion difference, for example, a CD-SEM (Critical Dimension-Scanning Electron Microscope) is used. The dimension measured as the processing conversion difference is used, for example, for adjusting a processing parameter when a wafer processed after the wafer is manufactured.

[0127] Figure 20 For example, in the processing of step S16, in the landing region US, a distance between the reference pattern RPU and an end of a step portion adjacent to the reference pattern RPU in the X direction (hereinafter, referred to as a step end of an upper side step portion) is measured. Specifically, in the landing region US, dimensions of "al" and "bl" shown are measured. The "al" is a length in the X direction between the step end of the upper side step portion and a portion of the reference pattern RPU most distant from the step end in the X direction. The "bl" is a length in the X direction between the step end of the upper side step portion and a portion of the reference pattern RPU closest to the step end in the X direction. Then, a distance between the center of gravity of the reference pattern RPU and the step end of the upper side step portion is calculated by a calculation formula "(al+bl) / 2".

[0128] For example, in the processing of step S16, in the landing region US, a distance between the reference pattern RPU and an end of a step portion adjacent to the reference pattern RPU in the X direction (hereinafter, referred to as a step end of an upper side step portion) is measured. Specifically, in the landing region US, dimensions of "al" and "bl" shown are measured. The "al" is a length in the X direction between the step end of the upper side step portion and a portion of the reference pattern RPU most distant from the step end in the X direction. The "bl" is a length in the X direction between the step end of the upper side step portion and a portion of the reference pattern RPU closest to the step end in the X direction. Then, a distance between the center of gravity of the reference pattern RPU and the step end of the upper side step portion is calculated by a calculation formula "(al+bl) / 2".

[0129] ​In addition, "E1", "E2", "E3", and "E4" shown in the drawing respectively denote end portions of the first-stage, second-stage, third-stage, and fourth-stage step portions within the contact region US. The end portion E1 corresponds to a step end of the upper-side step portion. In the step S16, the distance between the center of gravity of the reference pattern RPU and the end portion E1 can be calculated, and the distances between the center of gravity of the reference pattern RPU and the end portions E2, E3, and E4, respectively, can be calculated. Then, by calculating the distance in the X direction between the adjacent end portions based on the calculated distances, the width of the step portion provided between the adjacent end portions in the X direction is calculated. Based on the calculation result, when a wafer to be processed after the wafer is manufactured, it is possible to adjust the processing parameters of the step associated with the step S13. Further, the number of end portions for which the distance from the center of gravity of the reference pattern RPU is measured can be appropriately omitted. In the adjustment of the processing parameters in the step S13, the average of the widths of the plurality of step portions provided in the upper-side step portion can also be used.

[0130] Similarly, in the processing of the step S16, in the contact region LS, the distance between the reference pattern RPL and an end portion of a step portion adjacent to the reference pattern RPL in the X direction (hereinafter, referred to as a step end of a lower-side step portion) is measured. Specifically, in the contact region LS, the dimensions of "α2" and "β2" shown in the drawing are measured. "α2" is the length in the X direction between the step end of the lower-side step portion and the portion in the reference pattern RPL most distant from the step end in the X direction. "β2" is the length in the X direction between the step end of the lower-side step portion and the portion in the reference pattern RPL closest to the step end in the X direction. Then, by calculating the formula "(α2+β2) / 2", the distance between the center of gravity of the reference pattern RPL and the step end of the lower-side step portion is calculated. The calculation result corresponds to the "machining conversion difference". Based on the calculation result, when a wafer to be processed after the wafer is manufactured, it is possible to adjust the processing parameters of the step associated with the step S15. Further, the width of the step portion in the contact region LS can also be measured similarly to the contact region US.

[0131] In the processing of step S17, the memory pillar MP is formed. Briefly, first, the insulator layer 35 is formed, and the step difference in the lead-out region HA is filled. Then, the upper surface of the structure is planarized by, for example, CMP (Chemical Mechanical Polishing). Next, a mask that opens a region corresponding to the plurality of memory pillars MP is formed. Then, the plurality of memory holes are formed by anisotropic etching processing using the mask. Then, the barrier insulating film 45, the insulating film 44, and the tunnel insulating film 43 are sequentially formed on the side surfaces and the bottom surface of the plurality of memory holes. Then, a portion of the barrier insulating film 45, the insulating film 44, and the tunnel insulating film 43 provided at the bottom of the memory hole is removed, and the semiconductor layer 41 and the core member 40 are formed in the memory hole. Then, a portion of the core member 40 provided at the upper portion of the memory hole is removed, and the semiconductor layer 41 is formed in the portion. Thus, the plurality of memory pillars MP are formed.

[0132] In the processing of step S18, as shown in Figure 21 and Figure 22 , the plurality of slits SLT are formed. Specifically, first, the insulator layer 36 is formed on the insulator layer 35. The insulator layer 36 protects the upper portion of the memory pillar MP. The insulator layers 35 and 36 are included in the insulator layer 34 shown in Figure 8 . Then, a mask that opens a region corresponding to the slit SLT is formed by photolithography or the like. Then, the slit SLT that individually divides the insulator layers 31, 32, 35, and 36 and the sacrificial members 50 and 51 is formed by anisotropic etching using the mask. In addition, in a region not shown in the drawing, the slit SLT also individually divides the insulator layer 33 and the sacrificial member 52.

[0133] In the processing of step S19, the replacement processing of the laminated wiring is performed, and the laminated wiring structure is formed as shown in Figure 23 . Specifically, first, the sacrificial members 50 to 52 are selectively removed through the slits SLT by wet etching using hot phosphoric acid or the like. The structure in which the sacrificial members 50 to 52 are removed is maintained by the plurality of memory pillars MP or the support pillar or the like, which is omitted from the drawing. Then, a conductor is embedded into the space obtained by removing the sacrificial members 50 to 52 through the slits SLT. The formation of the conductor in this step uses, for example, CVD (Chemical Vapor Deposition).

[0134] Then, the conductive body formed inside the slit SLT is removed by an etching-back treatment, and the conductive body formed in the adjacent wiring layer is separated. Thus, the conductive body layer 22 functioning as a select gate line SGS, the plurality of conductive body layers 23 each functioning as a word line WL0 to WL7, and the conductive body layer 24 functioning as a select gate line SGD are formed, respectively. Further, the conductive body layers 22 to 24 formed in this step can include a barrier metal. In this case, when the conductive body is formed after the sacrificial members 50 to 52 are removed, for example, titanium nitride as the barrier metal is formed, and then tungsten is formed.

[0135] In the processing of step S20, as shown in FIG. 6, an embedding process of the slit SLT is performed. Specifically, first, an insulating film (spacer SP) is formed so as to cover the side surface and the bottom surface of the slit SLT. Then, a part of the spacer SP provided at the bottom of the slit SLT is removed, and a part of the conductive body layer 21 is exposed at the bottom of the slit SLT. Then, a conductive body (contact LI) is formed inside the slit SLT, and the conductive body formed outside the slit SLT is removed, for example, by CMP. Then, a plurality of grooves are formed in parallel with the slit SLT between the slits SLT adjacent in the Y direction, and an insulating film is embedded in each of the grooves to form a slit SHE that divides the conductive body layer 24 in the Y direction. Figure 24

[0136] By the manufacturing steps of the semiconductor storage device 1 of the embodiment described above, the stacked wiring structure in the memory cell array 10 is formed. Further, the manufacturing steps described above are merely an example, and are not limited thereto. For example, other processes can be inserted between the manufacturing steps, and a part of the steps can be omitted or integrated. In addition, the manufacturing steps can be exchanged within a possible range. For example, the step of forming the memory pillar MP and the step of forming the stepped structure of the stacked wiring can be exchanged.

[0137] [3] Effects of Embodiment

[0138] According to the semiconductor storage device 1 of the embodiment described above, the yield of the semiconductor storage device can be improved, and the chip area of the semiconductor storage device 1 can be reduced. Hereinafter, the detailed situation of the effects of the semiconductor storage device 1 of the embodiment will be described using a comparative example.

[0139] ​A semiconductor memory device having a three-dimensional stacked memory cell has, for example, a stacked wiring including a word line WL, and a memory pillar MP that penetrates the stacked wiring and functions as a memory cell at a crossing portion with the word line WL. The stacked wiring has, for example, a portion (hereinafter referred to as a step portion) that is arranged in a stepped shape. A row decoder module 15 applies a voltage to the word line WL and the like via a contact connected to the step portion of the stacked wiring. If the step portion of the stacked wiring and the contact are misaligned when the semiconductor memory device is manufactured, there is a concern that a short circuit of the word line WL and the like will occur. Therefore, when the semiconductor memory device is manufactured, it is preferable to manage the completion state of the step portion of the stacked wiring, such as the position of the step portion.

[0140] Here, as a comparative example of the embodiment, a case where the step portion of the stacked wiring is arranged at both ends of the memory cell array 10 is described. Figure 25 An example of a planar layout of a semiconductor memory device representing a comparative example of the embodiment is shown. As shown in FIG. 17, the semiconductor memory device of the comparative example of the embodiment has at least one reference pattern RP in a region other than the memory cell array 10. The reference pattern RP is used to manage the completion state of the step portion of the stacked wiring and is arranged as an isolated island pattern in the vicinity of the memory cell array 10. Figure 25

[0141] Figure 26 An example of a cross section along lines XXVI-XXVI of FIG. 17 is shown. The region including the step portion of the stacked wiring and the reference pattern RP is shown. In addition, the insulator layer INS and the sacrificial member SM corresponding to the alternate stack are processed into a stepped shape, and the state before the replacement processing of the stacked wiring is performed. Figure 25 Figure 26 As shown in FIG. 18, in the management of the completion state of the step portion of the stacked wiring, as with the embodiment, for example, the interval between the step end and the reference pattern RP is measured. Figure 26

[0142] However, the reference pattern RP arranged in the region other than the memory cell array 10 can cause dust to be generated in a subsequent manufacturing step. For example, in a case where hydrogen fluoride is used in a cleaning step on the back surface of a wafer, it is possible to return to the front surface of the wafer. The returned hydrogen fluoride can dissolve the insulator layer INS of the reference pattern RP arranged in the vicinity of the outer periphery of the wafer. Furthermore, the sacrificial member SM of the isolated reference pattern RP can be scattered as dust from the front surface of the substrate. The generated dust can be a factor in the yield reduction of the semiconductor memory device. Therefore, in the semiconductor memory device, the reference pattern RP is preferably arranged in a configuration that can suppress the generation of dust.

[0143] ​​​In contrast, the semiconductor memory device 1 of the embodiment has a stadium-shaped stepped structure (lead-out portion HP). The lead-out portion HP includes contact areas US and LS and reference patterns RPU and RPL. The contact areas US and LS have stepped structures with different heights. The reference pattern RPU is used to measure the position of the upper step portion included in the contact area US and is provided continuously with any of the built-up wiring in the contact area US. The reference pattern RPL is used to measure the position of the lower step portion included in the contact area LS and is provided continuously with any of the built-up wiring in the contact area UL.

[0144] Thus, in the semiconductor memory device 1 of the embodiment, the reference patterns RPU and RPL are not isolated island patterns as in the comparative example of the embodiment. Therefore, the reference patterns RPU and RPL in the embodiment are unlikely to become a dust source, as in the comparative example. Therefore, the semiconductor memory device 1 of the embodiment can balance the adjustment of processing parameters by measuring step positions with the suppression of dust generation caused by isolated island patterns. As a result, the semiconductor memory device 1 of the embodiment can improve yield and reduce the chip area of ​​the semiconductor memory device 1.

[0145] Furthermore, in the semiconductor memory device 1 of the embodiment, the lower step portion in the contact region LS is formed by multi-step processing. Furthermore, the boundary portion of the multi-step processing is located between the reference patterns RPU and RPL. Specifically, the reference pattern RPU is located at the same height as the step end of the upper step portion in the contact region US, while the reference pattern RPL is located at the same height as the step end of the lower step portion in the contact region LS.

[0146] As a result, in the semiconductor memory device 1 of the embodiment, the measurement accuracy of the positions of the upper and lower step portions is improved. Furthermore, by improving the measurement accuracy of the position of the lower step portion, the process transfer differences resulting from multi-stage processing can be measured with high precision. Therefore, the semiconductor memory device 1 of the embodiment can set processing parameters that take into account the process transfer differences associated with multi-stage processing, thereby improving the yield of the semiconductor memory device 1.

[0147] Furthermore, in the semiconductor memory device 1 according to the embodiment, the mask REG1 for forming the reference patterns RPU and RPL is configured so that portions covering the reference patterns RPU and RPL are removed by a single thinning process.

[0148] Thus, in the semiconductor storage device 1 of the embodiment, each of the reference patterns RPU and RPL is formed of only one set of the insulator layer 32 and the conductor layer 23, and a configuration in which the width of the X direction of each of the reference patterns RPU and RPL is suppressed is achieved. As a result, the semiconductor storage device 1 of the embodiment can suppress an increase in the area of the lead-out portion HP accompanying the arrangement of the reference patterns RPU and RPL.

[0149] [4] Variation of the Embodiment

[0150] The semiconductor storage device 1 of the embodiment can be variously changed. Hereinafter, a first variation, a second variation, a third variation, and a fourth variation of the embodiment are described with respect to aspects in which the semiconductor storage device 1 of the embodiment is different from the embodiment.

[0151] (First Variation)

[0152] With respect to the embodiment, the number of stacked layers of the word line WL and the stepped configuration in the lead-out region HA of the semiconductor storage device 1 of the first variation of the embodiment are different.

[0153] Figure 27 is an example of a planar layout in the lead-out region HA of the memory cell array 10 included in the semiconductor storage device 1 of the first variation of the embodiment, and shows the same region as that of the embodiment with reference to which the embodiment is described. As shown in Figure 7 , in the first variation of the embodiment, the number of stacked layers of the word line WL is larger than that of the embodiment. In addition, in the memory cell array 10 of the first variation of the embodiment, the lead-out portion HP of the embodiment is divided into two lead-out portions HP1 and HP2 arranged in the X direction. Figure 27 The height of the stadium-shaped stepped configuration provided in the lead-out portion HP1 is higher than that of the stadium-shaped stepped configuration provided in the lead-out portion HP2. The lead-out portion HP1 includes the contact regions US1 and LS1. The lead-out portion HP2 includes the contact regions US2 and LS2. Each of the contact regions US1, LS1, US2, and LS2 includes stepped configurations having different heights. In addition, the contact regions US1, LS1, US2, and LS2 include the reference patterns RPU1, RPL1, RPU2, and RPL2, respectively.

[0154]

[0155] ​The reference pattern RPU1 is used to measure the position of the step structure provided in the contact region US1, with a portion continuously provided with any one of the build-up wiring forming the step structure. The reference pattern RPL1 is used to measure the position of the step structure provided in the contact region LS1, with a portion continuously provided with any one of the build-up wiring forming the step structure. The reference pattern RPU2 is used to measure the position of the step structure provided in the contact region US2, with a portion continuously provided with any one of the build-up wiring forming the step structure. The reference pattern RPL2 is used to measure the position of the step structure provided in the contact region LS2, with a portion continuously provided with any one of the build-up wiring forming the step structure.

[0156] Figure 28 is a cross-sectional view along Figure 27 the line XXVIII-XXVIII, showing an example of the cross-sectional structure in the lead-out region HA of the memory cell array 10 provided in the semiconductor storage device 1 of the first variation of the embodiment. As shown in Figure 28 the lead-out portion HP1, the contact regions US1 and LS1 have a structure symmetrical in the X direction except for the difference in height. In the lead-out portion HP2, the contact regions US2 and LS2 have a structure symmetrical in the X direction except for the difference in height.

[0157] For example, the step structure of the lead-out portion HP1 and the step structure of the lead-out portion HP2 differ only in height. That is, the contact region LS1 is provided by performing multi-stage processing after forming the same structure as the step structure of the contact region US1. The contact region LS2 is provided by performing multi-stage processing after forming the same structure as the step structure of the contact region US2. The difference in height between the lead-out portions HP1 and HP2 is provided by performing multi-stage processing after forming the same structure as the step structure of the lead-out portion HP1. The contact region US1 is disposed at a higher level than the contact region LS1. The contact region US2 is disposed at a higher level than the contact region LS2. The contact region LS1 is disposed at a higher level than the contact region US2. The other configurations of the semiconductor storage device 1 of the first variation of the embodiment are the same as those of the embodiment.

[0158] As explained above, the memory cell array 10 can have a plurality of lead-out portions HP each including a reference pattern RP. The user can measure the step positions of the contact regions US1, LS1, US2, and LS2 by measuring the step ends associated with the reference patterns RPU1, RPL1, RPU2, and RPL2 using a length measuring device such as a CD-SEM. As a result, the semiconductor storage device 1 of the first variation of the embodiment can set processing parameters taking into account the processing conversion difference caused by multi-stage processing, and can improve the yield of the semiconductor storage device 1.

[0159] Further, in the first modification of the embodiment, the case where the lead-out portion HP is divided into two is illustrated, but the lead-out portion HP can be divided into three or more. In this case, the divided lead-out portions HP have stadium-shaped stepped structures of different heights. In this case, the reference pattern RP can be provided in each of the junction regions US and LS of the respective lead-out portions HP. Thus, the user can measure the positions of the respective stepped structures of different heights using a length measuring device such as a CD-SEM.

[0160] (Second Modification)

[0161] The number of reference patterns RP provided in the semiconductor storage device 1 of the second modification of the embodiment differs from that of the first modification of the embodiment.

[0162] Figure 29 is an example of a planar layout in the lead-out region HA of the memory cell array 10 provided in the semiconductor storage device 1 of the second modification of the embodiment, and indicates the same regions as those in the Figure 7 embodiment. As shown in Figure 29 , the memory cell array 10 in the second modification of the embodiment has a configuration obtained by omitting the reference pattern RPU1 from the memory cell array 10 in the first modification of the embodiment. The other configurations of the semiconductor storage device 1 of the second modification of the embodiment are the same as those of the first modification of the embodiment.

[0163] The semiconductor storage device 1 of the second modification of the embodiment can reduce the area of the lead-out region HA by omitting the reference pattern RPU1, as compared with the first modification of the embodiment. The reference pattern RPU1 corresponds to the junction region US1 in which multi-stage processing is not performed. The stepped position in the junction region in which multi-stage processing is not performed is less likely to be shifted as compared with the stepped position in the junction region in which multi-stage processing is performed.

[0164] As described above, the reference pattern RP can be appropriately omitted in part according to the degree of quality control. In addition, the reference pattern RP can be omitted in the junction region corresponding to the middle layer, and the stepped position in the junction region corresponding to the middle layer can be estimated on the basis of the measurement result of the stepped position in the reference pattern RP in the junction region corresponding to the upper layer and the measurement result of the stepped position in the reference pattern RP in the junction region corresponding to the lower layer.

[0165] (Third Modification)

[0166] The stepped structure in the lead-out portion HP and the arrangement of the reference pattern of the semiconductor storage device 1 of the third modification of the embodiment differ from those of the embodiment.

[0167] Figure 30FIG. 1 is an example of a planar layout in the lead-out area HA of the memory cell array 10 of the semiconductor memory device 1 according to the third variation of the embodiment, and shows a difference from the example of FIG. 1 in FIG. 1 . Figure 7 Same area. Figure 30 As shown, a semiconductor memory device 1 according to a third variation of the embodiment has a structure in which, in a lead portion HP, the adjacent step structures in the X direction are included and the dummy step structures are omitted. The region in which one of the adjacent step structures in the X direction is formed is referred to as "contact region SR1," and the region in which the other of the adjacent step structures in the X direction is formed is referred to as "contact region SR2."

[0168] Specifically, word lines WL7, WL5, WL3, WL1, select gate line SGS, and word lines WL0, WL2, WL4, and WL6 are sequentially arranged on the multiple terrace portions within lead-out portion HP. In other words, contact region SR1 includes word lines WL7, WL5, and WL3, as well as select gate line SGS, while contact region SR2 includes word lines WL0, WL2, WL4, and WL6. Furthermore, a reference pattern RP is provided between the terrace portion of select gate line SGS and the terrace portion of word line WL0. Contact region SR2 includes reference pattern RPL. Similar to the embodiment, reference pattern RP includes a portion that is continuous with any of the build-up wiring lines forming the staircase structure provided in contact region SR2.

[0169] Figure 31 It is along Figure 30 The cross-sectional view taken along line XXXI-XXXI of FIG. 1 shows an example of a cross-sectional structure in the lead-out region HA of the memory cell array 10 in the semiconductor memory device 1 according to the third variation of the embodiment. Figure 31 As shown, in the lead portion HP, the staircase structure provided in the contact region SR1 has a step difference corresponding to the two sets of insulating layer 32 and conductive layer 23. Similarly, the staircase structure provided in the contact region SR2 has a step difference corresponding to the two sets of insulating layer 32 and conductive layer 23. Reference pattern RP is provided, for example, at the same height as word line WL1. The height of reference pattern RP is not limited to the height corresponding to one set of insulating layer 32 and conductive layer 23 and may have a height corresponding to two or more sets. The other configurations of the semiconductor memory device 1 according to the third variation of the embodiment are the same as those of the embodiment.

[0170] The stepped structure as the 3rd modification of the embodiment is formed by performing etching processing multiple times using multiple masks. In this case, a dummy stepped structure can not be formed, and a stepped structure capable of connecting the contact CC can be formed. In this case, the reference pattern RP can also be used to measure the width of the step portion. For example, the distance between the center of gravity of the reference pattern RP and the end portion of each step portion in the contact region SR1 is calculated. Similarly, the distance between the center of gravity of the reference pattern RP and the end portion of each step portion in the contact region SR2 is calculated. Further, the width of the step portion provided between the adjacent end portions in the X direction is calculated by calculating the distance between the adjacent end portions in the X direction based on the calculated multiple distances.

[0171] Based on the calculation result, when manufacturing a wafer to be processed after the wafer, it can be necessary to adjust the processing parameters of the steps associated with the formation of the stepped structure. The number of end portions to be measured from the distance to the center of gravity of the reference pattern RP can be appropriately omitted. The adjustment of the processing parameters of the steps associated with the formation of the stepped structure can use the average of the widths of the calculated multiple step portions. As a result, the semiconductor storage device 1 of the 3rd modification of the embodiment can manage the stepped position using the reference pattern RP, and the yield can be improved.

[0172] Further, in the 3rd modification of the embodiment, a case in which the laminated wiring is provided in the lead-out portion HP in a stepped shape having a step difference only in the X direction is exemplified, but is not limited thereto. In the lead-out portion HP, two or more steps in the Y direction can be further formed. The number of step differences formed in the X direction and the Y direction in the laminated word line WL can be designed to be any number.

[0173] (4th Modification)

[0174] The configuration of the storage region MA and the lead-out region HA of the semiconductor storage device 1 of the 4th modification of the embodiment is different from that of the embodiment.

[0175] Figure 32 is an example of a planar layout of the storage cell array 10 provided in the semiconductor storage device 1 of the 4th modification of the embodiment, and indicates the same regions as those in the embodiment. Figure 3 As shown in Figure 32 , the semiconductor storage device 1 of the 4th modification of the embodiment has one storage region MA and one lead-out region HA. The storage region MA and the lead-out region HA are adjacent to each other. The other configurations of the semiconductor storage device 1 of the 4th modification of the embodiment are the same as those of the embodiment. In this case, the stepped position can also be measured by appropriately providing the reference pattern RP in the lead-out portion HP. As a result, the semiconductor storage device 1 of the 4th modification of the embodiment can manage the stepped position using the reference pattern RP, and the yield can be improved.

[0176] Further, in the embodiment, a case where the memory cell array 10 has one lead-out region HA is exemplified, but is not limited thereto. In the memory cell array 10, as long as at least one lead-out region HA is provided, a plurality of lead-out regions HA can also be provided. The lead-out region HA can be arranged between two adjacent memory regions MA, or can be arranged so as to sandwich the memory region MA from both sides. In a case where only one lead-out region HA is provided, the lead-out region HA is preferably inserted into the middle portion of the memory region MA as in the embodiment. Thereby, the semiconductor storage device 1 can suppress delay of voltage variation at the end portion of the word line WL due to the wiring resistance of the word line WL.

[0177] [5] Others

[0178] In the embodiment, a case where the end portion of the associated stepped structure is used in the measurement of the processing conversion difference is exemplified, but is not limited thereto. As long as the user uses at least the center of gravity of the reference pattern RP in the measurement of the processing conversion difference, a stepped portion having different heights can also be used. In the embodiment, a case where one lead-out portion HP is provided for every two blocks BLK is exemplified, but is not limited thereto. One lead-out portion HP can also be provided for each block BLK. In this case, the lead-out portion HP and each reference pattern RP are not divided by the slit SLT.

[0179] The configuration of the memory cell array 10 in the semiconductor storage device 1 of the embodiment can also be other configurations. For example, the memory pillar MP can have a configuration in which a plurality of pillars are connected in the Z direction. The memory pillar MP can have a configuration in which a pillar corresponding to the select gate line SGD and a pillar corresponding to the word line WL are connected. The connection between the memory pillar MP and the bit line BL, and the connection between the contact CC and the conductor layer 26 can each be made through a plurality of contacts connected in the Z direction. In this case, the connection portion of the plurality of contacts can be inserted with a conductor layer.

[0180] In the drawings used for explanation in the embodiment, a case where the memory pillar MP has the same diameter in the Z direction is exemplified, but is not limited thereto. For example, the memory pillar MP can also have a tapered shape or an inverted tapered shape, and can also have a shape in which the middle portion is bulged (bent shape). Similarly, the slits SLT and SHE can each have a tapered shape or an inverted tapered shape, and can also have a bent shape. Further, in the embodiment, a case where the cross-sectional configuration of each of the memory pillar MP and the contact CC is circular is exemplified, but the cross-sectional configuration can also be elliptical, and can be designed to be any shape.

[0181] In the embodiment, the inside of each of the slits SLT and SHE can be composed of a single or a plurality of insulators. In this case, for example, a contact with respect to the source line SL (the conductive layer 21) is provided in the lead-out region HA. In the present specification, the position of the slit SLT is specified based on the position of the contact LI, for example. In the case where the slit SLT is composed of an insulator, the position of the slit SLT can be specified from a joint within the slit SLT or a material remaining within the slit SLT at the time of replacement processing.

[0182] In the embodiment, the case where the sense amplifier module 16 and the like are provided below the memory cell array 10 is described, but the present application is not limited thereto. For example, the semiconductor memory device 1 can be configured such that the laminated wiring such as the word line WL is formed on the semiconductor substrate 20, or can be configured such that a chip provided with the sense amplifier module 16 and the like is attached to a chip provided with the memory cell array 10. In the case where the semiconductor memory device 1 has the attached configuration of chips, the configuration corresponding to the semiconductor substrate 20 can be omitted.

[0183] In the present specification, "connection" means electrical connection, and does not exclude the case where other elements are interposed therebetween, for example. With respect to "electrical connection", an insulator can be interposed as long as the same operation as in the case of electrical connection is possible. "Columnar" means a configuration provided in a hole formed in the manufacturing step of the semiconductor memory device 1. With respect to "the same layer configuration", at least the order of formation of layers is the same.

[0184] In the present specification, "region" can also be regarded as a configuration included in the semiconductor substrate 20. For example, in the case where it is specified that the semiconductor substrate 20 includes the memory regions MA1 and MA2 and the lead-out region HA, the memory regions MA1 and MA2 and the lead-out region HA are respectively associated with different regions above the semiconductor substrate 20. "Height" corresponds to the interval in the Z direction of the configuration of the measurement object and the semiconductor substrate 20, for example. Further, as a reference of "height", a configuration other than the semiconductor substrate 20 can also be used.

[0185] The present application has been described with respect to a few embodiments, but these embodiments are presented by way of example only and are not intended to limit the scope of the application. These novel embodiments can be implemented in various other ways, and various omissions, substitutions and changes can be made without departing from the spirit of the application. These embodiments or variations thereof are included in the scope or spirit of the application, and are included in the application and the equivalent scope described in the claims.

Claims

1. A semiconductor memory device comprising: A substrate comprising a first region, a second region, and a plurality of block regions, wherein the first region and the second region are arranged in a first direction, the plurality of block regions are each extended in the first direction, and the plurality of block regions are arranged in a second direction intersecting the first direction; a plurality of conductive layers, each of which is divided in each of the plurality of block regions, the plurality of conductive layers being arranged in a third direction intersecting the first direction and the second direction and being spaced apart from each other, the plurality of conductive layers having a plurality of stepped portions, the plurality of stepped portions being arranged so as not to overlap with an upper conductive layer in each region where the second region overlaps the plurality of block regions; a plurality of pillars provided in each of the plurality of block regions, wherein each of the plurality of pillars penetrates the plurality of conductive layers, and portions where the pillars intersect the conductive layers function as memory cells; as well as a plurality of contacts, in each of the plurality of block regions, respectively disposed on the plurality of step portions; and The second region includes a first sub-region and a second sub-region arranged in the first direction, The first sub-region includes a first stepped structure, wherein the first stepped structure includes a structure in which a plurality of first terrace portions included in the plurality of terrace portions are stepped up or down in a direction along the first direction and toward the first region. The second sub-region includes a second stepped structure and a first pattern, the second stepped structure includes a structure in which a plurality of second terrace portions included in the plurality of terrace portions are stepped up or down in a direction along the first direction and away from the first region, and the first pattern is continuously provided with any one of the plurality of conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure, and at least one contact point is arranged between the first pattern and a stepped portion of the conductor layer provided continuously with the first pattern.

2. The semiconductor memory device according to claim 1, wherein the first stepped structure is arranged at a layer higher than the second stepped structure. The first pattern is provided continuously with any one of the plurality of conductive layers forming the second stepped structure.

3. The semiconductor memory device according to claim 2, wherein the first sub-region includes a second pattern, the second pattern being provided continuously with any one of the plurality of conductive layers forming the first stepped structure among the plurality of conductive layers. At least one contact point is arranged between a stepped portion of the conductor layer provided continuously with the second pattern and the second pattern. 4 . The semiconductor memory device according to claim 3 , wherein a height of a step formed between the first pattern and the second pattern is higher than a height of the second stepped structure, and the step is separated from both the first pattern and the second pattern.

5. The semiconductor memory device according to claim 1, wherein the first pattern is provided continuously with a conductive layer arranged next to a lowermost conductive layer among a plurality of conductive layers forming the second stepped structure. 6 . The semiconductor memory device according to claim 1 , wherein a width of the first pattern in the first direction is not more than twice a width of the terrace portion in the first direction. 7 . The semiconductor memory device according to claim 1 , wherein the first sub-region and the second sub-region are divided by a boundary portion between two adjacent block regions.

8. A semiconductor storage device according to claim 7, wherein the first sub-region and the portion of the second sub-region included in one of the two adjacent block regions have a structure symmetrical in the second direction with the portion of the first sub-region and the portion of the second sub-region included in the other of the two adjacent block regions. 9 . The semiconductor memory device according to claim 1 , wherein the first stepped structure and the second stepped structure have structures that are symmetrical in the first direction except for their heights.

10. The semiconductor memory device according to claim 1, wherein the second region further includes a third sub-region and a fourth sub-region arranged in the first direction, The third sub-region includes a third stepped structure, wherein the third stepped structure includes a structure in which the plurality of third terrace portions included in the plurality of terrace portions are stepped up or down in a direction along the first direction and toward the first region. The fourth sub-region includes a fourth stepped structure and a third pattern, the fourth stepped structure includes a structure in which a plurality of fourth terrace portions included in the plurality of terrace portions are upgraded or downgraded in a direction along the first direction and away from the first region. The third step structure is arranged at a level higher than the fourth step structure and lower than the second step structure. The third pattern is provided continuously with any one of the plurality of conductive layers forming the fourth stepped structure among the plurality of conductive layers. The third pattern is arranged between the third stepped structure and the fourth stepped structure, and at least one contact point is arranged between the third pattern and a stepped portion of the conductor layer provided continuously with the third pattern.

11. The semiconductor memory device according to claim 10 , wherein the third sub-region includes a fourth pattern, the fourth pattern being provided continuously with any one of the plurality of conductive layers forming the third stepped structure among the plurality of conductive layers. At least one contact point is arranged between the fourth pattern and a stepped portion of the conductor layer provided continuously with the fourth pattern. 12 . The semiconductor memory device according to claim 10 , wherein the third stepped structure and the fourth stepped structure have structures that are symmetrical in the first direction except for their heights.

13. The semiconductor memory device according to claim 10, wherein the first step structure and the second step structure have the same structure as the third step structure and the fourth step structure except for the height.

14. The semiconductor memory device according to claim 10, wherein a contact connected to the lowermost first terrace portion among the plurality of first terrace portions is not surrounded by a conductive layer adjacent to a conductive layer corresponding to the lowermost first terrace portion.

15. The semiconductor memory device according to claim 1, wherein the plurality of first terrace portions in the first sub-region include a first dummy step structure rising along the second direction, The plurality of second terrace portions include a second dummy step structure in the second sub-region that rises along the second direction. 16 . The semiconductor memory device according to claim 1 , wherein the plurality of conductive layers arranged in the third direction alternately include the first terrace portions and the second terrace portions. 17 . The semiconductor memory device according to claim 16 , wherein each of the first sub-region and the second sub-region does not include a dummy step structure that is upgraded or degraded along the second direction. 18 . The semiconductor memory device according to claim 1 , wherein the substrate further includes a third region, the third region includes at least one of the pillars, and the second region is located between the first region and the third region in the first direction. 19 . The semiconductor memory device according to claim 18 , wherein in each of the plurality of block regions, the plurality of conductive layers are provided continuously between the first region and the third region.

20. The semiconductor memory device according to claim 1, wherein the first pattern is used to measure a position of the second stepped structure.

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