Method of manufacturing semiconductor device and semiconductor device
By forming a gate oxide layer on a silicon carbide substrate using a two-step process, the interface defect problem caused by carbon impurity diffusion is solved, and the performance and reliability of the semiconductor device are improved.
Patent Information
- Application Number
- CN202410283186.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-19
AI Technical Summary
During the high-temperature oxidation process of forming a gate oxide layer on a silicon carbide substrate, carbon impurities diffuse, leading to an increase in interface defect density and fixed oxide charge density, which affects the performance and reliability of semiconductor devices.
A two-step process is used to form the gate oxide layer. First, the first oxide layer is formed by dry thermal oxidation at high temperature, and then the second oxide layer is formed by a deposition process at a lower temperature. The total thermal budget is controlled to reduce the carbon-silicon bond breakage, reduce the interface defect density and the fixed oxide charge density.
The interface defect density and fixed oxide charge density are effectively reduced, and the performance and reliability of the gate oxide layer and the semiconductor device containing the gate oxide layer are improved.
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Figure CN120674310A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device having a silicon carbide material and a gate oxide layer thereon, and a method of manufacturing the semiconductor device. Background Art
[0002] Silicon carbide (SiC), with its excellent physical, chemical, and electrical properties, has become a highly advantageous semiconductor material for manufacturing high-temperature, high-power electronic devices. Its quality factor for power devices is far superior to that of silicon. Silicon carbide power semiconductor devices offer a range of advantages, including high input impedance, fast switching speed, high operating frequency, and high-temperature and high-voltage resistance. They have found widespread application in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.
[0003] A current technical issue limiting the application of SiC power semiconductor devices is that during the high-temperature oxidation process of forming the gate oxide layer on the SiC substrate, although carbon impurities in the oxide layer diffuse out as carbon oxides, a small amount of carbon impurities remains within the oxide layer and at the silicon oxide / SiC interface. As a result, the electrical performance of SiC semiconductor devices degrades, leading to reduced device performance and reliability, a key obstacle to the realization of SiC-based power electronics. Summary of the Invention
[0004] To address the above-mentioned problems, multiple embodiments of the present disclosure provide a method for manufacturing a gate oxide layer on a silicon carbide material. This method can effectively reduce the phenomenon of carbon-silicon bond breaking in the silicon carbide material, thereby reducing carbon impurities in the gate oxide layer and the gate oxide layer / silicon carbide interface, thereby improving the performance of the gate oxide layer and the power semiconductor.
[0005] Various embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate comprises a silicon carbide material; forming a first oxide layer on the substrate by a thermal oxidation process at a first temperature and in the presence of oxygen; forming a second oxide layer on the first oxide layer by a deposition process at a second temperature, wherein a gate oxide layer of the semiconductor device comprises the first oxide layer and the second oxide layer; and performing an annealing process after forming the second oxide layer in an environment comprising nitrogen or hydrogen. In some embodiments, the first temperature is greater than 1000° C. and the second temperature is less than 900° C.
[0006] In some embodiments, the thermal budget during formation of the first oxide layer is less than the thermal budget required for breaking carbon-silicon bonds in the silicon carbide material.
[0007] In some embodiments, the second oxide layer is formed via a high temperature oxide deposition process or an atomic layer deposition process.
[0008] In some embodiments, the second oxide layer is formed via a high temperature oxide deposition process, and the second temperature is 700° C. to 900° C.
[0009] In some embodiments, the second oxide layer is formed by an atomic layer deposition process, and the second temperature is 350° C. to 500° C.
[0010] In some embodiments, the first oxide layer has a first thickness, the second oxide layer has a second thickness, and the first thickness is less than the second thickness.
[0011] In some embodiments, the first thickness is in the range of (Angstrom) to The second thickness range is to
[0012] In some embodiments, the annealing process is performed in an ambient containing N2O, H2, N2, or POCl3.
[0013] Various embodiments of the present disclosure provide a semiconductor device comprising: a substrate, a gate oxide layer, and a gate. The substrate comprises silicon carbide. The gate oxide layer is disposed on the substrate, wherein the gate oxide layer comprises: a first oxide layer and a second oxide layer. The first oxide layer is in direct contact with the substrate, wherein the first oxide layer is formed by a thermal oxidation process. The second oxide layer is disposed on the first oxide layer, wherein the second oxide layer is formed by a deposition process, and the second oxide layer has a thickness in the range of to The gate is disposed on the gate oxide layer.
[0014] In some embodiments, in a silicon carbide semiconductor device, the first oxide layer has a first thickness, the second oxide layer has a second thickness, and the first thickness is smaller than the second thickness.
[0015] In some embodiments, in a silicon carbide semiconductor device, the first oxide layer has a thickness in the range of to The first thickness.
[0016] In some embodiments, in a silicon carbide semiconductor device, the deposition process for forming the second oxide layer is a high temperature oxide deposition process or an atomic layer deposition process. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] To make the objects, features, advantages and embodiments of the present disclosure more clearly understood, the detailed description of the accompanying drawings is as follows:
[0018] Figure 1 is a flow chart of a method of fabricating a gate oxide layer according to some embodiments.
[0019] Figure 2 is a partial schematic diagram of a semiconductor device including a silicon carbide material and a gate oxide layer according to some embodiments.
[0020] Figure 3 is a cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION
[0021] The following drawings and detailed descriptions clearly illustrate the spirit of the present disclosure. After understanding the implementation methods of the present disclosure, any person skilled in the art can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure.
[0022] Furthermore, to account for measurement errors and operational errors, the terms "about," "approximately," or "substantially" herein include the stated value and values within a range of deviation acceptable to those skilled in the art, such as ±30%, ±20%, ±15%, ±10%, or ±5%. Furthermore, the acceptable range of deviation may be selected based on the nature of the measurement or other properties that affect the operation.
[0023] In the high temperature oxidation process of forming a gate oxide layer on a silicon carbide substrate, a conventional method is to form a silicon oxide layer on the silicon carbide substrate by a dry thermal oxidation process. This process requires forming a silicon oxide layer with a thickness in the range of about 1000°C at a process temperature of about 1200°C. to However, during such conventional processes, the thermal budget is high enough to break some carbon-silicon bonds in the silicon carbide material, releasing carbon. This causes carbon impurities to appear at the silicon oxide / silicon carbide interface and within the oxide layer, increasing the interface defect density (Dit) and fixed oxide charge density (Qox), affecting the performance of the resulting semiconductor device.
[0024] The thermal budget is a combination of process temperature and time. Breaking the carbon-silicon bond in silicon carbide requires a sufficient thermal budget. In other words, controlling the thermal budget during gate oxide formation to be less than the thermal budget required to break the carbon-silicon bond reduces defects introduced during gate oxide formation.
[0025] By testing the broadband voltage of silicon oxide layers with different thicknesses formed by dry thermal oxidation process in silicon carbide semiconductor devices, it is found that when the thickness of the silicon oxide layer is less than In the case of , the interface defect density and fixed oxide charge density are at a low level. In the case of , it is found that the interface defect density and fixed oxide charge density will increase significantly. That is, the thickness of the silicon oxide layer formed by the high temperature thermal oxidation process is greater than The thermal budget can reach a point where it is sufficient to break the silicon-carbon bonds in the underlying silicon carbide material.
[0026] Therefore, in various embodiments of the present disclosure, a gate oxide layer is formed in two steps. First, in a first step, a first oxide layer is formed by a dry thermal oxidation process with a thickness not greater than The thickness of the gate oxide layer is then formed in a second step at a lower process temperature, so that the total thermal budget during the process of forming the gate oxide layer is lower and the carbon-silicon bond is not broken, thereby reducing carbon release.
[0027] In some embodiments, the process temperature of the second step is lower than that of the first step, preferably at least 150°C. For example, in one embodiment, the first step is performed at a process temperature of approximately 1200°C, and the second step is performed at a process temperature of approximately 800°C. In another embodiment, the first step is performed at a process temperature of 1200°C, and the second step is performed at a process temperature of 400°C. In other words, by lowering the process temperature at the end of the gate oxide formation, the overall thermal budget is reduced. Furthermore, since the process temperature of the second step does not allow for oxide growth via thermal oxidation, a deposition process is used instead to form the second oxide layer.
[0028] See also Figure 1 and Figure 2 , Figure 1 A flow chart illustrating a method of manufacturing a gate oxide layer according to some embodiments is shown. Figure 2 A partial cross-sectional view of a semiconductor device including a substrate and an oxide layer is shown according to some embodiments.
[0029] Method 100 begins with providing a silicon carbide substrate at operation 110. In some embodiments, the substrate includes a silicon carbide epitaxial layer. Figure 2 As shown in FIG, the semiconductor device 200 includes a substrate 210 , and the substrate 210 includes a silicon carbide material.
[0030] In operation 120 of method 100 , a first oxide layer is formed on the substrate via a thermal oxidation process at a first temperature, which may be in a range of 1050° C. to 1200° C. In some embodiments, the thermal oxidation process is a dry thermal oxidation process performed in the presence of oxygen.
[0031] As in Figure 2As shown in FIG, a first oxide layer 222 is formed on a substrate 210.
[0032] In some embodiments, the thermal budget for forming the first oxide layer 222 is controlled to not cause the silicon-carbon bond of the silicon carbide material of the substrate 210 to break, thereby controlling the duration of the thermal oxidation process and the thickness of the grown first oxide layer 222. In some embodiments, the duration of the thermal oxidation process may be, for example, 8 to 10 hours. In some embodiments, the first oxide layer 222 has a first thickness T1 that is less than Since the oxide layer grown by the thermal oxidation process is denser and has a stronger ability to resist breakdown, a certain thickness of the oxide layer grown by the thermal oxidation process is provided above the channel region of the semiconductor device to provide better gate oxide layer performance. In some embodiments, the first thickness T1 of the first oxide layer 222 is greater than In some embodiments, the first thickness T1 is in the range of to For example or
[0033] In operation 130 of method 100 , a second oxide layer is formed on the first oxide layer via a deposition process at a second temperature, which may be in a range of 700° C. to 900° C. In some embodiments, the deposition process is a high temperature oxide deposition process or an atomic layer deposition process.
[0034] As in Figure 2 As shown in FIG, a second oxide layer 224 is formed on the first oxide layer 222 , and the gate oxide layer 220 of the semiconductor device 200 includes the first oxide layer 222 and the second oxide layer 224 .
[0035] Because the thermal budget of a process is a combination of temperature and time, lowering the operating temperature during a period of the gate oxide layer formation process can reduce the total thermal budget of the gate oxide layer process. Specifically, by utilizing a lower process temperature during the formation of the second oxide layer 224, a lower thermal budget is achieved during the deposition process of operation 130 compared to the thermal oxidation process, which requires a higher temperature. This allows the total thermal budget for the gate oxide layer 220 formation to not cause the silicon-carbon bond in the silicon carbide material in the substrate 210 to break.
[0036] In some embodiments, the sum of the first thermal budget during formation of the first oxide layer and the second thermal budget during formation of the second oxide layer (ie, the total thermal budget) is less than the thermal budget required for carbon-silicon bond breaking in the silicon carbide material.
[0037] In some embodiments, the combination of precursor materials for the high temperature oxide deposition process comprises SiH4 and O 2、 SiH2Cl2 and N2O, or Si2H2 and O2. In some embodiments, the high temperature oxide deposition process may be performed for a time period of, for example, 8 to 10 hours.
[0038] In some embodiments, the second oxide layer 224 is formed by an atomic layer deposition process at a temperature ranging from approximately 300° C. to 500° C., preferably 400° C. In some embodiments, the precursor materials for the atomic layer deposition process are diisopropyl aminosilane (DIPAS) or tris(dimethylamino)silane (3DMAS), and O 3 . In some embodiments, the atomic layer deposition process can be performed for, for example, approximately 20 minutes to 40 minutes.
[0039] In some embodiments, the steps of forming the second oxide layer via an atomic layer deposition process are as follows:
[0040] (a) introducing a pulse of diisopropylaminosilane into the chamber of the atomic layer deposition apparatus; (b) introducing a pulse of nitrogen or argon gas for purging; (c) introducing a pulse of ozone or deionized water into the chamber of the atomic layer deposition apparatus; (d) introducing a pulse of nitrogen or argon gas for purging; (e) looping steps (a) to (d) to form a second oxide layer 224 on the surface of the first oxide layer 222 through an atomic layer deposition process.
[0041] In some embodiments, as in Figure 2 As shown in FIG, the second oxide layer 224 has a second thickness T2, and the second thickness T2 is used to ensure the total thickness T3 of the gate oxide layer 220, so as to ensure the threshold voltage of the semiconductor device 200 and make the gate oxide layer 220 less likely to be broken down. In some embodiments, the second thickness T2 of the second oxide layer 224 is greater than the first thickness T1 of the first oxide layer 222. In some embodiments, the second thickness T2 of the second oxide layer 224 is in the range of to For example 220, or In some embodiments, the total thickness T3 of the gate oxide layer 220 is to within the range.
[0042] In operation 140 of method 100 , a thermal annealing process is performed in an environment containing N 2 O, H 2 , N 2 or POCl 3 . The thermal annealing process can reduce unsaturated dangling bonds at the interface, thereby reducing the interface state density, improving the interface quality, and enhancing the reliability of the gate oxide layer 220 .
[0043] In some embodiments, the thermal annealing process is performed at a temperature in a range of 1500° C. to 1700° C. In some embodiments, the thermal annealing process is performed for a time in a range of approximately 60 minutes to 120 minutes.
[0044] In some embodiments, multiple additional operations may be performed before, during, and after the multiple operations of method 100 to form other structural regions or elements of the semiconductor device, such as forming various doped regions, source regions, source contacts, drain contacts, gate elements, or the like.
[0045] See also Figure 3 , depicts a schematic cross-sectional view of a semiconductor device according to some embodiments. Semiconductor device 300 is a metal-oxide-semiconductor field-effect transistor (MOSFET). Semiconductor device 300 includes a drain metal 302, a substrate 304, a source metal 310, a gate oxide layer 320, and a gate 330.
[0046] The substrate 304 includes a silicon carbide material and has a plurality of regions provided therein. The plurality of regions include n + Substrate layer 340, drift layer 342, P well 344, n + Source region 346, p + Contact region 348 , and channel region 350 .
[0047] As in Figure 3 As shown in FIG, the gate oxide layer 320 is composed of a stack of a first oxide layer 322 and a second oxide layer 324 .
[0048] The first oxide layer 322 of the gate oxide layer 320 is formed by a thermal oxidation process, and is disposed on and directly contacts the channel region 350 , so as to provide a reliable oxide layer / channel region interface.
[0049] The second oxide layer 324 of the gate oxide layer 320 is formed by a deposition process at a relatively low process temperature, such as a high temperature thermal oxidation deposition process or an atomic layer deposition process, to maintain the total thickness of the gate oxide layer 320 and reduce the total thermal budget during the process.
[0050] The gate oxide layer formation method provided by multiple embodiments of the present disclosure can reduce the total thermal budget of the process through a two-step process, effectively reduce the carbon impurities generated during the process, thereby reducing the interface defect density and fixed oxide charge density, and improving the channel mobility, thereby improving the performance of the gate oxide layer and the semiconductor device containing the gate oxide layer.
[0051] Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.
[0052]
Explanation of symbols
[0053] 100: Method
[0054] 110: Operation
[0055] 120: Operation
[0056] 130: Operation
[0057] 140: Operation
[0058] 200:Semiconductor devices
[0059] 210:Substrate
[0060] 220: Gate oxide layer
[0061] 222: first oxide layer
[0062] 224: Second oxide layer
[0063] 300:Semiconductor device
[0064] 302: Drain metal
[0065] 304:Substrate
[0066] 310: Source Metal
[0067] 320: Gate oxide layer
[0068] 322: first oxide layer
[0069] 324: Second oxide layer
[0070] 330: Gate
[0071] 340: substrate layer
[0072] 342: Drift layer
[0073] 344:P well
[0074] 346: Source region
[0075] 348:Contact area
[0076] 350: Channel area
[0077] T1: First thickness
[0078] T2: Second thickness
[0079] T3: Total thickness.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: providing a substrate, wherein the substrate comprises a silicon carbide material; forming a first oxide layer on the substrate by a thermal oxidation process at a first temperature and in the presence of oxygen; forming a second oxide layer on the first oxide layer at a second temperature by a high temperature oxide deposition process or an atomic layer deposition process, wherein the gate oxide layer of the semiconductor device comprises the first oxide layer and the second oxide layer; as well as An annealing process is performed after forming the second oxide layer in an atmosphere containing nitrogen or hydrogen.
2. The method for manufacturing a semiconductor device according to claim 1, wherein A thermal budget during the forming of the first oxide layer is less than another thermal budget required for breaking carbon-silicon bonds in the silicon carbide material.
3. The method for manufacturing a semiconductor device according to claim 1, wherein The second oxide layer is formed by a high temperature oxidation deposition process or an atomic layer deposition process.
4. The method for manufacturing a semiconductor device according to claim 1, wherein The second oxide layer is formed through a high temperature oxidation deposition process, and the second temperature is 700° C. to 900° C.
5. The method for manufacturing a semiconductor device according to claim 1, wherein The second oxide layer is formed by an atomic layer deposition process, and the second temperature is 300° C. to 500° C.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The first oxide layer has a range of to The first thickness.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The annealing process is also performed in an environment containing N2O, H2, N2 or POCl3.
8. A semiconductor device, characterized in that: Include: a substrate comprising silicon carbide; A gate oxide layer is disposed on the substrate, wherein the gate oxide layer comprises: a first oxide layer directly contacting the substrate, wherein the first oxide layer is formed by a thermal oxidation process; and A second oxide layer is disposed on the first oxide layer, wherein the second oxide layer is formed by a deposition process, and the second oxide layer has a range of to The second thickness of as well as A gate is disposed on the gate oxide layer.
9. The semiconductor device according to claim 8, wherein The first oxide layer has a range of to The first thickness.
10. The semiconductor device according to claim 9, wherein The deposition process is a high temperature oxidation deposition process or an atomic layer deposition process.