Test system and test method

Abstract

A test system includes an evaluation subsystem, an optical inspection subsystem, and a process control processor. The evaluation subsystem is configured to receive test data from the wafer testing device, wherein the test data includes a test image of the wafer. The evaluation subsystem is configured to receive analysis yield data of the wafer and receive identification data based on the test image. The process control processor is configured to perform a test operation in response to the wafer test device to generate test data, identify image specifications of the plurality of probe marks in the test image in response to the optical inspection subsystem, and generate identification data, and performing an evaluation operation in response to the evaluation subsystem to generate an evaluation result based on the test data, the analysis yield data and the identification data. Therefore, the productivity and the efficiency of the test wafer can be improved. In addition, manual work and human errors can be avoided or reduced, and therefore the overall productivity of the testing technology is improved.

Description

Technical Field

[0001] The present invention relates to a testing system and a testing method. Background Art

[0002] In integrated circuit manufacturing, testing is a crucial step in detecting defects introduced during the manufacturing process and determining their root causes. Prior to the packaging process, in-circuit probe testing is performed between wafers to verify that each die meets product specifications.

[0003] Because probe mark inspection is performed by human operators, human error can be introduced into the process, impacting test quality and being extremely time-consuming. For example, test cycle time and yield rates are impacted. Probe mark inspections based on customer complaints can also impact manufacturers' overall service quality, and the need for operators and engineers to handle them increases production costs. Consequently, time to market, scrap rates, and product quality are all impacted. Therefore, providing test systems and methods that can overcome these issues is one of the research and development goals in the relevant field. Summary of the Invention

[0004] The technical aspect of the present invention is a testing system.

[0005] According to some embodiments of the present invention, a test system includes an evaluation subsystem, an optical inspection subsystem, and a process control processor. The evaluation subsystem is configured to receive test data from a wafer test device, wherein the test data includes a test image of a wafer. The evaluation subsystem is configured to receive analyzed yield data of the wafer and receive identification data based on the test image. The process control processor is configured to generate test data in response to the wafer test device performing a test operation, generate identification data in response to the optical inspection subsystem recognizing image specifications of multiple probe marks in the test image, and generate an evaluation result based on the test data, analyzed yield data, and identification data in response to the evaluation subsystem performing an evaluation operation.

[0006] In some embodiments of the present invention, the process control processor is further configured to transmit the test data, the analysis yield data, and the identification data to the evaluation subsystem in an automated mode.

[0007] In some embodiments of the present invention, the process control processor is further configured to perform verification operations on the wafer to generate analytical yield data.

[0008] In some embodiments of the present invention, the test system further includes a database server connected to the process control processor, and the database server is configured to store the test data, the analysis yield data, and the identification data.

[0009] In some embodiments of the present invention, the database server is further connected to the evaluation subsystem, and the database server is configured to store the evaluation results.

[0010] In some embodiments of the present invention, the testing system further includes a recipe server connected to the process control processor, and the recipe server is configured to store recipe data corresponding to the wafer testing device.

[0011] In some embodiments of the present invention, the image specifications include coordinates of the probe mark, a plurality of distances between the probe mark and a plurality of edges of a plurality of pads on the wafer, or a combination thereof.

[0012] In some embodiments of the present invention, the evaluation operation includes determining the test data, analyzing the yield data, and identifying whether the data meets a plurality of quality thresholds.

[0013] In some embodiments of the present invention, if the test data, analytical yield data, and identification data meet a quality threshold, the evaluation result indicates a pass result, and if any of the test data, analytical yield data, and identification data fails to meet the quality threshold, the evaluation result indicates a fail result.

[0014] In some embodiments of the present invention, the test data includes the distribution of a plurality of probes of a probe card of a wafer testing apparatus, the distance between the probes of the probe card and the surface of the wafer, the specifications of the probes of the probe card, or a combination thereof.

[0015] The technical aspect of the present invention is a testing method.

[0016] According to some embodiments of the present invention, a testing method includes performing a test operation by a wafer testing apparatus to generate test data, wherein the test data includes a test image of a wafer; performing a verification operation on the wafer to generate analytical yield data; identifying image specifications of a plurality of probe marks in the test image to generate identification data based on the test image; and performing an evaluation operation by an evaluation subsystem to generate an evaluation result based on the test data, the analytical yield data, and the identification data.

[0017] In some embodiments of the present invention, performing the evaluation operation includes determining the test data, analyzing the yield data, and identifying whether the data meets a plurality of quality thresholds.

[0018] In some embodiments of the present invention, if any of the test data, analytical yield data, and identification data fails to meet a quality threshold, the evaluation result indicates a failed result.

[0019] In some embodiments of the present invention, if the test data, the analysis yield data, and the identification data meet the quality threshold, the evaluation result indicates a passing result. The testing method further includes executing a production process.

[0020] In some embodiments of the present invention, performing a verification operation on the wafer to generate analytical yield data includes analyzing test data to obtain yield data, and comparing the yield data with predetermined yield data to generate the analytical yield data.

[0021] In some embodiments of the present invention, performing the test operation includes detecting the distribution of a plurality of probes of the probe card, detecting the distance between the probes of the probe card and the surface of the wafer, and detecting the specifications of the probes of the probe card.

[0022] In some embodiments of the present invention, the image specifications of the probe mark in the test image include coordinates of the probe mark, distances between the probe mark and edges of the pads of the wafer, or a combination thereof.

[0023] In some embodiments of the present invention, the testing method further includes obtaining recipe data corresponding to the wafer testing device.

[0024] In some embodiments of the present invention, performing the test operation further includes heating a probe card of a wafer testing apparatus based on the recipe data, and performing a cleaning operation on a plurality of probes of the probe card based on the recipe data.

[0025] In some embodiments of the present invention, the testing method further includes transmitting the test data, the analysis yield data, and the identification data to an evaluation subsystem.

[0026] According to the above-described embodiments of the present invention, since the test system includes an evaluation subsystem, an optical inspection system, and a process control processor, it is possible to improve the productivity and efficiency of wafer testing. Furthermore, manual work and human errors can be avoided or reduced, thereby improving the overall productivity of the test process.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary only, and are intended to provide further explanation of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To make the above and other objects, features, advantages and embodiments of the present invention more apparent, the accompanying drawings are described as follows:

[0029] Figure 1 Schematic diagram of a testing system according to some embodiments of the present invention.

[0030] Figure 2 According to some embodiments of the present invention Figure 1 Schematic diagram of the wafer testing device of the test system.

[0031] Figure 3 Schematic diagram of multiple test images of a wafer according to some embodiments of the present invention.

[0032] Figure 4Flowchart of a testing method according to some embodiments of the present invention.

[0033] Figure 5 Flowchart of a testing method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0034] The following drawings illustrate various embodiments of the present invention. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details are not intended to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not essential and therefore should not be used to limit the present invention. Furthermore, to simplify the drawings, some conventional structures and components are depicted in a simplified schematic manner. Furthermore, for ease of viewing, the dimensions of the components in the drawings are not drawn to scale.

[0035] It should be understood that, in the present invention and the following patent scope, when an element is referred to as being "connected" or "coupled" to another element, it can mean that it is directly connected or coupled to the other element, or there may be other components in between. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there will be no other elements in between. In addition, "electrically connected" or "connected" can be used to indicate that two or more elements operate or act with each other.

[0036] It should be understood that in the present invention and the following patent scope, the terms "first," "second," etc. may be used to describe various elements. However, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element. Similarly, a second element may be referred to as a first element without departing from the spirit and scope of the embodiments.

[0037] Figure 1 Schematic diagram of a test system 10 according to some embodiments of the present invention. In some embodiments, the test system 10 is used as one of multiple test stages for evaluating a wafer (or multiple wafers) prior to release (or production). In some embodiments, the test system 10 is a test stage that utilizes optical testing to identify surface defects on the wafer. In some embodiments, the test system 10 is an automated system that generates test data, analyzes yield data, and identifies data before the wafer (or wafer test device) is released, and generates evaluation results based on the test data, analyzed yield data, and identified data.

[0038] See Figure 1The test system 10 includes a wafer tester 110, a process control processor 120, an evaluation subsystem 130, an optical inspection subsystem 140, a database server 150, a recipe server 160, and a release subsystem 170. The evaluation subsystem 130 is connected to the process control processor 120, the database server 150, and the release subsystem 170. The optical inspection subsystem 140 is connected to the process control processor 120 and the database server 150. The database server 150 is connected to the wafer tester 110, the process control processor 120, the evaluation subsystem 130, and the optical inspection subsystem 140. The recipe server 160 is connected to the wafer tester 110 and the process control processor 120. The release subsystem 170 is connected to the process control processor 120 and the evaluation subsystem 130.

[0039] The evaluation subsystem 130 is configured to receive test data from the wafer testing device 110, wherein the test data includes multiple test images of the wafer. The evaluation subsystem 130 is also configured to receive analytical yield data of the wafer and receive identification data based on the test image. The process control processor 120 is configured to generate test data in response to the wafer testing device 110 performing a test operation, to identify image specifications of multiple probe marks in the test image in response to the optical inspection subsystem 140 and to generate identification data, and to generate an evaluation result based on the test data, analytical yield data and identification data in response to the evaluation subsystem 130 performing an evaluation operation. Through the configuration of the test system 10, the productivity and efficiency of testing wafers can be improved. In addition, manual work and human errors can be avoided or reduced, thereby improving the overall productivity of the testing process.

[0040] The process control processor 120 is configured to transmit the test data, the analysis yield data, and the identification data to the evaluation subsystem 130 in an automated mode. The process control processor 120 is also configured to transmit the test data, the analysis yield data, and the identification data to the database server 150 in an automated mode. The automated mode executed by the process control processor 120 can avoid or reduce human errors.

[0041] The process control processor 120 is configured to perform a verification operation on the wafer to generate analytical yield data. In some embodiments, performing the verification operation includes analyzing the test data to obtain yield data of the wafer, and comparing the yield data of the wafer with predetermined yield data to generate analytical yield data. The predetermined yield data can be stored in the database server 150, the recipe server 160, or other appropriate storage unit. In some embodiments, the process control processor 120 is configured to create a production demand plan. The production demand plan can include using the wafer testing device 110 to test multiple items. In other words, at least one of the test data, analytical yield data, and identification data corresponds to the production demand plan. The production demand plan can be stored in the database server 150, the recipe server 160, or other appropriate storage unit. In some embodiments, the process control processor 120 is a central processing unit (CPU), a controller, or other analytical device (or component) with analytical capabilities.

[0042] The evaluation subsystem 130 is configured to perform an evaluation operation, including determining whether the test data, the analytical yield data, and the identification data meet a plurality of quality thresholds. In some embodiments, if the test data, the analytical yield data, and the identification data all meet the quality thresholds, the evaluation result indicates a pass result; if any of the test data, the analytical yield data, and the identification data fail to meet the quality thresholds, the evaluation result indicates a fail result. The process control processor 120 is further configured to perform subsequent operations based on the evaluation result. In some embodiments, if the test data, the analytical yield data, and the identification data all meet the quality thresholds, the evaluation subsystem 130 is configured to generate an evaluation result indicating a pass result, and the process control processor 120 is configured to control the release subsystem 170 to execute the production process. Conversely, if any of the test data, the analytical yield data, and the identification data fail to meet the quality thresholds, the evaluation subsystem 130 is configured to generate an evaluation result indicating a fail result, and the process control processor 120 is configured to execute the inspection process (and not control the release subsystem 170 to execute the production process). In some embodiments, the optical inspection subsystem 140 includes automated optical inspection (AOI) equipment. In some embodiments, the optical inspection subsystem 140 includes a processor and a storage unit, wherein the processor is configured to capture a test image of the test data and recognize an image specification of a probe mark in the test image to generate identification data, and the storage unit is configured to store the test image and the identification data.

[0043] The database server 150 is configured to receive test data, analyze yield data, and identify data, and is further configured to store the test data, analyze yield data, and identify data. In some embodiments, the database server 150 is configured to receive evaluation results from the evaluation subsystem 130, and is further configured to store the evaluation results.

[0044] In some embodiments, the evaluation subsystem 130 and the database server 150 are collectively referred to as a single server. That is, the single server (including the database storage unit and the evaluation unit) is configured to receive test data, analyze yield data, and identify data, and generate evaluation results based on the test data, the analyzed yield data, and the identified data.

[0045] In some embodiments, the recipe server 160 is configured to store recipe data corresponding to the wafer testing apparatus 110 . The recipe data may include temperature parameters of the wafer testing apparatus 110 , cleaning parameters of the wafer testing apparatus 110 , or other suitable parameters of the wafer testing apparatus 110 .

[0046] See Figure 2 , Figure 2 According to some embodiments of the present invention Figure 1 Schematic diagram of a wafer testing device 110 of a test system. The wafer testing device 110 includes a tester 210, a test head 220, a loader 230, a detection device 240, and an interface board 250. The tester 210 is configured to apply an electrical signal to a wafer W through the test head 220 and analyze the response of the wafer W. The loader 230 is configured to load or unload the wafer W. In some embodiments, the loader 230 includes a cargo compartment for accommodating the wafer W, an opener for opening the door of the cargo compartment, and a transfer robot for transferring the wafer W from the cargo compartment to the detection device 240. The detection device 240 includes a probe machine 241, a probe card 242 having a plurality of probes (or probe needles), a chamber housing 244 defining a housing space for performing electrical testing, and a support table 246 located on the bottom side of the chamber housing 244 for supporting the wafer W. The interface board 250 is configured to provide electrical connection between the test head 220 and the probe card 242. In some embodiments, when the probe card 242 is connected to the test head 220 through the interface board 250 and contacts the wafer W, a testing operation is performed.

[0047] In some embodiments, the prober 241 of the inspection apparatus 240 is a camera device configured to obtain a test image of the wafer W. The test image includes a surface image of the device under test (DUT) on the wafer W. For example, during a test operation, the bonding pads of the DUT (or device under test) on the wafer W come into contact with the probes 2421 of the probe card 242, and the test image includes probe marks left by the probes 2421 of the probe card 242 on the bonding pads above the DUT on the wafer W. In some embodiments, the prober 241 of the inspection apparatus 240 is a complementary metal-oxide semiconductor (CMOS) camera, a charge-coupled device (CCD) camera, a video recorder, or other suitable type of camera. In some embodiments, the detection device 240 further includes a temperature control unit, a dry gas supply unit and / or a flow control unit, wherein the temperature control unit is used to control the test temperature of the wafer W, the dry gas supply unit is used to supply dry gas to the accommodating space in the chamber housing 244, and the flow control unit is used to control the dry gas supply unit based on the test temperature to adjust the flow rate of the dry gas.

[0048] In some embodiments, the wafer testing apparatus 110 further includes a support member 260 located on the top side of the chamber housing 244 . The support member 260 is configured to secure the test head 220 such that the test head 220 is disposed above the top side of the chamber housing 244 .

[0049] In some embodiments, the wafer testing apparatus 110 is configured to perform testing operations and generate test data. The test data may include the distribution of the probes 2421 of the probe card 242, the distance between the probes 2421 of the probe card 242 and the surface of the wafer W, the specifications of the probes 2421, the specifications of the wafer W, or a combination thereof.

[0050] Figure 3 3 is a schematic diagram of a test image 310, a test image 320, and a test image 330 of a wafer W according to some embodiments of the present invention. Figures 1 to 3 , the test images 310, 320, and 330 can be generated by the wafer testing apparatus 110 by performing a test operation. In other words, the test images 310, 320, and 330 depict Figure 2 In the test image 310, the wafer W includes a bonding pad 312 and a probe mark 314. The probe mark 314 overlaps a portion of the bonding pad 312 and is separated from the edge of the bonding pad 312. The test image 310 is identified (e.g., by Figure 1The optical inspection subsystem 140 of the embodiment of the present invention is configured to generate first identification data (e.g., first identification data indicating that the probe mark overlaps with the pad and is separated from the edge of the pad), and the first identification data is determined or evaluated (e.g., by Figure 1 The evaluation subsystem 130 of the test image 320 is configured to generate an evaluation result indicating a passing result. In some embodiments, the probe mark 314 is separated from the edge of the bonding pad 312 by a distance Dx in the direction X and by a distance Dy in the direction Y. In the test image 320, the wafer W includes a bonding pad 322 and a probe mark 324, which overlaps a portion of the bonding pad 312 and contacts the edge of the bonding pad 322. The test image 320 is identified (e.g., by Figure 1 The optical inspection subsystem 140 of FIG. 1 is configured to generate second identification data (e.g., second identification data indicating that the probe mark overlaps with the pad and contacts the edge of the pad), and the second identification data is determined or evaluated (e.g., by Figure 1 The evaluation subsystem 130 of the test image 330 is used to generate an evaluation result indicating a failure result. In the test image 330, the wafer W includes a bonding pad 332 and a probe mark 334, and the probe mark 334 does not overlap with any portion of the bonding pad 312. The test image 330 is identified (e.g., by Figure 1 The optical inspection subsystem 140 of FIG. 140 is configured to generate third identification data (e.g., third identification data indicating that the probe mark does not overlap with any portion of the pad), and the third identification data is determined or evaluated (e.g., by Figure 1 evaluation subsystem 130) to generate an evaluation result indicating a fault result.

[0051] See now Figure 4 . Figure 4 FIG. 4 is a flow chart of a test method 400 according to some embodiments of the present invention. Figure 4 Additional steps are provided before, during, and after the test method 400, and some of the steps described may be replaced, eliminated, or moved for additional implementations of the test method 400. The test method 400 may include steps 410 to 480, which will be described below with reference to FIG. Figures 1 to 4 is described in more detail, and the test method 400 may be performed by Figure 1 and Figure 2 The test system 10 shown performs.

[0052] The test method 400 begins at step 410 by creating a production demand plan. Figure 1 and Figure 2 In some embodiments of step 410, a production requirement plan is created by the process control processor 120. The production requirement plan may include multiple items to be tested using the wafer testing apparatus 110. In some embodiments, the production requirement plan includes multiple items to be tested and multiple quality thresholds corresponding to the items to be tested.

[0053] The test method 400 continues to step 420 where the recipe data is obtained. Figure 1 and Figure 2 In some embodiments of step 420, the recipe data is obtained from the recipe server 160. The recipe server 160 is connected to the wafer testing device 110 and the process control processor 120. The recipe server 160 is configured to store recipe data corresponding to the wafer testing device 110. For example, the recipe data includes temperature parameters of the wafer testing device 110, cleaning parameters of the wafer testing device 110, or other suitable parameters of the wafer testing device 110.

[0054] The testing method 400 continues to step 430, where a wafer testing device performs a testing operation to obtain test data, wherein the test data includes a test image of the wafer. Figures 1 to 3 In some embodiments of step 430 , the process control processor 120 is configured to generate test data in response to the wafer testing device 110 performing a test operation. In some embodiments, the test data includes a test image of the wafer W. The test image displays electrical specifications of the bonding pads above the components under test on the wafer W. In some embodiments, the production requirement plan includes a plurality of items to be tested, and the test operation is performed based on the items in the production requirement plan to obtain the test data.

[0055] In some embodiments, step 430 includes multiple steps 431 to 437, and can be performed using Figure 1 and Figure 2 The test system 10 is shown. Figure 5 According to some embodiments of the present invention Figure 4 Flowchart of step 430 of the testing method 400 . Figure 5 The flowchart shown in is only an example and is not intended to limit the present invention to the scope explicitly stated in the patent claims. Figure 5 Provide additional steps before, during, and after the steps of Figure 5 Additional implementations of the steps may replace, eliminate, or move some of the steps described.

[0056] In step 431, the probe card is replaced. Figure 1 and Figure 2 In some embodiments of step 431, the probe card 242 is replaced. In step 432, the probe card is heated. Figure 1 and Figure 2In some embodiments, in step 432, the probe card 242 is heated. In some embodiments, the support table 246 of the inspection apparatus 240 includes a heater disposed thereon. The heater of the support table 246 of the inspection apparatus 240 is configured to heat the probe card 242. In some embodiments, the probe card 242 of the inspection apparatus 240 of the wafer testing apparatus 110 is heated to a temperature based on temperature parameters of the recipe data obtained from the recipe server 160.

[0057] In step 433, the distribution of the probes of the probe card is detected. Figure 1 and Figure 2 In some embodiments, at step 433, the distribution of probes 2421 of the probe card 242 is detected. In some embodiments, the tester 210 applies an input electrical signal from the test head 220 connected to the probe card 242, and the distribution of the probes 2421 of the probe card 242 can be detected from the response of the wafer W (or other test wafer) to the input electrical signal. The distribution of the probes 2421 can indicate the horizontal positions of the probes 2421 and / or the horizontal spacing between any two adjacent probes 2421.

[0058] In step 434, the distance between the probes of the probe card and the surface of the wafer is detected. Figure 1 and Figure 2 In some embodiments, at step 434 , the distance between the probes 2421 of the probe card 242 and the surface of the wafer W is detected. For example, an optical inspection is performed using the probe machine 241 to detect the distance between the probes 2421 of the probe card 242 and the surface of the wafer W. The distance between the probes 2421 of the probe card 242 and the surface of the wafer W indicates the distance required when the probes 2421 of the probe card 242 contact the wafer W in a probe marking operation (e.g., step 437 ).

[0059] In step 435, a cleaning operation is performed on the probes of the probe card. Figure 1 and Figure 2 In some embodiments of step 435, a cleaning operation is performed by using a cleaning wafer to clean (e.g., grind or stick) the tip portions of the probes 2421 of the probe card 242 to improve the accuracy of performing the probe marking operation (i.e., step 437). In some embodiments, the cleaning operation is performed on the probes 2421 of the probe card 242 based on the recipe data of the cleaning parameters obtained from the recipe server 160. In some embodiments, the cleaning operation is performed by immersing the probes 2421 in a cleaning agent to chemically react the probes 2421 with the cleaning agent. The probes 2421 are then rinsed with clean water to remove the reactants attached to the probes 2421.

[0060] In step 436, the specifications of the probes of the probe card are inspected. Figure 1 and Figure 2 In some embodiments, step 436 detects the specifications of the probes 2421 of the probe card 242. For example, optical inspection is performed using the probe machine 241 to detect the specifications of the probes 2421 of the probe card 242. The specifications of the probes 2421 of the probe card 242 may include the length of the probes 2421, the width of the probes 2421, the size of the probes 2421, other appropriate specifications of the probes 2421, or a combination thereof.

[0061] At step 437, a probe marking operation is performed to generate a test image. Figures 1 to 3 In some embodiments of step 437, a probe marking operation is performed to generate a test image. Specifically, the wafer W is loaded into the accommodation space in the chamber housing 244 and placed on the support table 246 to face the probe card 242. Then, the probes 2421 of the probe card 242 physically contact the bonding pads of the wafer W, leaving probe marks of the probes 2421 on the bonding pads of the wafer W. Thus, a test image (e.g., Figure 3 310, test image 320 or test image 330).

[0062] In some embodiments, as Figures 1 to 4 As shown, the test data includes the distribution of the probes 2421 of the probe card 242, the distance between the probes 2421 of the probe card 242 and the surface of the wafer W, the specifications of the probes 2421 of the probe card 242, the test image, the size of the wafer W, the test time, other appropriate data, or a combination thereof.

[0063] The testing method 400 continues at step 440 by performing verification operations on the wafer to generate analytical yield data. Figure 1 and Figure 2 In some embodiments of step 440, a verification operation is performed on wafer W to generate analytical yield data. In some embodiments, the process control processor 120 is configured to perform the verification operation. In some embodiments, performing the verification operation includes analyzing the test data to obtain yield data of wafer W, and comparing the yield data of wafer W with default yield data to generate analytical yield data. The default yield data can be obtained (or generated) by using another wafer testing device in a similar method in step 430 for the same wafer. The default yield data can be stored in the database server 150. Alternatively, the default yield data can be stored in the recipe server 160.

[0064] The testing method 400 continues with step 450 of identifying the image specifications of the probe marks in the test image to generate identification data based on the test image. Figures 1 to 3 In some embodiments of step 450, image specifications of the probe marks in the test images (e.g., test image 310, test image 320, and test image 330) are recognized to generate identification data based on the test images. The process control processor 120 is configured to control, in an automated mode, the transmission of the test images to the optical inspection subsystem 140 in response to the wafer testing apparatus 110, and to generate identification data in response to the optical inspection subsystem 140 recognizing the image specifications of the probe marks in the test images. In some embodiments, the image specifications of the probe marks in the test images are data used to inspect the quality of the test wafers. The aforementioned image specifications may include coordinates of the probe marks relative to a reference point on the bonding pads of the wafer W, a distance between the probe marks and an edge of the bonding pads of the wafer W, a position of the probe marks relative to an edge of the bonding pads of the wafer W, an overlap relationship between the probe marks and the bonding pads of the wafer W, or a combination thereof. In some embodiments, the wafer testing device 110 is configured to transmit a test image of the test data and related information (e.g., the distribution of the probes 2421 , the distance between the probes 2421 of the probe card 242 and the surface of the wafer W, the specifications of the probes 2421 of the probe card 242 , etc.) to the database server 150 .

[0065] The testing method 400 continues at step 460 by transmitting the test data, analysis yield data, and identification data to the evaluation subsystem. Figure 1 and Figure 2 In some embodiments, at step 460, the test data, the analytical yield data, and the identification data are transmitted to the evaluation subsystem 130 in an automated mode. In other words, the evaluation subsystem 130 is configured to receive the test data, the analytical yield data from the wafer testing device 110, and the identification data from the optical inspection subsystem 140 in an automated mode. In some embodiments, the testing method 400 further includes transmitting the test data, the analytical yield data, and the identification data to the database server 150 in an automated mode.

[0066] The testing method 400 continues to step 470, where the evaluation subsystem performs evaluation operations on the test data, the analysis yield data, and the identification data to generate evaluation results. Figures 1 to 3 In some embodiments of step 470, the evaluation subsystem 130 performs an evaluation operation on the test data, the analytical yield data, and the identification data to generate an evaluation result based on the test data, the analytical yield data, and the identification data. In some embodiments, performing the evaluation operation includes determining whether the test data, the analytical yield data, and the identification data meet a quality threshold. In some embodiments, if all of the test data, the analytical yield data, and the identification data meet the quality threshold, the evaluation result indicates a pass result; if any of the test data, the analytical yield data, and the identification data fails to meet the quality threshold, the evaluation result indicates a fail result.

[0067] In some embodiments, the evaluation subsystem 130 is configured to convert the test data, the analysis yield data, and the identification data into a first value, a second value, and a third value, respectively, and to compare the first value, the second value, and the third value with a quality threshold to generate an evaluation result.

[0068] In some embodiments, the evaluation operation includes determining whether the distance between the probe mark of the identification data and the edge of the pad meets a quality threshold. Figures 1 to 3 As shown, when the distance Dx or the distance Dy is within a specific range indicating that the probe mark overlaps with the edge of the pad and is separated from the pad, the evaluation subsystem 130 is configured to evaluate that the identification data meets the quality threshold, and thus the evaluation result corresponding to the identification data indicates a pass result. In various embodiments, as Figures 1 to 3 As shown, when the distance Dx or the distance Dy is within another specific range indicating that the probe mark does not overlap with the edge of the pad or contacts the pad, the evaluation subsystem 130 is configured to evaluate that the identification data fails to meet the quality threshold, and thus the evaluation result corresponding to the identification data indicates a failure result.

[0069] In some embodiments, the testing method 400 further includes, before performing the evaluation operation, capturing a portion of the test data, analyzing a portion of the yield data, and / or identifying a portion of the data by the process control processor 120. In some embodiments, the testing method 400 further includes transmitting the evaluation result to the database server 150 in response to a command sent by the process control processor 120.

[0070] The test method 400 continues to step 480 to perform subsequent operations based on the evaluation results. Figures 1 to 3 In some embodiments of step 480, the process control processor 120 is configured to perform subsequent operations based on the evaluation results. If the test data, the analytical yield data, and the identification data meet the quality threshold, the evaluation subsystem 130 is configured to generate an evaluation result indicating a pass result, and the process control processor 120 is then configured to control the release subsystem 170 to execute the production process. Conversely, if any of the test data, the analytical yield data, and the identification data fail to meet the quality threshold, the evaluation subsystem 130 is configured to generate an evaluation result indicating a fail result, and the process control processor 120 is then configured to execute an inspection process. For example, the inspection process includes at least one of steps 430, 440, 450, 460, and 470.

[0071] In some embodiments, as Figure 1As shown, the testing method 400 further includes generating a process / product report based on the evaluation results by the evaluation subsystem 130. The process / product report can be transmitted to the database server 150 or other subsystems / servers for review by a supervisory operator.

[0072] It should be noted that Figure 1 The test system 10 shown in FIG. 1 may also include a method for implementing Figures 1 to 5 A processing device that implements one or more of the described tools, subsystems, methods, or operations.

[0073] In summary, since the test system includes an evaluation subsystem, an optical inspection subsystem, and a process control processor, it can improve the productivity and efficiency of testing wafers. In addition, manual work and human errors can be avoided or reduced, thereby improving the overall productivity of the test process.

[0074] Although the present invention has been disclosed above in terms of embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0075]

Explanation of symbols

[0076] 10: Test system

[0077] 110: Wafer testing equipment

[0078] 120: Process Control Processor

[0079] 130:Evaluation Subsystem

[0080] 140: Optical inspection subsystem

[0081] 150: Database Server

[0082] 160: Recipe Server

[0083] 170: Release subsystem

[0084] 210:Testing machine

[0085] 220:Test head

[0086] 230: Loader

[0087] 240: Detection device

[0088] 241:Probe Machine

[0089] 242:Probe Card

[0090] 2421:Probe

[0091] 244: Chamber shell

[0092] 246: Support platform

[0093] 250: Interface board

[0094] 260: Support element

[0095] 310: Test image

[0096] 312: Solder pad

[0097] 314: Probe labeling

[0098] 320: Test image

[0099] 322: Solder pad

[0100] 324: Probe labeling

[0101] 330:Test image

[0102] 332: Solder pad

[0103] 334: Probe labeling

[0104] 400:Test Method

[0105] 410,420,430,440,450,460,470,480: Steps

[0106] 431,432,433,434,435,436,437: Steps

[0107] Dx, Dy: distance

[0108] X: direction

[0109] Y: direction.

Claims

1. A testing system, characterized in that: Include: Evaluation subsystem, configured with: receiving test data from a wafer testing device, wherein the test data includes a test image of the wafer; receiving analysis yield data of the wafer; as well as receiving recognition data based on the test image; Optical inspection subsystem; as well as Process control processor configured with: generating the test data in response to the wafer testing apparatus performing a test operation; in response to the optical inspection subsystem identifying image specifications of a plurality of probe marks in the test image and generating the identification data; as well as In response, the evaluation subsystem performs an evaluation operation to generate an evaluation result based on the test data, the analysis yield data, and the identification data. 2 . The test system of claim 1 , wherein the process control processor is further configured to transmit the test data, the analysis yield data, and the identification data to the evaluation subsystem in an automated mode. 3 . The test system of claim 1 , wherein the process control processor is further configured to perform a verification operation on the wafer to generate the analytical yield data.

4. The test system according to claim 1, wherein: Also includes: The database server is connected to the process control processor and is configured to store the test data, the analysis yield data and the identification data. 5 . The test system according to claim 4 , wherein the database server is further connected to the evaluation subsystem, and the database server is configured to store the evaluation result. The test system according to claim 1 , wherein: Also includes: The recipe server is connected to the process control processor and is configured to store recipe data corresponding to the wafer testing device. 7 . The test system of claim 1 , wherein the image specifications include coordinates of the plurality of probe marks, a plurality of distances between the plurality of probe marks and a plurality of edges of a plurality of pads of the wafer, or a combination thereof. 8 . The test system of claim 1 , wherein the evaluating operation comprises determining whether the test data, the analysis yield data, and the identification data meet a plurality of quality thresholds.

9. The test system of claim 8 , wherein the evaluation result indicates a pass result if the test data, the analytical yield data, and the identification data satisfy the plurality of quality thresholds, and wherein the evaluation result indicates a fail result if any of the test data, the analytical yield data, and the identification data fails to satisfy the plurality of quality thresholds.

10. The test system according to claim 1, wherein the test data includes a distribution of multiple probes of a probe card of the wafer testing device, a distance between the multiple probes of the probe card and the wafer surface, a specification of the multiple probes of the probe card, or a combination thereof.

11. A testing method, characterized in that: Include: performing a test operation by a wafer testing device to generate test data, wherein the test data includes a test image of the wafer; performing a verification operation on the wafer to generate analytical yield data; identifying an image specification of a plurality of probe marks in the test image to generate identification data based on the test image; as well as An evaluation subsystem performs an evaluation operation to generate an evaluation result based on the test data, the analysis yield data, and the identification data.

12. The testing method according to claim 11, wherein performing the evaluation operation comprises: It is determined whether the test data, the analysis yield data, and the identification data meet a plurality of quality thresholds. 13 . The testing method of claim 12 , wherein the evaluation result indicates a failure result if any one of the test data, the analysis yield data, and the identification data fails to meet the plurality of quality thresholds.

14. The testing method of claim 12, wherein if the test data, the analysis yield data, and the identification data satisfy the plurality of quality thresholds, the evaluation result indicates a passing result, and The testing method further comprises executing a production process.

15. The testing method according to claim 11, wherein performing the verification operation on the wafer to generate the analytical yield data comprises: analyzing the test data to obtain yield data; and The yield data is compared with predetermined yield data to generate the analyzed yield data.

16. The testing method according to claim 11, wherein performing the testing operation comprises: detecting distribution of a plurality of probes of a probe card; detecting a distance between the plurality of probes of the probe card and a surface of the wafer; and The specifications of the plurality of probes of the probe card are detected. 17 . The testing method according to claim 11 , wherein the image specifications of the plurality of probe marks in the test image include coordinates of the plurality of probe marks, distances between the plurality of probe marks and edges of a plurality of pads on the wafer, or a combination thereof.

18. The testing method according to claim 11, wherein: Also includes: Recipe data corresponding to the wafer testing device is obtained.

19. The testing method according to claim 18, wherein performing the testing operation further comprises: heating the probe card of the wafer testing apparatus based on the recipe data; and A cleaning operation is performed on the plurality of probes of the probe card based on the recipe data.

20. The testing method according to claim 11, wherein: Also includes: The test data, the analysis yield data, and the identification data are transmitted to the evaluation subsystem.

Images