Method for staged processing of chip manufacturing defective module, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a method for manufacturing a defective module by processing chips in a grading mode, electronic equipment and a medium, and the method comprises the steps: S1, obtaining a chip composition module set {B1, B2,..., Bn,..., BM}; step S2, acquiring B1n, B2n and B3n corresponding to each Bn; s3, determining a group Cn corresponding to the Bn according to the B1n, the B2n and the B3n corresponding to each Bn; s4, testability design testing is carried out on each Bn according to the group Cn corresponding to each Bn, a testing result corresponding to each Bn is determined, and the testing result comprises corresponding group information; and S5, determining a chip shielding target according to the test result corresponding to each Bn, and setting non-necessary operation logic in the shielding target to be in a shielding state. According to the invention, the efficiency and the accuracy of processing the chip manufacturing defective module are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method, electronic equipment and medium for hierarchically processing chip manufacturing defect modules. Background Art

[0002] During the chip manufacturing process, chips may contain manufacturing defects due to manufacturing factors. Larger chip areas result in lower chip yields. To ensure continued use of more chips, defective modules can be disabled and downgraded, thereby reducing chip defect rates and improving chip yields. However, existing methods for handling chip manufacturing defect modules are complex and prone to errors, resulting in low efficiency and poor accuracy. Therefore, improving the efficiency and accuracy of chip manufacturing defect handling modules has become a pressing technical issue. Summary of the Invention

[0003] The present invention aims to provide a method, electronic equipment and medium for hierarchically processing chip manufacturing defect modules, thereby improving the efficiency and accuracy of processing chip manufacturing defect modules.

[0004] According to a first aspect of the present invention, a method for hierarchically processing chip manufacturing defect modules is provided, comprising: Step S1: Get the chip module set {B1, B2, ..., B n ,...,B M}, B n The nth chip component module, where n ranges from 1 to N, and N is the total number of chip component modules contained in the chip. A chip component module includes both essential and non-essential logic. A chip component module is the smallest unit capable of shielding defects. Step S2: Get each B n Corresponding B1 n 、B2 n 、B3 n , B1 n B n Corresponding first-level module identification, B2 n B n Corresponding secondary module identification, B3 n B n Corresponding preset function identifiers, the secondary module includes at least one chip component module, the primary module includes at least one secondary module, and the chip component module is located in the secondary module, or is located in the primary module and not in the secondary module, or is located outside the primary module; Step S3: According to each B n Corresponding B1 n 、B2 n 、B3n Determine B n Corresponding group C n ; Step S4: According to each B n Corresponding group C n For each B n Conduct testability design test to determine each B n Corresponding test results, including corresponding group information; Step S5: According to each B n The corresponding test results determine the chip shielding target, and set the non-essential operation logic in the shielding target to a shielding state.

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0007] The present invention has significant advantages and beneficial effects compared to the prior art. Through the above-mentioned technical solution, the method, electronic device, and medium provided by the present invention for hierarchically processing chip manufacturing defect modules can achieve considerable technological advancement and practicality, and have wide industrial application value, and have at least the following beneficial effects: The present invention divides each chip component module into corresponding groups according to the functions corresponding to the different levels of the chip component module, performs testability design testing according to the group to which each chip component module belongs, and determines the chip shielding target based on the test results and corresponding group information corresponding to each chip component module. The present invention simplifies the process of processing chip manufacturing defect modules and improves the efficiency and accuracy of processing chip manufacturing defect modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flow chart of a method for hierarchically processing chip manufacturing defect modules provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The present invention provides a method for hierarchically processing chip manufacturing defect modules, such as Figure 1 Shown, including: Step S1: Get the chip module set {B1, B2, ..., B n ,...,B M}, B n The nth chip component module, where n ranges from 1 to N, and N is the total number of chip component modules contained in the chip. The chip component module includes necessary and unnecessary logic, and the chip component module is the smallest unit that can shield defects (disable).

[0012] Among them, the chip level is divided by disabling the chip component modules (blocks) with manufacturing defects in the chip, so that more chips can continue to be used.

[0013] Step S2: Get each B n Corresponding B1 n 、B2 n 、B3 n , B1 n B n Corresponding first-level module identification, B2 n B n Corresponding secondary module identification, B3 n B n Corresponding to the preset function identifier, the secondary module includes at least one chip component module, the primary module includes at least one secondary module, the chip component module is located in the secondary module, or is located in the primary module and not in the secondary module, or is located outside the primary module.

[0014] It should be noted that the secondary module must be located within the primary module. The submodules of the secondary module must include the chip component module, the submodules of the primary module must include the secondary module, and the submodules of the primary module may also include the chip component module. The chip component module may also be located outside the primary module. For example, the chip component module corresponds to the logic that the chip must run, or some chip component modules with preset functions. Specifically, the secondary module may be a computing unit. The preset function refers to a user-specified function, and the preset function may specifically be an image processing function.

[0015] Step S3: According to each B n Corresponding B1 n 、B2 n 、B3 n Determine B n Corresponding group C n .

[0016] Step S4: According to each B n Corresponding group C n For each B n Conduct testability design test to determine each B n The corresponding test results include the corresponding group information.

[0017] Step S5: According to each B n The corresponding test results determine the chip shielding target, and set the non-essential operation logic in the shielding target to a shielding state.

[0018] As an embodiment, step S2 includes: Step S21: If B n If it is outside the first level module and does not have a preset function, then B1 n 、B2 n 、B3 n All are set to empty.

[0019] It is understandable that B1 n 、B2 n 、B3 n Setting them all to empty specifically means that they can be set to an empty identifier, and the specific identifier symbol is not limited here.

[0020] Step S22: If B n Located outside the first-level module and has a preset function, B1 n 、B2 n Set to empty, and set B3 n Set as the preset function identifier.

[0021] Step S23: If B n If it is located in the first-level module but not in the second-level module and does not have the preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n 、B3 n Set to empty.

[0022] Step S24: If B n If it is located in the first-level module and not in the second-level module and has the preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to empty, and set B3n Set as the preset function identifier.

[0023] Step S25: If B n Located in the secondary module and does not have a preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to the corresponding secondary module identifier, and set B3 n Set to empty.

[0024] Step S26: If B n Located in the secondary module and has a preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to the corresponding secondary module identifier, and set B3 n Set as the preset function identifier.

[0025] It should be noted that, through steps S21 to S26, according to each B n The location and corresponding function are to determine each B n Corresponding B1 n 、B2 n 、B3 n information.

[0026] As an embodiment, the embodiment of the present invention is divided into 6 groups, specifically G0, G1, G2, G3, G4, and G5. Step S3 includes: Step S31: If B1 n 、B2 n 、B3 n If it is empty, set C n =G0.

[0027] Step S32: If B1 n 、B2 n Empty, B3 n If not empty, set C n =G3.

[0028] Step S33: If B1 n Not empty, B2 n 、B3 n If it is empty, set C n =G4.

[0029] Step S34: If B1 n Not empty, B2 n Empty, B3 n If not empty, set C n =G2.

[0030] Step S35: If B1 n、B2 n Not empty, B3 n If it is empty, set C n =G1.

[0031] Step S36: If B1 n 、B2 n 、B3 n If both are not empty, set C n =G5.

[0032] It should be noted that, through steps S31 to S36, it is possible to n Corresponding B1 n 、B2 n 、B3 n Information for each B n Divide into corresponding groups.

[0033] As an example, each B n Including multiple registers, the step S4 includes: Step S41: If B n Corresponding C n For G0, B n The corresponding clock signal is labeled G0 and is input to B n in all registers.

[0034] It should be noted that B n The corresponding clock signal is labeled G0 and is input to B n Of all the registers in B n Each register can be traced back to B n The corresponding clock signal marked G0 will also be B n All registers are divided into group G0.

[0035] Step S42: If B n Corresponding C n Gm, m ranges from 1 to 5, then judge B n Is there a register that must run the logic? If so, execute step S43; otherwise, execute step S44.

[0036] It should be noted that for B divided into Gm n , B n There may also be some registers corresponding to the logic that must be run, and these registers also need to be marked as the G0 group.

[0037] Step S43: B n The corresponding clock signal is labeled G0 and is input to B n The register that must run the logic is B nThe corresponding clock signal is labeled Gm and input to B n For registers that do not necessarily need to run the logic, execute step S45.

[0038] It should be noted that, through step S43, B n The registers that must run the logic are divided into G0 group, and B n Registers that are not required for logic execution are divided into the Gm group.

[0039] Step S44: B n The corresponding clock signal is labeled Gm and input to B n In all registers, execute step S45.

[0040] Step S45: Based on B n The registers with the same clock signal input mark generate scan chains, and design for testability (DFT) is performed based on the scan chains to determine B n The test results of the corresponding scan chains and the group labels of the clock signals corresponding to the scan chains.

[0041] It should be noted that if the scan test chain is abnormal, it means that the corresponding B n abnormal.

[0042] As an embodiment, in step S41 and step S43, the B n The corresponding clock signal is labeled G0 and includes: In B n The clock input interface is inserted into the marker buffer for marking G0. n The corresponding clock signal is labeled G0 after passing through the label buffer labeled G0.

[0043] In the steps S43 and S44, the n The corresponding clock signal mark Gm includes: In B n The clock input interface is inserted into the marker buffer for marking Gm, B n The corresponding clock signal is labeled Gm after passing through the label buffer labeled Gm.

[0044] It is understandable that if B n Corresponding C n For G0, only B n A marker buffer for marking G0 is inserted into the clock input interface of the n Corresponding C n is Gm and B n If there are registers that must run logic in B nThe clock input interface of the B is inserted into two marker buffers, one for marking G0 and one for marking Gm. n Corresponding C n is Gm and B n If there is no register that must run the logic, then only B n The clock input interface of the clock is inserted into a marker buffer for marking Gm.

[0045] As an implementation, step S5 includes: Step S51: If the scan chain corresponding to G0 is abnormal, the chip is determined to be unavailable and the process ends; otherwise, steps S52 and S53 are executed in parallel.

[0046] It can be understood that the scan chain corresponding to G0 refers to the scan chain corresponding to the clock signal group marked as G0.

[0047] Step S52: If there is a scan chain abnormality corresponding to G3, the chip component module with the G3 scan chain abnormality and the chip component module with a non-empty preset function identifier that interacts with the chip component module with the G3 scan chain abnormality in the secondary module are determined as chip shielding targets; otherwise, execute step S54.

[0048] It can be understood that the scan chain corresponding to G3 refers to the scan chain corresponding to the clock signal group marked as G3.

[0049] Step S53: If there is an abnormality in the scan chain corresponding to G4, and the number of first-level modules involved in the abnormality in the scan chain corresponding to G4 is greater than or equal to the first preset threshold, the chip is determined to be unavailable and the process ends. If there is an abnormality in the scan chain corresponding to G4, and the number of first-level modules involved in the abnormality in the scan chain corresponding to G4 is less than the first preset threshold, the first-level module involved in the abnormality in the scan chain corresponding to G4 is determined as a chip shielding target and step S54 is executed.

[0050] It can be understood that the scan chain corresponding to G4 refers to the scan chain corresponding to the clock signal group marked as G4.

[0051] Step S54: If there is a scan chain anomaly corresponding to G2, and the number of first-level modules involved in the scan chain anomaly corresponding to G2 is greater than or equal to the second preset threshold, then all chip component modules whose preset function identifiers are not empty are determined as chip shielding targets; if there is a scan chain anomaly corresponding to G2, and the number of first-level modules involved in the scan chain anomaly corresponding to G2 is less than the second preset threshold, then the first-level modules involved in the scan chain anomaly corresponding to G2 are determined as chip shielding targets.

[0052] It can be understood that the scan chain corresponding to G2 refers to the scan chain corresponding to the clock signal group marked as G2.

[0053] Step S55: If there is a scan chain anomaly corresponding to G1, and the number of secondary modules involved in the scan chain anomaly corresponding to G1 contained in the primary module exceeds a third preset threshold, the primary module is set as a chip shielding target, and the secondary modules involved in the scan chain anomaly corresponding to G1 in the primary module that is not a chip shielding target are set as chip shielding targets.

[0054] It can be understood that the scan chain corresponding to G1 refers to the scan chain corresponding to the clock signal group marked as G1.

[0055] Step S56: If there is a scan chain anomaly corresponding to G5, and the number of secondary modules involved in the scan chain anomaly corresponding to G5 contained in the primary module exceeds the third preset threshold, then the primary module is set as the chip shielding target, and the secondary modules involved in the scan chain anomaly corresponding to G5 in the primary module that is not the chip shielding target are set as the chip shielding target.

[0056] It can be understood that the scan chain corresponding to G5 refers to the scan chain corresponding to the clock signal group marked as G5.

[0057] Step S57: Set all chip shielding targets to shielding status.

[0058] It should be noted that setting the chip shielding target to the shielding state does not affect the use of the unshielded component modules in the chip.

[0059] As an embodiment, step S3 further includes: Step S10, obtain the shielding category possibility identifier {H1 k ,H2 k ,H3 k}, H1 k G k The corresponding first-level module shielding possibility indicator, H2 k G k Corresponding secondary module shielding possibility indicator, H3 k G k The corresponding preset function shielding possibility identifier includes R1 and R2. R1 indicates that there is shielding possibility, and R2 indicates that there is no shielding possibility. The value range of k is 1 to 5.

[0060] It should be noted that, according to the group division conditions, the shielding category possibility identifier corresponding to each group Gk can be determined, and the specific results are shown in the following table.

[0061]

[0062] Step S20: If B i Able to B j Transmit signal, and there is B i The corresponding group Gk corresponds to Hv k R1, B j The corresponding group Gk corresponds to Hv k For R2, the value range of v is 1 to 3, then in B i To B j The interface for transmitting signals is equipped with protection unit E ij and protection control unit F ij , E ij Setting B i To B j Safety value of input, F ij To control E ij Opening and closing, F ij Default Control E ij In the closed state, when B i Identified as a shielded target and B j When it is determined to be a non-shielded target, F ij Control E ij In the open state, B i To B j Enter a safe value. , B i and B j All are {B1,B2,...,B n ,...,B M}, the chip composition module, i≠j.

[0063] It should be noted that B i The corresponding group Gk corresponds to Hv k R1, B j The corresponding group Gk corresponds to Hv k R2 refers to B i The corresponding group Gk corresponds to H1 k R1 and B j The corresponding group Gk corresponds to H1 k R2, or B j The corresponding group Gk corresponds to Hv k R2 refers to B i The corresponding group Gk corresponds to H2 k R1 and B j The corresponding group Gk corresponds to H2 k R2, or B j The corresponding group Gk corresponds to Hv k R2 refers to Bi The corresponding group Gk corresponds to H3 k R1 and B j The corresponding group Gk corresponds to H3 k is R2. During the chip design phase, F ij Default Control E ij In the closed state. If step S5 determines that B i is a shielded target and B j For non-shielded targets, F ij Control E ij In the open state, B i To B j Enter a safe value so that i After being blocked B i To B j The input interface also outputs the correct value.

[0064] As an embodiment, in order to ensure that the protection logic is set comprehensively, the security set in step S6 may be further verified, and the step S20 may further include: Step S30: randomly setting a shielding target and the number of shielding targets for the chip.

[0065] The randomly set shielding targets may be one or more of a chip component module, a primary module, and a secondary module, and the number of shielding targets corresponding to each chip component module may be randomly set.

[0066] Step S40: Set the clock buffer output corresponding to each shielded target to an indeterminate state X for random verification. If the indeterminate state X is transmitted to a non-shielded target, a protection logic missing prompt is generated.

[0067] It should be noted that if the protection logic is fully configured, the indeterminate state X will not be transmitted to the non-shielded target. If it is transmitted to the non-shielded target, it means that the protection logic is missing and the configuration needs to be further checked.

[0068] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0069] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0070] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0071] The embodiment of the present invention divides each chip component module into corresponding groups according to the functions corresponding to the different levels of the chip component module, performs testability design testing according to the group to which each chip component module belongs, and determines the chip shielding target based on the test results and corresponding group information corresponding to each chip component module. The present invention simplifies the process of processing chip manufacturing defect modules and improves the efficiency and accuracy of processing chip manufacturing defect modules.

[0072] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for hierarchically processing chip manufacturing defect modules, characterized in that: include: Step S1: Get the chip module set {B1, B2, ..., B n ,...,B M }, B n The nth chip component module, where n ranges from 1 to N, and N is the total number of chip component modules contained in the chip. A chip component module includes both essential and non-essential logic. A chip component module is the smallest unit capable of shielding defects. Step S2: Get each B n Corresponding B1 n 、B2 n 、B3 n , B1 n B n Corresponding first-level module identification, B2 n B n Corresponding secondary module identification, B3 n B n Corresponding preset function identifiers, the secondary module includes at least one chip component module, the primary module includes at least one secondary module, and the chip component module is located in the secondary module, or is located in the primary module and not in the secondary module, or is located outside the primary module; Step S3: According to each B n Corresponding B1 n 、B2 n 、B3 n Determine B n Corresponding group C n ; Step S4: According to each B n Corresponding group C n For each B n Conduct testability design test to determine each B n Corresponding test results, including corresponding group information; Step S5: According to each B n The corresponding test results determine the chip shielding target, and set the non-essential operation logic in the shielding target to a shielding state.

2. The method according to claim 1, characterized in that The step S2 comprises: Step S21: If B n If it is outside the first level module and does not have a preset function, then B1 n 、B2 n 、B3 n All are set to empty; Step S22: If B n Located outside the first-level module and has a preset function, B1 n 、B2 n Set to empty, and set B3 n Set as preset function identifier; Step S23: If B n If it is located in the first-level module but not in the second-level module and does not have the preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n 、B3 n Set to empty; Step S24: If B n If it is located in the first-level module and not in the second-level module and has the preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to empty, and set B3 n Set as the preset function identifier; Step S25: If B n Located in the secondary module and does not have a preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to the corresponding secondary module identifier, and set B3 n Set to empty; Step S26: If B n Located in the secondary module and has a preset function, then B1 n Set to the corresponding first-level module identifier, and set B2 n Set to the corresponding secondary module identifier, and set B3 n Set as the preset function identifier.

3. The method according to claim 1, characterized in that The step S3 comprises: Step S31: If B1 n 、B2 n 、B3 n If it is empty, set C n =G0; Step S32: If B1 n 、B2 n Empty, B3 n If not empty, set C n =G3; Step S33: If B1 n Not empty, B2 n 、B3 n If it is empty, set C n =G4; Step S34: If B1 n Not empty, B2 n Empty, B3 n If not empty, set C n =G2; Step S35: If B1 n 、B2 n Not empty, B3 n If it is empty, set C n =G1; Step S36: If B1 n 、B2 n 、B3 n If both are not empty, set C n =G5.

4. The method according to claim 3, characterized in that The step S4 comprises: Step S41: If B n Corresponding C n For G0, B n The corresponding clock signal is labeled G0 and is input to B n In all registers; Step S42: If B n Corresponding C n For Gm, the value range of m is 1 to 5, then judge B n Is there a register that must run the logic? If so, go to step S43; otherwise, go to step S44; Step S43: B n The corresponding clock signal is labeled G0 and is input to B n The register that must run the logic is B n The corresponding clock signal is labeled Gm and input to B n For registers that do not necessarily need to run logic, execute step S45; Step S44: B n The corresponding clock signal is labeled Gm and input to B n In all registers, execute step S45; Step S45: Based on B n The registers with the same clock signal input mark generate scan chains, and testability design is tested based on the scan chains to determine B n The test results of the corresponding scan chains and the group labels of the clock signals corresponding to the scan chains.

5. The method according to claim 4, characterized in that In the steps S41 and S43, the n The corresponding clock signal is labeled G0 and includes: In B n The clock input interface is inserted into the marker buffer for marking G0, B n The corresponding clock signal is marked as G0 after passing through the marking buffer marked G0; In the steps S43 and S44, the n The corresponding clock signal mark Gm includes: In B n The clock input interface is inserted into the marker buffer for marking Gm, B n The corresponding clock signal is labeled Gm after passing through the label buffer labeled Gm.

6. The method according to claim 4, characterized in that The step S5 comprises: Step S51: If the scan chain corresponding to G0 is abnormal, the chip is determined to be unavailable and the process ends; otherwise, steps S52 and S53 are executed in parallel; Step S52: If there is an abnormality in the scan chain corresponding to G3, the chip component module with the abnormal G3 scan chain and the chip component modules whose preset function identifiers interact with the chip component module with the abnormal G3 scan chain in the secondary module are not empty are determined as chip shielding targets; otherwise, step S54 is executed; Step S53: If there is an abnormality in the scan chain corresponding to G4, and the number of primary modules involved in the abnormality in the scan chain corresponding to G4 is greater than or equal to the first preset threshold, the chip is determined to be unavailable and the process ends. If there is an abnormality in the scan chain corresponding to G4, and the number of primary modules involved in the abnormality in the scan chain corresponding to G4 is less than the first preset threshold, the primary modules involved in the abnormality in the scan chain corresponding to G4 are determined as chip shielding targets, and step S54 is executed. Step S54: If there is a scan chain anomaly corresponding to G2, and the number of primary modules involved in the scan chain anomaly corresponding to G2 is greater than or equal to a second preset threshold, all chip component modules whose preset function identifiers are not empty are determined as chip shielding targets; if there is a scan chain anomaly corresponding to G2, and the number of primary modules involved in the scan chain anomaly corresponding to G2 is less than the second preset threshold, the primary modules involved in the scan chain anomaly corresponding to G2 are determined as chip shielding targets; Step S55: If there is a scan chain abnormality corresponding to G1, and the number of secondary modules involved in the scan chain abnormality corresponding to G1 contained in the primary module exceeds a third preset threshold, then the primary module is set as a chip shielding target, and the secondary modules involved in the scan chain abnormality corresponding to G1 in the primary modules that are not chip shielding targets are set as chip shielding targets; Step S56: If there is a scan chain anomaly corresponding to G5, and the number of secondary modules involved in the scan chain anomaly corresponding to G5 in the primary module exceeds a third preset threshold, then the primary module is set as a chip shielding target, and the secondary modules involved in the scan chain anomaly corresponding to G5 in the primary modules that are not chip shielding targets are set as chip shielding targets; Step S57: Set all chip shielding targets to shielding status.

7. The method according to claim 1, characterized in that After step S3, the following steps are also included: Step S10, obtain the shielding category possibility identifier {H1 k ,H2 k ,H3 k }, H1 k G k The corresponding first-level module shielding possibility indicator, H2 k G k Corresponding secondary module shielding possibility indicator, H3 k G k The corresponding preset function shielding possibility flag includes R1 and R2. R1 indicates that shielding possibility exists, and R2 indicates that shielding possibility does not exist. The value range of k is 1 to 5; Step S20: If B i Able to B j Transmit signal, and there is B i The corresponding group Gk corresponds to Hv k R1, B j The corresponding group Gk corresponds to Hv k For R2, the value range of v is 1 to 3, then in B i To B j The interface for transmitting signals is equipped with protection unit E ij and protection control unit F ij , E ij Setting B i To B j Safety value of input, F ij To control E ij Opening and closing, F ij Default Control E ij In the closed state, when B i Identified as a shielded target and B j When it is determined to be a non-shielded target, F ij Control E ij In the open state, B i To B j Enter a safe value, B i and B j All are {B1,B2,...,B n ,...,B M }, the chip composition module, i≠j.

8. The method according to claim 1, characterized in that After step S20, the following steps are further included: Step S30: randomly setting a shielding target and the number of shielding targets for the chip; Step S40: Set the clock buffer output corresponding to each shielded target to an indeterminate state X for random verification. If the indeterminate state X is transmitted to a non-shielded target, a protection logic missing prompt is generated.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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