Semiconductor device and semiconductor device preparation method

Abstract

The invention relates to the field of semiconductors, particularly provides a semiconductor device and a preparation method of the semiconductor device, and aims to solve the problems that in the prior art, the anti-radiation reinforcement effect is limited, and a protected area is limited in an isolation area and cannot be expanded to a device area. To this end, the semiconductor device of the present application comprises: a substrate; the isolation region and the active region are located in the substrate; the active device is positioned in the active region and the surface of the active region; the first dielectric layer covers the isolation region, the active region and the active device on the surface of the active region; the first type of plug holes are located in the first dielectric layer, first sub-plug holes of the first type of plug holes are distributed above the isolation area in a suspension mode, and second sub-plug holes of the first type of plug holes are distributed above the active device in a suspension mode; the second type of plug holes penetrate through the first dielectric layer; the first filling material is filled in the first type of plug holes and the second type of plug holes, and the first filling material is an anti-radiation material; and the first metal layer is positioned on the second type of plug holes and is electrically connected with the first filling material in the second type of plug holes.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and specifically provides a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0002] In modern aerospace, aviation, space stations and other application scenarios, the support of various electronic system equipment is indispensable. In outer space, due to the presence of space charged particles, space neutral particles and a small amount of space rays, the semiconductor devices (including integrated circuits) in these electronic system equipment will inevitably experience radiation effects. This radiation effect is mainly a total dose radiation effect and a single particle effect. Among them, the total dose radiation effect is the destruction of silicon dioxide bonds in the thick oxide film (oxide layer formed by shallow trench process, or oxide layer formed by local oxidation) in the device by cosmic rays, resulting in a charge accumulation effect, which degrades the performance of the circuit or even impairs its function.

[0003] Existing technologies primarily use specific ion implantation at the interface between the thick oxide layer and the silicon substrate to increase the turn-on voltage of the product field region, thereby improving the radiation resistance of the core device. However, ion implantation for radiation resistance hardening requires additional process technology, which inevitably increases the difficulty of product manufacturing, thereby reducing product yield and / or increasing manufacturing costs. Furthermore, ion implantation for radiation resistance hardening can only improve device radiation resistance to a certain extent and cannot completely eliminate the impact of total radiation dose on the device.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor device (including integrated circuit) and a corresponding method for preparing the semiconductor device. Summary of the Invention

[0005] In order to overcome the above-mentioned defects, the present application is proposed to solve the technical problems that ion implantation has limited effect on the radiation resistance reinforcement of the isolation region and the protected area is limited to the isolation region and cannot be extended to the device region.

[0006] In a first aspect, the present application provides a semiconductor device, comprising:

[0007] substrate;

[0008] an isolation region in the substrate and an active region defined by the isolation region;

[0009] Active devices located in the active area and on the surface of the active area;

[0010] a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region;

[0011] A first type of plugged via is located in the first dielectric layer, wherein a first sub-plugged via of the first type is suspended and distributed above the isolation region, and a second sub-plugged via of the first type is suspended and distributed above the active device;

[0012] a second type of plugged via, wherein the second type of plugged via penetrates the first dielectric layer and exposes the electrode of the active device;

[0013] A first filling material is filled in the first type of plug holes and the second type of plug holes, wherein the first filling material is a radiation-resistant material;

[0014] The first metal layer is located on the second-type plug hole and is electrically connected to the first filling material in the second-type plug hole.

[0015] In a technical solution of the above semiconductor device, the depth of the first type of plug hole is 1 / 3 to 2 / 3 of the depth of the first dielectric layer.

[0016] In one technical solution of the above semiconductor device, the lateral size of the first type of plug hole is the same as the lateral size of the second type of plug hole;

[0017] The distances between adjacent plug holes are comparable, wherein the plug holes include the first type of plug holes or the second type of plug holes;

[0018] A plurality of the first-type plug holes are distributed in other areas of the first dielectric layer except the area occupied by the second-type plug holes.

[0019] In one technical solution of the above-mentioned semiconductor device, the active device is a field effect transistor, and the electrodes include a gate, a source, and a drain; or the active device is a triode, and the electrodes include a base, a collector, and an emitter; or the active device is a diode, and the electrodes include an anode and a cathode.

[0020] In a technical solution of the above semiconductor device, the isolation region is a shallow trench isolation region or a silicon local oxidation region.

[0021] In a technical solution of the above semiconductor device, the first filling material is tungsten.

[0022] In one technical solution of the above semiconductor device, the present invention further comprises:

[0023] a second dielectric layer located on the first dielectric layer;

[0024] A first type of through hole and a second type of through hole are located in the second dielectric layer, wherein the first type of through hole is suspended and distributed in other areas of the second dielectric layer except the area occupied by the second type of through hole, and the second type of through hole exposes the first metal layer; wherein the orthographic projection of the first type of plug hole on the substrate is equivalent to the orthographic projection of the first type of through hole on the substrate.

[0025] A second filling material and a third filling material are filled in the first type of through-holes and the second type of through-holes, respectively, wherein the third filling material is electrically connected to the first metal layer, and both the second filling material and the third filling material are radiation-resistant materials;

[0026] The second metal layer is located on the second-type through-hole and is electrically connected to the third filling material in the second-type through-hole.

[0027] In a technical solution of the above semiconductor device, the second filling material and the third filling material are both tungsten.

[0028] In a second aspect, the present application provides a method for preparing a semiconductor device, comprising:

[0029] forming an isolation region and an active region defined by the isolation region in a substrate;

[0030] forming active devices in the active area and on the surface of the active area;

[0031] forming a first dielectric layer to cover the isolation region, the active region, and the active devices on the surface of the active region;

[0032] forming a first type of plugged via located in the first dielectric layer, wherein a first sub-plugged via of the first type of plugged via is suspended and distributed above the isolation region, and a second sub-plugged via of the first type of plugged via is suspended and distributed above the active device;

[0033] forming a second type of plug hole, penetrating the first dielectric layer to expose the electrode of the active device;

[0034] forming a first filling material to fill the first type plug holes and the second type plug holes, wherein the first filling material is a radiation-resistant material;

[0035] A first metal layer is formed on the second-type plug hole and is electrically connected to the first filling material in the second-type plug hole.

[0036] The present application provides a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device specifically includes: a substrate; an isolation region located in the substrate and an active region defined by the isolation region; active devices located in the active region and on the surface of the active region; a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region; a first type of plugged via located in the first dielectric layer, with a first sub-plugged via of the first type suspended above the isolation region and a second sub-plugged via of the first type suspended above the active device; a second type of plugged via extending through the first dielectric layer to expose an electrode of the active device; a first filling material filled in the first and second types of plugged vias, wherein the first filling material is a radiation-resistant material; and a first metal layer located on the second type of plugged via and electrically connected to the first filling material in the second type of plugged via. The semiconductor device with the first type of plugged via proposed in the present application can improve the radiation resistance of the semiconductor device while maintaining the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The disclosure of this application will be more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the figures represent similar components, where:

[0038] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application;

[0039] Figure 2 A schematic diagram of a cross-sectional structure of another semiconductor device provided in an embodiment of the present application;

[0040] Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0041] Figures 4 to 10 This embodiment of the present application provides Figure 3 Schematic diagram of the cross-sectional structure of the semiconductor device formed in the key steps.

[0042] Reference Signs List :

[0043] 1: substrate; 2: shallow trench isolation region; 3: active region; 4: first dielectric layer; 5: first type of plugged via; 6: first sub-plugged via; 7: second type of plugged via; 8: first metal layer; 9: source; 10: drain; 11: gate; 12: gate oxide layer; 13: sidewall; 14: second sub-plugged via; 15: second dielectric layer; 16: first type of through hole; 17: second type of through hole; 18: second metal layer; 19: silicon local oxidation isolation region. DETAILED DESCRIPTION

[0044] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the scope of protection of the present application.

[0045] In the description of this application, for ease of description, spatially relative terms such as "below," "beneath," "under," "above," and "upper" may be used to describe the relationship between one element and another. When an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers.

[0046] It should also be understood that, for ease of description, the term "A and / or B" refers to all possible combinations of A and B, such as just A, just B, or A and B. The term "at least one of A or B" or "at least one of A and B" has a similar meaning to "A and / or B" and may include just A, just B, or A and B. The singular forms "a" and "the" may also include plural forms.

[0047] The specific implementation of the present application will be described in detail below with reference to the accompanying drawings.

[0048] Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present application. Figure 1 As shown, the semiconductor device includes a substrate 1; a plurality of shallow trench isolation regions (STIs) 2 located in the substrate 1 and an active region 3 defined by the shallow trench isolation regions 2; active devices located in the active region 3 and on the surface of the active region 3; a first dielectric layer 4 covering the shallow trench isolation regions 2, the active region 3 and the active devices on the surface of the active region 3; a first type of plugged via 5 located in the first dielectric layer 4, with a first sub-plugged via 6 of the first type of plugged via 5 suspended above the isolation region, and a second sub-plugged via 14 of the first type of plugged via 5 suspended above the active device; a second type of plugged via 7, the second type of plugged via 7 penetrating the first dielectric layer 4 to expose the electrode of the active device; a first filling material filled in the first type of plugged via 5 and the second type of plugged via 7, wherein the first filling material is a radiation-resistant material; and a first metal layer 8 located on the second type of plugged via 7 and electrically connected to the first filling material in the second type of plugged via 7.

[0049] The new plug hole structure with radiation resistance proposed in this application is different from the conventional contact hole layout. The solution of this application has two types of plug holes. The second type of plug hole 7 is the same as the existing process and is mainly used for connecting the electrodes of the active device. Specifically, when the active device is a MOS device, the bottom of this type of plug hole is mainly in contact with the source 9, drain 10 or gate 11 of the MOS device. The first sub-plug hole 6 and the second sub-plug hole 14 of the first type of plug hole 5 are new plug hole types proposed in this application. The bottom of this type of plug hole is located on the surface of the STI thick oxide layer and above the active device. Multiple first sub-plug holes 6 can be arranged above the STI, and the lateral width of the multiple first sub-plug holes 6 is greater than the lateral width of the STI. The first sub-plug holes 6 do not contact the STI and the active device, so they will not affect the device performance. The second sub-plug holes 14 are suspended and distributed above the active area except for the second type of plug hole 7 to protect the device area from radiation.

[0050] Preferably, the first filling material is tungsten. Since metal tungsten has excellent radiation resistance, filling tungsten in the first type of plug holes 5 on the surface of the STI thick oxide layer and the surface of the active device can achieve radiation protection for the STI oxide layer and the active device.

[0051] In this embodiment, the substrate 1 may be a semiconductor single-layer structure or a multi-layer structure made of a material containing silicon, such as silicon, silicon carbide, or a material not containing silicon, such as gallium arsenide, gallium nitride, indium phosphide, sapphire, etc.

[0052] In this embodiment, the thickness of the shallow trench isolation region 2 is 2000 angstroms to 4000 angstroms. The distance between adjacent shallow trench isolation regions 2 can be determined according to the size of the active region 3.

[0053] Optionally, the active device is a MOS device, which further includes a channel region located in the substrate 1 of the active region 3, wherein a source electrode 9 and a drain electrode 10 are located on both sides of the channel region; a gate oxide layer 12 between the gate electrode 11 and the channel region; and a sidewall spacer 13 surrounding the gate electrode 11. These are all related to the prior art and will not be described in detail here.

[0054] In a specific example, the thickness of the gate oxide layer 12 may be 10 angstroms to 200 angstroms, the thickness of the gate 11 may be 1000 angstroms to 3000 angstroms, and the thickness of the spacer 13 may be 200 angstroms to 1000 angstroms.

[0055] Those skilled in the art will appreciate that, although a metal oxide semiconductor field effect transistor is used as an example of an active device in this embodiment, the present application is not limited thereto. Alternatively, a triode may be used, with corresponding electrodes including a base, a collector, and an emitter; or a diode may be used, with corresponding electrodes including an anode and a cathode. In essence, the present invention is applicable to any application requiring radiation protection of the shallow trench isolation region 2 and active devices.

[0056] In this embodiment, the material of the first dielectric layer 4 may be an insulating material such as silicon dioxide.

[0057] In this embodiment, tungsten filling and chemical mechanical polishing require a sufficient process window. Therefore, the lateral dimensions of the first-type plugged vias 5 and the second-type plugged vias 7 are the same, and the distance between adjacent plugged vias is comparable. Multiple first-type plugged vias are distributed in areas of the first dielectric layer other than those occupied by the second-type plugged vias. Furthermore, adjacent plugged vias refer to two adjacent first-type plugged vias 5, or two adjacent second-type plugged vias 7.

[0058] In this embodiment, the depth of the first-type plug hole 5 is 1 / 3 to 2 / 3 of the depth of the first dielectric layer 4. On the one hand, a certain thickness of tungsten can be provided above the oxide layer of the isolation region to achieve radiation protection for the oxide layer of the isolation region. On the other hand, the first-type plug hole 5 is suspended in the first dielectric layer 4 and does not contact the port of the active device. In addition, the active area 3 is evenly covered, thereby providing radiation protection for the entire device.

[0059] In this embodiment, the material of the first metal layer 8 can be copper or aluminum. Furthermore, the semiconductor device of the present application also includes: a second dielectric layer 15 located on the first dielectric layer 4; a first type of through hole 16 and a second type of through hole 17 located in the second dielectric layer 15, wherein the first type of through hole 16 is suspended and distributed in the second dielectric layer except for the area occupied by the second type of through hole, and the second type of through hole 17 exposes the first metal layer 8; wherein, preferably, the orthographic projection of the first type of plug hole 5 on the substrate is equivalent to the orthographic projection of the first type of through hole 16 on the substrate; a second filling material and a third filling material, respectively filled in the first type of through hole 16 and the second type of through hole 17, wherein the third filling material is electrically connected to the first metal layer 8, and the second filling material and the third filling material are both radiation-resistant materials; a second metal layer 18, located on the second type of through hole 17, and electrically connected to the third filling material in the second type of through hole 17.

[0060] In this embodiment, the orthographic projection of the first type plug via on the substrate may overlap with the orthographic projection of the first type through hole on the substrate, and the orthographic projection of the first type through hole on the substrate may cover the orthographic projection of the first type plug via on the substrate.

[0061] In this embodiment, the depth of the first type through hole 16 is 1 / 3 to 2 / 3 of the depth of the second dielectric layer 15 .

[0062] Preferably, when the first metal is aluminum, both the second and third filler materials are tungsten. Furthermore, designs similar to the second-type vias are applicable to multi-layered back-end metal layers. The more layers, the better the overall radiation resistance. When the first metal is copper, the vias in existing processes are also copper. Copper has weak radiation resistance, so it is not recommended to have second-type vias in the Cu back-end metal layer.

[0063] The first type through-holes 16 are filled with radiation-resistant material, such as tungsten, so that the total thickness of tungsten above the isolation region is increased, thereby further enhancing the radiation resistance of the isolation region.

[0064] The above embodiment is based on the isolation region being STI as an example. However, those skilled in the art will appreciate that the present application is not limited thereto. The isolation region 3 in the semiconductor may also be a silicon local oxidation isolation region 19, such as Figure 2 In the semiconductor structure given in this embodiment, except for the isolation region, the other structures are the same as Figure 1 The structures in are the same.

[0065] Combine Figure 3 、 Figure 4-10 This application also provides a Figure 1 or Figure 2 Still taking the isolation region as STI as an example, specifically, the preparation method includes steps S101 to S107.

[0066] Step S101 : forming an isolation region and an active region defined by the isolation region in a substrate.

[0067] Figure 4 FIG. 1 shows a cross-sectional view after forming the shallow trench isolation region 2. In this embodiment, the trench of the shallow trench isolation region 2 can be formed by an etching process, and then a layer of silicon dioxide is formed on the inner wall of the trench. The silicon dioxide is then filled using chemical vapor deposition, and finally, excess silicon dioxide is removed from the surface to planarize the surface of the substrate 1, thereby forming the shallow trench isolation region 2.

[0068] Those skilled in the art will appreciate that the distance between adjacent isolation regions in the cross-sectional view is determined by the size of the active region 3 therebetween.

[0069] Step S102: forming active devices in the active area and on the surface of the active area.

[0070] Next, in a CMOS process, ion implantation is performed in the active region 3 to form a channel region of the MOS device and a gate 11 oxide layer on the channel region, the gate 11 (for example, polysilicon material), and sidewalls 13 on both sides. Then, using the sidewalls 13 as a mask, the source 9 and drain 10 of the MOS device are formed. The structure after formation is as follows: Figure 5 shown.

[0071] Step S103: forming a first dielectric layer to cover the isolation region, the active region and the active devices on the surface of the active region.

[0072] Figure 6 FIG2 shows a cross-sectional view after performing this step. In this embodiment, a first dielectric layer 4 is deposited on substrate 1, covering the isolation region and the MOS device. The deposition method may be chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, thermal reaction sub-atmospheric pressure chemical vapor deposition, etc., without limitation herein.

[0073] Step S104: forming a first type of plug hole in the first dielectric layer, wherein a first sub-plug hole of the first type of plug hole is suspended above the isolation region, and a second sub-plug hole of the first type of plug hole is suspended above the active device.

[0074] Figure 7 In this embodiment, a patterned mask is formed on the first dielectric layer 4 by photolithography, and then the first sub-via 6 and the second sub-via 14 of the first type of plug hole 5 are formed by etching.

[0075] Step S105: forming a second type of plug hole, penetrating the first dielectric layer, and exposing the electrode of the active device.

[0076] Figure 8 In this embodiment, a patterned mask is formed on the first dielectric layer 4 by photolithography, and then the second type plug hole 7 is formed by etching.

[0077] In one embodiment, to ensure a sufficient process window, the first type plug holes 5 and the second type plug holes 7 have the same lateral dimensions, and the distance between adjacent plug holes is comparable. In the first dielectric layer 4, the first type plug holes 5 are evenly distributed in the area outside the second type plug holes 7.

[0078] Step S106 : forming a first filling material to fill the first type of plug holes and the second type of plug holes, wherein the first filling material is a radiation-resistant material.

[0079] Figure 9 FIG. 3 is a cross-sectional view after performing this step. In this embodiment, the first filling material is a radiation-resistant material, such as tungsten.

[0080] In this embodiment, when the first filling material is tungsten, preferably, 100 to 200 angstroms of Ti and 200 to 500 angstroms of TiN are first deposited by physical vapor deposition. The Ti / TiN layer can prevent tungsten from reacting with silicon and facilitate the adhesion of the subsequent tungsten layer. Then, rapid annealing is used to heat it to 600 to 700 degrees Celsius to repair the crystal damage on the silicon surface caused by etching, and at the same time, the Ti / TiN layer is alloyed with silicon. Then, a tungsten layer is deposited by chemical vapor deposition to fill the first type of plug hole 5 and the second type of plug hole 7.

[0081] Step S107 : forming a first metal layer on the second type plug hole, electrically connected to the first filling material in the second type plug hole.

[0082] Figure 10 The figure shows a cross-sectional view after this step. The first metal layer 8 only needs to be connected to the second type plug hole 7, and the first type plug hole 5 does not need to be connected to the metal layer. For example, in a CMOS process, the metal layer can be copper or aluminum.

[0083] At this point, the most basic structure of this application has been completed.

[0084] Further, if Figure 1 As shown, the preparation method of the present application also includes:

[0085] forming a second dielectric layer 15 on the first dielectric layer 4;

[0086] A first type of through hole 16 and a second type of through hole 17 are formed in the second dielectric layer 15, wherein the first type of through hole 16 is suspended and distributed in other areas of the second dielectric layer except for the area occupied by the second type of through hole, and the second type of through hole 17 exposes the first metal layer 8; wherein the orthographic projection of the first type of plug hole on the substrate is equivalent to the orthographic projection of the first type of through hole on the substrate;

[0087] forming a second filling material and a third filling material to fill the first type through-hole 16 and the second type through-hole 17 respectively, wherein the third filling material is electrically connected to the first metal layer 8, and both the second filling material and the third filling material are radiation-resistant materials;

[0088] A second metal layer 18 is formed on the second type through-hole 17 and is electrically connected to the third filling material in the second type through-hole 17 .

[0089] The number of back-end metal layers depends on the needs of the front-end device and can be one or more layers. The figure uses two layers as an example.

[0090] When the metal layer adopts the aluminum wire process, that is, when the metal layer is made of aluminum, the second filling material and the third filling material both use tungsten, which is a radiation-resistant material. This means that if the second filling material and the third filling material are formed at the same time, the dual effects of satisfying the radiation-resistant function and simplifying the process can be achieved.

[0091] Of course, the third filling material and the second filling material may also be formed separately.

[0092] It should be noted that in CMOS processes, when the metal layer uses a copper wire process, a dual damascene structure is generally adopted. That is, the metal layer and the second filler material are both made of copper. If the third filler material is formed simultaneously with the second filler material, it is also copper. Because copper has weak radiation resistance, the radiation resistance function is mainly provided by the first filler material in the first-type plug hole. Therefore, to enhance the radiation resistance, the third filler material can be a radiation-resistant material, but it needs to be formed separately from the second filler material.

[0093] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effect of the present application, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0094] Thus far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is readily understood by those skilled in the art that the scope of protection of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present application.

Claims

1. A semiconductor device comprising: substrate; an isolation region in the substrate and an active region defined by the isolation region; Active devices located in the active area and on the surface of the active area; a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region; A first type of plugged via is located in the first dielectric layer, wherein a first sub-plugged via of the first type is suspended and distributed above the isolation region, and a second sub-plugged via of the first type is suspended and distributed above the active device; a second type of plugged via, wherein the second type of plugged via penetrates the first dielectric layer and exposes the electrode of the active device; A first filling material is filled in the first type of plug holes and the second type of plug holes, wherein the first filling material is a radiation-resistant material; The first metal layer is located on the second-type plug hole and is electrically connected to the first filling material in the second-type plug hole.

2. A semiconductor device according to claim 1, characterized in that The depth of the first type plug hole is 1 / 3 to 2 / 3 of the depth of the first dielectric layer.

3. The semiconductor device according to claim 2, wherein: The transverse dimension of the first type of plug hole is the same as the transverse dimension of the second type of plug hole; The distances between adjacent plug holes are comparable, wherein the plug holes include the first type of plug holes or the second type of plug holes; A plurality of the first-type plug holes are distributed in other areas of the first dielectric layer except the area occupied by the second-type plug holes.

4. The semiconductor device according to claim 1, wherein The active device is a field effect transistor, and the electrodes include a gate, a source, and a drain; or the active device is a triode, and the electrodes include a base, a collector, and an emitter; or the active device is a diode, and the electrodes include an anode and a cathode.

5. The semiconductor device according to claim 1, wherein The isolation region is a shallow trench isolation region or a silicon local oxidation region. The semiconductor device according to claim 1 , wherein: The first filling material is tungsten.

7. The semiconductor device according to claim 1, wherein Also includes: a second dielectric layer located on the first dielectric layer; a first type of through-hole and a second type of through-hole located in the second dielectric layer, wherein the first type of through-hole is suspended and distributed in an area other than an area occupied by the second type of through-hole in the second dielectric layer, and the second type of through-hole exposes the first metal layer; wherein the orthographic projection of the first type of plugged via on the substrate is equal to the orthographic projection of the first type of through-hole on the substrate; A second filling material and a third filling material are filled in the first type of through-holes and the second type of through-holes, respectively, wherein the third filling material is electrically connected to the first metal layer, and both the second filling material and the third filling material are radiation-resistant materials; The second metal layer is located on the second-type through-hole and is electrically connected to the third filling material in the second-type through-hole.

8. The semiconductor device according to claim 7, wherein: The second filling material and the third filling material are both tungsten.

9. A method for preparing a semiconductor device, comprising: forming an isolation region and an active region defined by the isolation region in a substrate; forming active devices in the active area and on the surface of the active area; forming a first dielectric layer to cover the isolation region, the active region, and the active devices on the surface of the active region; forming a first type of plugged via located in the first dielectric layer, wherein a first sub-plugged via of the first type of plugged via is suspended and distributed above the isolation region, and a second sub-plugged via of the first type of plugged via is suspended and distributed above the active device; forming a second type of plug hole, penetrating the first dielectric layer to expose the electrode of the active device; forming a first filling material to fill the first type plug holes and the second type plug holes, wherein the first filling material is a radiation-resistant material; A first metal layer is formed on the second-type plug hole and is electrically connected to the first filling material in the second-type plug hole.

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