Control method of uninterruptible power supply, uninterruptible power supply, and storage medium

Abstract

The application relates to the new energy technology field, in particular to a control method of an uninterruptible power supply (UPS), the UPS and a storage medium. The control method of the UPS comprises the following steps: when a power grid is in a normal state and a battery of the UPS is in a full power state, the UPS is controlled to enter a full bypass working mode; in the full bypass working mode, the driving signals of a high-frequency upper tube Q1, a high-frequency lower tube Q2 and a power-frequency upper tube Q3 are turned off, and the power-frequency lower tube Q4 is controlled to be turned on for a preset time length in each power-frequency cycle. According to the method, the first waveform cycle of the UPS switching cannot be caused to lose waves due to insufficient driving capacity of the power-frequency upper tube, and the rapid switching of the UPS can be realized.

Description

Technical Field

[0001] This application relates to the field of new energy technology, and in particular to a control method for an uninterruptible power supply, an uninterruptible power supply, and a storage medium. Background Technology

[0002] Currently, most portable energy storage products with inverters adopt a standby uninterruptible power supply (UPS) topology. Among them, UPS switching time is an important performance indicator of standby UPS.

[0003] Due to cost considerations, the drive circuits of the IGBT transistors in the full-bridge inverter of UPS systems mostly adopt a bootstrap drive scheme. Simultaneously, unipolar modulation is also commonly used in the inverter waveform generation method. When the grid is connected and the battery is fully charged, the full-bridge inverter drive shuts down to stop charging. If the grid connection drops at this time, the inverter drive switches from its off state to off-grid operation mode to maintain load output. However, the bootstrap circuit requires a bootstrap process (i.e., a continuous drive voltage on the power frequency upper transistor) when switching the inverter drive from off to normal waveform generation. This bootstrap process requires the power frequency lower transistor to conduct to charge the bootstrap capacitor. In unipolar modulation, the power frequency upper and lower transistors are alternately and complementaryly turned on at the power frequency. When the grid disconnection phase is in the negative half-cycle, the first cycle after UPS switching requires the power frequency upper transistor to conduct and the power frequency lower transistor to turn off (to maintain a stable phase). Since the bootstrap capacitor has not yet charged, the drive signal is insufficient to drive the power frequency upper transistor to conduct, resulting in the waveform of the current cycle not being output, thus increasing the UPS switching time.

[0004] Therefore, there is an urgent need for a control method for uninterruptible power supplies to enable UPS to quickly switch from grid mode to battery mode under any circumstances. Summary of the Invention

[0005] The embodiments of this application aim to provide a control method for an uninterruptible power supply, an uninterruptible power supply, and a storage medium to solve the problem in the prior art that the switching time of a UPS is too long when the phase of the power grid disconnection is in the negative half-cycle.

[0006] To address the aforementioned technical problems, this application provides the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a control method for an uninterruptible power supply (UPS), wherein the UPS includes an inverter, the inverter includes a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power-frequency upper transistor Q3, and a power-frequency lower transistor Q4, and the method includes:

[0008] When the power grid is in a normal state and the uninterruptible power supply (UPS) battery is fully charged, control the UPS to enter a full bypass working mode.

[0009] In the fully bypassed operating mode, the drive signals of the high-frequency upper transistor Q1, the high-frequency lower transistor Q2, and the power frequency upper transistor Q3 are turned off, and the power frequency lower transistor Q4 is controlled to conduct for a preset duration in each power frequency cycle.

[0010] Optionally, the preset duration for controlling the conduction of transistor Q4 at the power frequency in each power frequency cycle includes:

[0011] The preset conduction time of transistor Q4 is controlled during the positive half-cycle phase interval of each power frequency cycle.

[0012] Optionally, the preset duration for controlling the conduction of transistor Q4 during the positive half-cycle phase interval of each power frequency cycle includes:

[0013] The grid phase is detected, and it is determined whether the grid phase and the preset turn-on phase meet the preset error. If yes, the power frequency lower tube Q4 is turned on for a preset time and then turned off. If no, the power frequency lower tube Q4 is turned off. The preset turn-on phase is in the positive half-cycle phase interval, and when the power frequency lower tube Q4 is turned on for a preset time based on the preset turn-on phase, the grid phase is still in the positive half-cycle phase interval.

[0014] Optionally, the preset activation phase is around 90°.

[0015] Optionally, the uninterruptible power supply further includes a drive circuit, which includes a bootstrap capacitor and a bootstrap resistor, and the preset duration is determined based on the charging parameters of the bootstrap capacitor and the bootstrap resistor.

[0016] Optionally, the preset duration is less than half of the power frequency cycle.

[0017] Optionally, the inverter is a bidirectional inverter, and the method further includes:

[0018] When the power grid is in an abnormal state or the battery of the uninterruptible power supply is not fully charged, the uninterruptible power supply is controlled to enter the normal working mode.

[0019] Perform the following steps in the normal operating mode:

[0020] During the positive half-cycle phase interval of each power frequency cycle, the high-frequency upper transistor Q1 and the high-frequency lower transistor Q2 are controlled to conduct complementaryly based on the pulse width modulation signal, while the power frequency upper transistor Q3 is continuously turned off.

[0021] During the negative half-cycle phase interval of each power frequency cycle, the high-frequency upper transistor Q1 and the high-frequency lower transistor Q2 are complementaryly turned on based on the pulse width modulation signal, the power frequency upper transistor Q3 is continuously turned on, and the power frequency lower transistor Q4 is continuously turned off.

[0022] Secondly, embodiments of this application provide an uninterruptible power supply (UPS), which includes an inverter and a controller. The inverter includes a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power frequency upper transistor Q3, and a power frequency lower transistor Q4. The controller includes at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the method described above.

[0023] Optionally, the uninterruptible power supply further includes a driving circuit, which includes a driving IC, a bootstrap capacitor Cb, a bootstrap resistor Rb, and a bootstrap diode Db. The driving IC includes Vi, Vcc, Vb, Vo, and Vs terminals. The Vcc terminal is connected to the Vb terminal after passing through the bootstrap resistor Rb and the bootstrap diode Db. The bootstrap capacitor Cb is connected between the Vb terminal and the Vs terminal. The Vs terminal is connected to the N-terminal of the inverter AC output and the emitter of the mains frequency transistor Q3. The Vi terminal is connected to the controller, and the Vo terminal is connected to the gate of the mains frequency transistor Q3.

[0024] Thirdly, embodiments of this application provide a computer storage medium storing instructions or programs that, when executed by at least one processor, cause the at least one processor to perform any of the methods described above.

[0025] The beneficial effects of this application's embodiments are as follows: Unlike existing technologies, this application provides a control method for an uninterruptible power supply (UPS). The UPS includes an inverter, comprising a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power frequency upper transistor Q3, and a power frequency lower transistor Q4. When the power grid is in a normal state and the UPS battery is fully charged, the UPS is controlled to enter a full bypass operating mode. In this mode, the drive signals for the high-frequency upper transistor Q1, high-frequency lower transistor Q2, and power frequency upper transistor Q3 are turned off, and the power frequency lower transistor Q4 is controlled to conduct for a preset duration in each power frequency cycle. This method changes the original method of turning off all inverter transistor drives in the full bypass operating mode to maintaining the power frequency lower transistor drive, and controls the power frequency lower transistor to operate with a very small duty cycle in each power frequency cycle. This ensures that the bootstrap capacitor of the power frequency upper transistor is always in an energy storage state. When the phase of the power grid disconnection is in the negative half-cycle, the first waveform cycle of the UPS switching will not suffer from waveform loss due to insufficient drive capability of the power frequency upper transistor, thus enabling rapid UPS switching. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0027] Figure 1 This is a schematic diagram of the structure of an uninterruptible power supply provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the topology of a standby UPS provided in an embodiment of this application;

[0029] Figure 3 yes Figure 2 Schematic diagram of the drive circuit for the medium-frequency power transistor Q3;

[0030] Figure 4 yes Figure 2 A schematic diagram of the drive circuit for the medium-frequency upper transistor Q3 and the power-frequency lower transistor Q4;

[0031] Figure 5 This is a schematic diagram of the structure of a controller provided in an embodiment of this application;

[0032] Figure 6 This is a flowchart of a control method for an uninterruptible power supply provided in an embodiment of this application;

[0033] Figure 7 This is a flowchart of another uninterruptible power supply control method provided in the embodiments of this application;

[0034] Figure 8 This is a comparative schematic diagram of the grid voltage waveform and the conduction waveform of transistor Q4 at power frequency provided in the embodiments of this application;

[0035] Figure 9a This is a schematic diagram of the voltage output waveform after the power grid is disconnected and the uninterruptible power supply is controlled using existing technology, as provided in the embodiments of this application.

[0036] Figure 9b This is a schematic diagram of the voltage output waveform after the power grid is disconnected and the uninterruptible power supply is controlled by the solution of this application according to an embodiment of the present application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0039] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0040] Please refer to Figure 1 , Figure 1 The modular structure of a standby UPS is shown. For example... Figure 1 As shown, the standby UPS 100 includes a mains input terminal 10, a bidirectional inverter 20, a battery 30, a controller 40, a first switch 50, a second switch 60, and a load output terminal 70. The mains input terminal 10 is connected to the first switch 50. The bidirectional inverter 20 is connected to the battery 30, the first switch 50, and the second switch 60. The second switch 60 is then connected to the load output terminal 70. The controller 40 establishes a communication connection with the bidirectional inverter 20, the battery 30, the first switch 50, and the second switch 60.

[0041] After the standby UPS 100 is connected to the power grid, the controller 40 controls the first switch 50 and the second switch 60 to close and controls the bidirectional inverter 20 to enter rectification mode. The power grid outputs to the load output terminal 70 via the first switch 50 and the second switch 60, and simultaneously charges the battery 30 through the bidirectional inverter 20. Once the battery 30 is fully charged, if the power grid is in a normal state, the standby UPS 100 enters a full bypass operating mode. In existing technology, after the standby UPS 100 enters the full bypass operating mode, all inverter transistors of the bidirectional inverter 20 are turned off, and the power grid is directly connected to the load output terminal 70. When the power grid is disconnected, a power grid disconnection is detected, the controller 40 turns on all inverter transistors of the bidirectional inverter 20, and controls the first switch 50 to open and the second switch 60 to close, so that the electrical energy from the battery 30 is inverted by the bidirectional inverter 20 and output to the load output terminal 70.

[0042] Please refer to Figure 2 , Figure 2 A topology diagram of an energy storage system 200 is shown. The energy storage system 200 includes a standby UPS 100, a load, and a power grid. The standby UPS 100 includes a bidirectional inverter 20 and a filter 80. The bidirectional inverter 20 consists of four insulated-gate bipolar transistors (IGBTs). Figure 2These four IGBTs are labeled as high-frequency upper transistor Q1, high-frequency lower transistor Q2, power frequency upper transistor Q3, and power frequency lower transistor Q4. The collectors of high-frequency upper transistor Q1 and power frequency upper transistor Q3 are connected to the positive terminal of the DC bus, while the drains of high-frequency lower transistor Q2 and power frequency lower transistor Q4 are connected to the negative terminal of the DC bus. The emitters of high-frequency upper transistor Q1 and power frequency upper transistor Q3 are connected to the collectors of high-frequency lower transistor Q2 and power frequency lower transistor Q4, respectively. Furthermore, the emitter of high-frequency upper transistor Q1 and the collector of high-frequency lower transistor Q2 are also connected to the low-level (L) stage of the inverter's AC output, and the emitter of power frequency upper transistor Q3 and the collector of power frequency lower transistor Q4 are also connected to the neutral (N) stage of the inverter's AC output. The filter 80 consists of an inductor and a capacitor.

[0043] Please refer to Figure 3 , Figure 3 yes Figure 2 A schematic diagram of the driving circuit for the high-frequency MOSFET Q3. This driving circuit includes a driver IC, a bootstrap capacitor Cb, a bootstrap resistor Rb, and a bootstrap diode Db. The driver IC includes Vi, Vcc, Vb, Vo, and Vs terminals. The Vcc terminal is connected to the Vb terminal via the bootstrap resistor Rb and the bootstrap diode Db. The bootstrap capacitor Cb connects to the Vb and Vs terminals. The Vs terminal is connected to the N-terminal of the inverter AC output and the emitter of the high-frequency MOSFET Q3. The Vi terminal is connected to the controller 40 to receive the drive control signal from the controller 40 for the high-frequency MOSFET Q3. The Vo terminal is connected to the gate of the high-frequency MOSFET Q3 and outputs a voltage signal to the gate of the high-frequency MOSFET Q3 after receiving the drive control signal at the Vi terminal. The voltage at the Vcc terminal can be 15V~20V. When the low-frequency MOSFET Q4 is turned on, it can form... Figure 3 The loop shown by the dashed line charges the bootstrap capacitor Cb. When the transistor Q4 is turned off at power frequency, the voltage of the bootstrap capacitor Cb will not change abruptly, thus maintaining the voltage difference between the Vcc and Vs terminals of the driver IC at approximately 15V. Therefore, although the voltage at the Vs terminal fluctuates with AC changes, after bootstrap charging, the driver IC can meet the driving capability required for the IGBT to turn on at the gate voltage Vge (typically around 15V).

[0044] For the lower-frequency transistor Q4, since its emitter is grounded, it only requires a constant voltage input to its gate to be driven. In one embodiment, a dual-channel driver IC can be used to simultaneously drive the upper-frequency transistor Q3 and the lower-frequency transistor Q4. Figure 4 As shown, Figure 2A schematic diagram of the drive circuit for the power frequency upper transistor Q3 and the power frequency lower transistor Q4. This drive circuit includes a dual-channel driver IC, a bootstrap capacitor C1, a bootstrap resistor Rb, a bootstrap diode Db, and a filter capacitor C2. The dual-channel driver IC includes terminals Vih, Vil, Vi, Vcc, Vbh, Vbl, Voh, Vol, Vsh, and Vsl. Among these, Vih, Vbh, Vsh, and Voh terminals correspond to the power frequency upper transistor Q3, and their connection method is similar to... Figure 3 The Vi, Vb, Vs, and Vo terminals are the same and will not be described again here. The Vil, Vbl, Vsl, and Vol terminals correspond to the mains frequency transistor Q4. Their connection method is as follows: the Vcc terminal is directly connected to the Vbl terminal, a filter capacitor C2 is connected between the Vbl terminal and the Vsl terminal (grounded), the Vsl terminal is also connected to the emitter of the mains frequency transistor Q4, the Vil terminal is connected to the controller 40 to receive the drive control signal of the controller 40 to the mains frequency transistor Q4, and the Vol terminal is connected to the gate of the mains frequency transistor Q4 to output a voltage signal to the gate of the mains frequency transistor Q4 after receiving the drive control signal at the Vil terminal.

[0045] Please refer to Figure 5 , Figure 5 This illustrates one structure of the controller 40. For example... Figure 5 As shown, the controller 40 includes at least one processor 41 and a memory 42. The memory 42 can be built into the controller 40 or external to the controller 40. The memory 42 can also be a remotely configured memory connected to the controller 40 via a network.

[0046] Memory 42, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 42 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal, etc. Furthermore, memory 42 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 42 may optionally include memory remotely located relative to processor 41, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0047] The processor 41 performs various functions of the terminal and processes data by running or executing software programs and / or modules stored in the memory 42 and calling data stored in the memory 42, thereby performing overall monitoring of the terminal, such as implementing the uninterruptible power supply control method described in any embodiment of this application.

[0048] Processor 41 can be one or more. Figure 5 The example provided is a processor 41. Processor 41 and memory 42 can be connected via a bus or other means. Processor 41 may include a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a controller, a field-programmable gate array (FPGA) device, etc. Processor 41 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0049] Please refer to Figure 6 , Figure 6 A flowchart of a control method for an uninterruptible power supply (UPS) is shown. The UPS includes an inverter and a controller. The inverter includes a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power-frequency upper transistor Q3, and a power-frequency lower transistor Q4. In some embodiments, the UPS can be controlled via, for example... Figures 1-5 The structure shown is implemented in detail in the above embodiments, and will not be repeated here.

[0050] like Figure 6 As shown, the control method for this uninterruptible power supply includes:

[0051] Step S601: When the power grid is in a normal state and the uninterruptible power supply (UPS) battery is fully charged, control the UPS to enter a full bypass working mode.

[0052] In one embodiment, the uninterruptible power supply also detects the voltage, frequency, and waveform of the power grid to determine whether the power grid is in a normal state. For example, zero-crossing detection can be used to determine whether the power grid exists.

[0053] Step S602: In the fully bypass working mode, turn off the drive signals of high-frequency upper tube Q1, high-frequency lower tube Q2 and power frequency upper tube Q3, and control the power frequency lower tube Q4 to conduct for a preset duration in each power frequency cycle.

[0054] When the inverter is operating normally, the power frequency transistor Q4 is continuously turned on during the positive half-cycle phase interval. In one embodiment, when the uninterruptible power supply is in full bypass mode, the power frequency transistor Q4 is controlled to conduct for a preset duration during the positive half-cycle phase interval (i.e., 0°~180°) of each power frequency cycle. For example, the power frequency transistor Q4 is controlled to conduct for a preset duration near a preset turn-on phase of each power frequency cycle before being turned off. This preset turn-on phase is within the positive half-cycle phase interval, and when the power frequency transistor Q4 conducts for the preset turn-on phase for the preset duration, the grid phase is still within the positive half-cycle phase interval. Considering that there may be deviations in the detected grid phase, the preset turn-on phase can be set to a phase value around 90° to reduce the possibility of reverse conduction of the power frequency transistor Q4.

[0055] In other embodiments, the on-time of the lower frequency transistor Q4 can be controlled for a preset duration during the negative half-cycle phase interval (i.e., 180°~360°) of each power frequency cycle. It should be noted that turning on the lower frequency transistor Q4 during the negative half-cycle may cause the DC bus capacitor to overcharge. This is because, during the negative half-cycle, the N-stage potential of the AC output is higher than the L-stage potential, and current flows from the L-stage to the N-stage. If the lower frequency transistor Q4 is turned on during this stage, it will charge the inductor in filter 80. When Q4 is turned off again, the energy in the inductor will be released to the DC bus terminal through the body diode of the upper frequency transistor Q3, potentially causing the DC bus capacitor to overcharge. To solve this problem, the duty cycle of the lower frequency transistor Q4 during the negative half-cycle can be limited, or a clamping diode or a TVS (Transient Voltage Suppressor) can be added to force energy discharge when the BUS voltage exceeds a threshold.

[0056] In one embodiment, the conduction duration (i.e., the preset duration) can be determined based on the charging parameters of the bootstrap capacitor and bootstrap resistor, but should be less than half of the power frequency cycle (e.g., when the rated frequency is 50Hz, half of the power frequency cycle is 10ms). Generally, the bootstrap capacitor and bootstrap resistor are small, and charging can usually be completed in microseconds. Therefore, a preset duration of 1ms to 2ms is more than sufficient. It is understood that during other periods of the power frequency cycle, the power frequency transistor Q4 is in the off state. Figure 8 As shown, at power frequency, transistor Q4 only occupies a very small duty cycle for conduction near the 90° phase of each power frequency cycle.

[0057] Please refer to Figure 7 , Figure 7 A flowchart of another uninterruptible power supply control method is shown, which includes the following steps:

[0058] Step S701: Determine whether the power grid is in a normal state. If yes, proceed to step S702; otherwise, proceed to step S708.

[0059] Step S702: Determine whether the battery of the uninterruptible power supply is fully charged. If yes, proceed to step S703; otherwise, proceed to step S708.

[0060] Step S703: Turn off the drive signals of high-frequency upper transistor Q1, high-frequency lower transistor Q2 and power frequency upper transistor Q3.

[0061] Step S704: Detect the grid phase.

[0062] Step S705: Determine whether the grid phase and the preset turn-on phase meet the preset error. If yes, proceed to step S706; otherwise, proceed to step S707.

[0063] For example, when the preset activation phase is 90° and the preset error is 1°, the grid phase is within the range of [89°, 91°] and meets the preset error.

[0064] Step S706: Control the power frequency tube Q4 to conduct for a preset time and then turn it off.

[0065] Step S707: Control the power frequency down transistor Q4 to turn off.

[0066] Step S708: Control the uninterruptible power supply to enter normal operating mode.

[0067] In one embodiment, the uninterruptible power supply (UPS) includes a bidirectional inverter. Under normal operating conditions, the bidirectional inverter can operate in either rectification or inversion mode depending on the grid status and battery charging status. Specifically, when the grid is in an abnormal state, the bidirectional inverter operates in inversion mode; when the grid is in a normal state and the UPS battery is not fully charged, the bidirectional inverter operates in rectification mode. Regardless of whether the bidirectional inverter is in inversion or rectification mode, the UPS performs the following steps under normal operating conditions: controlling the high-frequency upper transistor Q1 and the high-frequency lower transistor Q2 to conduct complementaryly based on a pulse width modulation signal; during the positive half-cycle phase interval of each power frequency cycle, the power frequency upper transistor Q3 remains off, and the power frequency lower transistor Q4 remains on; during the negative half-cycle phase interval of each power frequency cycle, the power frequency upper transistor Q3 remains on, and the power frequency lower transistor Q4 remains off.

[0068] Please refer to Figure 9a and Figure 9b , Figure 9a The diagram shows the voltage output waveform after an uninterruptible power supply (UPS) is controlled using existing technology following a power grid outage. Figure 9b The diagram shows a schematic of the voltage output waveform after the uninterruptible power supply (UPS) is controlled using the scheme described in this application following a power grid outage. Figure 9a and Figure 9bAs can be seen, when the power grid goes offline during the negative half-cycle, in order to maintain the AC voltage phase change from abruptly, the first cycle after UPS switching should start from the negative half-cycle (i.e., the upper power frequency transistor is turned on). With existing technologies, the bootstrap capacitor is not charged, resulting in insufficient power frequency upper transistor conduction and loss of the negative half-cycle waveform. However, with the solution proposed in this application, because the lower power frequency transistor is turned on for a very small duty cycle in each power frequency cycle, the bootstrap capacitor is always in an energy storage state, allowing for immediate normal output during the negative half-cycle, significantly shortening the UPS switching time.

[0069] This application also provides a computer storage medium storing instructions or programs that are executed by one or more processors, enabling the one or more processors to perform the uninterruptible power supply control method described in any of the above method embodiments.

[0070] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general-purpose hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.

[0071] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions within the technical scope disclosed in this application. Therefore, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A control method for an uninterruptible power supply, characterized in that, The uninterruptible power supply includes an inverter, which includes a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power-frequency upper transistor Q3, and a power-frequency lower transistor Q4. The method includes: When the power grid is in a normal state and the uninterruptible power supply (UPS) battery is fully charged, control the UPS to enter a full bypass working mode. In the fully bypass working mode, the drive signals of the high-frequency upper transistor Q1, the high-frequency lower transistor Q2, and the power frequency upper transistor Q3 are turned off. The grid phase is detected, and it is determined whether the grid phase meets the preset error with the preset turn-on phase. If yes, the power frequency lower transistor Q4 is turned on for a preset time and then turned off. If no, the power frequency lower transistor Q4 is turned off. The preset turn-on phase is in the positive half-cycle phase interval, and when the power frequency lower transistor Q4 is turned on for a preset time based on the preset turn-on phase, the grid phase is still in the positive half-cycle phase interval.

2. The method according to claim 1, characterized in that, The preset activation phase is 90°.

3. The method according to claim 1 or 2, characterized in that, The uninterruptible power supply also includes a drive circuit, which includes a bootstrap capacitor and a bootstrap resistor. The preset duration is determined based on the charging parameters of the bootstrap capacitor and the bootstrap resistor.

4. The method according to claim 1 or 2, characterized in that, The preset duration is less than half of the power frequency cycle.

5. The method according to claim 1 or 2, characterized in that, The inverter is a bidirectional inverter, and the method further includes: When the power grid is in an abnormal state or the battery of the uninterruptible power supply is not fully charged, the uninterruptible power supply is controlled to enter the normal working mode. Perform the following steps in the normal operating mode: During the positive half-cycle phase interval of each power frequency cycle, the high-frequency upper transistor Q1 and the high-frequency lower transistor Q2 are controlled to conduct complementaryly based on the pulse width modulation signal, while the power frequency upper transistor Q3 is continuously turned off and the power frequency lower transistor Q4 is continuously turned on. During the negative half-cycle phase interval of each power frequency cycle, the high-frequency upper transistor Q1 and the high-frequency lower transistor Q2 are complementaryly turned on based on the pulse width modulation signal, the power frequency upper transistor Q3 is continuously turned on, and the power frequency lower transistor Q4 is continuously turned off.

6. An uninterruptible power supply, characterized in that, The uninterruptible power supply includes an inverter and a controller. The inverter includes a high-frequency upper transistor Q1, a high-frequency lower transistor Q2, a power frequency upper transistor Q3, and a power frequency lower transistor Q4. The controller includes at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1 to 5.

7. The uninterruptible power supply according to claim 6, characterized in that, The uninterruptible power supply also includes a drive circuit, which includes a drive IC, a bootstrap capacitor Cb, a bootstrap resistor Rb, and a bootstrap diode Db. The drive IC includes a Vi terminal, a Vcc terminal, a Vb terminal, a Vo terminal, and a Vs terminal. The Vcc terminal is connected to the Vb terminal after passing through the bootstrap resistor Rb and the bootstrap diode Db. The bootstrap capacitor Cb is connected between the Vb terminal and the Vs terminal. The Vs terminal is connected to the N-terminal of the inverter AC output and the emitter of the power frequency transistor Q3. The Vi terminal is connected to the controller, and the Vo terminal is connected to the gate of the power frequency transistor Q3.

8. A computer storage medium, characterized in that, The computer storage medium stores instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the method as described in any one of claims 1 to 5.

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