Adaptive signal latching circuit and leakage protection device

Abstract

This invention relates to the field of latching circuit technology, specifically disclosing an adaptive signal latching circuit and leakage protection device, comprising: a power input module, a signal sampling and amplification module, a signal latching module, and an output drive module; the signal sampling and amplification module is used to sample, amplify, and delay-filter the target signal; the signal latching module is used to enter a latching state when the voltage of the delayed-filtered amplified signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage, and while in the latching state, it can maintain the latching state and generate and output a latching current based on the delayed-filtered amplified signal; the output drive module is used to generate a drive signal based on the latching current and can discharge the power input module until the power supply voltage is less than the minimum latching sustaining voltage. The adaptive signal latching circuit provided by this invention can reduce the complexity of the signal latching circuit while avoiding accidental activation of the drive output.

Description

Technical Field

[0001] This invention relates to the field of latching circuit technology, and in particular to an adaptive signal latching circuit and a leakage current protection device. Background Technology

[0002] Signal latch circuits are circuits used to temporarily store and maintain signal states. They are widely used in various electronic devices. With the continuous development of circuit technology, signal latch circuits are also constantly being optimized and improved.

[0003] Signal latching circuits in the prior art, such as Figure 1 As shown, this signal latch circuit directly connects the output of the signal sampling amplifier to the input of the comparator. The output of the comparator is connected to the set terminal S of the SR latch, and the output of the SR latch is connected to the driver module. When a signal is input to the signal sampling amplifier, its latch will be triggered into the latching state, and simultaneously control the output driver module to turn on the output transistor. The output of the timing reset circuit is connected to the reset terminal R of the SR latch. When the SR latch enters the latching state, it turns on the enable signal of the counter, and the counter starts counting. When the count reaches the set time, the SR latch is reset, the output driver module is turned off, and the circuit returns to its initial state. Although this signal latch circuit structure is relatively common, the existing signal latch circuit has the following defects that affect its performance: First, the circuit does not perform delay filtering on the sampled signal after amplification, which often leads to some high-frequency interference signals falsely triggering the latch, ultimately causing the output module to turn on erroneously. Second, this circuit requires the introduction of a voltage comparator, an SR latch, and a complex timing reset circuit, resulting in many circuit modules, a complex circuit structure, and high cost.

[0004] Therefore, how to reduce the complexity of signal latching circuits while avoiding accidental activation of drive output has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides an adaptive signal latching circuit and a leakage protection device, which solves the problems of complex signal latching circuits and the inability to avoid accidental activation of drive output in related technologies.

[0006] As a first aspect of the present invention, an adaptive signal latch circuit is provided, comprising: a power input module, a signal sampling and amplification module, a signal latch module, and an output driving module, wherein the signal sampling and amplification module, the signal latch module, and the output driving module are all connected to the power input module, the signal latch module is connected to the signal sampling and amplification module, and the output driving module is connected to the signal latch module;

[0007] The power input module is used to provide power voltage to the signal sampling amplification module, the signal latching module and the output drive module;

[0008] The signal sampling and amplification module is used to sample and amplify the target signal and perform delay filtering to obtain a delayed and amplified signal.

[0009] The signal latching module is used to enter the latching state when the voltage of the delayed filter amplified signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage. When in the latching state, it can maintain the latching state and generate and output the latching current according to the delayed filter amplified signal.

[0010] The output drive module is used to generate a drive signal based on the latching current and can discharge the power input module until the power supply voltage is less than the minimum latching holding voltage.

[0011] The minimum latching sustaining voltage is greater than the latching threshold start voltage.

[0012] Furthermore, the signal latching module includes: a latching function unit and a latching current output unit, the latching function unit is connected to the latching current output unit, the latching function unit is connected to the output terminal of the signal sampling amplification module, and the latching current output unit is connected to the power input module and the output drive module respectively;

[0013] The latching function unit is used to enter the latching state when the voltage of the delayed filter amplification signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the latching minimum holding voltage. When in the latching state, it can maintain the latching state and generate a latching current according to the delayed filter amplification signal.

[0014] The latching current output unit is used to output the latching current.

[0015] Furthermore, the latching current output unit includes: a first transistor and a second transistor, the control terminal of the first transistor and the control terminal of the second transistor are connected, the first terminal of the first transistor and the first terminal of the second transistor are both connected to the power input module, the second terminal of the first transistor is connected to the control terminal of the first transistor, and the second terminal of the second transistor is connected to the output driving module.

[0016] Furthermore, the latching function unit includes: a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0017] One end of the second resistor is connected to the second terminal of the first transistor, and the other end of the second resistor is connected to the first terminal of the third transistor;

[0018] The first terminal of the third transistor is also connected to the first terminal of the fourth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, and the second terminal of the third transistor is connected to the output terminal of the signal sampling and amplification module.

[0019] The second terminal of the fourth transistor is connected to the control terminal of the fourth transistor;

[0020] The second terminal of the fifth transistor is connected to the output terminal of the signal sampling and amplification module. The second terminal of the fifth transistor is also connected to the control terminal of the fifth transistor. The control terminal of the fifth transistor is also connected to the control terminal of the sixth transistor. The first terminal of the fifth transistor is connected to the first terminal of the sixth transistor.

[0021] The second terminal of the sixth transistor is connected to the second terminal of the fourth transistor;

[0022] The second terminal of the seventh transistor is connected to the first terminal of the fifth transistor, the control terminal of the seventh transistor is connected to the second terminal of the seventh transistor, and the first terminal of the seventh transistor is connected to signal ground.

[0023] Furthermore, the signal sampling and amplification module includes: a signal amplification unit and a delay filtering unit. The input terminal of the signal amplification unit is used to input the target signal, the output terminal of the signal amplification unit is connected to the delay filtering unit, and the output terminal of the delay filtering unit is connected to the signal latching module.

[0024] The signal amplification unit is used to perform multi-stage amplification processing on the target signal to obtain the target amplified signal;

[0025] The delay filtering unit is used to perform delay filtering on the target amplified signal to obtain a delayed filtered amplified signal.

[0026] Furthermore, the signal amplification unit includes a first-stage amplifier and a second-stage amplifier. The positive and negative input terminals of the first-stage amplifier are both used to input the target signal. The negative output terminal of the first-stage amplifier is connected to the positive input terminal of the second-stage amplifier, and the positive output terminal of the first-stage amplifier is connected to the negative input terminal of the second-stage amplifier. The output terminal of the second-stage amplifier is the output terminal of the signal amplification unit.

[0027] Furthermore, the delay filtering unit includes: a first constant current source, a second constant current source, and a second capacitor. The input terminal of the first constant current source is connected to the power input module, the output terminal of the first constant current source is connected to the input terminal of the second constant current source, and the control terminal of the first constant current source is connected to the output terminal of the signal amplification unit.

[0028] The output terminal of the second constant current source is connected to signal ground, one end of the second capacitor is connected to the input terminal of the second constant current source, the other end of the second capacitor is connected to the signal ground, and one end of the second capacitor is the output terminal of the delay filter unit.

[0029] Furthermore, the output driving module includes a driving unit and a discharging unit. The discharging unit is connected to the output terminal of the driving unit. The driving unit is connected to the output terminal of the signal latching module and the power input module, respectively. The output terminal of the driving unit is the output terminal of the output driving module.

[0030] The driving unit is used to generate a driving signal based on the latching current and output the driving signal;

[0031] The discharge unit is used to discharge the power input module until the power supply voltage is less than the minimum latching holding voltage.

[0032] Furthermore, the driving unit includes an eighth transistor, a ninth transistor, and a third resistor. The control terminal of the eighth transistor is connected to the output terminal of the signal latch module, the second terminal of the eighth transistor is connected to the power input module, the first terminal of the eighth transistor is connected to the control terminal of the ninth transistor, the second terminal of the ninth transistor is connected to the control terminal of the eighth transistor, one end of the third resistor is connected to the control terminal of the ninth transistor, the other end of the third resistor is connected to the first terminal of the ninth transistor, and the other end of the third resistor is the output terminal of the output driving module.

[0033] The discharge unit includes a third constant current source, the input terminal of which is connected to the other end of the third resistor, and the output terminal of which is connected to signal ground.

[0034] As another aspect of the present invention, a leakage current protection device is provided, wherein the adaptive signal latching circuit described above is included.

[0035] The adaptive signal latch circuit provided by this invention provides power to the signal sampling amplification module, the signal latch module, and the output drive module through a power input module. The signal sampling amplification module can sample and amplify the target signal and perform delay filtering to obtain a delayed filtered amplified signal. The signal latch module can enter the latching state when the voltage of the delayed filtered amplified signal is greater than the latching threshold start voltage, and exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage. When in the latching state, it can maintain the latching state and generate and output a latching current according to the delayed filtered amplified signal. The output drive module can generate a drive signal according to the latching current and discharge the power input module until the power supply voltage is less than the minimum latching sustaining voltage. This adaptive signal latch circuit not only performs precise sampling and amplification of the target signal through a signal sampling and amplification module, but also performs delay filtering, thereby filtering out glitches and other signal spikes in the delayed and amplified signal and avoiding false triggering of the signal latch module. In addition, the signal latch module can latch and hold the precisely sampled signal in the latched state, eliminating the need for the SR latch in existing conventional circuits. Furthermore, the output drive module can discharge the power input module, gradually reducing the power supply voltage and automatically unlocking and resetting the signal latch module, eliminating the need for a complex timing reset circuit. Therefore, the adaptive signal latch circuit provided by this invention not only has the functions of accurately sampling and latching the target sampled signal and automatically unlocking and resetting, but also has the advantages of simple structure, low cost, and high reliability. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.

[0037] Figure 1 This is a schematic diagram of a signal latching circuit in the prior art.

[0038] Figure 2 The diagram shows the structure of the adaptive signal latch circuit provided by this invention.

[0039] Figure 3 The circuit diagram shows one embodiment of the adaptive signal latching circuit provided by the present invention.

[0040] Figure 4 The circuit diagram shows another embodiment of the adaptive signal latch circuit provided by the present invention.

[0041] Figure 5 The circuit diagram of the leakage current protection device provided by the present invention.

[0042] Figure 6The waveform diagram is shown for the adaptive signal latch circuit provided by this invention. Detailed Implementation

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] This embodiment provides an adaptive signal latch circuit. Figure 2 This is a structural block diagram of the adaptive signal latch circuit 10 according to an embodiment of the present invention, as shown below. Figure 2 As shown, it includes: a power input module 100, a signal sampling and amplification module 200, a signal latch module 300, and an output drive module 400. The signal sampling and amplification module 200, the signal latch module 300, and the output drive module 400 are all connected to the power input module 100. The signal latch module 300 is connected to the signal sampling and amplification module 200, and the output drive module 400 is connected to the signal latch module 300.

[0047] The power input module 100 is used to provide power voltage to the signal sampling amplification module 200, the signal latching module 300 and the output drive module 400.

[0048] In this embodiment of the invention, the power input module 100 can rectify the input AC voltage to obtain a DC voltage, and then regulate the DC voltage to provide power supply for the signal sampling amplification module 200, the signal latching module 300 and the output driving module 400.

[0049] The signal sampling and amplification module 200 is used to sample and amplify the target signal and perform delay filtering to obtain a delayed and amplified signal.

[0050] In this embodiment of the invention, the signal sampling and amplification module 200 can sample and amplify the input target signal, and can also perform delay filtering on the amplified signal to obtain a delayed filtered amplified signal, which is to prevent high glitches and other signals from causing false triggering of the subsequent signal latching module.

[0051] The signal latch module 300 is used to enter the latching state when the voltage of the delayed filter amplified signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage. When in the latching state, it can maintain the latching state and generate and output the latching current according to the delayed filter amplified signal.

[0052] Specifically, the signal latch module 300 can enter the latching state when the voltage of the delayed filtering amplified signal is greater than the latching threshold start voltage. In the latching state, the signal latch module 300 can also maintain the latching state and generate a latching current according to the delayed filtering amplified signal, and output the latching current. When the power supply voltage applied to the signal latch module is less than the minimum latching holding voltage, the signal latch module 300 will exit the latching state.

[0053] In this embodiment of the invention, for example, the latch threshold start voltage can be 1.4V, and when the power supply voltage is working normally, it can be 5V. Then the minimum latch holding voltage can be set to 3V, so when the power supply voltage is lower than 3V, the signal latch module will exit the latching state.

[0054] The output drive module 400 is used to generate a drive signal based on the latching current and can discharge the power input module until the power supply voltage is less than the minimum latching holding voltage.

[0055] The minimum latching sustaining voltage is greater than the latching threshold start voltage.

[0056] In this embodiment of the invention, the output driving module 400 can generate a driving signal based on the latching current to drive the operation of the external switching transistor, and can discharge the power input module until the power supply voltage is less than the minimum latching holding voltage, so that the signal latching module can exit the latching state.

[0057] Therefore, the adaptive signal latch circuit provided by this invention provides power to the signal sampling amplification module, the signal latch module, and the output drive module through the power input module. The signal sampling amplification module can perform sampling amplification and delay filtering on the target signal to obtain a delayed filtered amplified signal. The signal latch module can enter the latching state when the voltage of the delayed filtered amplified signal is greater than the latching threshold start voltage, and exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage. When in the latching state, it can maintain the latching state and generate and output the latching current according to the delayed filtered amplified signal. The output drive module can generate a drive signal according to the latching current and discharge the power input module until the power supply voltage is less than the minimum latching sustaining voltage. This adaptive signal latch circuit not only performs precise sampling and amplification of the target signal through a signal sampling and amplification module, but also performs delay filtering, thereby filtering out glitches and other signal spikes in the delayed and amplified signal and avoiding false triggering of the signal latch module. In addition, the signal latch module can latch and hold the precisely sampled signal in the latched state, eliminating the need for the SR latch in existing conventional circuits. Furthermore, the output drive module can discharge the power input module, gradually reducing the power supply voltage and automatically unlocking and resetting the signal latch module, eliminating the need for a complex timing reset circuit. Therefore, the adaptive signal latch circuit provided by this invention not only has the functions of accurately sampling and latching the target sampled signal and automatically unlocking and resetting, but also has the advantages of simple structure, low cost, and high reliability.

[0058] In embodiments of the present invention, such as Figure 3 and Figure 4 As shown, the power input module 100 may specifically include a rectifier unit 110 and a power regulator unit 120, with the power regulator unit 120 connected to the rectifier unit 110. The power regulator unit 120 may specifically include a first resistor R1, a first capacitor C1, and a voltage clamping unit 121.

[0059] Specifically, the input terminal of the rectifier unit 110 is connected to an external AC power supply, and its output terminal is connected to the first resistor R1. The rectifier unit 110 may specifically include a full-bridge or a half-bridge, and can be implemented as a rectifier bridge.

[0060] Furthermore, one end of the first resistor R1 in the power supply regulator unit 120 is connected to the output terminal of the rectifier unit 110, and the other end is coupled to the common terminal of the first capacitor C1 and the voltage clamping unit 121; the other end of the first capacitor C1 is connected to signal ground.

[0061] It should be noted that the voltage clamping unit 121 is used in conjunction with the first current-limiting resistor R1. The characteristic of the voltage clamping unit 121 is that when the voltage applied to the voltage clamping unit 121 exceeds its own clamping threshold voltage, the current will increase dramatically; when the voltage is lower than its own clamping threshold voltage, the current will approach zero. Specifically, the voltage clamping unit 121 can be composed of a Zener diode and a resistor. Of course, other circuit configurations can also be used, as long as they can achieve the function of the voltage clamping unit 121. This embodiment of the invention is not limited to any particular configuration.

[0062] Therefore, when the DC voltage rectified by the rectifier unit 110 is high, the current flowing through the first resistor R1 is greater, and the voltage drop is also greater. All the excess voltage is absorbed by the first resistor R1. Combined with the filtering and energy storage effect of the first capacitor C1, the voltage output by the power supply regulator unit 120 will remain stable at the set clamping voltage value. Because the DC voltage rectified by the rectifier unit 110 is high, the first resistor R1 needs to be a power resistor with a large resistance value.

[0063] It should be noted that one end of the first resistor R1 can also be directly connected to an external AC power source, and the other end can be connected to the input terminal of the rectifier unit 110. The output terminal of the rectifier unit 110 is coupled to the common terminal of the first capacitor C1 and the voltage clamping unit 121. That is, the positions of the first resistor R1 and the rectifier unit 110 can be interchanged.

[0064] like Figure 3 and Figure 4 As shown, the signal sampling and amplification module 200 includes a signal amplification unit 210 and a delay filtering unit 220. The input terminal of the signal amplification unit 210 is used to input the target signal, the output terminal of the signal amplification unit 210 is connected to the delay filtering unit 220, and the output terminal of the delay filtering unit 220 is connected to the signal latching module 300.

[0065] The signal amplification unit 210 is used to perform multi-stage amplification processing on the target signal to obtain the target amplified signal;

[0066] The delay filtering unit 220 is used to perform delay filtering on the target amplified signal to obtain a delayed filtered amplified signal.

[0067] Specifically, such as Figure 3 and Figure 4As shown, the signal amplification unit 210 includes a first-stage amplifier and a second-stage amplifier. The positive and negative input terminals of the first-stage amplifier are both used to input the target signal. The negative output terminal of the first-stage amplifier is connected to the positive input terminal of the second-stage amplifier, and the positive output terminal of the first-stage amplifier is connected to the negative input terminal of the second-stage amplifier. The output terminal of the second-stage amplifier is the output terminal of the signal amplification unit.

[0068] Specifically, such as Figure 3 and Figure 4 As shown, the delay filtering unit 220 includes: a first constant current source I1, a second constant current source I2, and a second capacitor C2. The input terminal of the first constant current source I1 is connected to the power input module 100, the output terminal of the first constant current source I1 is connected to the input terminal of the second constant current source I2, and the control terminal of the first constant current source I1 is connected to the output terminal of the signal amplification unit 210.

[0069] The output terminal of the second constant current source I2 is connected to the signal ground, one end of the second capacitor C2 is connected to the input terminal of the second constant current source I2, the other end of the second capacitor C2 is connected to the signal ground, and one end of the second capacitor C2 is the output terminal of the delay filter unit 220.

[0070] In this embodiment of the invention, the current of the first constant current source I1 is greater than the current of the second constant current source I2, and the first constant current source I1 is controlled by the output control signal of the multi-stage amplifier, while the second constant current source I2 is always in the on state. When the sampled target signal is greater than the set threshold voltage, the first constant current source I1 will be turned on to charge the second capacitor C2, and its net charging current I = I1 - I2. The function of the second capacitor C2 is to delay and filter to prevent high-frequency glitches from causing the latch to be falsely triggered.

[0071] In embodiments of the present invention, such as Figure 3 and Figure 4 As shown, the signal latching module 300 includes a latching function unit 320 and a latching current output unit 310. The latching function unit 320 is connected to the latching current output unit 310. The latching function unit 320 is connected to the output terminal of the signal sampling amplification module 200. The latching current output unit 310 is connected to the power input module 100 and the output driving module 400, respectively.

[0072] The latching function unit 320 is used to enter the latching state when the voltage of the delayed filter amplification signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the latching minimum holding voltage. When in the latching state, it can maintain the latching state and generate a latching current according to the delayed filter amplification signal.

[0073] The latching current output unit 310 is used to output the latching current.

[0074] Specifically, such as Figure 3 and Figure 4 As shown, the latching current output unit 310 includes: a first transistor Q1 and a second transistor Q2. The control terminal of the first transistor Q1 and the control terminal of the second transistor Q2 are connected. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are both connected to the power input module 100. The second terminal of the first transistor Q1 is connected to the control terminal of the first transistor Q1. The second terminal of the second transistor Q2 is connected to the output driving module 400.

[0075] Specifically, such as Figure 3 and Figure 4 As shown, the latching function unit 320 includes: a second resistor R2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, and a seventh transistor Q7;

[0076] One end of the second resistor R2 is connected to the second terminal of the first transistor Q1, and the other end of the second resistor R2 is connected to the first terminal of the third transistor Q3;

[0077] The first terminal of the third transistor Q3 is also connected to the first terminal of the fourth transistor Q4, the control terminal of the third transistor Q3 is connected to the control terminal of the fourth transistor Q4, and the second terminal of the third transistor Q3 is connected to the output terminal of the signal sampling and amplification module 200.

[0078] The second terminal of the fourth transistor Q4 is connected to the control terminal of the fourth transistor Q4;

[0079] The second terminal of the fifth transistor Q5 is connected to the output terminal of the signal sampling and amplification module 200. The second terminal of the fifth transistor Q5 is also connected to the control terminal of the fifth transistor Q5. The control terminal of the fifth transistor Q5 is also connected to the control terminal of the sixth transistor Q6. The first terminal of the fifth transistor Q5 is connected to the first terminal of the sixth transistor Q6.

[0080] The second terminal of the sixth transistor Q6 is connected to the second terminal of the fourth transistor Q4;

[0081] The second terminal of the seventh transistor Q7 is connected to the first terminal of the fifth transistor Q5, the control terminal of the seventh transistor Q7 is connected to the second terminal of the seventh transistor Q7, and the first terminal of the seventh transistor Q7 is connected to signal ground.

[0082] It should be noted that the first transistor Q1 to the seventh transistor Q7 in the embodiments of the present invention can be implemented as either a bipolar transistor or a field-effect transistor, and the specific embodiments of the present invention are not limited thereto. For example Figure 3 The first transistor Q1 to the seventh transistor Q7 shown are illustrated using bipolar transistors as an example. Figure 4 The first transistor Q1 to the seventh transistor Q7 shown are illustrated using field-effect transistors as an example. Figure 3 As shown, when the first transistor Q1 to the seventh transistor Q7 are all bipolar transistors, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all PNP transistors, and the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are all NPN transistors. In this embodiment, the control terminal of the first transistor Q1 to the seventh transistor Q7 is the base, the first terminal is the emitter, and the second terminal is the collector. Figure 4 As shown, when the first transistor Q1 to the seventh transistor Q7 are all field-effect transistors, the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are all P-type MOS transistors, and the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are all N-type MOS transistors. In this embodiment, the control terminals of the first transistor Q1 to the seventh transistor Q7 are all gates, the first terminals are all sources, and the second terminals are all drains.

[0083] by Figure 3The following is a detailed explanation using an example. In this embodiment of the invention, the first transistor Q1 and the second transistor Q2 form an equal-ratio current mirror structure, and the collector current of the first transistor Q1 is equal to that of the second transistor Q2. The third transistor Q3 to the sixth transistor Q6 together form a latch-up structure, wherein the trigger terminal of the latch is connected to the output terminal of the signal sampling and amplification module 200. The principle of the latch-up structure is as follows: when the base potential of the fifth transistor Q5 (i.e., the voltage of the delayed filtering and amplified signal) rises to the sum of the turn-on threshold voltages of the fifth transistor Q5 and the seventh transistor Q7, Vth = 2 * Vbe, the fifth transistor Q5 and the seventh transistor Q7 will conduct, thereby turning on the sixth transistor Q6, pulling down the base potential of the third transistor Q3 and the fourth transistor Q4, and turning on the third transistor Q3 and the fourth transistor Q4. Because the fourth transistor Q4 is turned on, the base potential of the fifth transistor Q5 is maintained unchanged, so that the fifth transistor Q5 and the seventh transistor Q7 are continuously turned on, forming a positive feedback loop to achieve the latch-up effect of triggering latch-up. When the power supply voltage gradually decreases, the base potential of the fifth transistor Q5 and the sixth transistor Q6 will also gradually decrease. When the base voltage of the fifth transistor Q5 is lower than the sum of the turn-on threshold voltages of the fifth transistor Q5 and the seventh transistor Q7, Vth = 2 * Vbe, the fifth transistor Q5 and the seventh transistor Q7 will be turned off, and the latch-up structure will exit the locked state.

[0084] Therefore, in this embodiment of the invention, when a valid sampling signal is input, when the base voltage (voltage of the delayed filtering amplified signal) of the fifth transistor Q5 exceeds the latch-up threshold voltage, the latch-up structure is triggered, and all of the first transistors Q1 to the seventh transistor Q7 are turned on. The latch-up structure can generate a latch current according to the delayed filtering amplified signal. The second transistor Q2 mirrors and replicates the latch current of the first transistor Q1 and outputs the latch current to drive the output driving module 400 to turn on.

[0085] In embodiments of the present invention, such as Figure 3 and Figure 4 As shown, the output driving module 400 includes a driving unit 410 and a discharging unit 420. The discharging unit 420 is connected to the output terminal of the driving unit 410. The driving unit 410 is connected to the output terminal of the signal latch module 300 and the power input module 100, respectively. The output terminal of the driving unit 410 is the output terminal of the output driving module 400.

[0086] The driving unit 410 is used to generate a driving signal based on the latching current and output the driving signal.

[0087] The discharge unit 420 is used to discharge the power input module until the power supply voltage is less than the latch minimum holding voltage.

[0088] Specifically, such as Figure 3 and Figure 4 As shown, the driving unit 410 includes an eighth transistor Q8, a ninth transistor Q9, and a third resistor R3. The control terminal of the eighth transistor Q8 is connected to the output terminal of the signal latch module 300, the second terminal of the eighth transistor Q8 is connected to the power input module 100, the first terminal of the eighth transistor Q8 is connected to the control terminal of the ninth transistor Q9, the second terminal of the ninth transistor Q9 is connected to the control terminal of the eighth transistor Q8, one end of the third resistor R3 is connected to the control terminal of the ninth transistor Q9, the other end of the third resistor R3 is connected to the first terminal of the ninth transistor Q9, and the other end of the third resistor R3 is the output terminal of the output driving module 400.

[0089] The discharge unit 420 includes a third constant current source I3. The input terminal of the third constant current source I3 is connected to the other end of the third resistor R3, and the output terminal of the third constant current source I3 is connected to signal ground.

[0090] It should be noted that, in the embodiments of the present invention, the eighth transistor Q8 and the ninth transistor Q9 can be implemented as either bipolar transistors or field-effect transistors, and the specific embodiments of the present invention are not limited thereto. For example Figure 3 The eighth transistor Q8 and the ninth transistor Q9 shown are illustrated using bipolar transistors as an example. Figure 4 The eighth transistor Q8 and the ninth transistor Q9 shown are illustrated using field-effect transistors as an example. Figure 3 As shown, when both the eighth transistor Q8 and the ninth transistor Q9 are bipolar transistors, both are NPN transistors. In this embodiment, the control terminals of both the eighth transistor Q8 and the ninth transistor Q9 are bases, their first terminals are emitters, and their second terminals are collectors. Figure 4 As shown, when both the eighth transistor Q8 and the ninth transistor Q9 are field-effect transistors, both the eighth transistor Q8 and the ninth transistor Q9 are N-type MOS transistors. In this embodiment, the control terminals of both the eighth transistor Q8 and the ninth transistor Q9 are gates, the first terminals are sources, and the second terminals are drains.

[0091] Specifically, the eighth transistor Q8 serves as the output transistor of the entire adaptive signal latch circuit, used to drive external switching devices. Figure 3The following is a detailed explanation using an example. In this embodiment of the invention, the seventh transistor Q7 is used in conjunction with the third resistor R3 to limit the maximum output current of the eighth transistor Q8. The principle is as follows: the third resistor R3 samples the current flowing out of the eighth transistor Q8. When the voltage drop across the third resistor R3 is greater than the turn-on threshold voltage of the seventh transistor Q7, the seventh transistor Q7 turns on, pulling down the base potential of the eighth transistor Q8, reducing the turn-on degree of the eighth transistor Q8, thereby reducing the output current of the eighth transistor Q8; at the same time, the maximum output current of the eighth transistor Q8 must be greater than the pull-down current of the third constant current source I3.

[0092] It should be noted that in this embodiment of the invention, the output current of the eighth transistor Q8 is divided into two parts. One part is used to drive external switching devices, and the other part is shunt by the third constant current source I3. The current of the third constant current source I3 is greater than the maximum current on the first resistor R1. Therefore, when the eighth transistor Q8 is turned on, the first capacitor C1 in the power supply regulator unit 120 begins to discharge, and its voltage gradually decreases. When the voltage decreases to the minimum holding voltage of the latch structure, the latch structure will automatically unlock and return to the initial state, turning off the output drive module 400. This completes the automatic unlocking and reset function of the signal latch module 300, and the first capacitor C1 will begin to be recharged by the first resistor R1 to the clamping voltage value.

[0093] In summary, the adaptive signal latch circuit of this embodiment only needs to connect the output terminal of the target sampling signal to the input port of the multi-stage amplifier. It will automatically sample and amplify the target signal, and after delay filtering, input it into the signal latch module. The signal latch module latches and holds the input valid target signal, and at the same time generates a corresponding latch current signal. This latch current signal is transmitted to the control terminal of the output drive module, and then turns on the eighth transistor Q8 to drive the external switching device to work. At the same time, the third constant current source discharges the first capacitor C1, so that the output voltage of the power supply regulator unit 120 gradually decreases until the voltage drops to the threshold voltage for unlocking the signal latch module 300. This causes the signal latch module 300 to unlock and reset, turn off the eighth transistor Q8, stop the third constant current source I3 from discharging, and recharge the voltage on the first capacitor C1 in the power supply regulator unit 120 to the set voltage clamping voltage value. The system returns to the initial state and waits for the next signal detection.

[0094] Therefore, the adaptive signal latch circuit provided by this invention can not only accurately sample and latch the target signal, eliminating the need for voltage comparators and SR latches in conventional circuits, but also cleverly utilizes the constant current source discharge in the output drive module to gradually reduce the voltage of the power supply regulation unit, thereby automatically unlocking and resetting the signal latch unit, eliminating the need for complex timing and reset circuits. Thus, the adaptive signal latch circuit provided by this invention not only has the functions of accurately sampling and latching the target sampled signal and automatically unlocking and resetting, but also features simple structure, low cost, and high reliability.

[0095] As another embodiment of the present invention, a leakage current protection device is provided, which includes the adaptive signal latching circuit described above.

[0096] In this embodiment of the invention, the adaptive signal latching circuit described above is used in a leakage current protection device. Its purpose is to detect the leakage current signal Vleak on the live / neutral wire and output a corresponding drive signal to drive the external switching device to complete the tripping operation.

[0097] In embodiments of the present invention, such as Figure 5 As shown, by using 220V / 50Hz AC power Vac as the power supply for the system, the high-voltage AC power Vac is converted into high-voltage DC voltage by the rectifier unit 110, and then converted into low-voltage DC voltage Vdc by the first resistor R1, voltage clamping unit 121 and first capacitor C1 in the power supply voltage regulation unit 120. In this embodiment of the invention, the low-voltage DC voltage Vdc can be set to 5V for use by the low-voltage circuit module in the circuit system.

[0098] In this embodiment of the invention, the leakage signal on the live / neutral wire is converted into an induced current by an induction coil. This induced current then flows through a sampling resistor Rs to form the final leakage sampling signal Vleak. The two ends of the sampling resistor Rs are respectively connected to the input terminals of the multi-stage amplifier in the signal sampling amplification module 200. The diodes D1 and D2 connected in parallel with the sampling resistor Rs are used to clamp the input sampling voltage to prevent the input voltage difference from being too large and causing the input transistors of the multi-stage amplifier to break down. In this embodiment of the invention, the multi-stage amplifier in the adaptive signal latch circuit will automatically amplify the leakage signal Vleak and then control the opening of the first constant current source I1 to charge the second capacitor C2, which has a delay filtering effect and can effectively eliminate high-frequency glitches and interference signals. Since the second constant current source I2 is always on, the voltage across the second capacitor C2 is zero before the first constant current source I1 is turned on. Since the current of the first constant current source I1 is greater than the current of the second constant current source I2, the charging current for the second capacitor C2 after the first constant current source I1 is turned on is I = I1 - I2, and the voltage across the second capacitor C2 increases linearly.

[0099] Then, when the voltage on the second capacitor C2 gradually rises to the latch trigger threshold voltage in the signal latch module 300, all transistors from the first transistor Q1 to the seventh transistor Q7 are turned on, entering a latch-up state. In this embodiment of the invention, the latch trigger threshold voltage is jointly determined by the fifth transistor Q5 and the seventh transistor Q7, and its threshold voltage is V = Vbe5 + Vbe7 = 2 * Vbe = 1.2 volts. Once in the latch-up state, the current flowing out of the fifth transistor Q5 is greater than the pull-down current of the second constant current source I2. Even if the leakage signal Vleak disappears at this time and turns off the first constant current source I1, the first transistors from Q1 to Q7 will still be in the latch-up conducting state. At this time, the collector current of the second transistor Q2 in the signal latch module 300 will flow into the output drive module 400.

[0100] When the collector current of the second transistor Q2 flows into the base of the eighth transistor Q8 in the output drive module 400, the eighth transistor Q8 is turned on, driving the external switching device to work.

[0101] The seventh transistor Q7 is used in conjunction with the third resistor R3 to limit the maximum output current of the eighth transistor Q8. The principle is as follows: the third resistor R3 samples the current flowing out of the eighth transistor Q8. When the voltage drop across the third resistor R3 is greater than the turn-on threshold voltage Vbe of the seventh transistor Q7, the seventh transistor Q7 turns on, pulling down the base potential of the eighth transistor Q8, reducing the turn-on degree of the eighth transistor Q8, thereby limiting the output current of the eighth transistor Q8 and preventing the eighth transistor Q8 from being damaged due to excessive output current. At the same time, the maximum output current of the eighth transistor Q8 must be greater than the pull-down current of the third constant current source I3.

[0102] In this embodiment of the invention, the output current of the eighth transistor Q8 is divided into two parts. One part is used to drive the external switching device, and the other part is shunt by the third constant current source I3. The current of the third constant current source I3 is greater than the maximum current on the first current limiting resistor R1. Therefore, when the eighth transistor Q8 is turned on, the first capacitor C1 in the power supply regulator unit 120 begins to discharge slowly, and its voltage gradually decreases. When the voltage decreases to the minimum holding voltage of the latch structure, the latch structure will automatically unlock and return to the initial state, turning off the eighth transistor Q8 in the output drive module 400, causing the third constant current source I3 to stop discharging. The first capacitor C1 begins to recharge from the first resistor R1 to the clamping voltage value Vdc=5V, completing the automatic unlocking and reset function of the signal latch module.

[0103] It should be noted that in this embodiment of the invention, the resistance value of the first resistor R1 is usually set to be relatively large, generally a power resistor of several hundred kiloohms (kΩ) is selected to limit the current flowing through the first resistor R1. There are two purposes: the first purpose is to reduce the power consumption of the entire circuit system; the second purpose is to ensure that the maximum current flowing through the first resistor R1 is less than the shunt current of the third constant current source I3.

[0104] In this embodiment of the invention, the first capacitor C1 serves as an energy storage filter and has a relatively large capacitance value, typically ranging from a few microfarads to tens of microfarads. Meanwhile, the current of the third constant current source I3 is relatively small. Therefore, after the eighth transistor Q8 is turned on, the third constant current source I3 slowly discharges the first capacitor C1, causing the voltage on the first capacitor C1 to decrease slowly. During the period from when the voltage drops to when the signal latch module 300 is unlocked and reset, the eighth transistor Q8 has sufficient time to drive the external switching device to complete the signal transmission.

[0105] In embodiments of the present invention, such as Figure 6The diagram shows the waveform of the adaptive signal latching circuit of the present invention. When the input signal waveform arrives at the input terminal, the output voltage waveform of the signal sampling amplification module 200 begins to rise linearly. When the voltage rises to the latch threshold voltage Vth = 2 * Vbe = 1.2V, its latching structure is activated, automatically keeping the voltage constant at 1.2V, and simultaneously outputting a high-level voltage waveform to turn on the output drive module 400. After the output drive module 400 is turned on, it drives the external switching device to work, and at the same time, it uses the third constant current source I3 to regulate the voltage in the power supply stabilizing unit 120. The first capacitor C1 discharges slowly, and the output voltage waveform of the power supply regulator unit 120 gradually decreases. When the voltage of the power supply regulator unit 120 drops to the minimum holding voltage of the signal latch module 300, the latch structure of the signal latch module 300 automatically unlocks, returning to its initial state, shutting down the output drive module 400, and stopping the discharge of the first capacitor C1 in the power supply regulator unit 120. The first capacitor C1 then begins to recharge from the first resistor R1 to the clamping voltage value Vdc = 5V. Figure 6 As can be seen, the output voltage waveform of the power supply regulator unit 120 gradually rises to 5V, thus completing the entire process of the circuit system from signal sampling, amplification, output to automatic unlocking and reset, and then waiting for the next signal detection.

[0106] As can be seen from the above embodiments, the adaptive signal latch circuit provided by the present invention can not only accurately sample and latch the target signal, eliminating the need for voltage comparators and SR latches in conventional circuits, but also cleverly utilizes the constant current source discharge in the output drive module to gradually reduce the voltage of the power supply regulation unit, thereby automatically unlocking and resetting the signal latch unit, eliminating the need for complex timing and reset circuits. Therefore, the adaptive signal latch circuit provided by the present invention not only has the functions of accurately sampling and latching the target sampled signal and automatically unlocking and resetting, but also features simple structure, low cost, and high reliability.

[0107] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An adaptive signal latching circuit, characterized in that, include: The system includes a power input module, a signal sampling and amplification module, a signal latch module, and an output drive module. The signal sampling and amplification module, the signal latch module, and the output drive module are all connected to the power input module. The signal latch module is connected to the signal sampling and amplification module, and the output drive module is connected to the signal latch module. The power input module is used to provide power voltage to the signal sampling amplification module, the signal latching module and the output drive module; The signal sampling and amplification module is used to sample and amplify the target signal and perform delay filtering to obtain a delayed and amplified signal. The signal latching module is used to enter the latching state when the voltage of the delayed filter amplified signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the minimum latching sustaining voltage. When in the latching state, it can maintain the latching state and generate and output the latching current according to the delayed filter amplified signal. The output drive module is used to generate a drive signal based on the latching current and can discharge the power input module until the power supply voltage is less than the minimum latching holding voltage. The minimum latching sustaining voltage is greater than the latching threshold start voltage.

2. The adaptive signal latch circuit according to claim 1, characterized in that, The signal latching module includes a latching function unit and a latching current output unit. The latching function unit is connected to the latching current output unit. The latching function unit is connected to the output terminal of the signal sampling and amplification module. The latching current output unit is connected to the power input module and the output drive module respectively. The latching function unit is used to enter the latching state when the voltage of the delayed filter amplification signal is greater than the latching threshold start voltage, and to exit the latching state when the power supply voltage is less than the latching minimum holding voltage. When in the latching state, it can maintain the latching state and generate a latching current according to the delayed filter amplification signal. The latching current output unit is used to output the latching current.

3. The adaptive signal latch circuit according to claim 2, characterized in that, The latching current output unit includes a first transistor and a second transistor. The control terminals of the first transistor and the second transistor are connected. The first terminals of the first transistor and the second transistor are both connected to the power input module. The second terminal of the first transistor is connected to the control terminal of the first transistor. The second terminal of the second transistor is connected to the output driving module.

4. The adaptive signal latch circuit according to claim 3, characterized in that, The latching function unit includes: a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; One end of the second resistor is connected to the second terminal of the first transistor, and the other end of the second resistor is connected to the first terminal of the third transistor; The first terminal of the third transistor is also connected to the first terminal of the fourth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor, and the second terminal of the third transistor is connected to the output terminal of the signal sampling and amplification module. The second terminal of the fourth transistor is connected to the control terminal of the fourth transistor; The second terminal of the fifth transistor is connected to the output terminal of the signal sampling and amplification module. The second terminal of the fifth transistor is also connected to the control terminal of the fifth transistor. The control terminal of the fifth transistor is also connected to the control terminal of the sixth transistor. The first terminal of the fifth transistor is connected to the first terminal of the sixth transistor. The second terminal of the sixth transistor is connected to the second terminal of the fourth transistor; The second terminal of the seventh transistor is connected to the first terminal of the fifth transistor, the control terminal of the seventh transistor is connected to the second terminal of the seventh transistor, and the first terminal of the seventh transistor is connected to signal ground.

5. The adaptive signal latch circuit according to claim 1, characterized in that, The signal sampling and amplification module includes a signal amplification unit and a delay filtering unit. The input terminal of the signal amplification unit is used to input the target signal, the output terminal of the signal amplification unit is connected to the delay filtering unit, and the output terminal of the delay filtering unit is connected to the signal latching module. The signal amplification unit is used to perform multi-stage amplification processing on the target signal to obtain the target amplified signal; The delay filtering unit is used to perform delay filtering on the target amplified signal to obtain a delayed filtered amplified signal.

6. The adaptive signal latch circuit according to claim 5, characterized in that, The signal amplification unit includes a primary amplifier and a secondary amplifier. The positive and negative input terminals of the primary amplifier are both used to input the target signal. The negative output terminal of the primary amplifier is connected to the positive input terminal of the secondary amplifier, and the positive output terminal of the primary amplifier is connected to the negative input terminal of the secondary amplifier. The output terminal of the secondary amplifier is the output terminal of the signal amplification unit.

7. The adaptive signal latch circuit according to claim 5, characterized in that, The delay filtering unit includes: a first constant current source, a second constant current source, and a second capacitor. The input terminal of the first constant current source is connected to the power input module, the output terminal of the first constant current source is connected to the input terminal of the second constant current source, and the control terminal of the first constant current source is connected to the output terminal of the signal amplification unit. The output terminal of the second constant current source is connected to signal ground, one end of the second capacitor is connected to the input terminal of the second constant current source, the other end of the second capacitor is connected to the signal ground, and one end of the second capacitor is the output terminal of the delay filter unit.

8. The adaptive signal latch circuit according to claim 1, characterized in that, The output driving module includes a driving unit and a discharging unit. The discharging unit is connected to the output terminal of the driving unit. The driving unit is connected to the output terminal of the signal latching module and the power input module, respectively. The output terminal of the driving unit is the output terminal of the output driving module. The driving unit is used to generate a driving signal based on the latching current and output the driving signal; The discharge unit is used to discharge the power input module until the power supply voltage is less than the minimum latching holding voltage.

9. The adaptive signal latch circuit according to claim 8, characterized in that, The driving unit includes an eighth transistor, a ninth transistor, and a third resistor. The control terminal of the eighth transistor is connected to the output terminal of the signal latch module, the second terminal of the eighth transistor is connected to the power input module, the first terminal of the eighth transistor is connected to the control terminal of the ninth transistor, the second terminal of the ninth transistor is connected to the control terminal of the eighth transistor, one end of the third resistor is connected to the control terminal of the ninth transistor, the other end of the third resistor is connected to the first terminal of the ninth transistor, and the other end of the third resistor is the output terminal of the output driving module. The discharge unit includes a third constant current source, the input terminal of which is connected to the other end of the third resistor, and the output terminal of which is connected to signal ground.

10. A leakage current protection device, characterized in that, Includes the adaptive signal latching circuit as described in any one of claims 1 to 9.

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