Low-power-consumption selection chip control method for asymmetric comparator

Abstract

The invention relates to the technical field of comparators, in particular to an asymmetric comparator low-power-consumption selection chip control method, which comprises an asymmetric comparator core module and a signal preprocessing module, and is characterized in that a digital control logic module is respectively connected with the asymmetric comparator core module and a power management module; the power management module is also connected with the signal preprocessing module; the power supply management module comprises a dynamic voltage scaling adjusting module, a power supply gating system and a standby power supply; the dynamic voltage scaling adjusting module comprises an on-chip low voltage drop adjuster, a current sensor and a control unit; the power gating system comprises a central processing unit, a register module, a system power consumption controller and a power gating controller. The power supply voltage is adjusted in real time according to the actual working load and current condition of the system through accurate control of the dynamic voltage scaling adjusting module; in a low-load state, the power supply voltage of the asymmetric comparator core module and the like is reduced, and the overall power consumption of a chip is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of comparators, and in particular to a low-power selection chip control method for an asymmetric comparator. Background Art

[0002] A comparator is a circuit device that compares the amplitudes of two analog input voltage or current signals and generates an output signal indicating whether one analog input signal is greater than the other. Comparators are widely used in switching power supply control circuits. A comparator's two inputs are analog signals, and its output is a binary signal of 0 or 1. When the difference between the input voltages increases or decreases, and the sign remains unchanged, the output remains constant.

[0003] Asymmetric comparators, which have asymmetric threshold voltages, are essential components of analog circuits and play an indispensable role in numerous applications, such as sensor signal processing, power management, and biomedical monitoring. Traditional comparators have power consumption limitations and cannot meet the growing demand for low power consumption.

[0004] To this end, we propose an asymmetric comparator low-power selection chip control method. Summary of the Invention

[0005] The main purpose of the present invention is to provide a low-power selection chip control method for an asymmetric comparator, which adjusts the power supply voltage in real time according to the actual workload and current conditions of the system through precise control of a dynamic voltage scaling regulation module; under low-load conditions, the power supply voltage of the asymmetric comparator core module, etc. is reduced, greatly reducing the overall power consumption of the chip; and can effectively solve the problems in the background technology.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] An asymmetric comparator low-power selection chip includes an asymmetric comparator core module, a digital control logic module, a power management module, and a signal preprocessing module. The digital control logic module is connected to the asymmetric comparator core module and the power management module respectively, and the power management module is also connected to the signal preprocessing module.

[0008] The power management module includes a dynamic voltage scaling and regulation module, a power gating system and a backup power supply;

[0009] The dynamic voltage scaling regulation module includes an on-chip low-dropout regulator, a current sensor, and a control unit;

[0010] The power gating system includes a central processing unit, a register module, a system power consumption controller and a power gating controller.

[0011] By adopting the above technical solution, the power supply voltage is adjusted in real time according to the actual workload and current conditions of the system through precise control of the dynamic voltage scaling regulation module; under low-load conditions, the power supply voltage of the asymmetric comparator core module, etc. is reduced, greatly reducing the overall power consumption of the chip; compared with traditional comparator chips, the present invention can reduce power consumption, meet the stringent requirements of sensor signal processing, biomedical monitoring, etc. for low power consumption, extend the battery life of the device, and improve the portability and usage time of the device.

[0012] Specifically, the power gating system further includes a system interrupt controller for receiving a power failure interrupt signal sent by the power gating controller after controlling the power switch of the power domain to be turned off, and feeding back the power failure interrupt signal to the central processing unit.

[0013] Specifically, the system interrupt controller is further configured to receive a power-off interrupt signal sent by the power gating controller when detecting that the bus state is active, and feed the power-off interrupt signal back to the central processing unit.

[0014] Specifically, the signal preprocessing module includes a low-power filter circuit module and a low-power signal amplification module.

[0015] By adopting the above technical solution, the digital control logic module flexibly adjusts the operation of the power management module based on the comparison results and preset operating mode, enabling the chip to adapt to different application scenarios and operating states; whether in sensor signal processing, power management or biomedical monitoring and other fields, it can dynamically optimize power consumption and performance according to actual needs to meet diverse application requirements.

[0016] A method for controlling a low-power selection chip of an asymmetric comparator includes the following steps:

[0017] S1, the signal preprocessing module processes the external input signal and transmits the processed signal to the asymmetric comparator core module for comparison operation. After the asymmetric comparator core module completes the comparison operation, it feeds the output result back to the digital control logic module;

[0018] S2. The digital control logic module sends a command signal to the power management module based on the comparison result and the system preset working mode to adjust the supply voltage and current of each module;

[0019] The dynamic voltage scaling module provides an output signal to the power management module. The on-chip low voltage dropout regulator generates the output signal according to the command signal. The current sensor monitors the current of the output signal to provide a detection signal. The control unit provides the command signal according to the detection signal.

[0020] When the detection signal indicates that the current of the output signal is less than a specific value, the control unit provides the instruction signal to the on-chip low dropout regulator to reduce the voltage value of the output signal;

[0021] When the detection signal indicates that the current of the output signal is greater than the specific value, the control unit provides the command signal to the on-chip low dropout regulator to restore the reduced voltage value of the output signal;

[0022] When the detection signal indicates that the current of the output signal increases, the control unit provides the command signal to the on-chip low dropout regulator to increase the voltage value of the output signal;

[0023] S3. The power management module monitors the power consumption of each module in real time and feeds the information back to the digital control logic module so that it can make more reasonable decisions and achieve dynamic power consumption optimization of the entire system;

[0024] When the comparator output is stable and the system is in a low-load state, the supply voltage of the asymmetric comparator core module is reduced to reduce power consumption.

[0025] The beneficial effects of the present invention include: a low-power consumption asymmetric comparator selection chip control method according to the present invention;

[0026] First, significantly reduce power consumption: Through precise control of the dynamic voltage scaling module, the supply voltage is adjusted in real time according to the actual system workload and current conditions. Under low-load conditions, the supply voltage of the asymmetric comparator core module and other components is reduced, greatly reducing the overall power consumption of the chip. Compared with traditional comparator chips, this invention can reduce power consumption, meet the stringent low-power requirements of sensor signal processing, biomedical monitoring, etc., extend the battery life of the device, and improve the portability and usage time of the device.

[0027] Second, improved system stability and reliability: The power gating system, particularly the system interrupt controller's monitoring and feedback mechanism for power switch and bus status, ensures stable operation of all modules during power switching and system operation, preventing data loss or system failures caused by power anomalies. Furthermore, the signal preprocessing module filters and amplifies the input signal, improving its quality. This enables the asymmetric comparator core module to perform comparisons more accurately, improving the accuracy and stability of the entire system's signal processing.

[0028] Third, enhanced adaptability and flexibility: The digital control logic module flexibly adjusts the operation of the power management module based on comparison results and preset operating modes, allowing the chip to adapt to different application scenarios and operating states. Whether in sensor signal processing, power management, or biomedical monitoring, it can dynamically optimize power consumption and performance according to actual needs to meet diverse application requirements.

[0029] Fourth, optimize resource utilization: By monitoring the power consumption of each module in real time and feeding it back to the digital control logic module, the rational allocation and efficient utilization of internal chip resources are achieved; this avoids the resource waste caused by the fixed power supply mode in traditional chips, improves the overall performance and efficiency of the chip, and reduces hardware costs and energy consumption while ensuring functional realization. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below with reference to the accompanying drawings and examples.

[0031] Figure 1 It is a structural block diagram of the present invention;

[0032] Figure 2 This is a structural block diagram of the power management module of the present invention;

[0033] Figure 3 This is a structural block diagram of the dynamic voltage scaling and adjustment module of the present invention;

[0034] Figure 4 This is a structural block diagram of the power gating system of the present invention;

[0035] In the figure: 1. Asymmetric comparator core module; 2. Digital control logic module; 3. Power management module; 4. Signal preprocessing module; 5. Dynamic voltage scaling regulation module; 501. On-chip low voltage drop regulator; 502. Current sensor; 503. Control unit; 6. Power gating system; 601. Central processing unit; 602. Register module; 603. System power consumption controller; 604. Power gating controller; 7. Backup power supply. DETAILED DESCRIPTION

[0036] In order to make the technical means, creative features, objectives and effects achieved by the present invention easier to understand, the present invention is further described below in conjunction with specific implementation methods.

[0037] As an embodiment of the present invention, Figure 1-Figure 4 As shown, the asymmetric comparator low-power selection chip of the present invention includes an asymmetric comparator core module 1, a digital control logic module 2, a power management module 3 and a signal preprocessing module 4. The digital control logic module 2 is connected to the asymmetric comparator core module 1 and the power management module 3 respectively, and the power management module 3 is also connected to the signal preprocessing module 4;

[0038] The signal preprocessing module 4 includes a low-power filter circuit module and a low-power signal amplification module.

[0039] Low-power filter circuit module: In the signal preprocessing module 4, a low-power filter circuit is designed, such as a low-pass filter based on switched capacitor technology; the switched capacitor filter realizes the filtering function through the charging and discharging of the capacitor. Compared with the traditional resistor-capacitor (RC) filter, it does not require a large-value resistor, thereby reducing the chip area and power consumption; at the same time, by reasonably designing the capacitance value and switching frequency, the power consumption of the circuit can be reduced while meeting the filtering requirements; for example, when filtering the weak signal output by the sensor, the switched capacitor low-pass filter can effectively remove high-frequency noise, and due to its low power consumption characteristics, it will not have a significant impact on the power consumption of the entire system; in addition, an adaptive filtering algorithm can be used to dynamically adjust the filter parameters according to the characteristics of the input signal to further optimize the filtering effect and reduce power consumption.

[0040] Low-power signal amplification module: A low-power amplifier is selected as the core component of the signal amplification circuit, such as an operational amplifier based on CMOS technology, and its circuit structure is optimized; an operational amplifier with a folded cascode structure can effectively reduce power consumption while achieving high gain; by reasonably setting the bias current and operating voltage of the amplifier, the power consumption is minimized while meeting the signal amplification requirements; for example, when amplifying a weak signal after filtering, the folded cascode operational amplifier can amplify the signal to a level range suitable for the asymmetric comparator input, and its low power consumption characteristics help maintain low-power operation of the entire system; at the same time, the input and output impedance matching is considered in the design of the amplifier to reduce the loss during signal transmission, improve signal processing efficiency, and indirectly reduce power consumption.

[0041] The power management module 3 includes a dynamic voltage scaling module 5, a power gating system 6 and a backup power supply 7;

[0042] In the asymmetric comparator low-power selection chip system, the backup power supply 7 is mainly responsible for the important duties of emergency power supply and ensuring the stable operation of the system; when the system is operating normally, the backup power supply 7 is in standby state and does not participate in the main power supply work, and is only started when a specific abnormal situation occurs; when the system encounters a sudden power outage, the main power supply in the power management module 3 fails, or the power supply is interrupted due to external interference, the backup power supply 7 will respond quickly to provide power support for the key modules of the chip; taking the biomedical monitoring scenario as an example, if there is a sudden power outage during the monitoring process, the backup power supply 7 will start immediately to provide power for the asymmetric comparator core module 1, the digital control The control logic module 2 provides continuous power to enable the chip to continue to complete the current signal processing task, ensure that the collected human physiological signals will not be lost, and maintain the data integrity and processing continuity of the system; at the same time, the backup power supply 7 works closely with the power gating system 6; during the process of the backup power supply 7 starting to supply power, the power gating system 6 will monitor and adjust the power consumption of each module, give priority to ensuring the power supply needs of the core functional modules, shut down non-essential modules, further reduce power consumption, and extend the power supply time of the backup power supply 7, so as to buy more time for the system to restore normal power supply and ensure that the system can still maintain stable operation of key functions under abnormal circumstances.

[0043] The dynamic voltage scaling and regulation module 5 includes an on-chip low voltage dropout regulator 501 , a current sensor 502 and a control unit 503 ;

[0044] The on-chip low-voltage dropout regulator 501 is an important component of the dynamic voltage scaling regulation module 5 in the present asymmetric comparator low-power selection chip control method and plays an indispensable role. Its core function is to generate a corresponding output signal according to the instruction signal sent by the digital control logic module 2 through the control unit 503, so as to provide stable power supply for each module of the chip. During operation, the on-chip low-voltage dropout regulator 501 can maintain efficient and stable voltage regulation capabilities even when the input and output voltage difference is small. When the current sensor 502 detects the current change of the output signal, the control unit 503 will judge and send instructions based on the detection signal. For example, when the detection signal indicates that the current of the output signal is less than a specific value, it means that the system is in a low-load state. At this time, the control unit 503 will detect the current change of the output signal and send instructions. The element 503 instructs the on-chip low-voltage dropout regulator 501 to reduce the voltage value of the output signal, thereby reducing the chip's power consumption. When the current is greater than a specific value, or the current continues to increase, the control unit 503 will instruct the on-chip low-voltage dropout regulator 501 to restore or increase the voltage value of the output signal to meet the performance requirements of the chip under different working conditions. The on-chip low-voltage dropout regulator 501 works closely with the current sensor 502 and the control unit 503 to form a dynamic voltage regulation closed-loop system. This collaborative mode enables the chip to accurately adjust the supply voltage according to the actual workload, while ensuring the normal operation of the chip, while minimizing power consumption and improving energy utilization efficiency. It is one of the key links in achieving dynamic power consumption optimization of the asymmetric comparator low-power selection chip.

[0045] The current sensor 502 is a key component for realizing dynamic power consumption optimization of the asymmetric comparator low-power selection chip, and plays an important role as a "monitor" in the entire chip control process. It can accurately capture current change information and provide a key basis for system power consumption regulation; real-time current monitoring: the core task of the current sensor 502 is to monitor the current of the output signal generated by the low-voltage dropout regulator 501 on the chip in the dynamic voltage scaling regulation module 5 in real time; during the operation of the chip, it continuously collects current data, like a keen "electronic eye", not missing any details of current fluctuations; taking the biomedical monitoring scenario as an example, whether it is a state of small signal processing volume and weak current when the human body is at rest, or a state of increased signal processing volume and increased current due to human activity, the current sensor 502 can quickly perceive it; data feedback and command triggering: the current sensor 502 feeds back the monitored current information to the control unit 503 in the form of a detection signal; the control unit 503 makes a judgment based on these detection signals, and then issues a corresponding Instructions; When the detection signal shows that the current of the output signal is less than a specific value, it means that the system is in a low-load state. The control unit 503 will instruct the low-voltage dropout regulator 501 on the chip to reduce the output voltage and reduce power consumption; when the current is greater than the specific value, or the current continues to increase, the control unit 503 will instruct the low-voltage dropout regulator 501 on the chip to restore or increase the output voltage to meet the system's higher performance requirements; It can be said that the current sensor 502 is the key bridge connecting the actual current state and the system power consumption adjustment action. The accuracy and timeliness of the data it feedback directly affects the effect of the chip power consumption adjustment and the overall performance of the system; Ensuring stable system operation: The current sensor 502 also plays an important role in ensuring stable chip operation; By monitoring the current in real time, it can promptly detect abnormal current fluctuations, such as current mutations caused by faults such as short circuits; Once an anomaly is detected, the system can quickly take measures to avoid chip damage due to abnormal current, ensuring that the chip can operate safely and stably under various working conditions.

[0046] The power gating system 6 includes a central processing unit 601, a register module 602, a system power consumption controller 603 and a power gating controller 604;

[0047] Register module 602 is an indispensable part of power gating system 6. It is mainly responsible for storing and transmitting key control information, coordinating with other components to achieve refined management of chip power supply. It also stores software power-down configuration information: Register module 602 is like an "information warehouse" specifically used to store software power-down configuration information written by central processing unit 601. This configuration information includes the power-down strategy for each power domain under different working scenarios of the system. For example, in a biomedical monitoring device, when the device enters sleep mode, the central processing unit 601 will write the corresponding software power-down configuration information into register module 602. This information clearly specifies which power domains can be shut down and which need to maintain a minimum power supply, providing a precise instruction basis for subsequent power control.

[0048] Triggering a software power-down request: When the system meets the pre-set software power-down conditions, the register module 602 extracts the corresponding configuration information from the "information warehouse" and sends a software power-down request to the power gating controller 604. For example, when a biomedical monitoring device enters standby mode after a long period of inactivity, the register module 602 detects that the software power-down trigger conditions have been met and immediately sends a request signal to the power gating controller 604. After receiving the request, the power gating controller 604 begins to check the bus status of the relevant power domain. Only when the bus is in an idle state will it perform a power-down operation on the power domain according to the pre-set configuration, thereby effectively reducing chip power consumption.

[0049] Working in collaboration with other components: The register module 602 does not operate independently, but works closely with other components in the power gating system 6. It cooperates with the system power controller 603. The system power controller 603 monitors the system status and triggers hardware power-down requests from the hardware level, while the register module 602 controls it from the software level. These two-pronged approach ensures that the power gating system 6 can fully and accurately respond to the system's power management needs. At the same time, the register module 602 also maintains close data interaction with the central processor 601, receiving configuration instructions from the central processor 601 and providing feedback on the status of its own stored information to ensure the smooth operation of the entire chip power management process.

[0050] In the power management system of the asymmetric comparator low-power selection chip, the system power controller 603 is the core control unit for achieving low power consumption goals. It is mainly responsible for sensing the system operating status and accurately regulating the power supply accordingly, playing a key role in reducing power consumption and optimizing resource allocation; System status monitoring and power consumption judgment: The system power controller 603 constantly monitors the operating status of the central processing unit 601, including key parameters such as the processor's operating frequency and task load; In biomedical monitoring equipment, when the device is in standby or low data processing mode, the operating frequency of the central processing unit 601 decreases and the task load becomes smaller, and the system power controller 603 will keenly capture these state changes; Through internal preset algorithms and threshold standards, the system power controller 603 evaluates the current system power consumption level and determines whether the system is in low-power mode, providing a basis for subsequent power control;

[0051] Triggering a hardware power-down request: Once the system power consumption controller 603 determines that the system has entered low-power mode, it will send a hardware power-down request signal to the power gating controller 604. Taking the low-frequency usage period of biomedical monitoring equipment at night as an example, the system task load is greatly reduced at this time. After confirming that the low-power mode conditions are met, the system power consumption controller 603 quickly transmits the hardware power-down request signal to the power gating controller 604. After receiving the request, the power gating controller 604 will further detect the bus status of the relevant power domain. Only when the bus is in an idle state will it execute the operation of cutting off the power supply of the corresponding power domain, thereby shutting down non-essential modules and significantly reducing the overall power consumption of the chip.

[0052] Collaborative optimization of power management: The system power consumption controller 603 does not work in isolation, but works closely with other components in the power gating system 6. It cooperates with the register module 602, which stores software power-down configuration information, and the system power consumption controller 603 triggers power-down requests based on hardware monitoring results. The two jointly ensure the precise and efficient operation of the power gating system 6 from both the software and hardware levels. In addition, the system power consumption controller 603 also cooperates with other parts of the power management module 3 to feed back system power consumption status information to the digital control logic module 2, helping the digital control logic module 2 to more comprehensively understand the system operation status, and then make more reasonable power allocation and power consumption optimization decisions, achieving efficient utilization of chip resources and improving overall performance.

[0053] The power gating controller 604 is a key component of the power gating system 6 and plays a crucial role in the power management mechanism of the asymmetric comparator low-power selection chip. It is primarily responsible for precisely controlling the power supply on and off of the power domains to achieve the goal of reducing power consumption.

[0054] During system operation, the power gating controller 604 receives signal instructions from various sources. On the one hand, the register module 602 triggers a software power-down request based on the software power-down configuration information written by the central processor 601 and transmits it to the power gating controller 604. On the other hand, the system power controller 603 determines whether the system is in low-power mode based on the status of the central processor 601. If so, it sends a hardware power-down request to the power gating controller 604. Upon receiving the software or hardware power-down request, the power gating controller 604 immediately initiates a process for detecting the power domain bus status. Its internal bus status detection circuit interacts with the power domain bus low-power interface.

[0055] Taking the biomedical monitoring equipment in a low-load state as an example, if the system determines that some power domains can enter the low-power mode at this time, the power gating controller 604 will start working; only when the bus state detection circuit interacts successfully with the bus low-power interface and determines that the bus is in an idle state, the power gating controller 604 will perform power-off timing control on the power domain; in this process, the power gating controller 604 will send a series of control signals: send an isolation enable signal to the isolation unit to isolate the output signal of the power domain to prevent the uncertain signal generated by the power shutdown from affecting other circuit modules that are operating normally; send a reset control signal to the reset generation module to reset the power domain; send a clock gating signal to the clock generation module to control the clock of the power domain; send a shutdown control signal to the memory of the power domain to make it enter the shutdown mode; finally, send a shutdown control signal to the power switch of the power domain to cut off the power supply of the power domain to achieve the purpose of reducing power consumption;

[0056] After completing the power domain power switch shutdown operation, the power gating controller 604 will send a power-off interrupt signal to the system interrupt controller so that the system interrupt controller can feed this information back to the central processor 601 to inform the system of the change in the power domain status; if during the detection process, the bus status detection circuit fails to interact with the bus low-power interface and determines that the bus is in an active state, the power gating controller 604 will also send relevant signals to the system interrupt controller through the interrupt generation circuit, such as bus low-power rejection interrupt, so that the system can respond in time to avoid data transmission interruption or system failure due to improper power shutdown, thereby ensuring the stable operation of the entire chip system.

[0057] During use, taking the signal processing in biomedical monitoring equipment as an example, in the biomedical monitoring scenario, the external input signal is a human physiological signal. The low-power filter circuit module in the signal preprocessing module 4 first filters the collected external human physiological signal to remove high-frequency noise and low-frequency interference in the signal, and only retains the effective frequency band signal related to the physiological characteristics; then, the low-power signal amplification module amplifies the weak signal after filtering to make it reach a voltage range suitable for processing by the asymmetric comparator core module 1; the processed signal is transmitted to the asymmetric comparator core module 1, and the asymmetric comparator core module 1 compares the input signal according to the asymmetric threshold voltage set inside it. After the comparison is completed, the output result is fed back to the digital control logic module 2; the low-power filter circuit module in the signal preprocessing module 4 first filters the collected external human physiological signal to remove high-frequency noise and low-frequency interference in the signal, and only retains the effective frequency band signal related to the physiological characteristics; then, the low-power signal amplification module amplifies the weak signal after filtering to make it reach a voltage range suitable for processing by the asymmetric comparator core module 1; the processed signal is transmitted to the asymmetric comparator core module 1, and the asymmetric comparator core module 1 compares the input signal according to the asymmetric threshold voltage set internally, and feeds back the output result to the digital control logic module 2 after the comparison is completed.

[0058] like Figure 4 As shown, the present invention further includes that the power gating system 6 further includes a system interrupt controller, which is used to receive a power failure interrupt signal sent by the power gating controller 604 after controlling the power switch of the power domain to be turned off, and feed the power failure interrupt signal back to the central processor 601;

[0059] The system interrupt controller is further configured to receive a power-off interrupt signal sent by the power gating controller 604 when detecting that the bus state is active, and feed the power-off interrupt signal back to the central processing unit 601 .

[0060] A method for controlling a low-power selection chip of an asymmetric comparator, comprising the following steps:

[0061] S1, the signal preprocessing module 4 processes the external input signal and transmits the processed signal to the asymmetric comparator core module 1 for comparison operation. After the asymmetric comparator core module 1 completes the comparison operation, it feeds the output result back to the digital control logic module 2;

[0062] S2, the digital control logic module 2 sends a command signal to the power management module 3 based on the comparison result and the system preset working mode to adjust the supply voltage and current of each module;

[0063] The dynamic voltage scaling module 5 provides an output signal to the power management module 3. The on-chip low-dropout regulator 501 generates the output signal according to the command signal. The current sensor 502 monitors the current of the output signal to provide a detection signal. The control unit 503 provides the command signal according to the detection signal.

[0064] When the detection signal indicates that the current of the output signal is less than a specific value, the control unit 503 provides the instruction signal to the on-chip low dropout regulator 501 to reduce the voltage value of the output signal;

[0065] When the detection signal indicates that the current of the output signal is greater than the specific value, the control unit 503 provides the instruction signal to the on-chip low dropout regulator 501 to restore the reduced voltage value of the output signal;

[0066] When the detection signal indicates that the current of the output signal increases, the control unit 503 provides the command signal to the on-chip low dropout regulator 501 to increase the voltage value of the output signal;

[0067] S3, the power management module 3 will monitor the power consumption of each module in real time and feed the information back to the digital control logic module 2 so that it can make more reasonable decisions and achieve dynamic power consumption optimization of the entire system;

[0068] When the comparator output is stable and the system is in a low-load state, the supply voltage of the asymmetric comparator core module 1 is reduced to reduce power consumption.

[0069] When applying this asymmetric comparator low-power selection chip control method, the specific implementation process of the present invention is described by taking the signal processing in biomedical monitoring equipment as an example; in the biomedical monitoring scenario, the external input signal is a human physiological signal, which is usually relatively weak and mixed with various noises;

[0070] (1) Signal preprocessing stage: The low-power filter circuit module in the signal preprocessing module 4 first filters the collected external human physiological signals to remove high-frequency noise and low-frequency interference in the signals, and only retains the effective frequency band signals related to physiological characteristics; then, the low-power signal amplification module amplifies the weak signals after filtering to make them reach a voltage range suitable for processing by the asymmetric comparator core module 1; the processed signals are transmitted to the asymmetric comparator core module 1, and the asymmetric comparator core module 1 compares the input signals according to the asymmetric threshold voltage set within it, and after the comparison is completed, the output result is fed back to the digital control logic module 2;

[0071] (2) Power supply voltage and current adjustment stage: After receiving the output result of the asymmetric comparator core module 1, the digital control logic module 2 sends a command signal to the power management module 3 in combination with the system's preset biomedical monitoring working mode; the dynamic voltage scaling adjustment module 5 starts working, and the low voltage drop regulator 501 on the chip generates an output signal according to the command signal to power each module of the chip; the current sensor 502 monitors the current of the output signal in real time and feeds the detection signal back to the control unit 503; in the biomedical monitoring process, when the human body is in a resting state, the signal processing amount is small, and the current sensor 502 detects the output signal. If the current of the signal is less than a specific value, the control unit 503 will provide a command signal to the on-chip low-voltage dropout regulator 501 to reduce the voltage value of the output signal, thereby reducing the overall power consumption of the chip. When human activity causes changes in physiological signals and the signal processing volume increases, the current sensor 502 detects that the current of the output signal is greater than a specific value. The control unit 503 will provide a command signal to the on-chip low-voltage dropout regulator 501 to restore the previously reduced voltage value to ensure the normal operation performance of the chip. If the current continues to increase, the control unit 503 will further instruct the on-chip low-voltage dropout regulator 501 to increase the voltage value of the output signal to meet higher processing requirements.

[0072] (3) Dynamic power consumption optimization stage: The power management module 3 continuously monitors the power consumption of each module in real time. In the biomedical monitoring scenario, when the comparator output is stable, that is, the human physiological signal is in a relatively stable state and the system is in a low-load state, the power management module 3 feeds this information back to the digital control logic module 2. The digital control logic module 2 makes a decision based on this information to reduce the power supply voltage of the asymmetric comparator core module 1 and reduce unnecessary power consumption. At the same time, the power gating system 6 also plays a role. After detecting that the power switch of the relevant power domain is turned off, the system interrupt controller receives the power-off interrupt signal issued by the power gating controller 604 and feeds it back to the central processing unit 601, or when detecting that the bus state is active, it also receives and feeds back the power-off interrupt signal to ensure accurate control of power management and stable operation of the system.

[0073] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above-described embodiments. The above-described embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An asymmetric comparator low power selection chip, characterized in that: The invention comprises an asymmetric comparator core module (1), a digital control logic module (2), a power management module (3) and a signal preprocessing module (4), wherein the digital control logic module (2) is connected to the asymmetric comparator core module (1) and the power management module (3), respectively, and the power management module (3) is also connected to the signal preprocessing module (4); The power management module (3) includes a dynamic voltage scaling adjustment module (5), a power gating system (6) and a backup power supply (7); The dynamic voltage scaling and regulation module (5) comprises an on-chip low voltage dropout regulator (501), a current sensor (502) and a control unit (503); The power gating system (6) comprises a central processing unit (601), a register module (602), a system power consumption controller (603) and a power gating controller (604).

2. The asymmetric comparator low power selection chip according to claim 1, characterized in that: The power gating system (6) further comprises a system interrupt controller for receiving a power-off interrupt signal sent by the power gating controller (604) after controlling the power switch of the power domain to be turned off, and feeding back the power-off interrupt signal to the central processing unit (601).

3. The asymmetric comparator low power selection chip according to claim 2, characterized in that: The system interrupt controller is further configured to receive a power-off interrupt signal sent by the power gating controller (604) when detecting that the bus state is active, and feed the power-off interrupt signal back to the central processing unit (601).

4. The asymmetric comparator low power selection chip according to claim 1, characterized in that: The signal preprocessing module (4) comprises a low-power filter circuit module and a low-power signal amplification module.

5. A method for controlling an asymmetric comparator low-power selection chip, applied to an asymmetric comparator low-power selection chip according to any one of claims 1 to 4, characterized in that: The asymmetric comparator low power consumption selection chip control method comprises the following steps: S1, the signal preprocessing module (4) processes the external input signal and transmits the processed signal to the asymmetric comparator core module (1) for comparison operation. After the asymmetric comparator core module (1) completes the comparison operation, it feeds back the output result to the digital control logic module (2); S2, the digital control logic module (2) sends a command signal to the power management module (3) based on the comparison result and the system preset working mode to adjust the power supply voltage and current of each module; The dynamic voltage scaling adjustment module (5) provides an output signal to the power management module (3); the on-chip low voltage dropout regulator (501) generates the output signal according to the command signal; the current sensor (502) monitors the current of the output signal to provide a detection signal; and the control unit (503) provides the command signal according to the detection signal. When the detection signal indicates that the current of the output signal is less than a specific value, the control unit (503) provides the instruction signal to the on-chip low-dropout regulator (501) to reduce the voltage value of the output signal; When the detection signal indicates that the current of the output signal is greater than the specific value, the control unit (503) provides the command signal to the on-chip low-dropout regulator (501) to restore the reduced voltage value of the output signal; When the detection signal indicates that the current of the output signal increases, the control unit (503) provides the command signal to the on-chip low-dropout regulator (501) to increase the voltage value of the output signal; S3, the power management module (3) will monitor the power consumption of each module in real time and feed the information back to the digital control logic module (2) so that it can make more reasonable decisions and achieve dynamic power consumption optimization of the entire system; When the comparator output is stable and the system is in a low-load state, the power supply voltage of the asymmetric comparator core module (1) is reduced to reduce power consumption.

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