A Sigma-Delta ADC gate voltage bootstrap switching circuit for large-area image sensors

Abstract

This invention relates to a gate voltage bootstrap switching circuit for a Sigma-Delta ADC applied to a large-area image sensor, belonging to the field of integrated circuit technology. It includes a voltage input terminal Vin, a main switch M12, a substrate bias transistor M13, a dual-capacitor complementary bootstrap and volume effect dynamic compensation network, and a voltage output terminal Vout. Vin is connected to the source of M12, Vout is connected to the drain of M12, and the source of M13 is connected to the output of the dual-capacitor complementary bootstrap and volume effect dynamic compensation network. Furthermore, the output of the dual-capacitor complementary bootstrap and volume effect dynamic compensation network is synchronously connected to M12. This invention ensures that the gate voltage of M12 is accurately raised at the moment of sampling through dual-capacitor time-division pre-charging and complementary clock driving. Simultaneously, when the input Vin changes, M13 dynamically adjusts the substrate potential of M12 to counteract the threshold voltage Vth drift caused by substrate bias.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a Sigma-Delta ADC gate voltage bootstrap switching circuit applied to a large-area image sensor. Background Technology

[0002] Sigma-Delta analog-to-digital converters (SD-ADCs) are widely used in image sensors and medical devices, and are high-precision analog-to-digital converters. For SD-ADCs, the accuracy of the input signal sampling determines the conversion accuracy. In practice, the on-resistance of common MOSFET switches changes with the input signal, introducing nonlinearity into the ADC system, generating harmonic distortion, and ultimately affecting the ADC's accuracy. To solve this problem, a gate-voltage bootstrap switching circuit was designed to generate a constant gate-source voltage, ensuring that the on-resistance of the switch is unaffected by changes in the input signal.

[0003] The gate-voltage bootstrap switch achieves a constant gate-source voltage, ensuring a fixed on-resistance when the switch is turned on. This eliminates the dependence of on-resistance on the input signal, improves circuit nonlinearity, and enhances signal transmission accuracy. This structure is particularly suitable for high-precision sample-and-hold circuits. Furthermore, the gate-voltage bootstrap switch isolates the input signal from the control signal, reducing the impact of crosstalk between signals. Figure 1 The basic structure of a gate-source bootstrap switch to achieve a constant gate-source voltage is demonstrated. Among them, and It is a set of two-phase non-overlapping clocks, when When the voltage is high, M1 is off, switches S1 and S4 are on to charge C1, the voltage level of the upper plate of C1 is VDD, and the voltage level of the lower plate is 0; when... When the switch is high, S1 and S4 are off, while S2 and S5 are on. The upper and lower plates of capacitor C1 are connected to the gate and source of M1, respectively, making the gate-source voltage of M1 VDD, thus maintaining a constant on-resistance. Furthermore, since the gate-source voltage is the power supply voltage, the on-resistance is very small, allowing for a larger signal bandwidth.

[0004] Traditional gate-voltage bootstrap switching circuits use a single-capacitor bootstrap, which is prone to timing misalignment during pre-charging and sampling; at the same time, they only stabilize the gate-source voltage Vgs of the main switch. Due to the body effect, the threshold voltage drift caused by changes in the substrate voltage can also introduce nonlinearity into the circuit. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a Sigma-DeltaADC gate voltage bootstrap switching circuit for use in large-area image sensors. By employing precise control logic of "dual capacitors + dual clocks" through bootstrap logic, the timing mismatch problem existing in traditional bootstrap switching circuits is solved. Through additional dual-capacitor complementary bootstrap and volume effect dynamic compensation network, the Vgs and Vth of the switching transistor are controlled simultaneously to offset the threshold voltage drift caused by substrate bias. This solves the nonlinearity problem caused by the change of the on-resistance value of the traditional switching transistor with the input signal.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A Sigma-Delta ADC gate voltage bootstrap switching circuit for use in large-area image sensors includes: a voltage input terminal Vin, a main switch transistor M12, a substrate bias transistor M13, a dual-capacitor complementary bootstrap and volume effect dynamic compensation network, and a voltage output terminal Vout.

[0008] The voltage input terminal Vin is connected to the source of the main switch transistor M12, the voltage output terminal Vout is connected to the drain of the main switch transistor M12, the gate of the main switch transistor M12 and the substrate bias transistor M13 are connected to the ON pin, the drain of the substrate bias transistor M13 and the voltage input terminal Vin are connected to the source of the main switch transistor M12, the source of the substrate bias transistor M13 is connected to the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, and the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network is synchronously connected to the main switch transistor M12.

[0009] The dual-capacitor complementary bootstrap and body effect dynamic compensation network includes two-phase non-overlapping clocks CLK1 and CLK2, dual bootstrap capacitors C1 and C2, and several field response transistors M1 to M11. Among them, M3 and M4 form the first inverter, and M8 and M9 form the second inverter. The first and second inverters are combined with the two-phase clock CLK2 complementary clock control module. M3 to M7 are combined with the substrate bias transistor M13 to form a substrate potential follower network. The dual-capacitor complementary bootstrap and body effect dynamic compensation network ensures that the gate voltage of the main switch transistor M12 is accurately raised at the moment of sampling through the dual-capacitor time-division pre-charging and complementary clock driving method. At the same time, when the input Vin changes, the substrate potential of M12 is dynamically adjusted by M13 to offset the threshold voltage Vth drift caused by substrate bias.

[0010] Furthermore, in the first inverter, the drains of M3 and M4 are connected to each other and serve as the output of the first inverter; the source of M4 is connected to the power supply voltage VDD.

[0011] Furthermore, in the second inverter, the drains of M8 and M9 are connected to each other and serve as the output of the second inverter; the source of M8 is grounded, and the source of M9 is connected to the power supply voltage VDD.

[0012] Furthermore, CLK2 is simultaneously connected to the gate of the first inverter composed of the third field-effect transistor M3 and the fourth field-effect transistor M4, and the gate of the second inverter composed of the eighth field-effect transistor M8 and the ninth field-effect transistor M9.

[0013] Furthermore, CLK1 is simultaneously connected to the gates of the first field-effect transistor M1 and the second field-effect transistor M2, and the on / off state of the source and drain of the first field-effect transistor M1 and the second field-effect transistor M2 is controlled by inputting high and low levels.

[0014] Furthermore, the left plate of capacitor C1 is connected to the drain of the second inverter; the right plate of capacitor C1 is simultaneously connected to the gate of the tenth field-effect transistor M10 and the source of the eleventh field-effect transistor M11.

[0015] Furthermore, the lead wire connected to the left electrode of capacitor C2 serves as the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, connected to the source of substrate bias transistor M13 and main switch transistor M12. The source of M1, the source of M3 in the first inverter, and the source of the sixth field-effect transistor M6 are also connected to this lead wire. The right electrode of capacitor C2 is simultaneously connected to the drain of the seventh field-effect transistor M7 and the source of M10.

[0016] Furthermore, the drain of M10, the gate of M11, and the drain of M11 are all connected to the power supply voltage VDD.

[0017] Furthermore, in the dual-capacitor complementary bootstrap and body effect dynamic compensation network, the ON pin is connected to the gate of M6, the drain of M7, and the drain of the fifth field-effect transistor M5. The gate of M5 is connected to the EN pin, and the source of M5 is connected to the drain of M2.

[0018] Furthermore, among the field-effect transistors including M12 and M13, M4, M7, and M9 are P-type field-effect transistors, which are turned on when the input level is low and turned off when the input level is high; the remaining field-effect transistors are N-type field-effect transistors, which are turned on when the input level is high and turned off when the input level is low.

[0019] The beneficial effects of this invention are as follows:

[0020] This invention employs dual-capacitor time-division pre-charging and complementary clock driving to ensure that the gate voltage of the main switch M12 can be accurately raised at the moment of sampling, avoiding gate voltage drops or overcharging due to clock glitches. Compared to traditional gate voltage bootstrap switching circuits, this provides more flexible timing control and can adapt to high-frequency sampling scenarios. Simultaneously, M13 acts as the substrate bias transistor for M12, forming a dual-capacitor complementary bootstrap and body effect dynamic compensation network together with M3-M7: when the input Vin changes, M13 dynamically adjusts the substrate potential of M12, thereby offsetting the threshold voltage Vth drift caused by substrate bias. Compared to traditional bootstrap circuits that only stabilize Vgs, thus ignoring the nonlinearity of the on-resistance caused by Vth changes, the gate voltage bootstrap switching circuit in this embodiment simultaneously controls Vgs and Vth to offset the nonlinearity of the switch, further reducing nonlinearity.

[0021] This invention solves the timing mismatch problem of traditional bootstrap circuits by designing a gate voltage bootstrap switching circuit based on "dual-capacitor complementary bootstrap and volume effect dynamic compensation network". It breaks through the limitation of traditional bootstrap switching circuits that only stabilize Vgs, further reduces the nonlinearity of the circuit, ensures that the on-resistance of the sampling switch is constant throughout the entire signal cycle, and has a simple circuit structure, thereby improving the sampling accuracy of the Sigma-Delta analog-to-digital converter circuit.

[0022] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0024] Figure 1 A schematic diagram of the basic structure for achieving a constant gate-source voltage in a traditional gate-voltage bootstrap switch;

[0025] Figure 2 This is a schematic diagram of the gate voltage bootstrap switching circuit according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram illustrating the variation of the gate-source voltage of the gate-voltage bootstrap switch with the input signal according to an embodiment of the present invention;

[0027] Figure 4 This is a signal spectrum diagram of the gate voltage bootstrap switch output in an embodiment of the present invention. Detailed Implementation

[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0030] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0031] Please see Figures 2-4 This is a Sigma-Delta ADC gate voltage bootstrap switching circuit applied to large-area image sensors.

[0032] Example 1

[0033] This embodiment provides a Sigma-Delta ADC gate voltage bootstrap switching circuit applied to a large-area image sensor, such as... Figure 2A detailed circuit diagram of a gate voltage bootstrap switch circuit is shown, which includes a voltage input terminal Vin, a main switch transistor M12, a substrate bias transistor M13, a dual-capacitor complementary bootstrap and body effect dynamic compensation network, and a voltage output terminal Vout. The voltage input terminal Vin is connected to the source of the main switch transistor M12, and the voltage output terminal Vout is connected to the drain of the main switch transistor M12. The gates of the main switch transistor M12 and the substrate bias transistor M13 are connected to the ON pin. The drain of the substrate bias transistor M13 and the voltage input terminal Vin are both connected to the source of the main switch transistor M12. The source of the substrate bias transistor M13 is connected to the output terminal of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, and the output terminal of the dual-capacitor complementary bootstrap and body effect dynamic compensation network is synchronously connected to the main switch transistor M12.

[0034] The dual-capacitor complementary bootstrap and body effect dynamic compensation network includes two-phase non-overlapping clocks CLK1 and CLK2, dual bootstrap capacitors C1 and C2, and several field response transistors M1 to M11. Among them, M3 and M4 form the first inverter, and M8 and M9 form the second inverter. The first and second inverters are combined with the two-phase clock CLK2 complementary clock control module. M3 to M7 are combined with the substrate bias transistor M13 to form a substrate potential follower network. The dual-capacitor complementary bootstrap and body effect dynamic compensation network ensures that the gate voltage of the main switch transistor M12 is accurately raised at the moment of sampling through the dual-capacitor time-division pre-charging and complementary clock driving method. At the same time, when the input Vin changes, the substrate potential of M12 is dynamically adjusted by M13 to offset the threshold voltage Vth drift caused by substrate bias.

[0035] In this embodiment, CLK1 is connected to the gates of both the first field-effect transistor M1 and the second field-effect transistor M2. The on / off state of the source and drain of the first field-effect transistor M1 and the second field-effect transistor M2 is controlled by inputting high and low levels.

[0036] In this embodiment, CLK2 is simultaneously connected to the gate of the first inverter composed of the third field-effect transistor M3 and the fourth field-effect transistor M4, and the gate of the second inverter composed of the eighth field-effect transistor M8 and the ninth field-effect transistor M9.

[0037] In this embodiment, the left plate of capacitor C1 is connected to the drain of the second inverter composed of the eighth field-effect transistor M8 and the ninth field-effect transistor M9; the right plate of capacitor C1 is simultaneously connected to the gate of the tenth field-effect transistor M10 and the source of the eleventh field-effect transistor M11.

[0038] In this embodiment, the lead wire connected to the left plate of capacitor C2 serves as the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, connected to the source of substrate bias transistor M13 and main switch transistor M12. Furthermore, the source of M1, the source of M3 in the first inverter, and the source of the sixth field-effect transistor M6 are also connected to this lead wire. The right plate of capacitor C2 is simultaneously connected to the drain of the seventh field-effect transistor M7 and the source of M10, wherein M7 is a P-type field-effect transistor.

[0039] In the dual-capacitor complementary bootstrap and body effect dynamic compensation network, the ON pin is connected to the gate of M6, the drain of M7, and the drain of the fifth field-effect transistor M5. The gate of M5 is connected to the EN pin, and the source of M5 is connected to the drain of M2.

[0040] In the first inverter, the drains of M3 and M4 are connected to each other and serve as the output of the first inverter; the source of M4 is connected to the first power supply voltage VDD, where M4 is a P-type field-effect transistor and M3 is an N-type field-effect transistor.

[0041] In the second inverter, the drains of M8 and M9 are connected to each other and serve as the output of the second inverter; the source of M8 is grounded, the source of M9 is connected to the power supply voltage VDD, and the power supply voltage VDD is also connected to the gate of M11, the drain of M11, and the drain of M10. M9 is a P-type field-effect transistor and M8 is an N-type field-effect transistor.

[0042] In this embodiment, among the field-effect transistors including M12 and M13, M4, M7 and M9 are P-type field-effect transistors, which are turned on when the input level is low and turned off when the input level is high; the remaining field-effect transistors are N-type field-effect transistors, which are turned on when the input level is high and turned off when the input level is low.

[0043] When CLK1 is low and CLK2 is high, M1 and M2 are off. The left plate of capacitor C1 is connected to the inverter composed of M8 and M9, and is at a low level. The right plate is connected to the power supply voltage VDD after passing through the diode-connected M11, so the right plate is at a high level. M10 is turned on, charging the right plate of capacitor C2 to the power supply voltage VDD. Since CLK2 is high, after passing through the inverter composed of M3 and M4, the gate voltage of M7 is low, and M7 is turned on. At this time, the ON signal is high, so M13 is turned on. The left plate of capacitor C2 is connected to the Vin potential, so the potential of the right plate of C2 is VDD + Vin. Since M7 is turned on, the potential of ON is VDD + Vin. The substrate potential of M12 is the Vin potential of the left plate of capacitor C2. Therefore, Vbs of M12 is 0, and there is no body effect. Vgs is VDD and is not affected by the power supply voltage change. Therefore, the on-resistance of M12 is constant.

[0044] When CLK1 is high and CLK2 is low, M1 and M2 are turned on, and the ON position is low, while transistors M12 and M13 are turned off. The potential of the left plate of capacitor C1 changes from 0 to the power supply voltage VDD, therefore the potential of the right plate of C1 is 2VDD. M7 is turned off, M6 is turned on, and the potential of the left plate of capacitor C2 changes from Vin to low. Since M10 is turned on, the potential of the right plate of capacitor C2 changes from VDD+Vin to VDD. Therefore, throughout the entire process, the gate-source voltage of switch M12 remains constant.

[0045] In this embodiment, dual bootstrap capacitors C1 and C2 are used to coordinate with the two-phase non-overlapping clocks CLK1 and CLK2. Furthermore, M3, M4, M8, and M9 form a complementary clock control module. This dual-capacitor time-division pre-charging and complementary clock driving ensure that the gate voltage of the main switch M12 can be precisely raised at the moment of sampling, avoiding gate voltage drops or overcharging due to clock glitches. Compared to traditional gate voltage bootstrap switching circuits, this provides more flexible timing control and can adapt to high-frequency sampling scenarios. Simultaneously, M13 acts as the substrate bias transistor for M12, forming a dual-capacitor complementary bootstrap and volume effect dynamic compensation network together with M3-M7. When the input Vin changes, M13 dynamically adjusts the substrate potential of M12, thereby offsetting the threshold voltage Vth drift caused by substrate bias. Compared to traditional bootstrap circuits that only stabilize Vgs, thus ignoring the nonlinearity of the on-resistance caused by Vth changes, the gate voltage bootstrap switching circuit in this embodiment controls both Vgs and Vth to offset the nonlinearity of the switch, further reducing nonlinearity.

[0046] This circuit utilizes a capacitor charging and discharging mechanism to generate a constant gate-source voltage for the switching transistor, ensuring a constant on-resistance of the sampling switch throughout the entire sampling period. This guarantees accurate sampling of the input signal by the ADC and can be widely used in the sampling switch of SD-ADCs. Addressing the issue that the on-resistance of the sampling switch in Sigma-Delta ADC circuits varies with the input signal, introducing nonlinearity and affecting the ADC's sampling accuracy, this circuit designs a gate voltage bootstrap switch circuit based on a "dual-capacitor complementary bootstrap and volume effect dynamic compensation network" in the SD-ADC sampling switch. This overcomes the limitation of traditional bootstrap switch circuits that only stabilize Vgs, further reducing circuit nonlinearity and improving the performance of the SD-ADC analog-to-digital converter circuit.

[0047] In this embodiment, by designing a gate voltage bootstrap switching circuit based on "dual capacitor complementary bootstrap and volume effect dynamic compensation network", the timing mismatch problem of traditional bootstrap is solved, the limitation of traditional bootstrap switching circuits that only stabilize Vgs is overcome, the nonlinearity of the circuit is further reduced, the on-resistance of the sampling switch is kept constant throughout the entire signal cycle, and the circuit structure is simple, which improves the sampling accuracy of the Sigma-Delta analog-to-digital converter circuit.

[0048] Example 2

[0049] This embodiment experimentally verifies the proposed Sigma-Delta ADC gate voltage bootstrap switching circuit for use in large-area image sensors. In this embodiment, a 250 Hz sine wave is used as the input signal to comprehensively evaluate the circuit's performance under different input conditions.

[0050] Figure 3 This demonstrates how the gate-source voltage of the switching transistor (i.e., the main switching transistor M12) in a bootstrap switching circuit changes with the input signal. From... Figure 3 It can be clearly observed that the gate-source voltage variation is relatively small within a complete signal cycle, with a variation rate of only 4%. This result demonstrates that the gate-source bootstrap switching circuit can effectively stabilize the gate-source voltage and reduce voltage fluctuations caused by changes in the input signal. This stability is crucial for ensuring sampling accuracy and signal linearity, as it means that the switching transistor maintains relatively consistent conduction characteristics under different input levels.

[0051] To further verify the circuit's performance, this embodiment performed FFT (Fast Fourier Transform) spectrum analysis on the output signal after the switch. FFT spectrum analysis is a commonly used signal analysis method that can reveal the amplitude and phase information of different frequency components in a signal. Through spectrum analysis, the accuracy and linearity of the output signal can be observed intuitively.

[0052] Figure 4 The spectral analysis results of the output signal are presented. From Figure 4 As can be seen, by using a gate voltage bootstrap switch as the sampling switch, the input signal can be accurately sampled and transmitted. For a signal bandwidth of 1kHz, the effective number of bits (ENOB) of the input signal after passing through the bootstrap switch reaches 23.59 bits. The effective number of bits is one of the important indicators for measuring the performance of an ADC, reflecting the number of bits of signal that the ADC can accurately represent. A higher effective number of bits means that the circuit has higher sampling accuracy and lower quantization noise.

[0053] Furthermore, spectral analysis showed that the signal's signal-to-noise ratio (SNR) reached 143.78 dB, and its spurious-free dynamic range (SFDR) reached 148.86 dB. SNR is the ratio of signal power to noise power, reflecting the relative magnitude of useful and noise components in a signal. A higher SNR means a lower noise level and higher signal quality. SFDR, on the other hand, is the ratio of the maximum spurious component in a signal to its signal power, reflecting the circuit's ability to suppress spurious signals. A higher SFDR means the circuit can better suppress spurious signals and improve signal purity.

[0054] Based on the above analysis, the Sigma-Delta ADC gate voltage bootstrap switching circuit proposed in this invention for large-area image sensors exhibits excellent performance in terms of sampling accuracy, signal linearity, and noise suppression. This is attributed to the design of the dual-capacitor complementary bootstrap and the volume effect dynamic compensation network in the circuit. This effectively stabilizes the gate-source voltage, reduces voltage fluctuations caused by input signal variations, and compensates for threshold voltage drift caused by substrate bias by dynamically adjusting the substrate potential. These design measures collectively ensure that the switching transistor maintains relatively consistent conduction characteristics under different input levels, thereby improving the overall performance of the circuit.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A Sigma-Delta ADC gate voltage bootstrap switching circuit for use in large-area image sensors, characterized in that: It includes: The system consists of a voltage input terminal Vin, a main switch transistor M12, a substrate bias transistor M13, a dual-capacitor complementary bootstrap and volume effect dynamic compensation network, and a voltage output terminal Vout. The voltage input terminal Vin is connected to the source of the main switch transistor M12, the voltage output terminal Vout is connected to the drain of the main switch transistor M12, the gate of the main switch transistor M12 and the substrate bias transistor M13 are connected to the ON pin, the drain of the substrate bias transistor M13 and the voltage input terminal Vin are connected to the source of the main switch transistor M12, the source of the substrate bias transistor M13 is connected to the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, and the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network is synchronously connected to the main switch transistor M12. The dual-capacitor complementary bootstrap and body effect dynamic compensation network includes two-phase non-overlapping clocks CLK1 and CLK2, dual bootstrap capacitors C1 and C2, and several field response transistors M1 to M11. Among them, M3 and M4 form the first inverter, and M8 and M9 form the second inverter. The first and second inverters are combined with the two-phase clock CLK2 complementary clock control module. M3 to M7 are combined with the substrate bias transistor M13 to form a substrate potential follower network. The dual-capacitor complementary bootstrap and body effect dynamic compensation network ensures that the gate voltage of the main switch transistor M12 is accurately raised at the moment of sampling through the dual-capacitor time-division pre-charging and complementary clock driving method. At the same time, when the input Vin changes, the substrate potential of M12 is dynamically adjusted by M13 to offset the threshold voltage Vth drift caused by substrate bias. The left plate of capacitor C1 is connected to the drain of the second inverter; the right plate of capacitor C1 is simultaneously connected to the gate of the tenth field-effect transistor M10 and the source of the eleventh field-effect transistor M11. The lead wire connected to the left plate of capacitor C2 serves as the output of the dual-capacitor complementary bootstrap and body effect dynamic compensation network, connected to the source of substrate bias transistor M13 and main switch transistor M12. Furthermore, the source of M1, the source of M3 in the first inverter, and the source of the sixth field-effect transistor M6 are also connected to this lead wire. The right plate of capacitor C2 is simultaneously connected to the drain of the seventh field-effect transistor M7 and the source of M10.

2. The Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 1, characterized in that: In the first inverter, the drains of M3 and M4 are connected to each other and serve as the output of the first inverter; the source of M4 is connected to the power supply voltage VDD.

3. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 2, characterized in that: In the second inverter, the drains of M8 and M9 are connected to each other and serve as the output of the second inverter; the source of M8 is grounded, and the source of M9 is connected to the power supply voltage VDD.

4. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 3, characterized in that: CLK2 is simultaneously connected to the gate of the first inverter, which consists of the third field-effect transistor M3 and the fourth field-effect transistor M4, and the gate of the second inverter, which consists of the eighth field-effect transistor M8 and the ninth field-effect transistor M9.

5. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 4, characterized in that: CLK1 is connected to the gates of both the first field-effect transistor M1 and the second field-effect transistor M2. By inputting high and low levels, the on / off state of the source and drain of the first field-effect transistor M1 and the second field-effect transistor M2 is controlled.

6. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 5, characterized in that: The drain of M10, the gate of M11, and the drain of M11 are also connected to the power supply voltage VDD.

7. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to claim 6, characterized in that: In the dual-capacitor complementary bootstrap and body effect dynamic compensation network, the ON pin is connected to the gate of M6, the drain of M7, and the drain of the fifth field-effect transistor M5. The gate of M5 is connected to the EN pin, and the source of M5 is connected to the drain of M2.

8. A Sigma-Delta ADC gate voltage bootstrap switching circuit for a large-area image sensor according to any one of claims 1-7, characterized in that: Among the field-effect transistors including M12 and M13, M4, M7, and M9 are P-type field-effect transistors, which are turned on when the input level is low and turned off when the input level is high; the rest of the field-effect transistors are N-type field-effect transistors, which are turned on when the input level is high and turned off when the input level is low.

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