Circuit and method for reducing charge loss in a switched capacitor analog-to-digital converter

Abstract

Circuits and methods are disclosed for minimizing charge loss due to negative transient voltages at summing terminals (116, 120) of an analog-to-digital converter (ADC) (104). The ADC is coupled to a multi-bit digital-to-analog converter (DAC) (112A) at the summing terminals (116, 120). The ADC and the DAC include PMOS transistors and NMOS transistors whose timing is controlled to reduce charge loss. The PMOS transistors are turned on before the NMOS transistors. Also, the PMOS transistors of the ADC are turned on at a slower rate than the PMOS transistors of the DAC.

Description

Technical Field

[0001] This disclosure generally relates to switched capacitor circuits, and more particularly to circuits and methods for reducing charge loss due to negative transient voltages in switched capacitor analog-to-digital converters (ADCs). Background Technology

[0002] In a switched-capacitor analog-to-digital converter (ADC), during the sampling phase, a first set of switches closes to couple the sampling capacitor to the analog input voltage to charge the sampling capacitor. During the transfer phase, the first set of switches opens to decouple the sampling capacitor from the analog input voltage, and a second set of switches closes to transfer charge from the sampling capacitor to the integrator circuit.

[0003] In a delta-sigma ADC, the first-stage integrator can be coupled to a single-bit or multi-bit digital-to-analog converter (DAC) at a summing terminal or node. The DAC converts the digital signal into an analog signal. The DAC may include a DAC capacitor coupled to the summing terminal or node during the pass-through phase, thus connecting the ADC's sampling capacitor to the DAC capacitor. During the pass-through phase, the charge from the sampling capacitor combines with the charge from the DAC capacitor at the summing terminal or node. The charge from the sampling capacitor typically cancels out the charge from the DAC capacitor, resulting in a small amount of residual charge being passed from the summing terminal or node to the integrator circuitry.

[0004] To achieve high speed, low power consumption, and high signal-to-noise ratio (SNR) performance, the Δ-Σ ADC core needs to operate at a low supply voltage while sampling the analog input voltage at a significantly higher voltage. When using a high-efficiency amplifier with NMOS inputs, the low ADC core supply voltage necessitates operating the ADC's first-stage integrator circuit at a low input common-mode voltage.

[0005] When the charge from the ADC sampling capacitor and DAC capacitor begins to combine during the transfer phase, the voltage level at the summing terminal deviates from the nominal input common-mode voltage. When a large analog input voltage is applied, a large amount of charge combines, resulting in a large negative transient voltage at the summing terminal. Since the nominal input common-mode voltage at the summing terminal is already close to ground potential, a large negative transient voltage can cause a downslip below ground potential, resulting in charge loss in the sampling capacitor and DAC capacitor. Even a small amount of charge loss can lead to gain error, gain error drift, and a degraded nonlinear performance. Summary of the Invention

[0006] Various aspects of this disclosure relate to circuits and methods for reducing charge loss due to negative transient voltages in a switched-capacitor analog-to-digital converter (ADC). In one aspect, the circuit includes an ADC having a first capacitor coupled between a first sampling terminal and a first summing terminal, and a second capacitor coupled between a second sampling terminal and a second summing terminal. The ADC includes a first NMOS transistor and a first PMOS transistor coupled in parallel. The first PMOS transistor and the second PMOS transistor are configured to electrically disconnect the first sampling terminal and the second sampling terminal during a sampling phase and to electrically connect the first sampling terminal and the second sampling terminal during a transfer phase. The circuit also includes a digital-to-analog converter (DAC) having a third capacitor coupled between a first summing terminal and a first DAC terminal, and a fourth capacitor coupled between the second summing terminal and the second DAC terminal. The DAC includes a second NMOS transistor and a second PMOS transistor coupled in parallel. The second NMOS transistor and the second PMOS transistor are configured to electrically connect a first DAC output and a first DAC terminal during a transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during a sampling phase. The DAC also includes a third NMOS transistor and a third PMOS transistor coupled in parallel. The third NMOS transistor and the third PMOS transistor are configured to electrically connect the second DAC output and the second DAC terminal during the pass phase and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase.

[0007] In another aspect of this disclosure, gate signals are applied to the gate terminals of the first, second, and third PMOS transistors. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors. Furthermore, the gate signals are applied to the gate terminals of the first, second, and third NMOS transistors after the second and third PMOS transistors are fully turned on but before the first PMOS transistor is fully turned on. The first PMOS transistor turns on at a slower rate than the second and third PMOS transistors, and the first, second, and third NMOS transistors turn on after the first, second, and third PMOS transistors have turned on.

[0008] In another aspect of this disclosure, during the sampling phase, gate signals are removed from the gate terminals of the first PMOS transistor and the first NMOS transistor to electrically disconnect the first and second sampling terminals, and during the sampling phase, gate signals are removed from the gate terminals of the second PMOS transistor and the second NMOS transistor to electrically disconnect the first DAC output and the first DAC terminal. During the sampling phase, gate signals are removed from the gate terminals of the third PMOS transistor and the third NMOS transistor to electrically disconnect the second DAC output and the second DAC terminal.

[0009] In another aspect of this disclosure, the ADC includes a fourth switch configured to electrically connect the first and second summing terminals during a sampling phase and electrically disconnect the first and second summing terminals during a transfer phase. The DAC includes a fifth switch configured to electrically connect the first and second DAC terminals during a sampling phase and electrically disconnect the first and second DAC terminals during a transfer phase.

[0010] In another aspect of this disclosure, the ADC includes a differential integrator having first and second inputs coupled to respective first and second summing terminals during a transfer phase to integrate the residual charge at the first and second summing terminals.

[0011] In another aspect of this disclosure, a circuit includes an ADC having a first capacitor coupled between a first sampling terminal and a first summing terminal, and a second capacitor coupled between a second sampling terminal and a second summing terminal. The ADC includes a first NMOS transistor and a first PMOS transistor having respective source, drain, and gate terminals. The drain terminal of the first NMOS transistor is coupled to the source terminal of the first PMOS transistor, and the source terminal of the first NMOS transistor is coupled to the drain terminal of the first PMOS transistor. The first NMOS transistor and the first PMOS transistor are operable to electrically disconnect the first and second sampling terminals during a sampling phase and to electrically connect the first and second sampling terminals during a pass phase. The circuit also includes a DAC having a third capacitor coupled between a first summing terminal and a first DAC terminal, and a fourth capacitor coupled between the second summing terminal and the second DAC terminal. The DAC includes a second NMOS transistor and a second PMOS transistor having respective drain, source, and gate terminals. The drain terminal of the second NMOS transistor is coupled to the source terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor is coupled to the drain terminal of the second PMOS transistor. The second NMOS transistor and the second PMOS transistor are operable to electrically connect the first DAC output and the first DAC terminal during the pass phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase. The DAC also includes a third NMOS transistor and a third PMOS transistor having respective drain, source, and gate terminals. The drain terminal of the third NMOS transistor is coupled to the source terminal of the third PMOS transistor, and the source terminal of the third NMOS transistor is coupled to the drain terminal of the third PMOS transistor. The third NMOS transistor and the third PMOS transistor are operable to electrically connect the second DAC output and the second DAC terminal during the pass phase and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase. In another aspect of this disclosure, a gate signal is applied to the gate terminals of the first, second, and third PMOS transistors. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors. In another aspect of this disclosure, a gate signal is applied to the gate terminals of the first, second, and third NMOS transistors after the second and third PMOS transistors are fully turned on but before the first PMOS transistor is fully turned on. The first PMOS transistor turns on at a slower rate than the second and third PMOS transistors. After the first, second, and third PMOS transistors turn on, the first, second, and third NMOS transistors turn on.

[0012] In another aspect of this disclosure, a circuit includes an ADC having first and second summing terminals. The ADC includes a first capacitor coupled between a first sampling terminal and a first summing terminal, and a second capacitor coupled between a second sampling terminal and a second summing terminal. The ADC also includes a first NMOS transistor and a first PMOS transistor, which are coupled in parallel between the first and second sampling terminals and configured to electrically disconnect the first and second sampling terminals during a sampling phase and electrically connect the first and second sampling terminals during a transfer phase. The circuit also includes a DAC having a third capacitor coupled between a first summing terminal and a first DAC terminal, and a fourth capacitor coupled between the second summing terminal and a second DAC terminal. The DAC includes a second NMOS transistor and a second PMOS transistor, which are coupled in parallel and configured to electrically connect a first DAC output and a first DAC terminal during a transfer phase and electrically disconnect the first DAC output and the first DAC terminal during a sampling phase. The DAC also includes a third NMOS transistor and a third PMOS transistor, which are coupled in parallel and configured to electrically connect a second DAC output and a second DAC terminal during a transfer phase and electrically disconnect the second DAC output and the second DAC terminal during a sampling phase. In another aspect of this disclosure, a gate signal is applied to the gate terminals of the first, second, and third PMOS transistors. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors, thereby turning on the first PMOS transistor at a slower rate than the second and third PMOS transistors. Moreover, after the second and third PMOS transistors are fully turned on but before the first PMOS transistor is fully turned on, the gate signal is applied to the gate terminals of the first, second, and third NMOS transistors to minimize negative voltage transients at the first and second summing nodes during the transfer phase.

[0013] In another aspect of this disclosure, a method reduces charge loss at the summation terminals of an analog-to-digital converter (ADC) connected to a digital-to-analog converter (DAC) by controlling the timing of the PMOS and NMOS transistors of an ADC and a DAC. The method includes applying corresponding gate signals to the gate terminals of a first PMOS transistor of the ADC and the gate terminals of second and third PMOS transistors of the DAC. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors. As a result, the first PMOS transistor of the ADC turns on at a slower rate than the second and third PMOS transistors of the DAC. After the second and third PMOS transistors of the DAC are fully turned on but before the first PMOS transistor is fully turned on, the method includes applying a gate signal with a rising edge to the gate terminals of the first NMOS transistor of the ADC and the gate terminals of the second and third NMOS transistors of the DAC. As a result, the first NMOS transistor of the ADC and the second and third NMOS transistors of the DAC turn on at approximately the same rate. Attached Figure Description

[0014] Figure 1 This is a circuit according to an exemplary embodiment.

[0015] Figures 2A-2C The illustration shows a switch according to an exemplary embodiment.

[0016] Figures 3A-3B and Figures 4A-4B It is a timing diagram of the gate signal and voltage waveform. Detailed Implementation

[0017] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, which show some, but not all, embodiments. In fact, these concepts may be embodied in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided to satisfy applicable requirements of this disclosure.

[0018] Figure 1 This is a circuit 100 according to an exemplary embodiment of the present disclosure. Circuit 100 includes an analog-to-digital converter (ADC) 104, the first-stage integrator 108 of which is coupled at a first summing terminal or node 116 and a second summing terminal or node 120 to a single-bit or multi-bit DAC 112A-112N. The terms "terminal" and "node" are used interchangeably herein. Circuit 100 reduces charge loss at summing terminals or nodes 116 and 120 during the transfer phase by controlling the operation of the PMOS and NMOS transistors of the ADC 104 and DAC 112A-112N.

[0019] refer to Figure 1ADC 104 includes differential input terminals 121 and 122 that can be coupled to receive an analog input voltage. Differential input terminal 121 is coupled to a first sampling terminal or node 124 via an input switch S_INP, and differential input terminal 122 is coupled to a second sampling terminal or node 128 via an input switch S_INN. ADC 104 also includes a first capacitor C1 coupled between the first sampling terminal or node 124 and a first summing terminal or node 116. ADC 104 also includes a second capacitor C2 coupled between the second sampling terminal or node 128 and the second summing terminal or node 120. ADC 104 also includes a first switch S1 coupled between the first sampling terminal or node 124 and the second sampling terminal or node 128. The first switch S1 is configured to electrically disconnect the first sampling terminal or node 124 and the second sampling terminal or node 128 during a sampling phase and to electrically connect the first sampling terminal or node 124 and the second sampling terminal or node 128 during a transfer phase.

[0020] Continue to refer to Figure 1 DAC 112A includes a third capacitor C3 coupled between a first summing terminal 116 and a first DAC terminal 132, and a fourth capacitor C4 coupled between a second summing terminal 120 and a second DAC terminal 136. DAC 112A also includes a second switch S2 configured to electrically connect the first DAC output 140 and the first DAC terminal 132 during a pass phase and to electrically disconnect the first DAC output 140 and the first DAC terminal 132 during a sampling phase. DAC 112A also includes a third switch S3 configured to electrically connect the second DAC output 144 and the second DAC terminal 136 during a pass phase and to electrically disconnect the second DAC output 144 and the second DAC terminal 136 during a sampling phase.

[0021] Continue to refer to Figure 1 The ADC 104 includes a fourth switch S4 configured to electrically connect the first summing terminal 116 and the second summing terminal 120 during the sampling phase and to electrically disconnect the first summing terminal 116 and the second summing terminal 120 during the transfer phase. The DAC 112A includes a fifth switch S5 configured to electrically connect the first DAC terminal 132 and the second DAC terminal 136 during the sampling phase and to electrically disconnect the first DAC terminal 132 and the second DAC terminal 136 during the transfer phase.

[0022] Continue to refer to Figure 1The ADC 104 includes a differential integrator 150 having a first input 154 coupled to a first summing terminal 116 via a switch S6 during the transfer phase, and the ADC 104 also includes a second input 158 ​​coupled to a second summing terminal 120 via a switch S7 during the transfer phase. The differential integrator 150 includes an integrating capacitor C5 coupled between its first input 154 and its first output 162, and also includes an integrating capacitor C6 coupled between its second input 158 ​​and its second output 166.

[0023] During operation, during the sampling phase, switches S1, S2, S3, S6, and S7 are open, while switches S_INP, S_INN, S4, and S5 are closed, thereby providing capacitors C1 and C2 with the analog input voltage. Vin The charging conduction path. During the conduction phase, switches S1, S2, S3, S6, and S7 are closed, while switches S_INP, S_INN, S4, and S5 are open, thus providing a conduction path for the charge from capacitors C1, C2, C3, and C4 to combine at summing terminals 116 and 120. Most of the charge from capacitors C1, C2, C3, and C4 cancels each other out at summing terminals 116 and 120, causing the remaining charge to be integrated by differential integrator 150.

[0024] Figure 2A The switch S1 is illustrated in more detail. In an exemplary embodiment of this disclosure, the switch S1 includes a first NMOS transistor N1 and a first PMOS transistor P1 coupled in parallel, and the parallel-coupled transistors N1 and P1 are connected between a first sampling node 124 and a second sampling node 128. The first NMOS transistor N1 and the first PMOS transistor P1 include respective source terminals, drain terminals, and gate terminals. The drain terminal of the first NMOS transistor N1 is coupled to the source terminal of the first PMOS transistor P1, and the source terminal of the first NMOS transistor N1 is coupled to the drain terminal of the first PMOS transistor P1. The first NMOS transistor N1 and the first PMOS transistor P1 are operable to electrically disconnect the first sampling terminal 124 and the second sampling terminal 128 during a sampling phase and to electrically connect the first sampling terminal 124 and the second sampling terminal 128 during a transfer phase.

[0025] Continue to refer to Figure 2AThe driver circuit U1 is configured to control the operation of the first NMOS transistor N1 and the first PMOS transistor N2. During the transfer phase, the driver circuit U1 applies a gate signal to the gate terminals of the first NMOS transistor N1 and the first PMOS transistor P2 to turn on the first NMOS transistor N1 and the first PMOS transistor P2, and removes the gate signal from the gate terminals of the first NMOS transistor N1 and the first PMOS transistor P2 during the sampling phase to turn off the first NMOS transistor N1 and the first PMOS transistor P2.

[0026] Figure 2B The switch S2 is illustrated in more detail. In an exemplary embodiment of this disclosure, the switch S2 includes a second NMOS transistor N2 and a second PMOS transistor P2 coupled in parallel, and the parallel-coupled transistors N2 and P2 are connected between the first DAC terminal 132 and the first DAC output 140. The second NMOS transistor N2 and the second PMOS transistor P2 include respective source terminals, drain terminals, and gate terminals. The drain terminal of the second NMOS transistor N2 is coupled to the source terminal of the second PMOS transistor P2, and the source terminal of the second NMOS transistor N2 is coupled to the drain terminal of the second PMOS transistor P2. The second NMOS transistor N2 and the second PMOS transistor P2 are operable to electrically disconnect the first DAC output 140 and the first DAC terminal 132 during the sampling phase and to electrically connect the first DAC output 140 and the first DAC terminal 132 during the pass phase. Figure 2C Switch S3 is illustrated in more detail. Switch S3 includes a third NMOS transistor N3 and a third PMOS transistor P3 coupled in parallel, and the parallel-coupled transistors N3 and P3 are connected between the second DAC terminal 136 and the second output 144. The configuration and operation of switch S3 are similar to those of switch S2.

[0027] Continue to refer to Figure 2B and Figure 2CThe driver circuit U2 is configured to control the operation of the second NMOS transistor N2 and the second PMOS transistor P2, as well as the operation of the third NMOS transistor N3 and the third PMOS transistor P3. During the pass-through phase, the driver circuit U2 applies a gate signal to the gate terminals of the second NMOS transistor N2 and the second PMOS transistor P2 to turn them on, and removes the gate signal from the gate terminals of the second NMOS transistor N2 and the second PMOS transistor P2 during the sampling phase to turn them off. The driver circuit U2 also applies a gate signal to the gate terminals of the third NMOS transistor N3 and the third PMOS transistor P3 during the pass-through phase to turn them on, and removes the gate signal from the gate terminals of the third NMOS transistor N3 and the third PMOS transistor P3 during the sampling phase to turn them off.

[0028] In an exemplary embodiment of this disclosure, during the transfer phase, negative transient voltages at summing terminals 116 and 120 are prevented by controlling and sequencing the timing of the PMOS and NMOS transistors of switches S1, S2, and S3 to reduce charge loss. More specifically, the gate signal applied to the gate terminal of the first PMOS transistor P1 has a slower falling edge than the gate signals applied to the gate terminals of both the second PMOS transistor P2 and the third PMOS transistor P3. Because the gate signal applied to the gate terminal of the first PMOS transistor P1 has a lower negative slope than the gate signals applied to the gate terminals of the second PMOS transistor P2 and the third PMOS transistor P3, the second PMOS transistor P2 and the third PMOS transistor P3 turn on at a faster rate than the first PMOS transistor P1.

[0029] After the second PMOS transistor P2 and the third PMOS transistor P3 are fully turned on, but before the first PMOS transistor is fully turned on, a rising-edge gate signal is applied to the gate terminals of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3. Therefore, the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are turned on almost simultaneously.

[0030] Figure 3A This is a timing diagram illustrating the gate signals applied to the gate terminals of PMOS transistors P1, P2, and P3, and the gate terminals of NMOS transistors N1, N2, and N3. (Reference) Figure 3AAt t=1ns, gate signal 304 is applied to the gate terminal of the first PMOS transistor P1, while gate signal 308 is applied to the terminals of both the second PMOS transistor P2 and the third PMOS transistor P3. Although gate signals 304 and 308 are applied almost simultaneously, the falling edge of gate signal 304 is slower than the falling edge of gate signal 308. As a result, the first PMOS transistor P1 turns on at a slower rate than the second PMOS transistor P2 and the third PMOS transistor P3.

[0031] After the second PMOS transistor P2 and the third PMOS transistor P3 are fully turned on, but before the first PMOS transistor P1 is fully turned on, the gate signal 312 is applied to the gate terminals of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3. Because the same gate signal with a rising edge is applied to the first, second, and third NMOS transistors, the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 turn on at approximately the same rate.

[0032] Therefore, in an exemplary embodiment of this disclosure, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are turned on before the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3. Furthermore, the first PMOS transistor P1 turns on at a slower rate than PMOS transistors P2 and P3. Since PMOS transistors P2 and P3 conduct first the higher of the two voltages present at outputs 140 and 144, and also because PMOS transistor P1 conducts first the higher of the two voltages present at sampling nodes 124 and 128, and also because P1, P2, and P3 are turned on before N1, N2, and N3, the voltages at summing nodes 116 and 120 will begin to rise.

[0033] After PMOS transistors P1, P2, and P3 are turned on, NMOS transistors N1, N2, and N3 are turned on to complete the charge redistribution at summing terminals 116 and 120 during the transfer phase. By turning on PMOS transistors P1, P2, and P3 first and delaying the turn-on of NMOS transistors N1, N2, and N3, the voltage at summing terminals 116 and 120 preemptively rises to compensate for the subsequent voltage dip caused by the charge from the capacitor. NMOS switches N1, N2, and N3 are turned on approximately simultaneously to minimize the negative transient voltage at summing terminals 116 and 120.

[0034] Figure 3BThe diagram illustrates timing diagrams of voltage waveforms 316 and 320 obtained at summing terminals 116 and 120, respectively, during the propagation phases in response to gate signals 304, 308, and 312. By controlling the timing of gate signals 304, 308, and 312 during the propagation phases, the voltages at summing terminals 116 and 120 are maintained approximately 200 mV above ground potential, thereby preventing negative transient voltages at summing terminals 116 and 120. As a result, charge loss is reduced, thereby reducing gain error, gain error drift, and minimizing degradation of nonlinear performance.

[0035] Figure 4A This is a timing diagram of gate signals 404 and 408 whose timing is uncontrolled according to this disclosure. During the transfer phase, when gate signal 404 is applied to the gate terminals of PMOS transistors P1, P2 and P3 and gate signal 408 is applied to the gate terminals of NMOS transistors N1, N2 and N3, a negative transient voltage appears at summing terminals 116 and 120 during the transfer phase. Figure 4B This is a timing diagram of voltage waveforms 420 and 424 obtained at summing terminals 116 and 120 in response to gate signals 404 and 408 whose timing is uncontrolled according to this disclosure. Because the timing of gate signals 404 and 408 is uncontrolled, voltage waveforms 420 and 424 both exhibit negative transient drops during the propagation phase. Specifically, the voltage at summing terminal 116 drops below -400mV, resulting in charge loss and performance degradation. Figure 3B and Figure 4B The comparison clearly shows that by controlling the timing of the PMOS transistor and the NMOS transistor according to this disclosure, negative transient voltage at the summing terminal is prevented, thereby reducing charge loss and performance degradation.

[0036] In one aspect of this disclosure, a method reduces charge loss at the summation terminals of an analog-to-digital converter (ADC) connected to a digital-to-analog converter (DAC) by controlling the timing of the PMOS and NMOS transistors of the ADC and DAC. The method includes applying corresponding gate signals to the gate terminals of a first PMOS transistor of the ADC and the gate terminals of a second and third PMOS transistor of the DAC. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors. As a result, the first PMOS transistor of the ADC turns on at a slower rate than the second and third PMOS transistors of the DAC.

[0037] After the second and third PMOS transistors of the DAC are fully turned on but before the first PMOS transistor is fully turned on, the method includes applying a gate signal with a rising edge to the gate terminal of the first NMOS transistor of the ADC and the gate terminals of the second and third NMOS transistors of the DAC. As a result, the first NMOS transistor of the ADC and the second and third NMOS transistors of the DAC turn on at approximately the same rate. The method also includes turning off the first NMOS transistor and the first PMOS transistor of the ADC during the sampling phase to electrically disconnect the first and second sampling terminals of the ADC. The method further includes turning on the second NMOS transistor and the second PMOS transistor of the DAC during the transfer phase to electrically connect the first DAC output and the first DAC terminal. The method further includes turning on the third NMOS transistor and the third PMOS transistor of the DAC during the transfer phase to electrically connect the second DAC output and the second DAC terminal.

[0038] The functions of the various illustrative components, blocks, modules, circuits, and steps have been described in general terms above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the system as a whole. The described functionality may be implemented in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0039] For the sake of simplicity and clarity, the complete structure and operation of all systems suitable for use with this disclosure are not depicted or described herein. Instead, only systems unique to this disclosure or necessary for understanding this disclosure are depicted and described.

Claims

1. A circuit for reducing charge loss, comprising: Analog-to-digital converters (ADCs) include: A first capacitor is coupled between a first sampling terminal and a first summing terminal; A second capacitor is coupled between the second sampling terminal and the second summing terminal; A first NMOS transistor and a first PMOS transistor are coupled in parallel, and the first NMOS transistor and the first PMOS transistor are configured to electrically disconnect the first sampling terminal and the second sampling terminal during the sampling phase and electrically connect the first sampling terminal and the second sampling terminal during the transfer phase. as well as Digital-to-analog converters (DACs) include: A third capacitor is coupled between the first summing terminal and the first DAC terminal; A fourth capacitor is coupled between the second summing terminal and the second DAC terminal; A second NMOS transistor and a second PMOS transistor are coupled in parallel, the second NMOS transistor and the second PMOS transistor being configured to electrically connect the first DAC output and the first DAC terminal during the transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase; A third NMOS transistor and a third PMOS transistor are coupled in parallel, the third NMOS transistor and the third PMOS transistor being configured to electrically connect the second DAC output and the second DAC terminal during the transfer phase and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase. Specifically, corresponding gate signals are applied to the gate terminals of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, wherein the gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second PMOS transistor and the third PMOS transistor. Furthermore, after the second PMOS transistor and the third PMOS transistor are fully turned on but before the first PMOS transistor is fully turned on, a gate signal is applied to the gate terminals of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor.

2. The circuit according to claim 1, wherein, The first PMOS transistor turns on at a slower rate than the second PMOS transistor and the third PMOS transistor.

3. The circuit according to claim 1, wherein, After the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are turned on, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned on.

4. The circuit according to claim 1, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the first PMOS transistor and the first NMOS transistor to electrically disconnect the first sampling terminal and the second sampling terminal.

5. The circuit according to claim 1, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the second PMOS transistor and the second NMOS transistor to electrically disconnect the first DAC output and the first DAC terminal.

6. The circuit according to claim 1, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the third PMOS transistor and the third NMOS transistor to electrically disconnect the second DAC output and the second DAC terminal.

7. The circuit according to claim 1, wherein, The ADC includes a fourth switch configured to electrically connect the first summing terminal and the second summing terminal during the sampling phase and to electrically disconnect the first summing terminal and the second summing terminal during the transfer phase.

8. The circuit according to claim 1, wherein, The DAC includes a fifth switch configured to electrically connect the first DAC terminal and the second DAC terminal during the sampling phase and to electrically disconnect the first DAC terminal and the second DAC terminal during the transfer phase.

9. The circuit according to claim 1, wherein, The ADC includes a differential integrator having a first input and a second input, the first input and the second input being coupled to respective first summing terminals and second summing terminals during the transfer phase to integrate the remaining charge at the first summing terminal and the second summing terminal.

10. A circuit for reducing charge loss, comprising: Analog-to-digital converters (ADCs) include: A first capacitor is coupled between a first sampling terminal and a first summing terminal; A second capacitor is coupled between the second sampling terminal and the second summing terminal; A first NMOS transistor and a first PMOS transistor, the first NMOS transistor and the first PMOS transistor having respective source terminals, drain terminals and gate terminals, the drain terminal of the first NMOS transistor being coupled to the source terminal of the first PMOS transistor, and the source terminal of the first NMOS transistor being coupled to the drain terminal of the first PMOS transistor, the first PMOS transistor and the second PMOS transistor being operable to electrically disconnect the first sampling terminal and the second sampling terminal during a sampling phase and electrically connect the first sampling terminal and the second sampling terminal during a transfer phase; as well as Digital-to-analog converters (DACs) include: A third capacitor is coupled between the first summing terminal and the first DAC terminal; A fourth capacitor is coupled between the second summing terminal and the second DAC terminal; A second NMOS transistor and a second PMOS transistor, the second NMOS transistor and the second PMOS transistor having respective drain terminals, source terminals and gate terminals, the drain terminal of the second NMOS transistor being coupled to the source terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor being coupled to the drain terminal of the second PMOS transistor, the second NMOS transistor and the second PMOS transistor being operable to electrically connect the first DAC output and the first DAC terminal during the transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase; A third NMOS transistor and a third PMOS transistor, each having a corresponding drain terminal, source terminal, and gate terminal, wherein the drain terminal of the third NMOS transistor is coupled to the source terminal of the third PMOS transistor, and the source terminal of the third NMOS transistor is coupled to the drain terminal of the third PMOS transistor, the third NMOS transistor and the third PMOS transistor being operable to electrically connect the second DAC output and the second DAC terminal during the transfer phase, and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase. Specifically, corresponding gate signals are applied to the gate terminals of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, wherein the gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second PMOS transistor and the third PMOS transistor. Furthermore, after the second PMOS transistor and the third PMOS transistor are fully turned on but before the first PMOS transistor is fully turned on, a corresponding gate signal is applied to the gate terminals of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor.

11. The circuit according to claim 10, wherein, The first PMOS transistor turns on at a slower rate than the second PMOS transistor and the third PMOS transistor.

12. The circuit according to claim 10, wherein, After the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are turned on, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned on.

13. The circuit according to claim 10, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the first PMOS transistor and the first NMOS transistor to electrically disconnect the first sampling terminal and the second sampling terminal.

14. The circuit according to claim 10, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the second PMOS transistor and the second NMOS transistor to electrically disconnect the first DAC terminal and the first DAC output.

15. The circuit according to claim 10, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the third PMOS transistor and the third NMOS transistor to electrically disconnect the second DAC terminal and the second DAC output.

16. The circuit according to claim 10, wherein, The ADC includes a fourth switch configured to electrically connect the first summing terminal and the second summing terminal during the sampling phase and to electrically disconnect the first summing terminal and the second summing terminal during the transfer phase.

17. The circuit of claim 10, further comprising: An ADC gate driver configured to apply the corresponding gate signal to the gate terminals of the first PMOS transistor and the first NMOS transistor; as well as A DAC gate driver configured to apply corresponding gate signals to the gate terminals of the second PMOS transistor and the second NMOS transistor, and to the gate terminals of the third PMOS transistor and the third NMOS transistor. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors.

18. A circuit for reducing charge loss, comprising: Analog-to-digital converters (ADCs) include: A first capacitor is coupled between a first sampling terminal and a first summing terminal; A second capacitor is coupled between the second sampling terminal and the second summing terminal; A first NMOS transistor and a first PMOS transistor, the first NMOS transistor and the first PMOS transistor having respective drain terminals, source terminals and gate terminals, the drain terminal of the first NMOS transistor being coupled to the source terminal of the first PMOS transistor, and the source terminal of the first NMOS transistor being coupled to the drain terminal of the first PMOS transistor, the first NMOS transistor and the first PMOS transistor being operable to electrically disconnect the first sampling terminal and the second sampling terminal during a sampling phase and to electrically connect the first sampling terminal and the second sampling terminal during a transfer phase; An ADC gate driver configured to apply a corresponding gate signal to the gate terminals of the first PMOS transistor and the first NMOS transistor; A differential integrator having a first input and a second input coupled to the respective first summing terminal and second summing terminal during the transfer phase to integrate the residual charge at the first summing terminal and the second summing terminal; Digital-to-analog converters (DACs) include: A third capacitor is coupled between the first summing terminal and the first DAC terminal; A fourth capacitor is coupled between the second summing terminal and the second DAC terminal; A second NMOS transistor and a second PMOS transistor, the second NMOS transistor and the second PMOS transistor having respective drain terminals, source terminals and gate terminals, the drain terminal of the second NMOS transistor being coupled to the source terminal of the second PMOS transistor, and the source terminal of the second NMOS transistor being coupled to the drain terminal of the second PMOS transistor, the second NMOS transistor and the second PMOS transistor being operable to electrically connect the first DAC output and the first DAC terminal during the transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase; A third NMOS transistor and a third PMOS transistor, the third NMOS transistor and the third PMOS transistor having respective drain terminals, source terminals and gate terminals, the drain terminal of the third NMOS transistor being coupled to the source terminal of the third PMOS transistor, and the source terminal of the third NMOS transistor being coupled to the drain terminal of the third PMOS transistor, the third NMOS transistor and the third PMOS transistor being operable to electrically connect the second DAC output and the second DAC terminal during the transfer phase, and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase; A DAC gate driver configured to apply corresponding gate signals to the gate terminals of the second PMOS transistor and the second NMOS transistor, as well as the gate terminals of the third PMOS transistor and the third NMOS transistor. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors. Furthermore, the gate signal is applied to the gate terminals of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor after the second PMOS transistor and the third PMOS transistor are fully turned on but before the first PMOS transistor is fully turned on.

19. The circuit according to claim 18, wherein, The first PMOS transistor turns on at a slower rate than the second PMOS transistor and the third PMOS transistor.

20. The circuit according to claim 18, wherein, After the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are turned on, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned on.

21. The circuit according to claim 18, wherein, The ADC includes a fourth switch configured to electrically connect the first summing terminal and the second summing terminal during the sampling phase and to electrically disconnect the first summing terminal and the second summing terminal during the transfer phase.

22. The circuit according to claim 18, wherein, The DAC includes a fifth switch configured to electrically connect the first DAC terminal and the second DAC terminal during the sampling phase and to electrically disconnect the first DAC terminal and the second DAC terminal during the transfer phase.

23. The circuit according to claim 18, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the first PMOS transistor and the first NMOS transistor to electrically disconnect the first sampling terminal and the second sampling terminal.

24. The circuit according to claim 18, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the second PMOS transistor and the second NMOS transistor, as well as the gate terminals of the third PMOS transistor and the third NMOS transistor.

25. A circuit for reducing charge loss, comprising: Analog-to-digital converters (ADCs) include: First summing terminal and second summing terminal; A first capacitor is coupled between a first sampling terminal and a first summing terminal; A second capacitor is coupled between the second sampling terminal and the second summing terminal; A first NMOS transistor and a first PMOS transistor are coupled in parallel between the first sampling terminal and the second sampling terminal, and are configured to electrically disconnect the first sampling terminal and the second sampling terminal during the sampling phase and electrically connect the first sampling terminal and the second sampling terminal during the transfer phase. as well as Digital-to-analog converters (DACs) include: A third capacitor is coupled between the first summing terminal and the first DAC terminal; A fourth capacitor is coupled between the second summing terminal and the second DAC terminal; A second NMOS transistor and a second PMOS transistor are coupled in parallel and configured to electrically connect the first DAC output and the first DAC terminal during the transfer phase and to electrically disconnect the first DAC output and the first DAC terminal during the sampling phase. A third NMOS transistor and a third PMOS transistor, the third NMOS transistor and the third PMOS transistor being coupled in parallel and configured to electrically connect the second DAC output and the second DAC terminal during the transfer phase and to electrically disconnect the second DAC output and the second DAC terminal during the sampling phase. In this embodiment, a corresponding gate signal is applied to the gate terminals of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, and wherein the gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second PMOS transistor and the third PMOS transistor, thereby turning on the first PMOS transistor at a slower rate than the second PMOS transistor and the third PMOS transistor. Furthermore, after the second and third PMOS transistors are fully turned on but before the first PMOS transistor is fully turned on, a gate signal is applied to the gate terminals of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor to prevent negative transient voltages at the first summing terminal and the second summing terminal during the transfer phase.

26. The circuit according to claim 25, wherein, After the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are turned on, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are turned on.

27. The circuit according to claim 25, wherein, During the sampling phase, the gate signal is removed from the gate terminals of the first PMOS transistor and the first NMOS transistor to electrically disconnect the first sampling terminal and the second sampling terminal.

28. The circuit of claim 25, further comprising: An ADC gate driver configured to apply the corresponding gate signal to the gate terminals of the first PMOS transistor and the first NMOS transistor; as well as A DAC gate driver configured to apply corresponding gate signals to the gate terminals of the second PMOS transistor and the second NMOS transistor, and to the gate terminals of the third PMOS transistor and the third NMOS transistor. The gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors.

29. The circuit of claim 25, further comprising a differential integrator having a first input and a second input coupled to the respective first summing terminal and second summing terminal during the transfer phase for integrating the residual charge at the first summing terminal and the second summing terminal.

30. A method for reducing charge loss at a summation terminal of an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) by controlling the operation of a PMOS transistor and an NMOS transistor, the method comprising: A corresponding gate signal is applied to the gate terminal of the first PMOS transistor of the ADC and the gate terminals of the second and third PMOS transistors of the DAC, wherein the gate signal applied to the first PMOS transistor has a slower falling edge than the gate signals applied to the second and third PMOS transistors, and wherein the first PMOS transistor of the ADC turns on at a slower rate than the second and third PMOS transistors of the DAC; and After the second PMOS transistor and the third PMOS transistor are fully turned on, but before the first PMOS transistor is fully turned on, a corresponding gate signal is applied to the gate terminal of the first NMOS transistor of the ADC and the gate terminals of the second NMOS transistor and the third NMOS transistor of the DAC, wherein the gate signal applied to the first NMOS transistor of the ADC and the gate signal applied to the second NMOS transistor and the third NMOS transistor of the DAC have the same rising edge.

31. The method of claim 30, further comprising turning on the first NMOS transistor of the ADC and the second NMOS transistor and the third NMOS transistor of the DAC at the same rate.

32. The method of claim 30, further comprising, after the first PMOS transistor of the ADC and the second PMOS transistor and the third PMOS transistor of the DAC are turned on, turning on the first NMOS transistor of the ADC and the second NMOS transistor and the third NMOS transistor of the DAC.

33. The method of claim 30, further comprising turning on the first NMOS transistor and the first PMOS transistor of the ADC during the transfer phase to electrically connect the first sampling terminal and the second sampling terminal of the ADC.

34. The method of claim 30, further comprising turning off the first NMOS transistor and the first PMOS transistor of the ADC during the sampling phase to electrically disconnect the first sampling terminal and the second sampling terminal of the ADC.

35. The method of claim 30, further comprising turning on the second NMOS transistor and the second PMOS transistor of the DAC during the transfer phase to electrically connect the first DAC output and the first DAC terminal.

36. The method of claim 30, further comprising turning on the third NMOS transistor and the third PMOS transistor of the DAC during the transfer phase to electrically connect the second DAC output and the second DAC terminal.

37. The method of claim 30, further comprising turning off the second NMOS transistor and the second PMOS transistor of the DAC during the sampling phase to electrically disconnect the first DAC output and the first DAC terminal.

38. The method of claim 30, further comprising turning off the third NMOS transistor and the third PMOS transistor of the DAC during the sampling phase to electrically disconnect the second DAC output and the second DAC terminal.

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