System and method for single cycle dynamic hysteresis error control

Abstract

A signal quantization module comprising: a combining module configured to combine an input signal and a feedback signal to generate a combined signal; an integrator module coupled to the combining module and configured to generate an integrated signal using the combined signal; and a quantizer configured to generate an output signal based at least in part on the integrated signal, wherein the output signal is fed back to provide the feedback signal to the combining module and the integrator module, and wherein the quantizer is further configured to, when the quantizer is triggered at a first point in time, compare an input to the quantizer to a threshold hysteresis, and in response to the input to the quantizer reaching the threshold hysteresis, adjust the threshold hysteresis by an amount that characterizes a difference between a target hysteresis and the input to the quantizer at the first point in time.

Description

Technical Field

[0001] This invention generally relates to signal processing apparatus, and more particularly to apparatus for providing discrete or quantized outputs. Specific embodiments of the invention relate to mixed-signal circuitry, for example, combining analog and digital functions in an analog-to-digital converter. However, it should be understood that the invention is more broadly applicable to other applications. Background Technology

[0002] Hysteresis is a phenomenon where a system's response depends not only on the current input but also on the input history. Specifically, hysteresis introduces a tolerance band near a trigger threshold, causing the system to behave differently when the input rises compared to when it falls. Mixed-signal circuits typically include quantizers or comparators with hysteresis characteristics, where the input threshold used to drive the output from low to high differs from the input threshold used to drive the output from high to low. In this case, hysteresis often represents the minimum overdrive required to change the output, which can introduce a "dead zone," or a region of input values ​​where the output does not change despite input fluctuations.

[0003] Any discussion of the background art throughout the specification should not be construed as an admission that the art is common knowledge or constitutes part of common knowledge in the art. Summary of the Invention

[0004] In one aspect, an implementation provides a signal quantization module comprising: a combination module configured to combine an input signal and a feedback signal; an integrator module connected to the combination module and configured to generate an integral signal using a summing signal; and a quantizer clock-controlled and configured to generate an output signal at least partially based on the integral signal, wherein the output signal is fed back to provide feedback signals to a summing circuit and an integrator circuit, and wherein the quantizer is further configured to: compare the input of the quantizer with a threshold hysteresis at the edge of a clock cycle at which the quantizer is triggered at a first time point, and adjust the threshold hysteresis by an amount representing the difference between a target hysteresis and the input of the quantizer at the first time point in response to the input of the quantizer crossing the threshold hysteresis, the amount representing the difference between the target hysteresis and the input of the quantizer at the first time point.

[0005] The implementation may include one or more of the following features.

[0006] In the signal quantization module, when the quantizer is triggered at a second time point after the first time point, the quantizer can operate to compare its input at the second time point with a threshold hysteresis that has been adjusted based on a quantity determined at the first time point. In response to changes in the input signal to the signal quantization module, these changes can propagate through the module to affect the quantizer's output signal as early as one clock cycle later. The threshold hysteresis can include a symmetrical pair of positive and negative hysteresis levels.

[0007] The positive hysteresis level can be adjusted whenever the quantizer input exceeds the positive hysteresis level while the output signal is at a digital low level. The negative hysteresis level can be adjusted whenever the quantizer input falls below the negative hysteresis level while the output signal is at a digital high level. When the quantizer input exceeds the current positive hysteresis level, the amount used to adjust the positive hysteresis level is determined by the difference between the quantizer input and the current positive hysteresis level. When the quantizer input falls below the negative hysteresis level, the amount used to adjust the negative hysteresis level is determined by the difference between the negative hysteresis level and the quantizer input. When the quantizer input exceeds the positive hysteresis level, the amount used to adjust the positive hysteresis level is determined by averaging the first difference between the quantizer input and the target hysteresis, and the second difference between the target hysteresis and the quantizer input. When the quantizer input falls below the negative hysteresis level, the amount used to adjust the negative hysteresis level is also determined by averaging the first and second differences.

[0008] Threshold hysteresis can be adjusted at the edge of each clock cycle when the quantizer is triggered, ensuring that the difference between the target hysteresis and the quantizer input is tone-free. When the input signal is at a constant level above the quantization threshold of the quantizer, the output signal may not exhibit tone. The output signal spectrum exhibits a power level below 100dB between 20Hz and 20kHz. Clock cycle edges can include rising edges. Clock cycle edges can include falling edges. The clock is characterized by a frequency higher than the frequency of the output signal generated by the quantizer. The clock frequency can be up to 100 times higher than the frequency of the output signal.

[0009] The signal quantization module may further include: a limiter circuit connected to the quantizer, such that the range of the quantizer's output signal is limited. The signal quantization module may also include: a filter circuit connected to the output of the quantizer and configured to process the quantizer's output signal and generate a modulated signal for at least one downstream circuit connected to the signal quantization module. The signal quantization module may be a high-order modulator comprising cascaded multi-stage combination modules and integrator circuits. Each stage in the cascade may include an instance of a combination module and an instance of an integrator circuit connected to the combination module. Each integrator circuit may include a capacitor. Each combination module may include an operational amplifier configured to sum the input signal and a feedback signal and drive the integrator circuit connected to the operational amplifier. The quantizer may include a gated comparator. The signal quantization module may further include: a digital filter connected to the quantizer and configured to receive the output signal; and a decimation filter connected to the digital filter and configured to generate a digital signal output for the signal quantization module.

[0010] In another aspect, the implementation may include a signal quantization module comprising: a plurality of input terminals configured to receive a plurality of input signals that are sequential in time and characterized by a frequency range; a combiner coupled to the input terminals and configured to process the plurality of input signals; and an output port coupled to the combiner and configured to generate one of a set of predetermined levels based at least in part on a result from the combiner, wherein the signal quantization module is driven by a set of threshold hysteresis values, wherein the signal quantization module is operable to generate a series of trigger events that occur at frequencies exceeding the frequency range of the input signals, such that in a first trigger event of the series of trigger events, the output port generates an output based at least in part on the threshold hysteresis value and the result of the combiner processing the plurality of input signals, and in a second trigger event following the first trigger event, in response to the combiner's output exceeding one of the threshold hysteresis values ​​in the set of threshold hysteresis values, one or more threshold hysteresis values ​​are updated by an amount, the amount depending at least in part on the difference between a target hysteresis and the combiner's output in the first trigger event.

[0011] The implementation may include one or more of the following features.

[0012] The one or more threshold hysteresis events can be updated at least in part based on the difference between the target hysteresis and the combiner's output at the first trigger event, and the duration between the first and second trigger events. The first or second trigger event can be generated based on a clock external to the signal quantization module and is independent of the input signal. The second trigger event can be generated internally by the signal quantization module at least in part based on the duration since the first trigger event.

[0013] In one implementation, a signal quantizer for quantizing an input signal is provided, the signal quantizer including a dynamic hysteresis adjustment feedback loop for adjusting a hysteresis threshold, wherein the adjustment of the hysteresis threshold is based at least in part on the difference between the input of the quantizer and the target hysteresis level of the quantizer.

[0014] This adjustment can be made in response to repeated triggers.

[0015] Recurring triggers can include clock signals with regular clock cycles.

[0016] This adjustment can be made within the same clock cycle.

[0017] The signal quantizer may include a positive hysteresis threshold and a negative hysteresis threshold, and both the positive and negative hysteresis thresholds are adjusted in the same way.

[0018] The quantizer can include positive hysteresis thresholds and negative hysteresis thresholds, and the positive and negative hysteresis thresholds can be adjusted separately.

[0019] The input to the quantizer can be provided by a Δ-∑ (delta-sigma) modulator.

[0020] Signal quantizers can be part of analog-to-digital converters or digital-to-analog converters.

[0021] In another implementation, a method for operating the quantizer is provided, which includes: The sum of the input signal and the previous output of the accumulator is added together to generate the accumulated signal; In response to a trigger, the accumulated signal is compared with one or more thresholds; and When it is determined that the accumulated signal exceeds one or more thresholds, at least one of the one or more thresholds is selectively adjusted by an amount based at least in part on the difference between the accumulated signal and the target threshold.

[0022] In a further implementation, a threshold comparator is provided for comparing an input signal with a threshold. This threshold comparator includes a dynamic hysteresis adjustment feedback loop that adjusts the hysteresis threshold near the threshold. The adjustment of the hysteresis threshold is based at least in part on the difference between the comparator's input and the comparator's target hysteresis level.

[0023] Implementations of the invention can be carried out in computer-implemented methods, hardware computing systems, and tangible computer-readable media. For example, a system comprising one or more computers can be configured to perform specific actions by installing software, firmware, hardware, or combinations thereof on the system, which, in operation, cause the system to perform these actions. One or more computer programs can be configured to perform specific actions by including instructions that, when executed by a data processing device, cause the device to perform these actions.

[0024] Details of one or more implementations of the subject matter of this specification are set forth in the specification, claims, and drawings. Other features, aspects, and advantages of the subject matter will become apparent from the specification, claims, and drawings. Attached Figure Description

[0025] Exemplary embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, wherein:

[0026] Figure 1A An example of a graph of a first-order Σ-Δ modulator used in the prior art is shown.

[0027] Figures 1B to 1D Various waveforms and representative noise spectra associated with this example are shown.

[0028] Figure 2A An example of a graph of a second-order Σ-Δ modulator used in the prior art is shown.

[0029] Figures 2B to 2F Various waveforms and representative noise spectra associated with this example are shown.

[0030] Figures 3A-3B An example of a first-order Σ-Δ modulator with single-cycle dynamic hysteresis control according to an implementation of the present invention is shown.

[0031] Figures 3C-3E Various waveforms and representative noise spectra associated with this example are shown.

[0032] Figures 3C to 3H Comparable waveforms and representative noise spectra associated with a first-order Σ-Δ modulator under static hysteresis control are shown.

[0033] Figure 4AAn example of a graph of a second-order Σ-Δ modulator with single-cycle dynamic hysteresis control according to an implementation of the present invention is shown.

[0034] Figure 4B It shows Figure 4A A representative noise spectrum of the example.

[0035] Figure 4C A representative noise spectrum of a second-order Σ-Δ modulator under static hysteresis control is shown.

[0036] Figure 5A and Figure 5B The diagrams show a comparison and contrast of static hysteresis control and dynamic hysteresis control according to some implementations of the present invention.

[0037] Figure 6 A flowchart illustrating a method for operating a quantizer according to one implementation is shown.

[0038] The same reference numerals and symbols in the various figures indicate the same elements. Detailed Implementation

[0039] Embodiments of the invention will be described with reference to signal processing devices (such as signal quantizers) used to provide discrete or quantized outputs. The operation of these devices will be described in the context of mixed-signal circuits (such as analog-to-digital converters). However, it should be understood that the invention is applicable to a wider range of signal processing aspects, such as hysteresis controllers, event cameras, and machine learning models such as neural networks.

[0040] These devices are preferably suited for processing input signals that have a temporal sequence or temporal continuity (indicating that the information they contain changes over time).

[0041] As an example of a mixed-signal circuit, a Σ-Δ modulator converts a continuous analog or high-bit pulse code modulation (PCM) digital signal into a lower-bit output at a higher frequency, where the pulse density represents the signal level in the band of interest. For compatibility with Class D audio or power inverters (e.g., for electric vehicles such as electric vehicles (EVs), photovoltaic (PV) converters, generators, etc.), the output frequency is typically kept low enough to minimize power loss and distortion as required by the application. To achieve these desired properties using known techniques, a large number of successive stages are required to maintain a satisfactory signal-to-noise ratio (SNR) and total harmonic distortion (THD) through a process known as "noise shaping." The increased stages and noise shaping measures result in circuit complexity, additional delay / phase shift, reduced stability, spurious tones, and significant dead zones. However, the implementation of the present invention can achieve high oversampling rate (OSR) and low quantization noise in the band of interest using only two (2) or fewer stages, while reducing tone amplitude and pushing tone frequencies below the band of interest. These implementations incorporate a dynamic hysteresis error correction quantizer / comparator, which can be installed on various systems where the quantization error can be measured and used to dynamically correct the hysteresis error based on each trigger or clock cycle.

[0042] More specifically, these implementations focus on using the measured quantization error from one cycle for dynamic hysteresis adjustment to adjust the hysteresis threshold for the next or subsequent cycles, rather than polarity-based hysteresis or range-based quantizers. For example, US6,924,757 describes a method for varying the hysteresis based on the range of the input signal. This approach can result in step responses and potential instabilities, thus requiring multiple stages to maintain performance. In contrast, the implementations of this invention can adjust the hysteresis threshold every clock cycle (or a subset of clock cycles) to correct for instantaneous quantization errors (e.g., from the immediately preceding clock cycle), thereby significantly reducing the number of stages required to implement the circuitry's functionality. These implementations can allow the output switching frequency (Fsw) to slow down while maintaining a high clock frequency, where the accumulator will ramp up to positive and negative values ​​instead of simply changing polarity (e.g., switching). These features not only reduce quantization errors by several orders of magnitude but also typically eliminate dead time, even in single-stage designs. Furthermore, because the hysteresis threshold is variable and changes over time at a granular level of each clock cycle, the finite state machine (FSM) repetition of the tone is greatly expanded to include the number of possible states. Consequently, both the amplitude and frequency of the tone are significantly reduced. Additionally, some implementations can incorporate overflow protection, such as overflow protection for a single accumulator to ensure broad system stability. Among various implementations, overcurrent protection (OCP) can be combined with the Δ-Σ modulator so that inverters (e.g., those used in Class D audio amplifiers and EV motors) can have limit protection combined with the signal encoder.

[0043] These implementations incorporate low-complexity, single-bit, high-quality signal reproduction, which can be easily adapted to existing microcontrollers for mass-market high-quality signal conversion. Notably, these implementations provide a single-bit output natively compatible with the switching output stage, and this single-bit output is inherently linear when the transfer function has both full-scale positive and negative reference points, making multi-bit quantizers unnecessary. In various implementations, the output switching frequency (Fsw) is low enough to directly drive a Class D / power inverter without intermediate filtering and remodulation circuitry. It is noteworthy that these implementations are designed for single-cycle quantization error correction, which can be used, for example, in Σ-Δ modulators. For instance, these implementations produce ultra-low propagation delay due to low complexity and parallel quantization correction. Ultra-low propagation delay facilitates noise cancellation over wideband and enables low-latency variable frequency motor control. These implementations incorporate open-loop control, allowing analog volume control by controlling the output voltage without bit shifting, while maintaining the dynamic range of the output without bit loss. Furthermore, these implementations allow for stability protection. For example, real-time overcurrent protection (OCP) can be embedded in the quantizers or comparators of these implementations.

[0044] These implementations can drive similar nodes in large networks (e.g., neural networks) with improved hysteresis control. Nodes in this network can receive multiple input signals that are continuous in time and characterized by a frequency range. The network can include a combiner that combines the input signals and generates a single output value. When data representing a continuously updated source of information is presented to the network, the applied hysteresis quantization can improve the overall performance and linearity of the network's stochastic behavior, thereby improving performance by updating the weights of the inputs in the combiner through backpropagation of the error. In this way, these implementations can efficiently deploy both digital-based and analog-based neural networks, using synchronous (clocked) operation, or spontaneous or spike (internally generated triggering) operation, or any combination of operations.

[0045] These implementations can also improve the overall level and stability of event activation in sensors with numerous sensing and quantization units associated with physical inputs such as light. For example, in an event-based digital camera, each pixel generates an output at regular or irregular intervals based on detected events corresponding to changes in light intensity. The output can be in three states—rising, falling, or no event. In conventional designs, the selection of the output state, or the triggering of rising or falling events, is based on the output of a single light-related signal and a logarithmic or similar nonlinear combination. Using the disclosed implementations to provide updates to the hysteresis threshold associated with transition events allows for improved performance when representing changing input signals with fewer output events. In this way, the disclosed implementations can improve the operation of threshold comparators used for neuromorphic sensing.

[0046] Figure 1AA diagram 100 of a first-order Σ-Δ modulator used in the prior art is shown. As a logical illustration, diagram 100 shows electrical components (e.g., capacitors) represented as mathematical devices (e.g., a “Σ” accumulator). The input signal 101 (V_in) can be limited to, for example, a range of -1V to +1V. The summing circuit 102 represents a combination module where the current controlled by V_in and DAC is summed. This represents a “Δ” operation (e.g., V_in - V(DAC)). Here, DAC is an exponential analog-to-digital converter. V(DAC) represents the feedback signal from quantizer 104. Generally, V(DAC) represents the quantizer output. The result of the “Δ” operation is then accumulated in capacitor C1, which performs the “Σ” operation as represented by integrator 103. In an analog input system, integrator 103 can be an analog integrator, which can be implemented using either switched capacitor technology or standard analog linear technology. In a digital input system, integrator 103 is a discrete-time integrator implemented using standard digital hardware such as adders and registers.

[0047] Here, X1 is the output of integrator 103. Quantizer 104 is connected to integrator 103 to receive the output X1. Quantizer 104 outputs a high level when X1 is positive and a low level when X1 is negative. Quantizer 104 is time-gated by clock signal CLK, allowing its output to reach DAC+ (and its complementary signal DAC-) on each rising edge of the clock signal. The clock signal can be 50 MHz. Within the scope of this invention, the term "quantizer" (as a 1-bit quantizer) can be used interchangeably with "comparator". The output of quantizer 104 can be provided to a 1-bit digital-to-analog (DAC) converter (e.g., module 105) to provide a feedback signal (DAC-) to summing circuit 102. The output of quantizer 104 can also be provided to a digital filter or digital decimation filter, thereby producing a continuous output to drive downstream devices or components.

[0048] Figure 1B Figure 110 is shown from a macroscopic perspective, which includes [the following text is missing from the original] Figure 1A An example of the voltage waveform generated by the Σ-Δ modulator is shown in Figure 110. In Figure 110, V_in, corresponding to waveform 111, is a constant voltage of 100µV. This voltage is high enough to exceed the quantization threshold of quantizer 104. V(X1), corresponding to waveform 113, shows the integrator repetition mode and quantization error. The effect of the repetition mode can be seen in V(Out+), which corresponds to waveform 114, representing the filtered output of the comparator. For example, as described above, a two-stage output filter with a roll-off frequency of 50kHz can be used to filter the output of quantizer 104. Figure 1BThe V(DAC-) waveform shown in waveform 112 exhibits an average frequency of 23.75MHz, which may be too fast for a practical switching-mode power stage.

[0049] Figure 1C Figure 120 is shown from a microscopic perspective, which includes and Figure 1B The same example is used here, but the timescale has been magnified to better illustrate the effect of time quantization on integrator X1 and V(Out+). The step phenomenon in V(X1) at approximately 160µs corresponding to waveform 123 is due to the integrator requiring two clock cycles to trigger instead of triggering in one clock cycle previously. This step phenomenon causes a DC offset, as reflected in the filtered output of V(out+), corresponding to waveform 124. At this clock frequency, V(X1) corresponding to waveform 123 is in the peak-to-peak range of 42mV. Specifically, at... Figure 1C In the middle, due to the need for two (2) clock cycles for transition, the peak-to-peak voltage of X1 is approximately 40.27mV. Waveform 122 shows an enlarged view of V(DAC-), which exhibits an average frequency of 23.75MHz. Waveform 121 shows V_in, which is a constant voltage of 100µV that is high enough to exceed the quantization threshold of quantizer 104.

[0050] Figures 1B to 1C The results for quantization error and spurious tones at high switching frequency (Fsw) are shown, while Figures 1D to 1E The results for low Fsw quantization error and spurious tones are shown separately. For example, Figure 1D Figure 130 shows the waveform obtained when the clock signal is reduced to 1MHz. Therefore, the output switching frequency (Fsw) of V(DAC-) corresponding to waveform 132 is limited to around 500kHz. Here, a similar cyclic pattern is generated at a slower rate and with a larger quantization error. Notably, the peak-to-peak voltage of V(X1) corresponding to waveform 133 now exceeds 2.2V. Waveform 131 shows V_in, a constant voltage of 100µV that is high enough to exceed the quantization threshold of quantizer 104. Waveform 134 shows the filtered output V(Out+). Figure 1E Includes graph 140 showing the noise spectrum in the frequency band of interest. (e.g.) Figure 1E As shown, the noise level of the noise spectrum in the band of interest starts from -74dB (relative to 0dB corresponding to the maximum output).

[0051] Figure 2A An example of a graph 200 of a second-order Σ-Δ modulator used in the prior art is shown. (With) Figure 1ASimilarly, Figure 200 shows a logic diagram. The input signal 201 (V_in) can be limited to, for example, a range of -1V to +1V. The summing circuit 202 performs the summation of V_in and the current controlled by the DAC. The summation represents a "Δ" operation (e.g., V_in - V(DAC)). The result of the Δ operation is then accumulated in capacitor C1, which performs a "∑" operation, as shown in integrator 203. Here, X1 is the result signal of integrator 203, which is the first stage of the ∑-Δ modulator. The summing circuit 204 performs the summation of V(X1) and the current controlled by the DAC, and the result is then accumulated by integrator 205. Here, X2 is the result output of integrator 205. A quantizer 206 is connected to integrator 205 to receive the result output X2. Quantizer 206 outputs a high level when X2 is positive and a low level when X2 is negative. The quantizer 206 is time-gated by the clock signal CLK, allowing its output to reach DAC+ (and its complementary signal DAC-) on each rising edge of the clock signal. The output of the quantizer 206 can be provided to a 1-bit DAC (e.g., modules 207 and 208) to provide corresponding feedback signals to the summing circuits 202 and 204.

[0052] Figures 2B to 2F Various waveforms and representative noise spectra associated with a second-order Σ-Δ modulator are shown. For example, Figure 2B and Figure 2C Figure 210 (macro view) and Figure 220 (micro view) are shown respectively, each figure including a series of figures. Figure 2A Examples of voltage waveforms generated by the second-order Σ-Δ modulator are shown. For example, Figure 210 shows waveform 211 of V_in, where V_in is a constant voltage of 100µV, which is high enough for the quantization threshold of quantizer 206. Waveform 212 shows an example of V(DAC-), exhibiting an average frequency of 23.75MHz. Here, the clock frequency is 50MHz. As mentioned above, this frequency is too fast for a true switch-mode power stage. Waveforms 213 and 214 show examples of V(X1) and V(X2), respectively, illustrating the integrator repetition mode and quantization error. Waveform 215 shows an example of V(Out+) as a filtered representation of the comparator output. Figure 220 shows the same example in a microscopic view, where the time scale is magnified to better illustrate the effect of time quantization on integrators X1 and X2 and V(Out+). Here, waveforms 223, 224, and 225 correspond to V(X1), V(X2), and V(Out+), respectively. Waveforms 221 and 222 correspond to V(V_in) and V(DAC-), respectively. These examples demonstrate quantization error and spurious tones when using a high switching frequency (Fsw) at a clock frequency of 50 MHz.

[0053] In comparison, Figure 2D and Figure 2E The waveform produced by a slower switching frequency (Fsw) is shown. As shown in the figures, Graph 230 (macro view) and Graph 240 (micro view) include waveforms produced by... Figure 2A An example of a voltage waveform generated by a second-order Σ-Δ modulator with a clock signal of 1MHz. Using a clock frequency of 1MHz, the switching frequency (Fsw) of V(DAC-) (corresponding to...) Figure 2D Waveform 232 and Figure 2E The waveform (242) in the image is limited to approximately 500 kHz. This reduced switching frequency produces a similar cyclic pattern at a slower rate, although the quantization error is much larger. It is worth noting that, corresponding to... Figure 2D Waveform 233 and Figure 2E The waveform 243 in the image has V(X1) and the corresponding waveform V(X1) in the image. Figure 2D Waveforms 234 and Figure 2E The peak-to-peak voltages of both waveforms 244 and V(X2) exceed 2.2V. Figure 2D Waveform 231 and Figure 2E Waveform 241 in the figure shows V_in, which is a constant voltage of 100µV that is high enough to exceed the quantization threshold of quantizer 206. Figure 2D Waveform 235 and Figure 2E Waveform 245 in the figure shows the filtered output V(Out+). Figure 2F Includes Figure 250, which shows the resulting noise spectrum in the band of interest, with noise levels starting at -84 dB (relative to 0 dB corresponding to the maximum output).

[0054] Preferred embodiments of the invention will now be described.

[0055] First refer to Figure 6 The diagram illustrates a process flowchart of a method 600 for operating a quantizer according to one implementation. Method 600 includes accumulating the sum of the input signal and the past outputs of the quantizer in step 601 to generate an accumulated signal. This accumulation can be the result of a summing and integrating circuit in a Δ-Σ modulator as described above.

[0056] In step 602, in response to a trigger (e.g., a clock signal), the accumulated signal is compared with one or more target hysteresis thresholds. This comparison can be performed by feeding the accumulated signal to one or more comparators, in which one or more target thresholds represent hysteresis thresholds. The hysteresis threshold defines a range of input values ​​for which the comparator does not switch its output state. This range creates a threshold band or buffer to prevent frequent switching due to small fluctuations or noise in the input signal. The one or more comparators may have one hysteresis threshold, two hysteresis thresholds (e.g., an upper threshold and a lower threshold), or more than one number of hysteresis thresholds.

[0057] In step 603, it is determined whether the accumulated signal is greater than the corresponding target hysteresis threshold (or lower than the lower target hysteresis threshold). For the upper hysteresis threshold, if the accumulated signal is not greater than the threshold, control returns to step 601, and accumulation occurs at the start of the next trigger or clock cycle. Similarly, for the lower hysteresis threshold, if the accumulated signal is not less than the threshold, control returns to step 601, and accumulation occurs at the start of the next trigger or clock cycle. In this case, the quantizer still produces a quantized output, but the threshold is not adjusted.

[0058] In step 604, when it is determined that the accumulated signal exceeds one or more thresholds (or falls below one or more thresholds in the case of a lower hysteresis threshold), at least one of the one or more thresholds is selectively adjusted. For example, if an upper threshold is exceeded, that threshold is adjusted. In the case of multiple thresholds (e.g., an upper threshold and a lower threshold), these thresholds may be adjusted by the same or different amounts depending on the measured overshoot or undershoot. Specifically, the threshold(s) are adjusted based on the amount of difference between the accumulated signal and a target hysteresis threshold. The target hysteresis threshold is a predefined system parameter and may be based on a comparator reference level. In some embodiments, the target hysteresis threshold is set based on the target operating frequency of the quantizer. In some embodiments, the target hysteresis threshold is set based on the target application of the device in which the signal quantizer or signal quantization module operates. In some embodiments, the target threshold(s) may be changed. In some embodiments, the target hysteresis threshold is fixed over time. In other embodiments, the target hysteresis threshold may vary over time in conjunction with the dynamic hysteresis control described herein.

[0059] When dynamically adjusting the upper and lower hysteresis thresholds, the dynamic adjustment of the thresholds can be carried out independently of each other, or can be related to or proportional to each other.

[0060] In step 605, the quantizer state is changed to generate the quantizer output, and control returns to step 601 to apply the updated (one or more) hysteresis thresholds.

[0061] Now go to Figures 3A-3B An example of a first-order Σ-Δ modulator with single-cycle dynamic hysteresis control according to an implementation of the present invention is shown. Although these implementations are described with reference to a voltage signal, it should be understood that these implementations are equally applicable to a wide variety of other types of signals that can be processed.

[0062] For example, Figure 3A A diagram 300 of a first-order dynamic hysteresis Σ-Δ modulator according to some implementations of the present invention is shown. Diagram 300 is a logic diagram illustrating electrical components (e.g., capacitors) represented as mathematical devices (e.g., “Σ” accumulators). The input signal 301 (V_in) can be limited to, for example, a range between -1V and +1V. A combinational module in the form of a summing circuit 302 can perform the summation of the current controlled by V_in and the DAC. The summation represents a “Δ” operation, such as the operation provided by the V_in-DAC. The result of the Δ operation is then accumulated in capacitor C1 of integrator 303, which performs the “Σ” operation. Here, X1 is the output of integrator 303. A quantizer 304 is coupled to integrator 303 to receive the output X1.

[0063] The quantizer 304 operates with dynamic hysteresis control, in which a hysteresis threshold is adjusted each clock cycle. More generally, without a regular clock signal, the hysteresis threshold can be dynamically adjusted by another repeated trigger, either internally or externally. In cases where the quantizer 304 includes both high-level and low-level transitions, this adjustment may affect both low-to-high and high-to-low transitions, as illustrated in boxes 304A and 304B. Specifically, at the edge of the clock cycle or at the trigger signal when the quantizer is triggered, the quantizer can compare its input to a target hysteresis threshold. In response to the current input of the quantizer crossing the hysteresis threshold, the hysteresis threshold is adjusted according to an amount characterizing the difference between the target hysteresis threshold and the quantizer's input, so that the adjusted hysteresis threshold is applied the next time the quantizer is triggered (e.g., in the next clock cycle). In cases where the quantizer is incorporated into a Σ-Δ modulator, the quantizer's input represents the current accumulator value of the modulator. However, in other types of systems, the quantizer's input represents other inputs.

[0064] The dynamically adjusted hysteresis threshold represents the current error value used to modify system behavior to reduce quantization error. This differs from a target hysteresis threshold, which is either constant or can be modified independently over time. Importantly, in this invention, the amount of adjustment to the current hysteresis threshold is always at least partially based on or referenced to the level of the target hysteresis threshold. This is a significant difference from prior art systems (such as US6,924,757). In particular, it can be adjusted independently of the range of the input signal to be quantized.

[0065] As described above, the hysteresis threshold is adjusted based on the difference between the target hysteresis threshold and the quantizer input. Here, "difference" can refer to a precise difference calculation, such as simple subtraction, or it can represent the relative difference between two values ​​so that the applied correction reduces error or discrepancy in subsequent samples. In other words, the system uses this difference as an indicator of how much the target hysteresis threshold deviates and determines the correction that will reduce this difference. In some implementations, the adjustment may be a portion of the determined difference between the target hysteresis threshold and the quantizer input. In some implementations, the adjustment may be based on memory or knowledge of previous adjustments to the hysteresis threshold.

[0066] The quantizer 304 is time-gated by a clock signal CLK, allowing its output to reach DAC+ (and its complementary signal DAC-) as the quantizer is triggered at each edge of the clock signal. The edges can be rising edges, falling edges, or both. In some implementations, the quantizer is triggered at other times relative to the clock or trigger signal. The clock signal can be 50 MHz. The output of the quantizer 304 can be provided to a 1-bit digital-to-analog (DAC) converter (e.g., buffer module 305) to provide a feedback signal (DAC-) to the summing circuit 302. The output 306 of the quantizer 304 is also provided to a digital filter or digital decimation filter, thereby producing a continuous output to drive downstream devices or components.

[0067] Figure 3B Provided with Figure 3AA representative model of the same first-order dynamic hysteresis Σ-Δ modulator is shown in Figure 310. The input signal V_in (311) is modeled as a voltage source V1. The current controlled by the input signal V_in (311) and the feedback signal V(DAC-) (315) is summed at node 312, where a summing circuit can be implemented. This summation corresponds to a "Δ" operation (e.g., V_in - V(DAC)). The result of the Δ operation is then accumulated in an accumulator 313 with a capacitor C2 performing the "∑" operation. As shown, the accumulator 313 includes overflow protection, for example, using a limiting diode D2. Here, X1 is the output of the accumulator 313. A quantizer 314 is connected to the accumulator 313 to receive the output X1 as its input. The quantizer 314 includes a dynamic hysteresis comparator 314A, which is controlled by dynamic hysteresis, wherein a threshold hysteresis is adjusted at each clock cycle or repeated trigger time so that the adjusted threshold hysteresis is applied the next time the quantizer is triggered (e.g., in the next clock cycle). The threshold hysteresis adjustment is performed by updating the threshold hysteresis value(s) of the comparator(s) or other device(s) triggered from low to high (and vice versa). An initial target hysteresis threshold can be predefined and set based on the desired operating frequency of the device or the desired application. This target hysteresis threshold is then dynamically updated.

[0068] The quantizer 314 also includes a D flip-flop 314B time-gated by a clock signal CLK (represented as a voltage source V2 (316)). This configuration allows the output of the quantizer 314 to reach DAC+ (and its complementary signal DAC-) on each rising edge of the clock signal. The clock signal can be 50 MHz. The feedback signal (DAC-) is provided to the summing node 312 in the modeling diagram.

[0069] Figure 3CFigure 320 illustrates an example of dynamic hysteresis control according to some implementations of the present invention. In Figure 320, waveform 322 represents V(DAC-), and waveform 323 represents V(X1). Line 324 represents the target level (pos_Hyst) for positive hysteresis, which can be set to, for example, 500mV. Lines 329A and 329B represent the inputs of the quantizer. In this example, the target level (neg_Hyst) for negative hysteresis is set to -500mV. Line 321 represents the actual level of the dynamically updated hysteresis threshold pos_Hyst. Initially, lines 324 and 321 are identical, both 500mV in this example. At the first clock edge T1 when V(X1) is higher than line segment 321A, the quantizer output changes from high to low, causing V(X1) to drop. Segment 325D1 corresponds to the difference between the peak value of V(X1) at T1 and line 324. This difference is also known as the quantization error (Qerr), which in this example is the overshoot at T1. Subtracting the overshoot from the target hysteresis threshold pos_Hyst causes line 321 to drop, resulting in line segment 321B. At the next clock edge T2, when V(X1) is above line segment 321B, the difference between V(X1) and line 324 is measured. Here, the peak value of V(X1) is still slightly above line 324. Therefore, the difference represented by segment 325D2 is subtracted from line 321 again, pushing it down to line segment 321C. In the case of a third event T3 (not shown) where the peak value of V(X1) is below line 321, the quantization error will be negative, thus causing line 321 to rise by that amount. It is worth noting that a similar dynamic adjustment is performed on neg_Hyst, independent of the dynamic adjustment of pos_Hyst. Figure 3D Figure 330 is shown, which shows a macroscopic view of the single-cycle dynamic hysteresis quantizer error correction across more than 19 positive peaks across V (X1).

[0070] Figure 3E Figure 340 is shown, illustrating an example of the noise spectrum of a first-order Σ-Δ modulator with single-cycle dynamic hysteresis according to some implementations of the present invention. This noise spectrum covers the frequency band of interest within the audio range (e.g., from 20 Hz to 20 kHz). As described above, an input of 100 µV is used (to elicit a mode response). Here, the noise is below -100 dB with no noticeable tone, whereas in the case of static hysteresis, the worst tone is approximately -74 dB, as above. Figure 2F As shown. Therefore, improvements related to the implementation of the present invention have been confirmed.

[0071] Figure 3F and Figure 3GMacroscopic view 350 and microscopic view 360 of the waveform generated by the first-order static hysteresis Σ-Δ are shown, as described in US6,924,757B2, where hysteresis control is applied according to the range of the input voltage of the Σ-Δ modulator. Quantization error and spurious tones are shown in both macroscopic view 350 and microscopic view 360. Figure 3H Including Figure 370, which shows the noise spectrum of V(Out+), where the noise floor is below -100dB, but there are obvious tonal noise spikes in the kilohertz range.

[0072] Figure 4A An example graph of a second-order Σ-Δ modulator with single-cycle dynamic hysteresis control, depending on the implementation method, is shown. Figure 2A Similarly, Figure 400 shows a logic diagram where the input signal 401 (V_in) is limited to, for example, a range of -1V to +1V. Summing circuit 402 performs the summation of the current controlled by V_in and DAC-. The summation represents a "Δ" operation (e.g., V_in - V(DAC)). The result of the Δ operation is then accumulated in capacitor C1, which performs a "∑" operation, as shown in integrator 403. Here, X1 is the result signal of integrator 403, which is the first stage of the ∑-Δ modulator. Summing circuit 404 performs the summation of the current controlled by V(X1) and V(DAC-), the result of which is then accumulated by integrator 405. Here, X2 is the result output of integrator 405. Quantizer 406 is connected to integrator 405 to receive the result output X2. Quantizer 406 operates in conjunction with... Figure 3A The example shown in quantizer 304 exhibits consistent dynamic hysteresis control. Hysteresis adjustment is performed in each clock cycle and affects both the low-to-high and high-to-low transitions, as illustrated in boxes 406A and 406B. Quantizer 406 is time-gated by the clock signal CLK, allowing the output of quantizer 406 to reach DAC+ (and its complementary signal DAC-) on each rising edge of the clock signal. The output of quantizer 406 can provide a feedback signal (DAC-) to summing circuit 402 (via buffer 407) and summing circuit 404 (via buffer 408).

[0073] Figure 4B Including figure 410, which shows Figure 4A The noise spectrum of a second-order Σ-Δ modulator. Figure 4C Including figure 420, which shows Figure 2A The noise spectrum of a second-order Σ-Δ modulator. Side-by-side comparison shows that... Figure 4C The noise spectrum has a distinct tone in the kilohertz range (starting from -105 dB), while Figure 4CThe noise spectrum shows only tones below -117 dB, which is slightly above the noise floor. Therefore, improved performance superior to known prior art is demonstrated.

[0074] The following pseudocode provides an example of a dynamic hysteresis adjustment process according to some implementations of the present invention.

[0075] If (Output == low)

[0076] {

[0077] if (input >= positive_hysteresis)

[0078] {

[0079] Output = high

[0080] positive_hysteresis = positive_hysteresis + ( target_hysteresis -input )

[0081] }

[0082] }

[0083] else if (input <= negative_hysteresis)

[0084] {

[0085] Output = low

[0086] negative_hysteresis= negative_hysteresis - ( target_Hysteresis +input )

[0087] }

[0088] Initially, a dynamic hysteresis adjustment process implemented on mixed-signal circuits (such as Σ-Δ modulators including quantizers or comparators) determines whether the clock signal driving the mixed-signal circuit is at a clock edge. If the clock signal has not yet reached a clock edge, such as a rising or falling edge, no action is required because no triggering has occurred.

[0089] In response to the arrival of the clock edge, the dynamic hysteresis adjustment process can determine, for example, whether the quantizer's output is at a logic low level. In response to determining that the quantizer's output is at a digital low level, the dynamic hysteresis adjustment process can determine whether the quantizer's input has increased to reach a positive hysteresis (pos_Hyst) level. As mentioned above, the presence of hysteresis introduces the overdrive required to change the output, which may depend on the quantizer's switching direction (e.g., from digital low to digital high, or from digital high to digital low). Here, if the comparison between the input and the positive hysteresis level indicates that the input is increasing and reaching a positive hysteresis level, the quantizer's output switches from digital low to digital high. Within the same clock cycle, during the comparison, the positive hysteresis level is adjusted to accommodate the difference between the input and the target hysteresis so that in the next clock cycle, the adjusted positive hysteresis (which remembers the error from the previous clock cycle) can be used to cumulatively further correct the error. The above example (e.g.) Figures 3A to 3C The example shows a target hysteresis of 500mV when V_in is limited to the range of -1V to +1V. Since the target hysteresis is applied equally to the upper and lower limits, the overall result is zero.

[0090] In response to determining that the quantizer output is not at a digital low level, the dynamic hysteresis adjustment process determines whether the quantizer input has decreased to reach a negative hysteresis (neg_Hyst) level. Given the binary nature of the quantizer, it is at a digital high level when its output is not at a digital low level. Here, if a comparison between the input and the positive hysteresis level indicates that the input is decreasing and has reached a negative hysteresis level, the quantizer output switches from digital high to digital low. Within the same clock cycle, during the comparison, the negative hysteresis level is adjusted to accommodate the difference between the input and the negative hysteresis, so that in the next clock cycle, the adjusted negative hysteresis can be used to cumulatively further correct the error.

[0091] In the example above, the adjustment is applied to either the positive or negative hysteresis based on the difference between the measured input and the target hysteresis. In other examples, the adjustment can be applied to both the positive and negative hysteresis based on the average of the positive and negative side errors.

[0092] While the examples above describe a Σ-Δ modulator, these implementations can be applied to various mixed-signal circuits with hysteresis characteristics, including quantizers or comparators. As explained in detail above, these implementations include dynamic hysteresis error-correcting quantizers / comparators, where hysteresis errors are dynamically corrected in each clock cycle so that the correction takes effect immediately in the next clock cycle. It is noteworthy that the correction in the implementations of this invention is independent of the input voltage range. The performance of these implementations, measured by the noise spectrum shown above, demonstrates significant improvements in significantly reducing the noise floor and tonal distortion. In fact, these implementations can adjust the hysteresis in each clock cycle to correct instantaneous quantization errors and require fewer stages, as in Σ-Δ modulators. The reduced complexity allows for a lower switching frequency while maintaining a high clock rate and associated oversampling rate. In this way, quantization errors are reduced by several orders of magnitude, as confirmed by the noise spectra of these implementations. Furthermore, dead time can also be eliminated by the implementations of this invention, where the output remains unchanged even if the input fluctuates. The benefits and advantages of the implementations of this invention are not limited to those discussed above.

[0093] As an illustration, these implementations can be incorporated into various hysteresis control applications (e.g., switching power supplies and motor control). In such exemplary applications, maintaining accurate control of physical quantities (e.g., voltage, current) is advantageous. These advantages include accuracy, precision, and stability associated with hysteresis controllers, consistent with the implementations of this invention. Because hysteresis controllers are designed to keep the controlled parameter within a narrow hysteresis band, errors introduced by hysteresis can lead to a lack of accuracy and precision in keeping the desired parameter within a specified range. Hysteresis controllers may overshoot or undershoot relative to the setpoint, resulting in reduced control precision, as well as dead zones—small changes in the input have no effect on the output. Hysteresis controllers may exhibit oscillating or jittering behavior when the controlled parameter fluctuates rapidly near the hysteresis band due to the controller constantly switching between on and off states. Such oscillations can cause a range of problems, including reduced system stability. In fact, hysteresis errors can affect the stability of the control system. Hysteresis errors introduce oscillations, hindering the attainment of a stable operating point. To mitigate hysteresis errors in hysteresis controllers, these implementations can be further incorporated with techniques such as improved feedback mechanisms, smaller hysteresis bands, and digital signal processing. These implementations can also incorporate advanced control techniques and algorithms, such as proportional-integral-derivative (PID) controllers. Furthermore, these implementations can include a variety of technologies depending on the specific application and the trade-offs between simplicity, cost, and performance.

[0094] Figure 5A and Figure 5BFigures 500 and 510 show a comparison and contrast of static hysteresis control and dynamic hysteresis control according to some implementations of the present invention. Figure 500 illustrates a hysteresis control scheme in which the switch is turned off to begin descent when curve 501 reaches the upper limit 502, and turned on when curve 502 reaches the lower limit 503. The average value is then set as the average of the upper and lower limits. The on and off times (and therefore the switching frequency) vary with the input and output signals to maintain curve 501. However, in practical implementations of hysteresis control, there is a comparator delay, and the switch does not turn on and off instantaneously when curve 501 reaches its limit, but rather after a very small delay, as shown in the figure. Given these delays, the actual average value may deviate from the desired level.

[0095] In contrast, Figure 510 illustrates a hysteresis control scheme according to some implementations of the invention, wherein the upper and lower limits are adjusted based on the error seen at the comparator (e.g., in each clock cycle). For illustration, the upper and lower limits are initially set to levels 512A and 513A, respectively. When curve 511 slopes up and exceeds level 512A (e.g., based on comparing the value on curve 511 with the upper limit), the upper limit is updated to level 512B to account for the error seen by the comparator. The switch is then turned off, causing curve 511 to slope down. When curve 511 crosses level 513A (e.g., based on comparing the value on curve 511 with the lower limit), the lower limit is then updated to level 513B to account for the error seen by the comparator. This dynamic adjustment is as follows: Figure 5B As shown in the “modification lag” section.

[0096] This invention can achieve high OSR and low quantization noise in the band of interest, typically requiring only two or fewer stages, while reducing pitch amplitude and frequency below the band of interest. This invention is applicable to any system that can measure quantization error and be used to correct dynamic hysteresis.

[0097] The benefits of implementing the present invention include:

[0098] Low complexity, high-quality single-bit signal reproduction, easy to integrate into existing microcontrollers, enabling high-quality signal conversion for the mass market.

[0099] Single-bit output, natively compatible with switching output stages, and inherently linear (no multi-bit required).

[0100] The output switching frequency (Fsw) is low enough to directly drive a Class D / power inverter without intermediate filtering and remodulation.

[0101] Single-cycle quantization error correction is applicable to any Σ-Δ configuration.

[0102] Ultra-low propagation delay (due to low complexity and parallel quantization correction). Crucial for wide-bandwidth noise cancellation, enabling low-latency variable frequency motor control, etc.

[0103] Simple stability protection.

[0104] Open-loop operation allows for “analog” volume control by changing the output voltage without bit shifting, maintaining dynamic range (without losing bits due to shifting).

[0105] Real-time overcurrent protection (OCP) embedded in the converter.

[0106] explain

[0107] In this specification, the terms "hysteresis level," "threshold hysteresis," "hysteresis threshold," and "hysteresis value" are used synonymously. In this regard, references to "controlling" or "adjusting" hysteresis refer to controlling or adjusting the hysteresis threshold.

[0108] Mixed-signal circuits are integrated circuits or electronic systems that process both analog and digital signals. They combine analog circuitry, which processes continuously variable signals, with digital circuitry, which processes discrete binary signals. This integration allows for interaction and conversion between the analog and digital domains, enabling functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), signal conditioning, and complex data processing within a single device. Mixed-signal circuits are crucial in applications where both types of signals coexist, such as in telecommunications, audio and video processing, instrumentation, and control systems.

[0109] A quantizer is a component in the signal quantization process responsible for converting a continuous range of signal values ​​into a finite set of discrete levels. This conversion involves mapping the amplitude of the input signal to the nearest value within a predefined set of levels to effectively discretize the signal for further digital processing, storage, or transmission. The quantization process inherently introduces quantization noise, or error, which is the difference between the actual analog value and its quantized representation. Quantizers are widely used in digital signal processing, telecommunications, audio and video compression, and a variety of other applications that require the conversion of continuous signals into discrete digital data.

[0110] The hysteresis threshold in a quantizer refers to the specific input level that determines when the quantizer will change its output state. It introduces a form of memory to prevent rapid switching between adjacent quantization levels. In a quantizer with hysteresis, each decision boundary typically has two thresholds: one for increasing the output level and one for decreasing the output level.

[0111] The described methods, processes, or logical flows represent one or more examples of functionality consistent with the present invention and are not intended to limit the invention to the described or illustrated implementations, but rather to be given the widest scope consistent with the described principles and features. The described methods, processes, or logical flows can be executed by one or more programmable computers that execute one or more computer programs to perform functions by manipulating input data and generating output data. These methods, processes, or logical flows can also be executed by dedicated logic circuitry, and the apparatus can also be implemented as dedicated logic circuitry, such as a central processing unit (CPU), graphics processing unit (GPU), FPGA (Field-Programmable Gate Array), or ASIC (Application-Specific Integrated Circuit). For example, the described logical flows can be executed by firmware that can be installed and activated on mixed-signal circuitry.

[0112] In the appended claims and the description herein, any of the terms “comprising,” “consisting of,” “comprising,” or similar terms are open-ended terms, meaning that at least the element / feature following the term is included, but other elements / features are not excluded. Therefore, the term “comprising” and its variations, when used in the claims or description, should not be construed as limiting the means, elements, or steps listed thereafter. For example, the scope of a device comprising A and B should not be limited to a device consisting only of elements A and B. Similarly, any terms “including,” “comprising,” or similar terms used herein are also open-ended terms, meaning that at least the element / feature following the term is included, but other elements / features are not excluded. Therefore, “comprising” is a synonym for “comprising” and means “including.”

[0113] As used herein, unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe a common object merely indicates that the objects referred to are different instances of similar objects and is not intended to imply that the objects described in this way must be in a given order in time, space, ranking, or any other way.

[0114] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims, but rather as descriptions of features specific to particular implementations. Certain features described in the context of individual implementations or embodiments may also be implemented in combination within a single implementation or embodiment. Conversely, various features described in the context of a single implementation may also be implemented individually or in any sub-combination in multiple implementations. Furthermore, although the features previously described may be described as functioning in certain combinations, or even originally claimed in this way, in some cases one or more features from the claimed combination may be removed, and the claimed combination may involve sub-combinations or variations thereof.

[0115] Specific implementations of the subject matter have been described. As will be apparent to those skilled in the art, other implementations, modifications, and arrangements of the described methods and embodiments are within the scope of the appended claims. Although operations are described in a specific order in the drawings or claims, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or requiring all of the operations shown to be performed (some operations may be considered optional) to achieve the desired result.

Claims

1. A signal quantizer for quantizing an input signal, the signal quantizer comprising a dynamic hysteresis adjustment feedback loop for adjusting a hysteresis threshold, wherein, The adjustment of the hysteresis threshold is based at least in part on the difference between the input of the quantizer and the target hysteresis level of the quantizer.

2. The signal quantizer as described in claim 1, wherein, The adjustment is made in response to repeated triggering.

3. The signal quantizer as described in claim 2, wherein, The recurring triggers include clock signals with regular clock cycles.

4. The signal quantizer as described in claim 3, wherein, The adjustments are made within the same clock cycle.

5. The signal quantizer as described in claim 1, wherein, The quantizer includes a positive hysteresis threshold and a negative hysteresis threshold, and both the positive and negative hysteresis thresholds are adjusted in the same way.

6. The signal quantizer as claimed in claim 1, wherein, The quantizer includes a positive hysteresis threshold and a negative hysteresis threshold, and the positive hysteresis threshold and the negative hysteresis threshold are adjusted separately.

7. The signal quantizer as claimed in claim 1, wherein, The input to the quantizer is provided by a Δ-∑ modulator.

8. The signal quantizer as claimed in claim 1, wherein, The signal quantizer forms part of the analog-to-digital converter.

9. A method for operating a quantizer, the method comprising: The input signal of the quantizer and the sum of the past outputs are accumulated to generate an accumulated signal; In response to a trigger, the accumulated signal is compared with one or more thresholds; When it is determined that the accumulated signal exceeds one or more thresholds, at least one of the one or more thresholds is selectively adjusted by an amount, the amount being at least partially based on the difference between the accumulated signal and the target threshold.

10. A signal quantization module, comprising: A combination module, configured to combine input signals and feedback signals to generate a combined signal; An integrator module, connected to the combination module and configured to generate an integral signal using the combined signal; as well as A quantizer configured to generate an output signal based at least in part on the integrated signal. The output signal is sent back to provide the feedback signal to the combination module and the integrator module, and The quantizer is further configured as follows: When the quantizer is triggered at the first time point, the input of the quantizer is compared with a threshold hysteresis, and In response to the input of the quantizer reaching the threshold hysteresis, the threshold hysteresis is adjusted by a certain amount, the amount representing the difference between the target hysteresis and the input of the quantizer at the first time point.

11. The signal quantization module as described in claim 10, wherein, When the quantizer is triggered at a second time point after the first time point, the quantizer operates to compare the input of the quantizer at the second time point with a threshold hysteresis that has been adjusted based on the quantity determined at the first time point.

12. The signal quantization module as described in claim 10 or 11, wherein, In response to a change in the input signal of the signal quantization module, the change propagates through the signal quantization module to affect the output signal of the quantizer as early as one clock cycle later.

13. The signal quantization module as described in any one of claims 10 to 12, wherein, The threshold hysteresis includes a symmetrical pair of positive hysteresis levels and negative hysteresis levels. Specifically, whenever the input of the quantizer exceeds the positive hysteresis level while the output signal is at a digital low level, the positive hysteresis level is adjusted, and Specifically, the negative hysteresis level is adjusted whenever the input of the quantizer drops below the negative hysteresis level while the output signal is at a digital high level.

14. The signal quantization module as described in claim 13, wherein, When the input of the quantizer exceeds the positive hysteresis level, the amount used to adjust the positive hysteresis level is determined by the difference between the input of the quantizer and the positive hysteresis level. Specifically, when the input of the quantizer drops below the negative hysteresis level, the amount used to adjust the negative hysteresis level is determined by the difference between the negative hysteresis level and the input of the quantizer.

15. The signal quantization module as described in claim 13, wherein, When the input of the quantizer exceeds the positive hysteresis level, the amount used to adjust the positive hysteresis level is determined by averaging the first difference between the input of the quantizer and the target hysteresis and the second difference between the target hysteresis and the input of the quantizer. When the input of the quantizer drops below the negative hysteresis level, the amount used to adjust the negative hysteresis level is also determined by the average of the first difference and the second difference.

16. The signal quantization module as described in any one of claims 10 to 15, wherein, When the quantizer is triggered, the threshold hysteresis is adjusted so that the difference between the target hysteresis and the input of the quantizer is tone-free.

17. The signal quantization module as described in any one of claims 10 to 16, wherein, When the input signal is at a constant level higher than the quantization threshold of the quantizer, the output signal does not exhibit tone phenomena.

18. The signal quantization module as described in any one of claims 1 to 17, wherein, The output signal exhibits a power level of less than 100 dB in the spectrum between 20 Hz and 20 kHz.

19. The signal quantization module as described in any one of claims 1 to 18, wherein, The quantizer is triggered at the edge of the clock cycle.

20. The signal quantization module as described in claim 19, wherein, The clock cycle edge includes a rising edge.

21. The signal quantization module as described in claim 20, wherein, The clock cycle edge includes a falling edge.

22. The signal quantization module as described in claim 20 or 21, wherein, The clock is characterized by having a frequency higher than that of the output signal generated by the quantizer.

23. The signal quantization module as described in claim 22, wherein, The frequency of the clock is up to 100 times higher than the frequency of the output signal.

24. The signal quantization module as described in any one of claims 10 to 23, further comprising: A limiter circuit is connected to the quantizer, such that the range of the quantizer's output signal is limited.

25. The signal quantization module as described in any one of claims 10 to 24, further comprising: A filter circuit is connected to the output of the quantizer and configured to process the output signal of the quantizer and generate a modulated signal for at least one downstream circuit connected to the signal quantization module.

26. The signal quantization module as described in any one of claims 1 to 25, wherein, The signal quantization module is a high-order modulator, which includes cascaded multi-stage summing circuits and integrator circuits. Each stage in the cascade includes an instance of the combining module and an instance of the integrator module connected to the combining module.

27. The signal quantization module as described in any one of claims 10 to 26, wherein, Each integrator module includes a capacitor.

28. The signal quantization module as described in any one of claims 10 to 27, wherein, Each combination module includes an operational amplifier, which is configured to: Summing the input signal and the feedback signal; and Drive the integrator module connected to the operational amplifier.

29. The signal quantization module as described in any one of claims 10 to 28, wherein, The quantizer includes a gated comparator.

30. The signal quantization module as described in any one of claims 10 to 29, further comprising: A digital filter, which is connected to the quantizer and configured to receive the output signal; as well as A decimation filter is connected to the digital filter and configured to generate a digital signal output for the signal quantization module.

31. A signal quantization module, comprising: Multiple input terminals, the multiple input terminals being configured to receive multiple input signals that are continuous in time and characterized by a frequency range; A combiner, connected to the input terminal and configured to process the plurality of input signals; An output port, connected to the combiner and configured to generate one of a predetermined level based at least in part on the result from the combiner. The signal quantization module is driven by a set of threshold hysteresis values. The signal quantization module is operable to generate a series of trigger events with a frequency exceeding the frequency range of the input signal, such that in a first trigger event of the series of trigger events, the output port generates an output based at least in part on a threshold hysteresis value and the result of the combiner processing the plurality of input signals, and in a second trigger event following the first trigger event, in response to the output of the combiner exceeding one of the threshold hysteresis values ​​in the set of threshold hysteresis values, one or more threshold hysteresis values ​​are updated by an amount, the amount of which depends at least in part on the difference between the target hysteresis and the output of the combiner in the first trigger event.

32. The signal quantization module as described in claim 31, wherein, The one or more hysteresis thresholds are updated at least in part based on the difference between the target hysteresis and the output of the combiner at the first triggering event, and the duration between the first triggering event and the second triggering event.

33. The signal quantization module as described in claim 31 or 32, wherein, The first trigger event or the second trigger event is generated based on a clock outside the signal quantization module and is independent of the input signal.

34. The signal quantization module as described in any one of claims 31 to 33, wherein, The second triggering event is generated by the signal quantization module based at least in part on the duration since the first triggering event.

35. The signal quantizer or signal quantization module as described in any of the preceding claims, wherein, The target hysteresis is set based on the target operating frequency of the quantizer.

36. The signal quantizer or signal quantization module as described in any one of claims 1 to 34, wherein, The target hysteresis is set based on the target application of the device in which the signal quantizer or signal quantization module is located.

37. A threshold comparator for comparing an input signal with a threshold, the threshold comparator including a dynamic hysteresis adjustment feedback loop that adjusts a hysteresis threshold near the threshold, wherein, The adjustment of the hysteresis threshold is based at least in part on the difference between the input of the comparator and the target hysteresis level of the comparator.

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