Novel discrete time switched capacitor integrator circuit
By designing a cascaded discrete-time switched-capacitor integrator circuit, combined with a floating inverting amplifier and complementary CMOS switches, the problem of integrated charge storage in traditional analog-to-digital converters was solved, achieving low-power and high-efficiency integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING ZHONGKE MICROELECTRONICS CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-05-26
AI Technical Summary
Traditional oversampling analog-to-digital converters have high power consumption in their switched-capacitor integrators, and when using a floating inverting amplifier, the integrated charge cannot be stored, resulting in poor integration performance.
A novel discrete-time switched-capacitor integrator circuit is designed, which employs a cascaded first-stage and second-stage integrator, combined with a floating inverting amplifier and complementary CMOS switches. The switching on and off is controlled by a clock signal to achieve a two-stage delayed second-order integration operation.
It effectively reduces the impact of clock feedthrough and channel charge on integration charge, improves integration efficiency, reduces power consumption, and achieves efficient integration operation.
Smart Images
Figure CN122092869A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a novel discrete-time switched-capacitor integrator circuit. Background Technology
[0002] Analog-to-digital (ADC) converters convert continuous analog signals into discrete digital signals. ADCs are generally classified into Nyquist ADCs and oversampling (non-Nyquist) ADCs. Nyquist ADCs can be further categorized into flash, pipelined, successive approximation, and newer hybrid architectures such as pipelined successive approximation. Oversampling ADCs typically include noise-shaping ADCs and newer hybrid noise-shaping successive approximation architectures. The variety of ADC types stems from the diverse requirements of various applications. For example, successive approximation ADCs are typically used in medium-speed, medium-precision applications; pipelined and flash ADCs are typically used in high-speed, low-precision, and ultra-high-speed applications; and oversampling ADCs are commonly used in medium-low speed, high-precision, and ultra-high-precision applications.
[0003] However, traditional oversampling analog-to-digital converters (ADCs) often have excessively high power consumption. Their structure typically includes modules such as switched-capacitor integrators, quantizers, feedback DACs (digital-to-analog converters), and timing circuits. The operational amplifier (op-amp) in the switched-capacitor integrator usually accounts for the largest share of power consumption, often in cascaded common-source amplifier structures or folded sleeve structures, reaching 60% or more of the ADC's total power consumption. To reduce power consumption, a new dynamic operational amplifier—the floating inverting amplifier—has been proposed in recent years. It has low power consumption, but it is used for simple pre-amplification and cannot be used for integration. If it is used for integration, passive interstage sampling can be used, but this will result in lossy integration. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a novel discrete-time switched-capacitor integrator circuit to solve the technical problem that integrated charge cannot be stored when using a floating inverting amplifier in existing discrete Sigma-Delta analog-to-digital converters.
[0005] As a first aspect of the present invention, a novel discrete-time switched-capacitor integrator circuit is provided, the novel discrete-time switched-capacitor integrator circuit comprising a first-stage integrator and a second-stage integrator, wherein the first-stage integrator and the second-stage integrator are cascaded together; wherein... The first-stage integrator includes a first-stage sampling capacitor, a first-stage integrating capacitor, a first-stage cascaded floating inverting amplifier, and multiple switches; one end of the first-stage sampling capacitor is connected to an external input signal, the other end of the first-stage sampling capacitor is connected to the input terminal of the first-stage cascaded floating inverting amplifier, and the two ends of the first-stage integrating capacitor are connected to the input terminal and the output terminal of the first-stage cascaded floating inverting amplifier through a set of switches; The second-stage integrator includes a second-stage sampling capacitor, a second-stage integrating capacitor, a second-stage cascaded floating inverting amplifier, and multiple switches; one end of the second-stage sampling capacitor is connected to the output terminal of the first-stage cascaded floating inverting amplifier, and the other end of the second-stage sampling capacitor is connected to the input terminal of the second-stage cascaded floating inverting amplifier; the two ends of the second-stage integrating capacitor are connected to the input and output terminals of the second-stage cascaded floating inverting amplifier through another set of switches. Specifically, while controlling the first-stage integrator to perform a sampling operation, the second-stage integrator is controlled to perform an integration operation; Specifically, while controlling the first-stage integrator to perform integration operations, the second-stage integrator is controlled to perform sampling operations.
[0006] Furthermore, the first-stage integrator includes a first-stage sampling capacitor. , First-stage integrating capacitor , First-stage cascaded floating inverting amplifier and switches , , , , , , , , Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage External positive phase input signal External inverted input signal Through switches respectively , With sampling capacitor , One end is connected to the sampling capacitor. , The other end is also connected to the first stage cascaded floating inverting amplifier. The non-inverting input terminal and the inverting input terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The non-inverting input terminal and the inverting output terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The inverting input and non-inverting output terminals; the first stage cascaded floating inverting amplifier Also connected to power supply voltage .
[0007] Furthermore, the second-stage integrator includes a second-stage sampling capacitor. , Second-stage integrating capacitor , Second-stage cascaded floating inverting amplifier and switches , , , Sampling capacitor Connected to the first stage cascaded floating inverting amplifier The inverting output terminal is connected to the second stage cascaded floating inverting amplifier. Between the non-inverting input terminals, the sampling capacitor Connected to the first stage cascaded floating inverting amplifier The non-inverting output terminal of the second-stage cascaded floating inverting amplifier is connected to the second-stage cascaded floating inverting amplifier. Between the inverting input terminals, the first stage integrating capacitor The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The non-inverting input and inverting output terminals, and the first-stage integrating capacitor. The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The inverting input and non-inverting output of the first stage; the second stage cascaded floating inverting amplifier. Also connected to the power supply voltage .
[0008] Furthermore, the first-stage cascaded floating inverting amplifier and the second-stage cascaded floating inverting amplifier Each includes four inverters and a coulomb capacitor. , and switches , , , , , , , , , , , The four inverters are INV1, INV2, INV3, and INV4. The input terminal of inverter INV1 The first stage cascaded floating inverting amplifier , The inverting input terminal of inverter INV1 is connected to the inverting input terminal of inverter INV3, and the output terminal of inverter INV3 is connected to the inverting input terminal of inverter INV3. The first stage cascaded floating inverting amplifier , The inverting output terminal; The input terminal of inverter INV2 The first stage cascaded floating inverting amplifier , The non-inverting input terminal of inverter INV2 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the non-inverting input terminal of inverter INV4. The first stage cascaded floating inverting amplifier , The non-inverting output terminal; The input terminal of inverter INV1 and the input terminal of inverter INV2 Through switches respectively , Connecting common-mode voltage The output of inverter INV1 and the input of inverter INV3 are connected by a switch. Connecting common-mode voltage The output of inverter INV2 and the input of inverter INV4 are connected by a switch. Connecting common-mode voltage The output terminal of inverter INV3 and the output of inverter INV4 Through switches respectively , Connecting common-mode voltage ; Coulomb capacitance Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV1 and INV2 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV1 and INV2 respectively; capacitor... Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV3 and INV4 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV3 and INV4 respectively.
[0009] Furthermore, each inverter includes a PMOS transistor. and NMOS transistor PMOS transistor The source terminal is connected to the power supply voltage. NMOS transistor The source terminal is grounded; PMOS transistor drain and NMOS transistor The drain terminal is connected to this terminal, which is the output terminal of each inverter. PMOS transistor Gate and NMOS transistor The gate is connected to this terminal, which is the input terminal of each inverter. .
[0010] Furthermore, the novel discrete-time switched-capacitor integrator circuit is controlled by four clock signals Φ1, Φ2, Φ1d, and Φ2d. Clock signals Φ1 and Φ1d have the same pulse width, but Φ1d lags behind Φ1; clock signals Φ2 and Φ2d have the same pulse width, but Φ2d lags behind Φ2; clock signals Φ1 and Φ2 are out of phase and do not overlap, and clock signals Φ1d and Φ2d are out of phase and do not overlap. The four clock signals Φ1, Φ2, Φ1d, and Φ2d are used to control the switches in the novel discrete-time switched-capacitor integrator circuit. When the clock signal is high, it controls the corresponding switch to close; when the clock signal is low, it controls the corresponding switch to open.
[0011] Furthermore, the clock signal Φ1 is used to control the switch. , The first stage cascaded floating inverting amplifier Internal switches , , , , , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ1d is used to control the switch. , , , , , and the first stage cascaded floating inverting amplifier internal switch and ; Clock signal Φ2 is used to control the switch. , The first stage cascaded floating inverting amplifier Internal switches , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ2d is used to control the switch. , , and the second-stage cascaded floating inverting amplifier and .
[0012] Furthermore, during the period from the start of the high level of clock signal Φ1 to the end of the high level of clock signal Φ1d, the corresponding switch is closed, the first-stage integrator performs a sampling operation, and the second-stage integrator performs an integration operation; During the period from the start of the clock signal Φ2 high level to the end of the clock signal Φ2d high level, the corresponding switch is closed, the first-stage integrator performs integration operation, and the second-stage integrator performs sampling operation.
[0013] Furthermore, the sampling path of the first-stage integrator is controlled by a switch. , , , and the first stage cascaded floating inverting amplifier Internal switches , , , , , , , , , Control; the integration path of the second-stage integrator is controlled by a switch. , , , and the second-stage cascaded floating inverting amplifier , , , control.
[0014] Furthermore, the integration path of the first-stage integrator is controlled by a switch. , , , , , and the first stage cascaded floating inverting amplifier within , , , Control; the sampling path of the second-stage integrator is controlled by the second-stage cascaded floating inverting amplifier. , , , , , , , , , control.
[0015] The novel discrete-time switched-capacitor integrator circuit provided by this invention has the following advantages: complementary CMOS switches are added across the feedback (integration) capacitor to simultaneously perform on and off operations, minimizing the impact of changes in effective integration charge caused by factors such as clock feedthrough and channel charge; at the same time, combined with the reset characteristics of the floating inverting amplifier, the second-order integration operation with two-stage delay is completed with very few switches. Attached Figure Description
[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof.
[0017] Figure 1 The schematic diagram of the novel discrete-time switched-capacitor integrator circuit provided by the present invention.
[0018] Figure 2 The schematic diagram of the cascaded floating inverting amplifier provided by the present invention.
[0019] Figure 3 The schematic diagram of the inverter provided by the present invention
[0020] Figure 4 The timing diagram of the four clock signals provided by this invention. Detailed Implementation
[0021] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a novel discrete-time switched-capacitor integrator circuit proposed according to the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0023] In explaining this invention, it should be noted that the terms "installation," "connection," and "linking" should be interpreted broadly unless otherwise specified. For example, a connection can be a fixed connection, a connection through a special interface, or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0024] This embodiment provides a novel discrete-time switched-capacitor integrator circuit, such as... Figure 1 As shown, the novel discrete-time switched-capacitor integrator circuit includes a first-stage integrator and a second-stage integrator, which are cascaded together; wherein, The first-stage integrator includes a first-stage sampling capacitor, a first-stage integrating capacitor, a first-stage cascaded floating inverting amplifier, and multiple switches; one end of the first-stage sampling capacitor is connected to an external input signal, the other end of the first-stage sampling capacitor is connected to the input terminal of the first-stage cascaded floating inverting amplifier, and the two ends of the first-stage integrating capacitor are connected to the input terminal and the output terminal of the first-stage cascaded floating inverting amplifier through a set of switches; The second-stage integrator includes a second-stage sampling capacitor, a second-stage integrating capacitor, a second-stage cascaded floating inverting amplifier, and multiple switches; one end of the second-stage sampling capacitor is connected to the output terminal of the first-stage cascaded floating inverting amplifier, and the other end of the second-stage sampling capacitor is connected to the input terminal of the second-stage cascaded floating inverting amplifier; the two ends of the second-stage integrating capacitor are connected to the input and output terminals of the second-stage cascaded floating inverting amplifier through another set of switches. Specifically, while controlling the first-stage integrator to perform a sampling operation, the second-stage integrator is controlled to perform an integration operation; Specifically, while controlling the first-stage integrator to perform integration operations, the second-stage integrator is controlled to perform sampling operations.
[0025] Preferably, the first-stage integrator includes a first-stage sampling capacitor. , First-stage integrating capacitor , First-stage cascaded floating inverting amplifier and switches , , , , , , , , Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage External positive phase input signal External inverted input signal Through switches respectively , With sampling capacitor , One end is connected to the sampling capacitor. , The other end is also connected to the first stage cascaded floating inverting amplifier. The non-inverting input terminal and the inverting input terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The non-inverting input terminal and the inverting output terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The inverting input and non-inverting output terminals; the first stage cascaded floating inverting amplifier Also connected to power supply voltage .
[0026] Preferably, the second-stage integrator includes a second-stage sampling capacitor. , Second-stage integrating capacitor , Second-stage cascaded floating inverting amplifier and switches , , , Sampling capacitor Connected to the first stage cascaded floating inverting amplifier The inverting output terminal is connected to the second stage cascaded floating inverting amplifier. Between the non-inverting input terminals, the sampling capacitor Connected to the first stage cascaded floating inverting amplifier The non-inverting output terminal of the second-stage cascaded floating inverting amplifier is connected to the second-stage cascaded floating inverting amplifier. Between the inverting input terminals, the first stage integrating capacitor The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The non-inverting input and inverting output terminals, and the first-stage integrating capacitor. The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The inverting input and non-inverting output of the first stage; the second stage cascaded floating inverting amplifier. Also connected to the power supply voltage .
[0027] It should be noted that common-mode voltage It is the DC bias voltage of the entire integrator circuit, providing the operating reference point for the entire integrator circuit; power supply voltage This provides power to the entire integrator circuit at its highest potential; additionally... Figure 1 In This represents the in-phase output signal of the integrator. This represents the inverted output signal of the integrator.
[0028] It should be noted that the first-stage sampling capacitor and The sizes are consistent, and the second-stage integrating capacitor is the same. and The sizes are consistent, and the first-stage integrating capacitor is the same. and The sizes are consistent, and the second-stage sampling capacitor is... and They are all the same size.
[0029] Preferred, such as Figure 2 As shown, the first stage cascaded floating inverting amplifier and the second-stage cascaded floating inverting amplifier Each includes four inverters and a coulomb capacitor. , and switches , , , , , , , , , , , The four inverters are INV1, INV2, INV3, and INV4; among them, < ; The input terminal of inverter INV1 The first stage cascaded floating inverting amplifier , The inverting input terminal of inverter INV1 is connected to the inverting input terminal of inverter INV3, and the output terminal of inverter INV3 is connected to the inverting input terminal of inverter INV3. The first stage cascaded floating inverting amplifier , The inverting output terminal; The input terminal of inverter INV2 The first stage cascaded floating inverting amplifier , The non-inverting input terminal of inverter INV2 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the non-inverting input terminal of inverter INV4. The first stage cascaded floating inverting amplifier , The non-inverting output terminal; The input terminal of inverter INV1 and the input terminal of inverter INV2 Through switches respectively , Connecting common-mode voltage The output of inverter INV1 and the input of inverter INV3 are connected by a switch. Connecting common-mode voltage The output of inverter INV2 and the input of inverter INV4 are connected by a switch. Connecting common-mode voltage The output terminal of inverter INV3 and the output of inverter INV4 Through switches respectively , Connecting common-mode voltage ; Coulomb capacitance Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV1 and INV2 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV1 and INV2 respectively; capacitor... Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV3 and INV4 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV3 and INV4 respectively.
[0030] It should be noted that the four inverters have exactly the same structure.
[0031] Preferred, such as Figure 3 As shown, each inverter includes a PMOS transistor. and NMOS transistor PMOS transistor The source terminal is connected to the power supply voltage. NMOS transistor The source terminal is grounded; PMOS transistor drain and NMOS transistor The drain terminal is connected to this terminal, which is the output terminal of each inverter. PMOS transistor Gate and NMOS transistor The gate is connected to this terminal, which is the input terminal of each inverter. .
[0032] Preferred, such as Figure 4 As shown, the novel discrete-time switched-capacitor integrator circuit is controlled by four clock signals Φ1, Φ2, Φ1d, and Φ2d. Clock signals Φ1 and Φ1d have the same pulse width, but the pulse of Φ1d lags slightly behind Φ1. Clock signals Φ2 and Φ2d have the same pulse width, but the pulse of Φ2d lags slightly behind Φ2. Clock signals Φ1 and Φ2 are out of phase and do not overlap at all, as are clock signals Φ1d and Φ2d. The four clock signals Φ1, Φ2, Φ1d, and Φ2d are used to control the switches in the novel discrete-time switched-capacitor integrator circuit. When the clock signal is high, it controls the corresponding switch to close; when the clock signal is low, it controls the corresponding switch to open.
[0033] Preferably, the clock signal Φ1 is used to control the switch. , The first stage cascaded floating inverting amplifier Internal switches , , , , , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ1d is used to control the switch. , , , , , and the first stage cascaded floating inverting amplifier Internal switches and ; Clock signal Φ2 is used to control the switch. , The first stage cascaded floating inverting amplifier Internal switches , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ2d is used to control the switch. , , and the second-stage cascaded floating inverting amplifier and .
[0034] It should be noted that the first stage is a cascaded floating inverting amplifier. Second-stage cascaded floating inverting amplifier The structures are exactly the same, but the control signals of the internal switches are exactly opposite.
[0035] Specifically, during the period from the start of the clock signal Φ1 high level to the end of the clock signal Φ1d high level, the corresponding switch is closed, the first-stage integrator performs a sampling operation, and the second-stage integrator performs an integration operation; During the period from the start of the clock signal Φ2 high level to the end of the clock signal Φ2d high level, the corresponding switch is closed, the first-stage integrator performs integration operation, and the second-stage integrator performs sampling operation.
[0036] It should be noted that the sampling path of the first-stage integrator is controlled by a switch. , , , and the first stage cascaded floating inverting amplifier Internal switches , , , , , , , , , Control; the integration path of the second-stage integrator is controlled by a switch. , , , and the second-stage cascaded floating inverting amplifier , , , control.
[0037] It should be noted that the integration path of the first-stage integrator is controlled by a switch. , , , , , and the first stage cascaded floating inverting amplifier within , , , Control; the sampling path of the second-stage integrator is controlled by the second-stage cascaded floating inverting amplifier. , , , , , , , , , control.
[0038] like Figures 1-4 As shown in the figure, the specific working process of the novel discrete-time switched-capacitor integrator circuit provided in this embodiment is as follows: (1) During the period from the start of the clock signal Φ1 high level to the end of the clock signal Φ1d high level, the switch , , , , , , , All closed. Internal switches , , , , , , , , , All closed, and , , , All switches are closed, and other switches are open. During this period, the first-stage sampling capacitor... , The upper plate begins sampling, and the power supply voltage... right Internal capacitors and Simultaneously charging, and The input and output terminals of all internal inverters INV are biased at a common-mode voltage. And ensure that before the high level of Φ1d ends, Internal and Filled to the point where the pressure difference between the two ends is , within and Currently conducting separate investigations All inverters inside discharge, causing the operational amplifier to... It works, and through the second-stage integrating capacitor , The second-stage sampled charge is integrated; that is, the second-stage integrator integrates while the first-stage integrator samples.
[0039] (2) During the period from the start of the high level of clock signal Φ2 to the end of the high level of clock signal Φ2d, the switch... , All closed, switch , , , All closed. within , , , All closed. switch , , , , , , , , , All switches are closed, and other switches are open; during this period within and To each All inverters inside discharge, causing the operational amplifier to... It works, and through the first-stage integrating capacitor , The integration operation of the first-stage sampled charge is completed; simultaneously, the second-stage sampling capacitor... , Sampling operation is performed; power supply voltage right Internal capacitors and Charging, and The input and output terminals of all internal inverters INV are biased at a common-mode voltage. And ensure that before the high level of Φ2d ends, Internal and Filled to the point where the pressure difference between the two ends is That is, the second-stage integrator samples while the first-stage integrator integrates.
[0040] After the high level of Φ1d ends, the integrating capacitor of the second-stage integrator... , Complementary switches at both ends , , , Simultaneously disconnected; similarly, after the high level of Φ2d ends, the integrating capacitor of the first-stage integrator... , Complementary switches at both ends , , , Simultaneous disconnection avoids the problem of the integrating capacitor being biased to the common-mode level when the floating inverting amplifier enters the sampling phase, thus clearing the integrating charge. Furthermore, using complementary switches minimizes the additional voltage caused by channel charge. Moreover, the simultaneous disconnection of the complementary switches at both ends cancels out the small amount of channel charge across the integrating capacitor, having almost no impact on the integrating voltage.
[0041] The time-domain descriptions of both the first-stage integrator and the second-stage integrator are as follows: ; After z-transform, the signal transfer functions of both the first-stage integrator and the second-stage integrator are: ; In the formula, For sampling capacitor, It is an integrating capacitor. The period is defined as n, where n is an integer. Therefore, the signal transfer function of the integrator circuit of this invention is:
[0042] .
[0043] This invention provides a novel discrete-time switched-capacitor integrator circuit. The input signal is sampled by a first-stage sampling capacitor and then integrated by an integrating capacitor. Simultaneously, the charge is sampled and integrated by a second-stage integrator. Complementary CMOS switches are added across the feedback (integration) capacitor, simultaneously performing on and off operations to minimize the impact of changes in effective integrated charge caused by factors such as clock feedthrough and channel charge. Furthermore, by combining the reset characteristics of a floating inverting amplifier, a two-stage delayed second-order integration operation is achieved with minimal switching.
[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A novel discrete-time switched-capacitor integrator circuit, characterized in that, The novel discrete-time switched-capacitor integrator circuit includes a first-stage integrator and a second-stage integrator, wherein the first-stage integrator and the second-stage integrator are cascaded together; wherein... The first-stage integrator includes a first-stage sampling capacitor, a first-stage integrating capacitor, a first-stage cascaded floating inverting amplifier, and multiple switches; one end of the first-stage sampling capacitor is connected to an external input signal, the other end of the first-stage sampling capacitor is connected to the input terminal of the first-stage cascaded floating inverting amplifier, and the two ends of the first-stage integrating capacitor are connected to the input terminal and the output terminal of the first-stage cascaded floating inverting amplifier through a set of switches; The second-stage integrator includes a second-stage sampling capacitor, a second-stage integrating capacitor, a second-stage cascaded floating inverting amplifier, and multiple switches; one end of the second-stage sampling capacitor is connected to the output terminal of the first-stage cascaded floating inverting amplifier, and the other end of the second-stage sampling capacitor is connected to the input terminal of the second-stage cascaded floating inverting amplifier; the two ends of the second-stage integrating capacitor are connected to the input and output terminals of the second-stage cascaded floating inverting amplifier through another set of switches. Specifically, while controlling the first-stage integrator to perform a sampling operation, the second-stage integrator is controlled to perform an integration operation; Specifically, while controlling the first-stage integrator to perform integration operations, the second-stage integrator is controlled to perform sampling operations.
2. The novel discrete-time switched-capacitor integrator circuit according to claim 1, characterized in that, The first-stage integrator includes a first-stage sampling capacitor. , First-stage integrating capacitor , First-stage cascaded floating inverting amplifier and switches , , , , , , , , Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage Sampling capacitor Both ends are connected by switches , Connecting common-mode voltage External positive phase input signal External inverted input signal Through switches respectively , With sampling capacitor , One end is connected to the sampling capacitor. , The other end is also connected to the first stage cascaded floating inverting amplifier. The non-inverting input terminal and the inverting input terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The non-inverting input terminal and the inverting output terminal; the first stage integrating capacitor The two ends are connected by a switch , Connected to the first stage cascaded floating inverting amplifier The inverting input and non-inverting output terminals; the first stage cascaded floating inverting amplifier Also connected to power supply voltage .
3. A novel discrete-time switched-capacitor integrator circuit according to claim 2, characterized in that, The second-stage integrator includes a second-stage sampling capacitor. , Second-stage integrating capacitor , Second-stage cascaded floating inverting amplifier and switches , , , Sampling capacitor Connected to the first stage cascaded floating inverting amplifier The inverting output terminal is connected to the second stage cascaded floating inverting amplifier. Between the non-inverting input terminals, the sampling capacitor Connected to the first stage cascaded floating inverting amplifier The non-inverting output terminal of the second-stage cascaded floating inverting amplifier is connected to the second-stage cascaded floating inverting amplifier. Between the inverting input terminals, the first stage integrating capacitor The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The non-inverting input and inverting output terminals, and the first-stage integrating capacitor. The two ends are connected by a switch , Connected to the second stage cascaded floating inverting amplifier The inverting input and non-inverting output of the first stage; the second stage cascaded floating inverting amplifier. Also connected to the power supply voltage .
4. A novel discrete-time switched-capacitor integrator circuit according to claim 3, characterized in that, First stage cascaded floating inverting amplifier and the second-stage cascaded floating inverting amplifier Each includes four inverters and a coulomb capacitor. , and switches , , , , , , , , , , , ; The four inverters are INV1, INV2, INV3, and INV4. The input terminal of inverter INV1 The first stage cascaded floating inverting amplifier , The inverting input terminal of inverter INV1 is connected to the inverting input terminal of inverter INV3, and the output terminal of inverter INV3 is connected to the inverting input terminal of inverter INV3. The first stage cascaded floating inverting amplifier , The inverting output terminal; The input terminal of inverter INV2 The first stage cascaded floating inverting amplifier , The non-inverting input terminal of inverter INV2 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the non-inverting input terminal of inverter INV4. The first stage cascaded floating inverting amplifier , The non-inverting output terminal; The input terminal of inverter INV1 and the input terminal of inverter INV2 Through switches respectively , Connecting common-mode voltage The output of inverter INV1 and the input of inverter INV3 are connected by a switch. Connecting common-mode voltage The output of inverter INV2 and the input of inverter INV4 are connected by a switch. Connecting common-mode voltage The output terminal of inverter INV3 and the output of inverter INV4 Through switches respectively , Connecting common-mode voltage ; Coulomb capacitance Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV1 and INV2 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV1 and INV2 respectively; capacitor... Both ends are connected by switches , Connect to power supply voltage and ground, in the library capacitance With switch Through a switch Connect inverters INV3 and INV4 respectively, and use the coulomb capacitor. With switch Through a switch Connect inverters INV3 and INV4 respectively.
5. A novel discrete-time switched-capacitor integrator circuit according to claim 4, characterized in that, Each inverter includes a PMOS transistor. and NMOS transistor PMOS transistor The source terminal is connected to the power supply voltage. NMOS transistor The source terminal is grounded; PMOS transistor drain and NMOS transistor The drain terminal is connected to this terminal, which is the output terminal of each inverter. PMOS transistor Gate and NMOS transistor The gate is connected to this terminal, which is the input terminal of each inverter. .
6. A novel discrete-time switched-capacitor integrator circuit according to claim 4, characterized in that, The novel discrete-time switched-capacitor integrator circuit is controlled by four clock signals Φ1, Φ2, Φ1d, and Φ2d. Clock signals Φ1 and Φ1d have the same pulse width, but the pulse of Φ1d lags behind Φ1; clock signals Φ2 and Φ2d have the same pulse width, but the pulse of Φ2d lags behind Φ2; clock signals Φ1 and Φ2 are out of phase and do not overlap at all, and clock signals Φ1d and Φ2d are out of phase and do not overlap at all. The four clock signals Φ1, Φ2, Φ1d, and Φ2d are used to control the switches in the novel discrete-time switched-capacitor integrator circuit. When the clock signal is high, it controls the corresponding switch to close; when the clock signal is low, it controls the corresponding switch to open.
7. A novel discrete-time switched-capacitor integrator circuit according to claim 6, characterized in that, Clock signal Φ1 is used to control the switch. , The first stage cascaded floating inverting amplifier internal switch , , , , , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ1d is used to control the switch. , , , , , and the first stage cascaded floating inverting amplifier internal switch and ; Clock signal Φ2 is used to control the switch. , The first stage cascaded floating inverting amplifier internal switch , , , and the second-stage cascaded floating inverting amplifier , , , ; Clock signal Φ2d is used to control the switch. , , and the second-stage cascaded floating inverting amplifier and .
8. A novel discrete-time switched-capacitor integrator circuit according to claim 7, characterized in that, During the period from the start of the clock signal Φ1 high level to the end of the clock signal Φ1d high level, the corresponding switch is closed, the first-stage integrator performs the sampling operation, and the second-stage integrator performs the integration operation; During the period from the start of the clock signal Φ2 high level to the end of the clock signal Φ2d high level, the corresponding switch is closed, the first-stage integrator performs integration operation, and the second-stage integrator performs sampling operation.
9. A novel discrete-time switched-capacitor integrator circuit according to claim 8, characterized in that, The sampling path of the first-stage integrator is a switch , , , and the first stage cascaded floating inverting amplifier internal switch , , , , , , , , , Control; the integration path of the second-stage integrator is controlled by a switch. , , , and the second-stage cascaded floating inverting amplifier , , , control.
10. A novel discrete-time switched-capacitor integrator circuit according to claim 8, characterized in that, The integration path of the first-stage integrator is connected by a switch. , , , , , and the first stage cascaded floating inverting amplifier within , , , Control; the sampling path of the second-stage integrator is controlled by the second-stage cascaded floating inverting amplifier. , , , , , , , , , control.