Network-on-chip virtual channel routing system, data forwarding method, and related devices

Abstract

The application relates to a network-on-chip virtual channel routing system, a data forwarding method and related equipment, which comprises a routing outlet calculation module, a virtual channel buffer allocation module, a virtual channel buffer module and a credit release module. The routing outlet calculation module is used for receiving a data packet transmitted by a network sender through a routing inlet and determining a routing outlet buffer to which the data packet needs to be forwarded. The virtual channel buffer allocation module is used for allocating a serial number of an idle virtual channel buffer to the data packet. The virtual channel buffer module comprises a plurality of virtual channel buffers corresponding to different routing outlet buffers, is used for storing the data packet in the corresponding virtual channel buffer according to the allocated serial number and recording data packet pointer information through a linked list, and sends the data packet to the routing outlet buffer when the routing outlet buffer is ready for data forwarding. The credit release module is used for releasing credit information to the network sender to control the maximum number of data packets sent by the network sender. The application improves the utilization rate and throughput of the virtual channel.

Description

Technical Field

[0001] This invention relates to the field of on-chip network technology, and in particular to an on-chip network virtual channel routing system, data forwarding method and related equipment. Background Technology

[0002] In general-purpose superscalar processors with multi-core CPUs and multi-chip interconnects, the scale of on-chip networks (NoCs) is constantly expanding as performance requirements continue to increase. This poses greater challenges to on-chip routers responsible for multi-core communication, requiring them to simultaneously meet performance specifications such as high bandwidth, low latency, small area, and low power consumption. To address this, Virtual Channels (VCs) in on-chip networks can resolve router buffer contention and deadlock issues. By dividing the physical channel into multiple independent logical communication paths, routers can easily achieve parallel transmission and buffer management of data packets.

[0003] However, the business traffic of general-purpose computing is based on complex cache consistency protocols. The read and write access shared by multiple cores includes various request types and handshake protocol dependencies, which may cause data packets to arrive out of order, further increasing the design complexity of the transceiver terminal. Therefore, it is necessary to address these issues by optimizing the virtual channel architecture.

[0004] Existing methods for implementing virtual channels at the input end of on-chip network routers mainly include the following three schemes:

[0005] The first method employs a fixed virtual channel scheme. The core of this scheme is that each egress's virtual channel only receives data packets destined for itself. Even if other egress virtual channels are full while this egress's virtual channel remains free, it cannot receive data packets destined for other egress channels. Its drawbacks are significant: to control area, the depth of each egress's virtual channel cannot be too long, resulting in extremely low virtual channel utilization and directly limiting throughput; simultaneously, the fixed allocation mode is difficult to adapt to dynamic traffic changes, further exacerbating the performance bottleneck.

[0006] The second method employs a shared virtual channel scheme. Initially, this scheme is consistent with the fixed virtual channel scheme, where each egress virtual channel receives data packets destined for itself by default. However, when other egress virtual channels are full and the current egress virtual channel has free space, it can receive data packets destined for that full egress. Compared to the fixed scheme, its virtual channel utilization is improved, but it has significant limitations: data packets on the same source-destination path may be out of order due to cross-egress buffering, increasing the complexity of out-of-order processing for the protocol terminal; and like the fixed scheme, only one data packet can be arbitrated per clock cycle, resulting in relatively low throughput.

[0007] The third method also employs a shared virtual channel scheme. Unlike the second method, it uses a shared virtual channel buffer, but each exit's pointer virtual channel must always point to a data packet destined for it. Its key advantages are: when the exit is idle, it can skip the buffer and output directly to the exit module, resulting in lower latency; and it can output data packets from all exits per clock cycle, leading to better throughput. However, its drawbacks are equally apparent: for the same data packet capacity, the storage area of ​​the pointer virtual channel increases significantly, and the sparse distribution of pointer virtual channels leads to low utilization, thus offsetting some of the performance advantages.

[0008] In summary, existing solutions have shortcomings in terms of key indicators such as utilization, throughput, latency, and area, making it difficult to simultaneously meet the comprehensive needs of on-chip network routers in high-performance scenarios. Summary of the Invention

[0009] This invention addresses the technical problem of low utilization rate of virtual channel design in existing on-chip network routers.

[0010] To address the aforementioned technical problems, in a first aspect, the present invention provides an on-chip network virtual channel routing system, comprising:

[0011] The routing egress calculation module is used to receive data packets transmitted from the network sender through the routing ingress and determine the routing egress buffer to which the data packets need to be forwarded, wherein each routing egress buffer corresponds to a routing egress.

[0012] The virtual channel buffer allocation module is used to allocate a sequence number of a free virtual channel buffer for the data packet;

[0013] The virtual channel buffer module includes multiple virtual channel buffers, each corresponding to a different routing egress buffer. These virtual channel buffers are shared. The virtual channel buffer module buffers cache data packets using the corresponding virtual channel buffer according to the sequence number assigned by the virtual channel buffer allocation module, and records pointer information of the data packets using a linked list. The virtual channel buffer module also sends the data packets to the routing egress buffer when the routing egress buffer is ready for data forwarding, and forwards the data via the routing egress buffer.

[0014] The credit release module is used to release credit information to the network sender to control the maximum number of data packets it can send.

[0015] Furthermore, the pointer information of the data packets recorded by the virtual channel buffer module through a linked list includes virtual channel buffer entries and exit pointer entries, wherein:

[0016] The virtual channel buffer table entry includes the following fields:

[0017] The entry validity bit is used to mark the validity of the current linked list entry of the virtual channel buffer;

[0018] An exit pointer is used to mark the route exit buffer to which the data packet needs to be forwarded;

[0019] The next packet validity bit is used to mark the validity of other packets that are forwarded to the same route egress buffer as the packet;

[0020] The next data packet pointer is used to mark the sequence number of the virtual channel buffer where other data packets corresponding to the valid bits of the next data packet are located;

[0021] Data packet information, used to mark the data content of the data packet;

[0022] The export pointer entry includes the following fields:

[0023] The valid bit of the exit pointer is used to mark whether the data packet in the virtual channel buffer needs to be sent to the routing exit buffer;

[0024] An exit header pointer is used to mark the first data packet in the virtual channel buffer that needs to be sent to the routing exit buffer;

[0025] The exit tail pointer is used to mark the last data packet in the virtual channel buffer that needs to be sent to the routing exit buffer.

[0026] Furthermore, the credit release module is specifically used for:

[0027] During system initialization, the credit information of a preset initial size is released into the network, the preset initial size being the same as the maximum number of entries in the linked list of the virtual channel buffer module;

[0028] When the routing egress calculation module receives the data packet, it releases the credit information of size 1 into the network. At the same time, it uses a preset credit register to record the current number of data packets as the accumulated credit information available to the network sender.

[0029] In each clock cycle, a credit information of size 1 is released into the network based on the accumulated credit information, and the value of the accumulated credit information is reduced.

[0030] Furthermore, the virtual channel buffer module is also used for:

[0031] After the data packet is sent to the routing egress buffer, the linked list of the corresponding virtual channel buffer is updated.

[0032] Furthermore, the routing egress calculation module determines the routing egress buffer to which the data packet needs to be forwarded based on the XY dimension order routing algorithm.

[0033] Furthermore, the virtual channel buffer allocation module uses a sequential lookup method to allocate a free virtual channel buffer sequence number to the data packet.

[0034] Secondly, the present invention also provides a data forwarding method, which is implemented in the on-chip network virtual channel routing system as described above, and the data forwarding method includes the following steps:

[0035] S201. Based on the routing egress calculation module, receive the data packet transmitted by the network sender through the routing ingress, and determine the routing egress buffer to which the data packet needs to be forwarded;

[0036] S202. Determine whether the routing egress buffer is ready for data forwarding, wherein:

[0037] If not, the virtual channel buffer allocation module allocates a free virtual channel buffer sequence number to the data packet; and according to the sequence number allocated by the virtual channel buffer allocation module, the virtual channel buffer module uses the virtual channel buffer with the corresponding sequence number to buffer the data packet, and records the pointer information of the data packet through a linked list;

[0038] If so, proceed to step S203;

[0039] S203. Determine whether the virtual channel buffer has the data packet in the cache waiting to be forwarded, wherein:

[0040] If so, based on the virtual channel buffer module, the data packet is sent to the routing egress buffer, and the data is forwarded via the routing egress;

[0041] If not, return to step S202;

[0042] S204. Based on the credit release module, release credit information to the network sender to control the maximum number of data packets it sends.

[0043] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a data forwarding program stored in the memory and executable on the processor, wherein the processor executes the data forwarding program to implement the steps in the data forwarding method described above.

[0044] Fourthly, the present invention also provides a storage medium storing a data forwarding program, which, when executed by a processor, implements the steps in the data forwarding method described above.

[0045] The beneficial effects achieved by this invention are that it proposes an on-chip network virtual channel routing system based on a linked list. This system ensures the order of data packets with the same source and destination through linked list pointer updates, improves the utilization and throughput of virtual channels, and reduces the latency of data packet transmission. Furthermore, the design of this invention based on the linked list pointer structure has a low area cost in the on-chip network. While meeting the routing performance requirements, it can also adapt to different scenario needs by configuring the number of virtual channel buffers, and has good compatibility. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of the on-chip network virtual channel routing system provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the credit release cycle provided in an embodiment of the present invention;

[0048] Figure 3 This is a flowchart illustrating the steps of the data forwarding method provided in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0051] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an on-chip network virtual channel routing system 100 provided in an embodiment of the present invention. The on-chip network virtual channel routing system 100 includes:

[0052] The routing egress calculation module 101 is used to receive data packets transmitted from the network sender through the routing ingress and determine the routing egress buffer to which the data packets need to be forwarded, wherein each routing egress buffer corresponds to a routing egress.

[0053] The virtual channel buffer allocation module 102 is used to allocate a sequence number of a free virtual channel buffer for the data packet;

[0054] The virtual channel buffer module 103 includes multiple virtual channel buffers corresponding one-to-one with different routing egress buffers. The different virtual channel buffers are designed to be shared. The virtual channel buffer module 103 is used to buffer the data packet using the virtual channel buffer with the corresponding sequence number allocated by the virtual channel buffer allocation module, and to record the pointer information of the data packet through a linked list. The virtual channel buffer module 103 is also used to send the data packet to the routing egress buffer when the routing egress buffer is ready for data forwarding, and to forward the data through the routing egress buffer.

[0055] Credit release module 104 is used to release credit information to the network sender to control the maximum number of data packets it sends.

[0056] To achieve the low-latency design goal, data packets transmitted from the network sender must be sent to the routing egress buffer within one clock cycle when the network is idle. This design is implemented under the premise that there are no data packets queuing in the virtual channel buffer that need to be sent to the same routing egress buffer, and that there is no back pressure from contention in the routing egress buffer. This is referred to as a fast path in this embodiment of the invention. Conversely, if data packets cannot be sent, they must first be stored in the virtual channel buffer; this is referred to as a slow path in this embodiment of the invention. It is understood that the on-chip network virtual channel routing system 100 proposed in this embodiment of the invention is designed for the slow path, aiming to improve the throughput of data packets stored in the virtual channel buffer.

[0057] Specifically, the high throughput of a routing system, i.e., the concurrent transmission of data packets corresponding to multiple routing egress buffers within a single clock cycle, only occurs when multiple routing egress buffers are back-pushed into the virtual channel buffer. To address this, this embodiment of the invention establishes an independent routing egress buffer for each routing egress to store data packets, and establishes a shareable virtual channel buffer for the data packets of each routing egress to improve utilization.

[0058] To achieve sequential output for packets with the same origin and destination, and reduce the complexity of upper-layer protocols, this embodiment of the invention uses a linked list to track the order information of data packets at each route exit within a shared virtual channel buffer. Data packets are sent sequentially according to the linked list entries. This design ensures that data packets with the same origin and destination are always sent in a first-in, first-out (FIFO) order. Specifically, in this embodiment, the pointer information of the data packets recorded by the virtual channel buffer module 103 through the linked list includes virtual channel buffer entries and exit pointer entries, wherein:

[0059] As shown in Table 1, the virtual channel buffer table entries include the following fields:

[0060] The entry validity bit is used to mark the validity of the current linked list entry of the virtual channel buffer;

[0061] An exit pointer is used to mark the route exit buffer to which the data packet needs to be forwarded;

[0062] The next packet validity bit is used to mark the validity of other packets that are forwarded to the same route egress buffer as the packet;

[0063] The next data packet pointer is used to mark the sequence number of the virtual channel buffer where other data packets corresponding to the valid bits of the next data packet are located;

[0064] Data packet information, used to mark the data content of the data packet;

[0065] Table 1 Virtual Channel Buffer Entries

[0066]

[0067] Similarly, to achieve the requirements of small area and low power consumption, this embodiment of the invention adopts a linked list design, using head pointers, tail pointers, and pointers to the next data packet exiting the same destination for each data packet to organize the sequence information. As shown in Table 2, the exit pointer entry includes the following fields:

[0068] The valid bit of the exit pointer is used to mark whether the data packet in the virtual channel buffer needs to be sent to the routing exit buffer;

[0069] An exit header pointer is used to mark the first data packet in the virtual channel buffer that needs to be sent to the routing exit buffer;

[0070] The exit tail pointer is used to mark the last data packet in the virtual channel buffer that needs to be sent to the routing exit buffer.

[0071] Table 2 Export Indicator Items

[0072]

[0073] Please refer to the following example: Figure 2 The schematic diagram of the credit release cycle shown is illustrated in this embodiment of the invention. Specifically, the credit release module 104 is used for:

[0074] During system initialization, the credit information of a preset initial size is released into the network, where the preset initial size is the same as the maximum number of entries in the linked list of the virtual channel buffer module; for example... Figure 2 In path A, the credit information of the preset initial size is equivalent to dynamically initializing the credit count of the network sender.

[0075] When the routing egress calculation module 101 receives the data packet, it releases a credit information of size 1 into the network. Simultaneously, it uses a preset credit register to record the current number of data packets as the accumulated credit information available to the network sender. Figure 2 In the B path, the newly added credit information is the number of data packets sent from the fast path or slow path to their respective exit buffers;

[0076] In each clock cycle, a credit information of size 1 is released into the network based on the accumulated credit information, and the value of the accumulated credit information is reduced; as... Figure 2 In the C path, the release of accumulated credit information will continue until the accumulated credit information reaches 0.

[0077] Specifically, when the on-chip network virtual channel routing system 100 has fully received the data packet and sent it to the egress buffer, it needs to release credit information into the network to inform the network sender. In existing scenarios, there may be situations where all routing egress points may send their respective data packets to their respective buffers within the same clock cycle. Therefore, theoretically, multiple credit information can be released into the network within one clock cycle. However, in reality, since the network sender can only send a maximum of one data packet based on the credit information in one clock cycle, the credit release module 104 in this embodiment does not need to release multiple credit information in one clock cycle (releasing multiple credit information would increase the wiring difficulty and the complexity of the network sender's processing). Instead, it releases multiple credit information over multiple clock cycles. As described in the above embodiment, the credit release module 104 releases only one credit information per clock cycle, which is equivalent to shaping and smoothing the credit release output.

[0078] Furthermore, in this embodiment of the invention, the virtual channel buffer module 103 is also used for:

[0079] After the data packet is sent to the routing egress buffer, the linked list of the corresponding virtual channel buffer is updated.

[0080] The routing egress calculation module 101 determines the routing egress buffer to which the data packet needs to be forwarded based on the XY-dimensional order routing algorithm. The XY-dimensional order routing algorithm is implemented through combinational logic, which has few logic levels. In this embodiment of the invention, it simplifies the routing process while ensuring timing convergence.

[0081] The virtual channel buffer allocation module 102 uses a sequential lookup method to allocate a free virtual channel buffer sequence number to the data packet. The sequential lookup method is also a simple logic, which can simplify the routing process while ensuring timing convergence.

[0082] The beneficial effects achieved by this invention are that it proposes an on-chip network virtual channel routing system based on a linked list. This system ensures the order of data packets with the same source and destination through linked list pointer updates, improves the utilization and throughput of virtual channels, and reduces the latency of data packet transmission. Furthermore, the design of this invention based on the linked list pointer structure has a low area cost in the on-chip network. While meeting the routing performance requirements, it can also adapt to different scenario needs by configuring the number of virtual channel buffers, and has good compatibility.

[0083] This invention also provides a data forwarding method, which is implemented as described in the on-chip network virtual channel routing system of the above embodiments. Please refer to [link / reference]. Figure 3 , Figure 3 This is a flowchart illustrating the steps of a data forwarding method provided in an embodiment of the present invention. The data forwarding method includes the following steps:

[0084] S201. Based on the routing egress calculation module, receive the data packet transmitted by the network sender through the routing ingress, and determine the routing egress buffer to which the data packet needs to be forwarded;

[0085] S202. Determine whether the routing egress buffer is ready for data forwarding, wherein:

[0086] If not, the virtual channel buffer allocation module allocates a free virtual channel buffer sequence number to the data packet; and according to the sequence number allocated by the virtual channel buffer allocation module, the virtual channel buffer module uses the virtual channel buffer with the corresponding sequence number to buffer the data packet, and records the pointer information of the data packet through a linked list;

[0087] If so, proceed to step S203;

[0088] S203. Determine whether the virtual channel buffer has the data packet in the cache waiting to be forwarded, wherein:

[0089] If so, based on the virtual channel buffer module, the data packet is sent to the routing egress buffer, and the data is forwarded via the routing egress;

[0090] If not, return to step S202;

[0091] S204. Based on the credit release module, release credit information to the network sender to control the maximum number of data packets it sends.

[0092] It is understood that step S204 is only used to release credit information. Referring to the functional description of the credit release module in the above embodiment, the execution of step S204 is not directly related to steps S201-S203, but is executed based on the system clock cycle.

[0093] Based on the steps in the data forwarding method in the above embodiments, the embodiments of the present invention can realize the same-origin-to-destination order of data packets based on the on-chip network virtual channel routing system, and improve the utilization and throughput of the virtual channel, and reduce the latency of data packet transmission. Refer to the description of the technical effects in the above embodiments, which will not be repeated here.

[0094] This invention also provides a computer device, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a data forwarding program stored in the memory 302 and capable of running on the processor 301.

[0095] The processor 301 calls the data forwarding program stored in the memory 302 to execute the steps in the data forwarding method provided in this embodiment of the invention. Please refer to... Figure 2 Specifically, it includes the following steps:

[0096] S201. Based on the routing egress calculation module, receive the data packet transmitted by the network sender through the routing ingress, and determine the routing egress buffer to which the data packet needs to be forwarded;

[0097] S202. Determine whether the routing egress buffer is ready for data forwarding, wherein:

[0098] If not, the virtual channel buffer allocation module allocates a free virtual channel buffer sequence number to the data packet; and according to the sequence number allocated by the virtual channel buffer allocation module, the virtual channel buffer module uses the virtual channel buffer with the corresponding sequence number to buffer the data packet, and records the pointer information of the data packet through a linked list;

[0099] If so, proceed to step S203;

[0100] S203. Determine whether the virtual channel buffer has the data packet in the cache waiting to be forwarded, wherein:

[0101] If so, based on the virtual channel buffer module, the data packet is sent to the routing egress buffer, and the data is forwarded via the routing egress;

[0102] If not, return to step S202;

[0103] S204. Based on the credit release module, release credit information to the network sender to control the maximum number of data packets it sends.

[0104] The computer device 300 provided in this embodiment of the invention can implement the steps in the data forwarding method as described in the above embodiments and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0105] This invention also provides a storage medium storing a data forwarding program. When the data forwarding program is executed by a processor, it implements the various processes and steps in the data forwarding method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0106] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to data forwarding programs or instructions (such as mobile phones, computers, servers, air conditioners, or network devices). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0107] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0108] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims, and all such changes are within the protection scope of the present invention.

Claims

1. An on-chip network virtual channel routing system, characterized in that, include: The routing egress calculation module is used to receive data packets transmitted from the network sender through the routing ingress and determine the routing egress buffer to which the data packets need to be forwarded, wherein each routing egress buffer corresponds to a routing egress. The virtual channel buffer allocation module is used to allocate a sequence number of a free virtual channel buffer for the data packet; The virtual channel buffer module includes multiple virtual channel buffers, each corresponding to a different routing egress buffer. These virtual channel buffers are shared. The virtual channel buffer module buffers cache data packets using the corresponding virtual channel buffer according to the sequence number assigned by the virtual channel buffer allocation module, and records pointer information of the data packets using a linked list. The virtual channel buffer module also sends the data packets to the routing egress buffer when the routing egress buffer is ready for data forwarding, and forwards the data via the routing egress buffer. A credit release module is used to release credit information to the network sender in order to control the maximum number of data packets it can send. Specifically, the credit release module is used for: During system initialization, the credit information of a preset initial size is released into the network, the preset initial size being the same as the maximum number of entries in the linked list of the virtual channel buffer module; When the routing egress calculation module receives the data packet, it releases the credit information of size 1 into the network. At the same time, it uses a preset credit register to record the current number of data packets as the accumulated credit information available to the network sender. In each clock cycle, a credit information of size 1 is released into the network based on the accumulated credit information, and the value of the accumulated credit information is reduced.

2. The on-chip network virtual channel routing system according to claim 1, characterized in that, The pointer information of the data packets recorded by the virtual channel buffer module through a linked list includes virtual channel buffer entries and exit pointer entries, wherein: The virtual channel buffer table entry includes the following fields: The entry validity bit is used to mark the validity of the current linked list entry of the virtual channel buffer; An exit pointer is used to mark the route exit buffer to which the data packet needs to be forwarded; The next packet validity bit is used to mark the validity of other packets that are forwarded to the same route egress buffer as the packet; The next data packet pointer is used to mark the sequence number of the virtual channel buffer where other data packets corresponding to the valid bits of the next data packet are located; Data packet information, used to mark the data content of the data packet; The export pointer entry includes the following fields: The valid bit of the exit pointer is used to mark whether the data packet in the virtual channel buffer needs to be sent to the routing exit buffer; An exit header pointer is used to mark the first data packet in the virtual channel buffer that needs to be sent to the routing exit buffer; The exit tail pointer is used to mark the last data packet in the virtual channel buffer that needs to be sent to the routing exit buffer.

3. The on-chip network virtual channel routing system according to claim 1, characterized in that, The virtual channel buffer module is also used for: After the data packet is sent to the routing egress buffer, the linked list of the corresponding virtual channel buffer is updated.

4. The on-chip network virtual channel routing system according to claim 1, characterized in that, The routing egress calculation module determines the routing egress buffer to which the data packet needs to be forwarded based on the XY dimension order routing algorithm.

5. The on-chip network virtual channel routing system according to claim 1, characterized in that, The virtual channel buffer allocation module uses a sequential lookup method to allocate a free virtual channel buffer sequence number to the data packet.

6. A data forwarding method, said data forwarding method being implemented based on the on-chip network virtual channel routing system according to any one of claims 1-5, characterized in that, The data forwarding method includes the following steps: S201. Based on the routing egress calculation module, receive the data packet transmitted by the network sender through the routing ingress, and determine the routing egress buffer to which the data packet needs to be forwarded; S202. Determine whether the routing egress buffer is ready for data forwarding, wherein: If not, the virtual channel buffer allocation module allocates a free virtual channel buffer sequence number to the data packet; and according to the sequence number allocated by the virtual channel buffer allocation module, the virtual channel buffer module uses the virtual channel buffer with the corresponding sequence number to buffer the data packet, and records the pointer information of the data packet through a linked list; If so, proceed to step S203; S203. Determine whether the virtual channel buffer has the data packet in the cache waiting to be forwarded, wherein: If so, based on the virtual channel buffer module, the data packet is sent to the routing egress buffer, and the data is forwarded via the routing egress; If not, return to step S202; S204. Based on the credit release module, release credit information to the network sender to control the maximum number of data packets it sends.

7. A computer device, characterized in that, include: The data forwarding method includes a memory, a processor, and a data forwarding program stored in the memory and executable on the processor, wherein the processor, when executing the data forwarding program, implements the steps of the data forwarding method as described in claim 6.

8. A storage medium, characterized in that, The storage medium stores a data forwarding program, which, when executed by a processor, implements the steps of the data forwarding method as described in claim 6.

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