Solid-state imaging device

Abstract

There is provided a solid-state imaging device according to the present invention including a pixel array including a plurality of pixels configured to output an analog signal by photoelectric conversion, and pixel partitions provided between the pixels, wherein the plurality of pixels are two-dimensionally arranged along a column in a first direction and a row in a second direction intersecting the first direction, and the pixel array includes a first region and a second region separated from each other by the pixel partition extending in the second direction.

Description

[0001] This application is a divisional application of Chinese patent application No. 202080064033.6. The application date of patent application No. 202080064033.6 is September 30, 2020, and the name of the invention is “Solid-state imaging device”. Technical Field

[0002] The present disclosure relates to a solid-state imaging device. Background Art

[0003] Conventional sensors, such as CMOS (Complementary Metal Oxide Semiconductor) devices, which include pixel arrays in which pixels are arranged, sequentially receive signals from predetermined devices, which disadvantageously reduces the frame rate. A possible configuration for increasing the frame rate includes a pixel array divided into multiple regions, with signal lines provided for each divided region, and analog circuits and logic circuits for receiving the signals. This configuration, which has poor compatibility with other circuits and can be complex, is not suitable for minimizing pixel size and increasing the number of pixels.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Publication No. 2012-054876 Summary of the Invention

[0007] Technical issues

[0008] To avoid this, consider dividing the pixel array into simple regions. This simple division allows multiple pixels in the pixel array that are adjacent to each other but are processed by different analog circuits (i.e., pixels that are adjacent to each other with a boundary between regions interposed between them) to propagate through signal lines with different signal processing timings. Due to the different signal processing timings, the timing of light reception for pixels that are adjacent to each other with a boundary interposed between them may be significantly different from that of other pixels that are adjacent to each other. This will cause rolling shutter deformation at the boundaries between regions.

[0009] The present disclosure provides a solid-state image pickup device including a plurality of regions in a pixel array and in which the occurrence of deformation is reduced.

[0010] Solution to the problem

[0011] According to one embodiment, a solid-state imaging device includes a first substrate and a second substrate. The first substrate includes a pixel array, wherein a plurality of pixels configured to output analog signals through photoelectric conversion are arranged two-dimensionally in columns along a first direction and rows along a second direction intersecting the first direction. The second substrate is stacked on the first substrate and includes an analog circuit that is positioned to overlap with the pixel array in a third direction intersecting the first and second directions and processes analog signals output from the pixels. The pixel array is divided into a first region and a second region by a pixel divider along the second direction, each region including continuous pixels. The analog circuit is divided into a first analog circuit and a second analog circuit that are connected to pixels belonging to the first region and pixels belonging to the second region, and the first analog circuit and the second analog circuit are adjacent to each other with a circuit divider interposed therebetween, and the circuit divider is positioned to overlap with the pixel divider in the third direction.

[0012] The pixel array may include a plurality of first signal lines arranged along a first direction, and may select one or more rows in the first direction from rows having pixels continuous in a second direction, and analog signals output from the pixels selected by the first signal lines may be processed by an analog circuit. The first signal lines may be used to specify pixels in units of rows.

[0013] The pixel array may include a plurality of second signal lines arranged along a second direction, and selecting one or more columns in the second direction from columns having pixels continuous in the first direction. Analog signals output from the pixels selected by the first signal lines are transmitted through the second signal lines and processed by analog circuits. The second signal lines may be electrically separated at pixel separators. The second signal lines are kept energized region by region in the pixel array without being connected to different regions, which enables shortening their routes.

[0014] The pixel dividing portion and the circuit dividing portion may be located near the middle of the pixel array in the first direction.

[0015] The solid-state imaging device may include a connection portion configured to connect the pixels and the analog circuit in a third direction at the pixel separator and the circuit separator. Thus, the second signal line may be separated near the middle of the pixel array, and the first substrate and the second substrate may be connected to each other near the separation.

[0016] The connection portion may include a first connection portion connected to the second signal line and configured to connect pixels belonging to the first region and the first analog circuit via the second signal line, and a second connection portion connected to the second signal line and configured to connect pixels belonging to the second region and the second analog circuit via the second signal line. The analog circuit of the second substrate may also be divided like the pixel array.

[0017] The solid-state imaging device may include a first switch configured to switch the connection state between the first connection portion and the second connection portion. Providing the first switch in the second substrate allows the floating diffusion portions in the first and second regions of the pixel array to maintain comparable potentials.

[0018] The first switch may switch a connection state between the first connection portion and the second connection portion based on a timing of an analog signal output to the analog circuit through the first connection portion or the second connection portion.

[0019] A plurality of first connection parts, a plurality of second connection parts, and a plurality of first switches may be provided along the second direction, and the plurality of first switches may be operable in a synchronized manner.

[0020] A plurality of first connection portions and a plurality of second connection portions may be provided along the second direction, and the solid-state imaging device may include a second switch configured to switch the connection state between the plurality of first connection portions, and a third switch configured to switch the connection state between the plurality of second connection portions. The second switch can maintain a constant potential in the row direction.

[0021] The second switch may switch the connection state between the first connection parts, and the third switch may switch the connection state between the second connection parts based on the timing of the analog signal output to the analog circuit through the first connection part or the second connection part.

[0022] The second switch and the third switch can be operated in a synchronized manner.

[0023] A plurality of second switches and a plurality of third switches may be provided along the second direction, and the plurality of second switches and the plurality of third switches may be operable in a synchronized manner.

[0024] A solid-state imaging device may include a first voltage source configured to apply a predetermined voltage to a plurality of first connection portions connected via a second switch, and a fourth switch configured to switch the connection state between the first voltage source and the plurality of first connection portions, wherein the second and fourth switches are operable in synchronization. This control allows the potential of the floating diffusion portion to be raised to a predetermined potential.

[0025] The solid-state imaging device may include a second voltage source configured to apply a predetermined voltage to a plurality of second connection portions connected via a third switch, and a fifth switch configured to switch the connection state between the second voltage source and the plurality of second connection portions, wherein the third and fifth switches are capable of operating in synchronization. Furthermore, all switches are capable of operating in synchronization. Synchronization may be performed based on the reset timing of the pixels or the timing of analog signal output from the pixels.

[0026] The number of the first connecting portions and the number of the second connecting portions may each be at least the same as the number of pixels present in a row.

[0027] The number of the first connection parts and the second connection parts can be at least the same as the product of the number of pixels existing in the row and the predetermined number. By providing the connection parts as described above, signals output from pixels belonging to the same row can be transmitted to the second substrate in parallel.

[0028] The connection portion may be in the form of a microbump, a micropad, or a through-hole.

[0029] The first analog circuit and the second analog circuit may process analog signals from different pixels belonging to one or more rows along the second direction at the same timing.

[0030] The first analog circuit and the second analog circuit may change the number of analog signals to be processed at the same timing according to predetermined conditions.

[0031] The second substrate may convert an analog signal into a digital signal, and the solid-state imaging device may include a logic circuit configured to process the digital signal.

[0032] The logic circuit may be positioned to intersect the analog circuit in a first direction.

[0033] The logic circuit may include a first logic circuit configured to process a digital signal output from the first analog circuit and a second logic circuit configured to process a digital signal output from the second analog circuit.

[0034] A solid-state imaging device may include a plurality of pixel dividing sections and a plurality of circuit dividing sections, as well as a pixel array divided into a plurality of regions and an analog circuit corresponding to each region.

[0035] The second substrate may include a signal processing circuit, an image processing circuit, a storage unit, a selector, and an interface. The signal processing circuit performs signal processing on a digital signal. The image processing circuit performs image processing on the digital signal, and the digital signal includes image information. The storage unit stores data selected from the digital signal, data output from the signal processing circuit, and data output from the image processing circuit. The selector selects at least one of the data output from the signal processing circuit, the data output from the image processing circuit, or the data stored in the storage unit. The interface outputs the data or signal selected by the selector to the outside, or receives input of data or signals from the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a block diagram of a solid-state imaging device according to an embodiment.

[0037] Figure 2 is a diagram illustrating the locations of a pixel array and analog circuits according to an embodiment.

[0038] Figure 3 is a diagram illustrating a stacked state of a pixel array and an analog circuit according to an embodiment.

[0039] Figure 4 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0040] Figure 5 is a diagram showing an overview of an analog circuit according to an embodiment.

[0041] Figure 6 is a diagram illustrating potentials in response to switch control of a second substrate according to an embodiment.

[0042] Figure 7 is a graph showing potentials in response to switch control of the second substrate according to a comparative example.

[0043] Figure 8 is a diagram illustrating a stacked state of a pixel array and an analog circuit according to an embodiment.

[0044] Figure 9 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0045] Figure 10 is a diagram showing a wiring example of a pixel array according to an embodiment.

[0046] Figure 11 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0047] Figure 12 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0048] Figure 13 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0049] Figure 14 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0050] Figure 15 is a diagram showing a wiring example of an analog circuit according to an embodiment.

[0051] Figure 16 is a diagram illustrating an example of a connection portion according to an embodiment.

[0052] Figure 17 is a diagram illustrating an example of a connection portion according to an embodiment.

[0053] Figure 18 is a diagram illustrating an example of a connection portion according to an embodiment.

[0054] Figure 19 FIG. 1 is a diagram illustrating an example of the position of a circuit on a second substrate according to an embodiment.

[0055] Figure 20 : is a diagram showing a stacked state of a solid-state imaging device according to an embodiment.

[0056] Figure 21 : is a diagram showing a stacked state of a solid-state imaging device according to an embodiment.

[0057] Figure 22 is a diagram illustrating application of voltage to an analog circuit according to an embodiment.

[0058] Figure 23 is a block diagram illustrating an example of an indirect time-of-flight sensor to which the present technology is applied.

[0059] Figure 24 This is a circuit diagram showing a configuration example of the pixel 10230 in an embodiment of the present technology.

[0060] Figure 25 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0061] Figure 26 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0062] Hereinafter, solid-state image pickup devices according to several embodiments will be described with reference to the accompanying drawings.

[0063] (First embodiment)

[0064] Figure 1 1 is a block diagram illustrating the functions of a solid-state imaging device 1 according to an embodiment. The solid-state imaging device 1 includes, for example, a first substrate 10 and a second substrate 20. The first substrate 10 includes an optical system 12 and a pixel array 14. The second substrate 20 includes an analog circuit 22, a logic circuit 24, and an input / output interface (hereinafter referred to as an input / output I / F) 26.

[0065] The optical system 12 is a system that corrects the optical path, aberration, etc. so that the pixel array 14 detects light. The optical system 12 including, for example, lenses (including virtual lenses) is installed so that the pixel array 14 appropriately receives light.

[0066] The pixel array 14 includes a plurality of pixels that perform photoelectric conversion on received light and output analog signals. The analog signal output from each pixel belonging to the pixel array 14 is transmitted to the second substrate 20 through the connection portion 30.

[0067] The analog circuit 22 is a circuit that processes the analog signal output from each pixel of the pixel array 14. The analog circuit 22 may include, for example, an ADC (Analog-to-Digital Converter) that converts the analog signal into image data or a digital signal. The analog circuit 22 outputs the digital image data converted from the analog signal to the logic circuit 24.

[0068] The analog circuit 22 may also include, for example, a DAC (digital-to-analog converter) that generates a digital signal for analog-to-digital conversion, a comparator that compares the voltage output from the DAC and the analog signal, a counter that counts the output from the comparator, and an amplifier that amplifies the output of the counter.

[0069] The logic circuit 24, which includes circuits for processing various acquired digital signals, performs appropriate signal processing on the digital signals output from the analog circuit 22. For example, the logic circuit 24, which is a digital circuit, may include a signal processing circuit and an image processing circuit. The image processing circuit may include, for example, a circuit for performing motion detection, a circuit for performing neural network processing, etc. The image processing circuit may also include circuits for performing, for example, various filtering processes, deformation processes, etc.

[0070] The input / output I / F 26 is an interface for outputting data output from the logic circuit 24 to the outside as needed and for receiving data input, requests, etc. from the outside. The solid-state imaging device 1 may further include a selector for selecting data output from the logic circuit 24, and the input / output I / F 26 may output a signal selected by the selector to the outside.

[0071] The connection portion 30 connects the first substrate 10 and the second substrate 20. In this embodiment, in particular, the connection is intended to output analog signals output from pixels belonging to the pixel array 14 located on the first substrate 10 to the analog circuit 22 located on the second substrate 20.

[0072] The above description is about the components related to the propagation paths of analog signals and digital signals according to the present embodiment. Therefore, any other components required for control are omitted. The first substrate 10 is appropriately provided with, for example, wiring that determines from which pixel of the pixel array 14 the output is to be received. In addition, the second substrate 20 is appropriately provided with a control circuit that is responsible for controlling the components of the solid-state imaging device 1. In addition, in addition to the above-mentioned connection portion 30, the connection between the first substrate 10 and the second substrate 20 can be appropriately additionally provided with, for example, a connection circuit for outputting a signal to a wiring that determines which pixel is selected from the pixels belonging to the pixel array 14.

[0073] Therefore, although not shown, elements, wiring, and the like for realizing the operation and effects of the solid-state imaging device 1 are appropriately provided.

[0074] Figure 2is a diagram showing an example of the positions of the pixel array 14 and the analog circuit 22 according to the present embodiment.

[0075] In the first substrate 10, the pixel array 14 includes a plurality of pixels 140 arranged in two dimensions. The pixels 140 are arranged along a first direction and a second direction. The pixels 140 each include, for example, a light receiving device such as a photodiode (PD), which receives light through a lens (i.e., the optical system 12) and outputs an analog signal based on the intensity of the received light. In the description, pixels that are continuous in the second direction are sometimes referred to as rows, and pixels that are continuous in the first direction are sometimes referred to as columns. That is, a plurality of rows of pixels that are continuous in the second direction are arranged in the first direction to form an array; in other words, a plurality of columns of pixels that are continuous in the first direction are arranged in the second direction to form an array.

[0076] The pixel array 14 has a first region 141 and a second region 142. The first region 141 and the second region 142 are separated from each other by a pixel separator 143. The pixel separator 143 is provided near the middle in the first direction, for example, across the pixel array 14 in the second direction.

[0077] The word "near the middle" means that, for example, in the case where the pixel array 14 includes n pixels 140 arranged along the first direction, the pixel separator 143 is arranged between the [n / 2]th pixel and the ([n / 2]+1)th pixel. [·] represents a floor function. It should be noted that this is not restrictive and the pixel separator 143 may be significantly or insignificantly offset to Figure 2 The pixel array 14 may be positioned at one of the upper side and the lower side thereof, rather than being exactly centered; however, “near the center” is broad in meaning here.

[0078] In the second substrate 20, for example, an analog circuit 22 is provided near the middle of the region where the pixel array 14 exists in a stacked state. In the second substrate 20, the dotted line indicates the range of the pixel array 14 provided in the stacked state in the first substrate 10. Therefore, the analog circuit 22 is provided so as to include the middle portion of the region where the pixel array 14 is provided and its vicinity.

[0079] The analog circuit 22 includes a first analog circuit 221 and a second analog circuit 222, and these circuits are arranged adjacent to each other with a circuit divider 223 interposed therebetween. When the first substrate 10 and the second substrate 20 are stacked, the circuit divider 223 is positioned so that, for example, it overlaps with the pixel divider 143 in the third direction. The position of the circuit divider 223 does not necessarily completely overlap with the pixel divider 143 and may be offset therefrom.

[0080] The first analog circuit 221 and the second analog circuit 222 each operate as an analog circuit. For example, the first analog circuit 221 and the second analog circuit 222 each operate as an ADC, converting analog signals output from the pixel 140 into digital signals and outputting them.

[0081] For example, in the vicinity of the pixel dividing portion 143 and the circuit dividing portion 223 , the pixel array 14 and the analog circuit 22 are connected by the connecting portion 30 that connects the first substrate 10 and the second substrate 20 .

[0082] Here, "nearby" refers to, for example, between the two pixels 140 closest to the pixel divider 143 in the first direction and the pixel divider 143. It should be noted that this is not restrictive, and for example, the connection portion 30 may not be located between the pixel 140 and the pixel divider 143, but may be positioned so as to overlap with one or more pixels 140 directly below it near the middle.

[0083] Figure 3 Schematically shows the positions of the pixel array 14 and the analog circuit 22 in the case where the first substrate 10 and the second substrate 20 are stacked. Figure 3 As shown, the pixel array 14 and the analog circuit 22 are stacked so that the pixel dividing section 143 and the circuit dividing section 223 overlap each other in the third direction near the middle of the pixel array 14 .

[0084] The connection portion 30 is positioned so as to connect the vicinity of the pixel divider 143 and the vicinity of the circuit divider 223 to each other along the third direction between the pixel array 14 and the analog circuit 22. The first analog circuit 221 and the second analog circuit 222 receive analog signals from the pixels 140 connected via the connection portion 30 and perform appropriate processing. As will be described later, for example, a digital circuit (logic circuit) is provided so as to be sandwiched outside the first analog circuit 221 and the second analog circuit 222 in the first direction.

[0085] Next, the connection between the pixel array 14 and the analog circuit 22 will be described in detail.

[0086] Figure 4 1 is a diagram showing an example of wiring of the pixel array 14 according to this embodiment. The analog signal output from the pixel 140 is transmitted through Figure 4 The wiring in is transmitted to the analog circuit 22. It should be noted that Figure 4 , the distance between pixels above and below the pixel divider 143 is drawn wider than the distance between other pixels; however, this is just for convenience of explanation, and the distance may actually be comparable to the distance between other pixels.

[0087] In the first substrate 10, the pixel array 14 is provided with a plurality of first signal lines 16 and a plurality of second signal lines 181 and 182. The second signal lines 181 and 182 in the same column are electrically separated near the pixel separator 143. In other words, in the first substrate 10, the second signal lines 181 connected to the pixels 140 belonging to the first region 141 and the second signal lines 182 connected to the pixels 140 belonging to the second region 142 are not directly electrically connected to each other.

[0088] Furthermore, the connection portion 30 includes a plurality of first connection portions 301 and a plurality of second connection portions 302 near the pixel dividing portion 143, and the pixels 140 are connected to the analog circuit 22 of the second substrate 20 via the second signal lines 181 and 182 and the connection portions. More specifically, the pixels 140 belonging to the first region 141 are connected to the analog circuit 22 via the second signal line 181 and the first connection portion 301, while the pixels 140 belonging to the second region 142 are connected to the analog circuit 22 via the second signal line 182 and the second connection portion 302.

[0089] The first signal lines 16 are wirings for selecting which row of pixels 140 in the pixel array 14 is to be processed for the analog signals output. For example, at the ends opposite to the pixels 140, the first signal lines 16 are connected to a row selection circuit, respectively, and select a row of signals to be output to the analog circuit 22 based on a signal from the row selection circuit.

[0090] The pixels 140 in a row selected by the first signal line 16 are transmitted to the first connection portion 301 or the second connection portion 302 through the second signal lines 181 and 182. Then, the first connection portion 301 or the second connection portion 302 outputs the analog signal output from the pixel 140 to the analog circuit 22 where analog signal processing is performed.

[0091] In the pixel array 14, the processing of the analog signal output from the pixel 140 is performed, for example, Figure 4 The lower lines in the are executed sequentially. For example, first the Figure 4 Pixels 140 in the bottom row of pixels 140 are processed in parallel in the analog circuit 22. The analog signals output from the pixels 140 are then processed in parallel in the analog circuit 22. Next, the upper row (i.e., the second row from the bottom) is processed in the same manner. This processing is performed, for example, by sequentially selecting rows from the bottom in response to a row-direction synchronization signal from a row selection circuit.

[0092] This also applies to the case where a pixel separator 143 is inserted between two rows; Figure 4After processing the row immediately below the pixel divider 143 in the first region, processing is performed on the row immediately above the pixel divider 143. In this case, signals from the pixels 140 belonging to the region 141 are transmitted to the analog circuit 22 via the second signal line 181 and the first connection portion 301, while signals from the pixels 140 belonging to the second region 142 are transmitted to the analog circuit 22 via the second signal line 182 and the second connection portion 302. Subsequently, scanning is sequentially performed from the lower side to the upper side of the second region 142 based on the row-direction synchronization signal.

[0093] For example, row selection is performed by applying a selection signal to one of the first signal lines 16 corresponding to the row selected by the row selection circuit based on a synchronization signal. The signal output portion of the pixel 140 belonging to the selected row and the current carrying state of the second signal lines 181 and 182 are controlled by the selection signal, so that the analog signal is output to the analog circuit 22. For example, the control of the current carrying state is performed by a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) having a gate connected to the first signal line 16 and having a drain and a source (alternatively, a source and a drain) connected to the pixel 140 and the second signal lines 181 and 182, respectively. This is not restrictive, and the current carrying state can be achieved by any other technology, for example, by a switch driven by a signal through the first signal line 16.

[0094] As described above, the area of ​​the pixel array 14 provided on the first substrate 10 is divided near its center, and the analog circuit 22 is positioned near its center in the stacked second substrate 20 so as to overlap. This shortens the transmission path of the signals output from the pixels 140 in the second signal lines 181 and 182. This shortened transmission path reduces the load on the second signal lines 181 and 182. Consequently, the solid-state imaging device 1 achieves reduced power consumption and faster analog signal processing. The sequential processing of rows in the pixel array 14 and this increased speed also reduce rolling shutter deformation.

[0095] (Second embodiment)

[0096] In the above embodiment, by additionally providing a switch in the second substrate 20 , the accuracy of analog signal processing can be further improved.

[0097] Figure 5 Schematically shows the connection of the circuit partitioning portion of the analog circuit 22 according to the present embodiment. Figure 5 The aspect ratio is adjusted in Figure 4 The approximate stacking relationship and approximate size relationship of the pixel array 14 in Figure 3 same.

[0098] As described above, the analog circuit 22 includes the first analog circuit 221 and the second analog circuit 222 with the circuit dividing section 220 interposed therebetween.

[0099] For example, the wiring connecting the first connection portion 301 from the first substrate 10 is located in the first analog circuit 221. For example, the wiring connecting the second connection portion 302 from the first substrate 10 is located in the second analog circuit 222. As shown in the figure, the connection portion is connected to the first analog circuit 221 or the second analog circuit 222 through, for example, a multiplexer (or analog switch) to process the transmitted analog signal. The analog circuit 22 may include a comparator circuit and a counter circuit (not shown) before the multiplexer so that the digital signal converted based on the output from the DAC is output to the multiplexer, etc.

[0100] In the second substrate 20 , the first switch 281 is provided between the first connection portion 301 and the second connection portion 302 .

[0101] The plurality of first connection parts 301 are connected to each other along the second direction, and the second switches 282 are provided between the first connection parts 301. The plurality of second connection parts 302 are connected to each other along the second direction, and the third switches 283 are provided between the second connection parts 302.

[0102] The plurality of first connection portions 301 are connected to a voltage source via a fourth switch 284, for example, at one end of a wiring interconnected by the second switch 282. The plurality of second connection portions 302 are connected to a voltage source via a fifth switch 285, for example, at one end of a wiring interconnected by the third switch 283. The voltage source may be a constant voltage source. Alternatively, the voltage applied by the voltage source may be uniform.

[0103] Multiple first switches 281 synchronously switch the current-carrying states between the first connection portion 301 and the second connection portion 302. In other words, each first connection portion 301 is connected to the second connection portion 302 at a predetermined timing, and the second connection portion is connected to the second signal line 182 in the same column as the second signal line 181 connected to the first connection portion in the pixel array 14. This connection is performed synchronously, so that the second signal line 181 and the second signal line 182 belonging to the same column in the plurality of columns are connected at the same timing in the second substrate 20. Therefore, the potentials of the first connection portion 301 and the second connection portion 302 are controlled to be the same at the predetermined timing, and this potential is output to the first analog circuit 221 and the second analog circuit 222. Due to this control, the potentials of the points in the analog circuit 22 that process pixels in the same column can be made equal.

[0104] The second switch 282 synchronously switches the current carrying state between the first connection portions 301. The third switch 283 synchronously switches the current carrying state between the second connection portions 302. Furthermore, the second switch 282 and the third switch 283 synchronously switch the current carrying state. In other words, the plurality of first connection portions 301 and the plurality of second connection portions 302 are connected to each other in a predetermined timing sequence and are controlled to have the same potential. This control allows the potential of the floating diffusion portions of the pixel 140 to be equalized.

[0105] Further, the second switch 282 and the third switch 283 may be synchronized to control the fourth switch 284 and the fifth switch 285. Such control makes it possible to increase the potential of the floating diffusion of the pixel 140 to a predetermined potential at a predetermined timing.

[0106] Furthermore, the first switch 281, the second switch 282, the third switch 283, the fourth switch 284, and the fifth switch 285 can be switched in a synchronized manner. For example, the switches can be switched on in synchronization from a reset period when an analog signal from a pixel 140 is received and processed to a next transmission period. This process allows the potential of the floating diffusion of the pixel 140 to be raised to a predetermined potential, and furthermore, the potentials of the first analog circuit 221 and the second analog circuit 222 are equalized.

[0107] Figure 6 An example of a timing diagram of the potentials of the first analog circuit 221 and the second analog circuit 222 when controlled using the aforementioned switches provided in the second substrate 20 is shown. The top diagram shows a row synchronization signal output from the row selection circuit. Based on the row synchronization signal, analog signals from pixels 140 belonging to a row are processed in parallel. The dashed line represents a reset signal, for example, which resets the charge in the circuits at this timing. At the time indicated by the dashed line, the row in which processing is switched from the first analog circuit 221 to the second analog circuit 222 is crossed.

[0108] The second figure from the top shows an example of a switch. The switches are turned on and off according to a synchronization signal. For example, the synchronization signal can be used to switch the states of all switches, or to switch only the first switch 281 independently, only the combination of the second switch 282 and the third switch 283 independently, or only the combination of the second switch 282, the third switch 283, the fourth switch 284, and the fifth switch 285 independently.

[0109] In this embodiment, for example, a synchronization signal is issued at the time when row scanning is completed. This is merely an example and is not intended to be limiting. For example, the synchronization signal need only be issued between the reset signal and the row synchronization signal. This timing can be written to a register, etc., provided in the solid-state imaging device 1. Furthermore, the synchronization signal (i.e., the time period during which the switch is turned on) can be set as desired within a range suitable for signal processing.

[0110] The third and fourth figures from the top illustrate potential transitions in the standby state. The fifth and sixth figures from the top illustrate potential transitions in the state of receiving analog signals. These potential transitions, for example, represent changes in the signals at the first connection 301 and the second connection 302.

[0111] In the diagram showing the potential state, the solid line shows the actual potential of the connection, and the dotted line shows that the potential state is unknown because the circuit is disconnected.

[0112] In contrast, Figure 7 FIG is a diagram showing a case where no switch control is performed (ie, all switches are turned off) as a comparative example. Figure 6 and Figure 7 To explain the function of the switch.

[0113] In the absence of the first switch 281, the processing of the first area 141 and the processing of the second area 142 are continuously performed in the first analog circuit 221 and the second analog circuit 222. In this case, at the time when the pixel 140 belonging to the row between which the pixel separator 143 is present is processed (e.g., Figure 7 Before the second analog circuit 222 is in the floating state (as indicated by the arrow in FIG), the potential of the second analog circuit 222 is unknown. Since signal processing is performed at an unknown potential, discontinuous signals are likely to occur. Signal discontinuities also occur not in the standby state but even during signal processing.

[0114] At the same time, the circuit can switch at the moment of eliminating the potential difference between the first analog circuit 221 and the second analog circuit 222 by turning on the first switch 281 at the end of the row in response to the synchronization signal. Figure 6 As shown by the arrows in , switching enables processing of analog signals from pixel 140 while maintaining continuity of the signal potential. Therefore, noise contamination due to discontinuity, excessive transient response, or measured potential lower than actual can be reduced.

[0115] Synchronous switching of the second switch 282 and the third switch 283 can shorten the Figure 7 The dotted lines in the figure show the floating period where the status is unknown. Figure 7In the case of region switching, the process starts from a floating state where the potential is unknown. Figure 6 As shown hashed, a stable analog signal can be obtained from the pixel 140 .

[0116] Furthermore, synchronization of the fourth switch 284 and the fifth switch 285 allows the floating potential to be controlled to a predetermined value, thereby obtaining a more stable measurement result.

[0117] As described above, continuity is ensured by the first switch 281, and the potential of the floating diffusion portion can be stabilized by the second switch 282, the third switch 283, the fourth switch 284 and the fifth switch 285, which enables high-precision processing even when the analog circuit 22 is divided.

[0118] Note that, as described above, only the first switch 281 may be switched, or only the second to fifth switches 282 to 285 may be switched. Furthermore, the first to fifth switches 281 to 285 may be switched synchronously. Alternatively, in another example, when the second to fifth switches 282 to 285 are switched on, control may be performed to switch on the first switch 281 at a later timing.

[0119] It should be noted that control can be performed as follows.

[0120] For example, when processing analog signals from pixels 140 belonging to the first region 141, the third switch 283 that connects the second connection portions 302 to each other can be always connected. By maintaining this connection, a relatively floating state can be maintained in the column until the pixel 140 to be processed is transferred from the first region 141 to the second region 142.

[0121] Furthermore, the fifth switch 285 may be in a connected state. By the third switch 283 and the fifth switch 285 thus being in a connected state, the floating state in the column can be maintained at a predetermined potential.

[0122] Likewise, when processing analog signals from the pixels 140 belonging to the second region 142 , the second switch 282 may be always connected, or the second switch 282 and the fourth switch 284 may be always connected.

[0123] (Third embodiment)

[0124] In the configuration of the above embodiment, one pixel partitioning section 143 and one corresponding circuit partitioning section 223 are provided respectively; however, this is not restrictive. In other words, the pixel array 14, the analog circuit 22, and the logic circuit 24 may be divided into more areas.

[0125] Figure 8is a diagram showing the stacking state of the pixel array 14 and analog circuit 22 according to this embodiment. The pixel array 14 includes three pixel dividers 143A, 143B, and 143C, while the corresponding second substrate 20 includes at least circuit dividers 223A and 223B, and further includes a circuit divider 223C. It should be noted that the circuit divider 223C is not an essential component.

[0126] The pixel array 14 is divided into two large regions by the pixel divider 143C. These regions are divided into a first region 141A and a second region 142A by the pixel divider 143A, and into a first region 141B and a second region 142B by the pixel divider 143B. Thus, the pixel array 14 is divided into four regions, for example.

[0127] For the pixels 140 that are continuous in the second direction, that is, pixels that belong to the same row, a single first signal line is provided as in the above embodiment. Meanwhile, the second signal lines connected to the pixels 140 that are continuous in the first direction and belong to the regions 141A, 142A, 141B, and 142B are divided between the regions as in the above embodiment and are output to the analog circuit 22 through the corresponding connection portions. In other words, in Figure 8 In the example of , four second signal lines are set for each column.

[0128] Figure 9 1 is a diagram showing an overview of the pixel array 14 according to the present embodiment. The pixel array 14 is divided into regions 141A, 142A, 141B, and 142B by pixel dividers 143A, 143B, and 143C. The divided regions are each provided with the same number of first signal lines 16 as the number of rows where the pixels 140 are located, for selecting whether to output the pixels 140 belonging to the same row. Figure 4 As shown, the distance between pixels is wider at locations that straddle the pixel divider; however, this is for ease of illustration only, and in practice, the distance may be comparable to the distance between other pixels.

[0129] In contrast, the second signal lines are arranged so that they are connected to the outputs of the pixels 140 belonging to the same column in each region, while being separated between different regions. For example, a plurality of second signal lines 181A arranged in region 141A connect the pixels 140 belonging to each column. At the same time, the second signal lines 181A are arranged so that they are not electrically connected to the second signal lines 182A, 181B, and 182B in the other regions 142A, 141B, and 142B.

[0130] Signal lines are connected to the second substrate 20 via connectors. For example, second signal line 181A in first region 141A is connected to analog circuit 22A via first connector 301A. The same applies to other signal lines; second signal line 182A in second region 142A is connected to analog circuit 22A via second connector 302A. Furthermore, the upper and lower sides in the figure are identical: second signal line 181B in first region 141B is connected to analog circuit 22B via first connector 301B, and second signal line 182B in second region 142B is connected to analog circuit 22B via second connector 302B.

[0131] The pixel array 14 may be divided into a plurality of regions by the plurality of pixel dividers 143 as described above. Figure 9 As shown, the second signal lines and the connection portions independently provided in each region are respectively connected to the analog circuits 22 of the second substrate 20 .

[0132] Return to Figure 8 , the second substrate 20 will be provided. Figure 9 The area of ​​the connection portion 30 is provided with a corresponding analog circuit. For example, the second substrate 20 includes an analog circuit 22A and an analog circuit 22B.

[0133] As described in the above embodiment, the circuit dividers 223A and 223B are present in each analog circuit 22 so that they overlap with the pixel dividers 143A and 143B in the third direction in a stacked state. The analog circuit 22A is divided into the first analog circuit 221A and the second analog circuit 222A by the circuit divider 223A, and the analog circuit 22B is divided into the first analog circuit 221B and the second analog circuit 222B by the circuit divider 223B. The configuration of each circuit is the same as Figure 5 The structure in is equivalent, so its detailed description is omitted.

[0134] For example, the logic circuit may be provided on the lower side of the first analog circuit 221A, between the second analog circuit 222A and the first analog circuit 221B, and on the upper side of the second analog circuit 222B in the drawing.

[0135] As described above, it is possible to increase the number of divisions of the pixel array 14. This increase in the number of divisions makes it possible to further reduce the load on the second signal line, thereby achieving further speed increase and reduction in power consumption.

[0136] (Fourth embodiment)

[0137] In the above embodiment, one second signal line is provided for one column; however, this is not restrictive. For example, multiple second signal lines may be provided for the pixels 140 belonging to one column. The multiple second signal lines may be provided with respective connection portions.

[0138] Figure 10 This figure schematically illustrates the pixel array, second signal lines, and connectors according to this embodiment. In the figure, the pixels, wiring, connectors, and the like are depicted on a flat surface; however, this is not restrictive. For example, a configuration in which pixels are positioned on the top surface, wiring is provided below them along a third direction, and the wiring and connectors are connected within the first substrate 10 is also acceptable.

[0139] The pixel array 14 includes a plurality of pixels 140. A plurality of second signal lines 181 and 182 are provided so that outputs from the pixels 140 belonging to the same column are connected thereto respectively. Unlike the above embodiment, the plurality of second signal lines 181 and 182 are provided between the columns. It should be noted that the first signal lines such as Figure 4 Set up as shown.

[0140] For example, twelve second signal lines 181 and 182 may be provided in each space between columns of pixels 140. In this case, analog signals output from twelve or fewer pixels 140 along the first direction may be output in parallel to the analog circuit 22 of the second substrate 20. In other words, analog signal processing may be applied in parallel to pixels 140 belonging to twelve or fewer rows at the same timing.

[0141] The first signal line (not shown) specifies no more than 12 rows at the same time. In the accompanying drawings, locations where the wiring from pixel 140 and the second signal line are connected are indicated by black dots, indicating an electrically connected location, while locations without black dots are not electrically connected. For example, a switch can be provided at the intersection of the wiring from pixel 140 and the second signal line, and the state of the switch can be appropriately switched via the first signal line to select a pixel 140 for analog signal processing.

[0142] As an example, Figure 11 The diagram shows the wiring of an analog circuit having 12 pairs of second signal lines and 12 pairs of connections. The left diagram shows the signal distribution when processing analog signals from pixels 140 belonging to the first region 141, while the right diagram shows the signal distribution when processing analog signals from pixels 140 belonging to the second region 142.

[0143] In the left figure, first connection 301 is represented by a solid line, and second connection 302 is represented by a dashed line. Thus, for each column, twelve pairs of connections are provided from first substrate 10 to second substrate 20. The six pairs of connections on the left transmit signals processed by first analog circuit 221, while the six pairs of connections on the right transmit signals processed by second analog circuit 222. First, second, and third switches 281, 282, and 283, not shown, may be provided between the respective connections. Furthermore, a fourth switch 284, a fifth switch 285, and a voltage source may be provided.

[0144] As shown in the left figure, when pixels 140 belonging to first region 141 are processed, the analog signals output from first connection portion 301 are appropriately distributed and output to first analog circuit 221 and second analog circuit 222. The analog circuits then process the analog signals in parallel. This allows signals from multiple pixels 140 to be output to multiple analog circuits via shorter paths.

[0145] When the pixel 140 to be subjected to signal processing transitions from a pixel belonging to the first area 141 to a pixel belonging to the second area 142, that is, when the first signal line selected by the row selection circuit exceeds the pixel dividing portion 143, a transition occurs as shown in the right figure. In response to this transition, the second connection portion 302 is allocated and connected to the first analog circuit 221 and the second analog circuit 222, so that signals from multiple pixels 140 can be appropriately processed in parallel in a manner similar to that described above.

[0146] As described above, this embodiment enables appropriate parallel processing of analog signals output from pixels 140 across multiple rows. Even when performing such processing, by providing the analog circuit 22 and appropriately arranging the signal lines as described in the above embodiment, the load on the second signal line can be reduced, thereby achieving high-speed analog signal processing and reduced power consumption.

[0147] Figures 12 to 15 The diagram shows various processing methods for routing, for example, so that 12 signals can be processed in parallel on a column-by-column basis as described above. Solid lines represent the wiring and connections to be used, while dashed lines represent the wiring and connections not in use at that moment. In this way, instead of processing pixels 140 in 12 rows of a column in parallel, processing can be performed in a switching manner depending on the desired image or settings such as low power consumption mode.

[0148] Figure 12 1 is a diagram showing an example of parallel processing of eight rows of pixels 140 in a column. For example, among the six pairs of first connection portions 301 and second connection portions 302, the connection portions in the middle portion can be used to form wiring. In this case, Figure 12In the embodiment, two of the 12 second signal lines at both ends and two in the middle are not used. By cooperating with the wiring of the first substrate 10 and the second substrate 20, eight rows of pixels 140 in one column can be processed in parallel.

[0149] Figure 13 1 is a diagram showing an example of parallel processing of, for example, four rows of pixels 140 in one column. In this way, four pixels can be processed in parallel using four connection portions and four wirings.

[0150] Figure 14 1 is a diagram showing an example of parallel processing of two rows of pixels 140 in one column. In this way, two pixels can be processed in parallel using two connection portions and two wirings.

[0151] For the case of 4 pixels or 2 pixels, the power consumption can be further reduced by not using the second analog circuit 222 . Figure 15 This diagram illustrates a case where two rows per column are processed without using second analog circuit 222. In this manner, it is also possible to process signals in parallel using only first analog circuit 221, without using second analog circuit 222. In this case, for example, control of third switch 283 and fifth switch 285 can be omitted, or first switch 281 can be omitted while providing sufficient time for the floating potential to fully charge.

[0152] Therefore, the wiring can be switched appropriately according to the situation. The situation may involve a predetermined condition. For example, in the case of a desire to shoot high-speed video, even if the power consumption increases, it can be achieved by using Figure 11 In contrast, in the case of taking a still image of a still object, etc., Figure 15 As shown, processing is applied by setting wiring to reduce power consumption.

[0153] Note that this embodiment describes a case where a single pixel divider and a single circuit divider are provided; however, this is not restrictive. In other words, even when multiple second signal lines are provided in each space between pixels, as described in this embodiment, the pixel array 14 and analog circuit 22 can be further divided. Furthermore, the number of wiring lines per column does not necessarily have to be 12; it can be 11 or fewer or 13 or more.

[0154] (Example of Connecting Portion)

[0155] will be Figure 1 The chip structure of the solid-state imaging device 1 in FIG. As described above, the solid-state imaging device 1 is in the form of a stacked body in which a first substrate 10 and a second substrate 20 are stacked. The first substrate 10 and the second substrate 20 are sometimes referred to as dies, respectively. For example, in Figure 2In the embodiment, the first substrate 10 and the second substrate 20 are respectively rectangular; however, the specific shape and size can be determined as desired. In addition, the sizes of the first substrate 10 and the second substrate 20 can be the same or different.

[0156] Figure 4 The pixel array 14 and the like are shown located on the first substrate 10. Additionally, at least a portion of the optical system 12 can be implemented in the first substrate 10 in an on-chip manner.

[0157] While including at least the analog circuit 22, the logic circuit 24, and the input / output I / F 26, the second substrate 20 also includes other necessary circuits. For example, a clock signal generation circuit may be provided that outputs a clock signal for determining the timing of the aforementioned row selection signal, synchronization signal, etc. Furthermore, a control circuit may be provided that fully or partially controls each circuit.

[0158] As a specific method of bonding the first substrate 10 and the second substrate 20 together, for example, a technology commonly known as CoC (Chip on Chip) can be used; the first substrate 10 and the second substrate 20 are cut out from a wafer and singulated, and then they are bonded to each other while being vertically stacked. Alternatively, a technology commonly known as CoW (Chip on Wafer) can be used; one of the first substrate 10 and the second substrate 20 (for example, the first substrate 10) is cut out from a wafer and singulated, and then the singulated first substrate 10 is bonded to the unsingulated second substrate 20. Alternatively, a technology commonly known as WoW (Wafer on Wafer) can be used; the first substrate 10 and the second substrate 20 are bonded to each other in a wafer state.

[0159] Various bonding methods may be used to bond the first substrate 10 and the second substrate 20. For example, plasma bonding may be used.

[0160] When bonding the first substrate 10 and the second substrate 20, the bonding shown in the following figure can be used to electrically connect the connecting portions of the first and second substrates 10 and 20. It should be noted that the specific state of the circuit is not shown; only the connection of the connecting portion is illustrated. Therefore, the illustration of various circuit components and the like is omitted in the drawings. Furthermore, the second signal line 181 will be described, but this also applies to the second signal line 182 and the like.

[0161] Figure 16is a diagram illustrating an example of a connection portion. As shown in the figure below, for example, the analog circuit 22 and the second signal line 181 are connected to the area where the second signal line 181 is located. Pixels 140 that receive light collected by the optical system 12 are connected to each other via the second signal line 181. The second signal line 181 is connected to the connection portion 30 including, for example, a microbump, and is therefore connected to the analog circuit 22. For example, respective micropads may be formed on both the pixel 140 side and the analog circuit 22 side, and the micropads may be connected to each other via the microbump.

[0162] Figure 17 1 is a diagram showing another example of a connection portion. For example, the connection portion 30 may be connected via a micro pad as shown in the figure. The first substrate 10 and the second substrate 20 may be directly connected to each other via the micro pad without inserting a substrate between the micro pads. Figure 16 The micro bumps in the .

[0163] Figure 18 The connection portion 30 may be in the form of a through hole, for example, and may connect the pixel 140 and the analog circuit 22 by bringing the through hole into contact with the second signal line 181 and the analog circuit 22 .

[0164] Furthermore, if necessary, for the pixel 140 , the first substrate 10 and the second substrate 20 connected by the connection portion 30 may be provided with additional connection lines for transmitting and receiving other signals.

[0165] (Example of Second Substrate)

[0166] Next, an embodiment of the second substrate 20 will be described. Figure 19 The example of implementing the second substrate 20 is shown. The area indicated by the dotted line in the second substrate 20 is the area in the first substrate 10 where the pixel array 14 exists.

[0167] For example, in the second substrate 20, the first analog circuit 221 and the second analog circuit 222 are positioned so that the circuit divider 223, which overlaps with the pixel divider in the third direction, is sandwiched therebetween. The DAC 23 can be provided adjacent to the analog circuits. For example, the logic circuit 24 can be provided so that the analog circuit 22 is sandwiched therebetween. The logic circuit 24 can include, for example, a first logic circuit adjacent to the first analog circuit 221 and a second logic circuit adjacent to the second analog circuit 222. In this case, the first logic circuit can process the signal output from the first analog circuit 221, and the second logic circuit can process the signal output from the second analog circuit 222.

[0168] In addition, if necessary, a CPU (Central Processing Unit) or a control unit may be provided. Furthermore, a memory 25 may be provided as a storage unit. The second substrate 20, which is a component independent of the pixel 140, includes the circuits required for the solid-state imaging device 1 as described above. In addition, although not shown, a selector, an input / output I / F 26, and the like may be provided.

[0169] Figure 20 The example of the two-layer solid-state imaging device 1 is shown. The first substrate 10 includes an optical system and a pixel array 14 having two-dimensionally arranged pixels 140. The first substrate 10 also includes wiring necessary to extract information about the pixels, such as first and second signal lines.

[0170] The second substrate 20 includes various switches for switching connection states between connection portions for connecting to the first substrate 10, an analog circuit 22, a logic circuit 24, a memory 25, and an input / output I / F 26. In addition, the second substrate 20 includes circuits required for controlling the solid-state imaging device 1.

[0171] Figure 21 1 is a diagram showing an example of a solid-state imaging device 1 in a three-layer form. The elements of the first substrate 10 and the second substrate 20 are Figure 19 The elements in the embodiment are substantially the same. However, the second substrate 20 does not include a memory, while the third substrate 40 includes a memory. Figure 21 In the embodiment, the third substrate 40 is located below the second substrate 20; however, this is not restrictive. In other words, the third substrate 40 may be disposed between the first substrate 10 and the second substrate 20.

[0172] Even in the case where the solid-state imaging device 1 has three layers, the connections between the layers are similar to those in the above-described embodiment; for example, the layers are connected by Figures 16 to 18 The connection methods shown are connected to each other.

[0173] Figure 22 2 is a diagram showing an example of the position of the power supply in the analog circuit 22 of the second substrate 20. In the figure, for visibility, only the case where the power supply is located at the position corresponding to the first analog circuit 221 is drawn; however, the power supply is also located on the second analog circuit 222 side.

[0174] In the drawings, for example, the shaded areas indicated by leftward-leaning lines are wiring to which a power supply voltage is applied, while the shaded areas indicated by rightward-leaning lines are wiring connected to a ground voltage. Thus, first analog circuit 221 is provided with wiring for power supply voltage and wiring for ground voltage at regular intervals. To facilitate understanding, the power supply is shown as being on the surface; however, the power supply is not on the surface but rather embedded, for example, beneath the circuitry of second substrate 20.

[0175] The analog circuit 22 is positioned in the middle, extending the power supply wiring on the chip of the second substrate 20. This reduces the power supply voltage observed at one end of the analog circuit 22 by an amount corresponding to the wiring resistance and current consumption. In this case, the uneven arrangement of the power supply wiring further degrades light-shielding properties in the second direction. To avoid this, the power supply wiring is arranged uniformly along the second direction, achieving horizontal equalization of the power supply. This reduces shadows in the second direction.

[0176] All embodiments have been described using CMOS sensors as an example; however, this is not limiting. This disclosure is applicable to CCDs (Charge Coupled Devices) and other types of light-receiving devices. For example, in a CCD, the charge of rows selected by a channel propagates sequentially and is processed by analog circuitry, achieving similar functions and effects.

[0177] The present disclosure may be used in indirect ToF sensors.

[0178] Figure 23 is a block diagram illustrating an example of an indirect time-of-flight sensor to which the present technology is applied.

[0179] [Construction example of an indirect time-of-flight sensor]

[0180] Figure 23 1 is a block diagram illustrating an example of an indirect time-of-flight sensor 10000 to which an embodiment of the present technology is applied. The indirect time-of-flight sensor 10000 includes a sensor chip 10001 and a circuit chip 10002 stacked on the sensor chip 10001 .

[0181] A pixel region 10020, comprising a plurality of pixels arranged in a two-dimensional grid pattern, is disposed on the sensor chip. Pixel region 10020 can be arranged in rows and columns and may include a plurality of column signal lines. Each column signal line is coupled to each pixel. Furthermore, a vertical drive circuit 10010, a column signal processing circuit 10040, a timing adjustment circuit 10050, and an output circuit 10060 are disposed on circuit chip 10002.

[0182] The vertical drive circuit 10010 is configured to drive pixels and output pixel signals to the column signal processing section 10040. The column signal processing section 10040 applies analog-to-digital (AD) conversion to the pixel signals and outputs the converted pixel signals to the output circuit. The output circuit 10060 applies CDS (Correlated Double Sampling) processing and other methods to the data from the column signal processing section 10040 and outputs the data to the subsequent signal processing circuit 10120.

[0183] The timing control circuit 10050 is configured to control each driving timing of the vertical driving circuit 10010. The column signal processing section and output circuit 10060 operates in synchronization with the vertical synchronization signal.

[0184] The pixel area 10020 includes a plurality of pixels arranged in a two-dimensional grid pattern. Each pixel is configured to receive infrared light and photoelectrically convert the infrared light into a pixel signal.

[0185] Furthermore, vertical signal lines VSL1 and VSL2 are routed vertically within each column of pixel 10230. Assuming the total number of columns in pixel region 10020 is M (M is an integer), a total of 2×M vertical signal lines are routed. Each pixel has two taps. Vertical signal line VSL1 connects to Tap A of pixel 10230, and vertical signal line VSL2 connects to Tap B of pixel 10230. Furthermore, vertical signal line VSL1 transmits pixel signal AINP1, and vertical signal line VSL2 transmits pixel signal AINP2.

[0186] The vertical drive circuit 210 sequentially selects and drives a row of pixel blocks 221, so that pixel signals AINP1 and AINP2 are simultaneously output from each pixel block 221 in the row. In other words, the vertical drive circuit 210 simultaneously drives the pixels 230 in the 2kth row and the (2k+1)th row. It should be noted that the vertical drive circuit 210 is an example of the drive circuit described in the claims.

[0187] Figure 24 10230 is a circuit diagram showing an example of the configuration of a pixel 10230 according to a mode of the present technology. Pixel 10230 includes a photodiode 10231, two transfer transistors 10232 and 10237, two reset transistors 10233 and 10238, two taps (floating diffusion layers 10234 and 10239), two amplifying transistors 10235 and 102339, and two selecting transistors 10236 and 10239.

[0188] The photodiode 10231 is configured to perform photoelectric conversion on received light to generate electric charge. The photodiode 10231 is arranged on the back side of the semiconductor substrate, opposite to the front side of the semiconductor substrate where the circuit is arranged. This type of solid-state imaging element is called a back-illuminated solid-state imaging element. It should be noted that a front-illuminated type configuration including the photodiode 10231 arranged on the front side can also be used instead of a back-illuminated type.

[0189] The transfer transistor 10232 is configured to transfer charges from the photodiode 10231 to Tap A 10239 and Tap B 10234 in sequence according to a transfer signal TRG from the vertical drive circuit 10010. Tap A 10239 and Tap B 10234 are configured to accumulate the transferred charges to generate a voltage according to the amount of accumulated charges.

[0190] The overflow transistor 10242 is a transistor configured to sequentially discharge the charge of the photodiode 10231 to VDD, and has a function of resetting the photodiode.

[0191] Reset transistors 10238 and 10233 are configured to extract charge from Tap A 10239 and Tap B 10234, respectively, to initialize the charge amount in response to a reset signal RSTp from the vertical drive circuit 210. Amplifier transistors 10240 and 10235 are configured to amplify the voltages of Tap A 10239 and Tap B 10234, respectively. Select transistors 10236 and 10241 are configured to output pixel signals, which are amplified voltage signals, to the column signal processing section 10040 via two vertical signal lines (e.g., VSL1 and VSL2) in response to a select signal SELp from the vertical drive circuit 210. VSL1 and VSL2 are connected to the input terminals of an analog-to-digital converter in the column signal processing circuit 10040.

[0192] It should be noted that the circuit configuration of the pixel 230 is not limited to Figure 23 The construction is shown by way of example in FIG.

[0193] The technology according to the present disclosure (the present technology) is applicable to a variety of products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, an unmanned aerial vehicle, a ship, or a robot.

[0194] Figure 25 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0195] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Figure 25In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0196] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices and mechanisms: a drive force generating device such as an internal combustion engine or a drive motor for generating the vehicle's drive force; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0197] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and other devices.

[0198] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, or characters on the road surface, or detect the distance thereto.

[0199] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0200] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, a driver status detection unit 12041 that detects the driver's status is connected to the in-vehicle information detection unit 12040. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0201] The microcomputer 12051 calculates control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following-distance-based driving, speed maintenance driving, collision warning of the vehicle, and lane departure warning of the vehicle.

[0202] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to drive automatically without relying on the driver's operation.

[0203] Furthermore, the microcomputer 12051 can output a control instruction to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights so as to, for example, switch from high beam to low beam, based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0204] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify information to a passenger of the vehicle or the outside of the vehicle. Figure 25 In the example of FIG, as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0205] Figure 26 This is a diagram illustrating an example of the installation position of the camera unit 12031.

[0206] exist Figure 26 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0207] For example, cameras 12101, 12102, 12103, 12104, and 12105 are positioned at the following locations: the front nose, side mirrors, rear bumper, and rear doors of vehicle 12100, and the upper portion of the windshield inside the vehicle. Camera 12101 located at the front nose and camera 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Cameras 12102 and 12103 located on the side mirrors primarily capture images from the sides of vehicle 12100. Camera 12104 located on the rear bumper or rear door primarily captures images from behind vehicle 12100. Camera 12105 located at the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0208] It should be noted that Figure 26 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located on the rear bumper or rear door. For example, by superimposing image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100, viewed from above, is obtained.

[0209] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0210] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104. Specifically, microcomputer 12051 can identify the nearest three-dimensional object that appears on the driving path of vehicle 12100 and travels in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher) as the leading vehicle. Furthermore, microcomputer 12051 can pre-set a following distance to be maintained ahead of the leading vehicle and execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Consequently, cooperative control aimed at autonomous driving, such as autonomous driving that allows the vehicle to travel autonomously without relying on driver input, can be implemented.

[0211] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data of 3D objects into 3D object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects. The microcomputer 12051 extracts the classified 3D object data and uses it to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that are visually recognizable by the driver of the vehicle 12100 and those that are difficult for the driver of the vehicle 12100 to visually recognize. The microcomputer 12051 then determines a collision risk, representing the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0212] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This identification of a pedestrian may be performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the object's outline to determine whether a pedestrian exists. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline for emphasis, superimposed on the identified pedestrian. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0213] The above embodiment can be arranged in the following manner.

[0214] (1) A solid-state imaging device comprising:

[0215] a first substrate having a pixel array in which a plurality of pixels configured to output analog signals through photoelectric conversion are two-dimensionally arranged in columns along a first direction and in rows along a second direction intersecting the first direction; and

[0216] a second substrate stacked on the first substrate, the second substrate including an analog circuit configured to overlap the pixel array in a third direction intersecting the first direction and the second direction and to process the analog signals output from the pixels, wherein

[0217] The pixel array is divided into a first area and a second area by pixel separators along the second direction, each area including consecutive pixels, and

[0218] The analog circuit is divided into a first analog circuit and a second analog circuit, the first analog circuit and the second analog circuit are connected to the pixels belonging to the first area and the pixels belonging to the second area, the first analog circuit and the second analog circuit are adjacent to each other with a circuit dividing portion interposed therebetween, and the circuit dividing portion is configured to overlap with the pixel dividing portion in the third direction.

[0219] (2) The solid-state imaging device according to (1), wherein

[0220] The pixel array includes a plurality of first signal lines arranged along the first direction, and one or more rows in the first direction are selected from rows having the pixels continuous in the second direction, and

[0221] The analog signal output from the pixel selected by the first signal line is processed by the analog circuit.

[0222] (3) The solid-state imaging device according to (2), wherein

[0223] The pixel array includes a plurality of second signal lines arranged along the second direction, and one or more columns in the second direction are selected from columns having the pixels continuous in the first direction.

[0224] The analog signal output from the pixel selected by the first signal line is transmitted through the second signal line and processed by the analog circuit,

[0225] The second signal line is electrically separated at the pixel dividing portion.

[0226] (4) The solid-state imaging device according to (3), wherein the pixel dividing section and the circuit dividing section are arranged near the middle of the pixel array in the first direction.

[0227] (5) The solid-state imaging device according to (3), comprising:

[0228] A connection portion is configured to connect the pixels and the analog circuit in the third direction at the pixel separation portion and the circuit separation portion.

[0229] (6) The solid-state imaging device according to (5), wherein

[0230] The connecting portion includes

[0231] a first connection portion connected to the second signal line and configured to connect the pixels belonging to the first area and the first analog circuit through the second signal line, and

[0232] A second connection portion is connected to the second signal line and is configured to connect the pixels belonging to the second area and the second analog circuit through the second signal line.

[0233] (7) The solid-state imaging device according to (6), comprising:

[0234] A first switch is configured to switch a connection state between the first connection portion and the second connection portion.

[0235] (8) The solid-state imaging device according to (7), wherein

[0236] Based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion,

[0237] The first switch switches the connection state between the first connection portion and the second connection portion.

[0238] (9) The solid-state imaging device according to (7) or (8), wherein

[0239] A plurality of first connecting portions, a plurality of second connecting portions, and a plurality of first switches are provided along the second direction, and

[0240] The plurality of first switches operate in a synchronized manner.

[0241] (10) The solid-state imaging device according to any one of (6) to (9), wherein

[0242] A plurality of the first connecting portions and a plurality of the second connecting portions are provided along the second direction,

[0243] The solid-state imaging device comprises:

[0244] a second switch configured to switch a connection state between the plurality of first connection portions; and

[0245] A third switch is configured to switch a connection state between the plurality of second connection portions.

[0246] (11) The solid-state imaging device according to (10), wherein

[0247] Based on the timing of the analog signal output to the analog circuit through the first connection portion or the second connection portion,

[0248] The second switch switches the connection state between the first connection parts, and

[0249] The third switch switches the connection state between the second connection parts.

[0250] (12) The solid-state imaging device according to (10) or (11), wherein the second switch and the third switch operate in a synchronized manner.

[0251] (13) The solid-state imaging device according to (10) or (11), wherein

[0252] A plurality of the second switches and a plurality of the third switches are arranged along the second direction, and

[0253] The plurality of second switches and the plurality of third switches operate in a synchronized manner.

[0254] (14) The solid-state imaging device according to any one of (10) to (13), comprising:

[0255] a first voltage source configured to apply a predetermined voltage to the plurality of first connection portions connected through the second switch; and

[0256] a fourth switch configured to switch a connection state between the first voltage source and the plurality of first connection portions, wherein:

[0257] The second switch and the fourth switch operate in a synchronous manner.

[0258] (15) The solid-state imaging device according to any one of (10) to (14), comprising:

[0259] a second voltage source configured to apply a predetermined voltage to the plurality of second connection portions connected through the third switch; and

[0260] a fifth switch configured to switch a connection state between the second voltage source and the plurality of second connection portions, wherein:

[0261] The third switch and the fifth switch operate in a synchronized manner.

[0262] (16) The solid-state imaging device according to any one of (6) to (15), wherein the number of the first connection portions and the second connection portions is at least the same as the number of the pixels existing in the row.

[0263] (17) The solid-state imaging device according to (16), wherein the number of the first connection portions and the second connection portions is at least the same as the product of the number of the pixels existing in the row and a predetermined number.

[0264] (18) The solid-state imaging device according to any one of (5) to (17), wherein

[0265] The connecting portion is in the form of a micro bump, a micro pad or a through hole.

[0266] (19) The solid-state imaging device according to any one of (1) to (18), wherein the first analog circuit and the second analog circuit process the analog signals from different pixels belonging to one or more rows along the second direction at the same timing.

[0267] (20) The solid-state imaging device according to (19), wherein the first analog circuit and the second analog circuit change the number of analog signals to be processed at the same timing according to a predetermined condition.

[0268] (21) The solid-state imaging device according to (20), wherein

[0269] The analog circuit converts the analog signal into a digital signal, and

[0270] The solid-state imaging device includes a logic circuit configured to process the digital signal.

[0271] (22) The solid-state imaging device according to (21), wherein the logic circuit is positioned so as to interpose the analog circuit in the first direction.

[0272] (23) The solid-state imaging device according to (21) or (22), wherein

[0273] The logic circuit includes

[0274] a first logic circuit configured to process the digital signal output from the first analog circuit, and

[0275] A second logic circuit is configured to process the digital signal output from the second analog circuit.

[0276] (24) The solid-state imaging device according to (1), comprising:

[0277] a plurality of the pixel dividing sections and a plurality of the circuit dividing sections; and

[0278] A pixel array is divided into a plurality of areas and the analog circuit corresponds to each of the areas.

[0279] (25) The solid-state imaging device according to any one of (1) to (24), wherein

[0280] The second substrate includes

[0281] a signal processing circuit configured to perform signal processing on the digital signal,

[0282] an image processing circuit configured to perform image processing on the digital signal, the digital signal including image information,

[0283] a storage section configured to store data freely selected from the digital signal, the data output from the signal processing circuit, and the data output from the image processing circuit,

[0284] a selector configured to freely select at least one of the data output from the signal processing circuit, the data output from the image processing circuit, and the data stored in the storage section, and

[0285] An interface is configured to output the data or signal selected by the selector to the outside or to receive input of data or signals from the outside.

[0286] (26) The solid-state imaging device according to any one of (7) to (15), wherein all of the switches operate in a synchronized manner.

[0287] (27) The solid-state imaging device according to (26), wherein synchronization is performed at a timing based on a reset timing of the pixel or a timing at which the analog signal is output from the pixel.

[0288] One aspect of the present disclosure is not limited to the above-described embodiments; it includes various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. If necessary, components of the embodiments may be combined and used. In other words, various additions, changes, and partial deletions may be made without departing from the conceptual concept and scope of the present disclosure as defined by the claims and their equivalents.

[0289] Reference Signs List

[0290] 1: Solid-state imaging device

[0291] 10: First substrate

[0292] 12: Optical system

[0293] 14: Pixel Array

[0294] 140: Pixels

[0295] 141, 141A, 141B: First Area

[0296] 142, 142A, 142B: Second area

[0297] 143, 143A, 143B, 143C: pixel dividers

[0298] 16: First signal line

[0299] 181, 182: Second signal line

[0300] 20: Second substrate

[0301] 22, 22A, 22B: Analog circuits

[0302] 221, 221A, 221B: First analog circuit

[0303] 222, 222A, 222B: Second analog circuit

[0304] 223, 223A, 223B, 223C: Circuit separator

[0305] 23: DAC

[0306] 24: Logic Circuits

[0307] 25: Memory

[0308] 26: Input / output interface

[0309] 281: First switch

[0310] 282: Second switch

[0311] 283: The third switch

[0312] 284: The fourth switch

[0313] 285: Fifth switch

[0314] 30: Connection

[0315] 301: First connection part

[0316] 302: Second connecting portion.

Claims

1. A solid-state imaging device comprising: A pixel array including a plurality of pixels configured to output analog signals through photoelectric conversion and a pixel separator provided between the pixels, wherein The plurality of pixels are two-dimensionally arranged along columns in a first direction and rows in a second direction intersecting the first direction, and the pixel array includes a first region and a second region separated from each other by the pixel separator extending in the second direction.

2. The solid-state imaging device according to claim 1, wherein The solid-state imaging device also includes an analog circuit stacked on the pixel array in a third direction intersecting the first direction and the second direction, the analog circuit processing the analog signal output from the pixel, and the analog circuit including a first analog circuit and a second analog circuit with a circuit divider inserted therebetween, the first analog circuit being connected to the pixels belonging to the first area, and the second analog circuit being connected to the pixels belonging to the second area.

3. The solid-state imaging device according to claim 2, wherein The circuit dividing portion is configured to overlap with the pixel dividing portion in the third direction.

4. The solid-state imaging device according to any one of claims 1 to 3, wherein The pixel separator is arranged near the center of the pixel array in the first direction.

5. The solid-state imaging device according to claim 3, wherein The pixel array comprises: a plurality of first signal lines arranged along the first direction, wherein one or more rows in the first direction are selected from rows having the pixels continuous in the second direction; and a plurality of second signal lines arranged along the second direction, wherein one or more columns in the second direction are selected from the columns having the pixels continuous in the first direction; The analog signal output from the pixel selected by the first signal line is transmitted through the second signal line and processed by the analog circuit, The second signal line is electrically cut off at the pixel separation portion.

6. The solid-state imaging device according to claim 5, comprising: A connection portion is configured to connect the pixels and the analog circuit in the third direction at the pixel separation portion and the circuit separation portion.

7. The solid-state imaging device according to claim 6, wherein The connecting portion includes: a first connection portion connected to the second signal line and configured to connect the pixels belonging to the first area and the first analog circuit through the second signal line; and A second connection portion is connected to the second signal line and is configured to connect the pixels belonging to the second area and the second analog circuit through the second signal line.

8. The solid-state imaging device according to claim 7, comprising: A first switch is configured to switch a connection state between the first connection portion and the second connection portion.

9. The solid-state imaging device according to claim 8, wherein A plurality of first connecting portions, a plurality of second connecting portions, and a plurality of first switches are provided along the second direction, and The plurality of first switches operate synchronously.

10. The solid-state imaging device according to claim 7, wherein A plurality of the first connection parts and a plurality of the second connection parts are provided along the second direction, and The solid-state imaging device comprises: a second switch configured to switch a connection state between the plurality of first connection portions; and A third switch is configured to switch a connection state between the plurality of second connection portions.

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