Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device capable of more reliably connecting pillars having a higher density to bit lines. According to one embodiment, a semiconductor memory device includes: a stacked body formed by stacking a plurality of conductive layers separated from each other; a plurality of columns each having a semiconductor layer extending in the stacked body in a first direction, which is a stacking direction of the stacked body, and arranged in (2n + 1) rows in a second direction intersecting the first direction, where n is an integer of 1 or more; a plurality of first plugs disposed at the upper ends of the plurality of pillars, respectively, and electrically connected to the semiconductor layer; and a plurality of bit lines extending in the second direction above the plurality of pillars and electrically connected to corresponding ones of the plurality of first plugs, respectively, the plurality of first plugs having a longitudinal direction in a direction intersecting the second direction when viewed from the first direction.

Description

[0001] Reference to related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-042009 (filing date: March 18, 2024), and this application incorporates all the contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0004] In semiconductor memory devices such as three-dimensional nonvolatile memories, high integration is progressing. Consequently, the pillars forming memory cells are becoming denser, and reliably connecting the bit lines corresponding to each pillar has become a challenge. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor memory device capable of more reliably connecting high-density pillars to bit lines.

[0006] A semiconductor storage device of an embodiment comprises: a laminate formed by stacking a plurality of conductive layers separately from each other; a plurality of pillars each having a semiconductor layer extending within the laminate in a stacking direction of the laminate, i.e., a first direction, and arranged in (2n+1) columns in a second direction intersecting the first direction, where n is an integer greater than 1; a plurality of first plugs respectively arranged at the upper ends of the plurality of pillars and electrically connected to the semiconductor layer; and a plurality of bit lines extending along the second direction above the plurality of pillars and respectively electrically connected to corresponding first plugs among the plurality of first plugs, wherein the plurality of first plugs have a length direction in a direction intersecting the second direction when viewed from the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram of a semiconductor memory device according to an embodiment.

[0008] Figure 2 1 is an equivalent circuit diagram showing an example of the configuration of a memory cell array included in the semiconductor memory device according to the embodiment.

[0009] Figure 3 It is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment.

[0010] Figure 4 FIG. 1 is a schematic diagram illustrating an example of the layout of various configurations in a storage area of ​​a semiconductor storage device according to an embodiment.

[0011] Figure 5This is a flowchart illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0012] Figure 6 FIG. 1 is a schematic diagram showing an example of the layout of various configurations in a storage area of ​​a semiconductor storage device according to a comparative example.

[0013] Figure 7 This is a schematic diagram showing an example of the layout of various configurations in a storage area of ​​a semiconductor storage device according to a modification of the embodiment. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the present invention is not limited to the following embodiments. In addition, the constituent elements in the following embodiments include elements that can be easily conceived by those skilled in the art or substantially the same elements.

[0015] (Configuration Example of Semiconductor Memory Device)

[0016] Figure 1 FIG is a block diagram of a semiconductor memory device 1 according to an embodiment. Figure 1 As shown, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, an instruction register 350, a sequencer 360, a ready / busy circuit 370, a voltage generating circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0017] The input / output circuit 310 controls input and output of a signal DQ with an external device such as a memory controller (not shown) that controls the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0018] The input circuit transmits data DAT such as write data WD received from an external device to the data register 540 , transmits an address ADD to the address register 340 , and transmits a command CMD to the command register 350 .

[0019] The output circuit transmits the status information STS received from the status register 330 , the data DAT such as the read data RD received from the data register 540 , and the address ADD received from the address register 340 to an external device.

[0020] The logic control circuit 320 receives signals such as a chip enable signal CEn, a command lock enable signal CLE, an address lock enable signal ALE, a write enable signal WEn, and a read enable signal REn from external devices, and controls the I / O circuit 310 and the sequencer 360 based on the received signals.

[0021] The status register 330 temporarily stores status information STS during, for example, data writing, reading, and erasing operations, and notifies an external device whether the operation has been completed normally.

[0022] The address register 340 temporarily stores the address ADD received from the external device via the input / output circuit 310 . The address register 340 also transmits the row address RA to the row decoder 520 and the column address CA to the column decoder 550 .

[0023] The command register 350 temporarily stores the command CMD received from the external device via the input / output circuit 310 and transmits the command CMD to the sequencer 360 .

[0024] The sequencer 360 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generating circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 according to the command CMD stored in the command register 350, thereby executing write operations, read operations, and erase operations.

[0025] The ready / busy circuit 370 sends a ready / busy signal R / Bn to an external device according to the operation status of the sequencer 360 .

[0026] The voltage generating circuit 380 generates voltages required for programming, reading, and erasing operations under the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generating circuit 380 to the memory cells in the memory cell array 510.

[0027] The memory cell array 510 includes a plurality of blocks BLK (BLK0 to BLKn). n is an integer greater than or equal to 2. A block BLK is a collection of memory cells associated with bit lines and word lines, and serves as a unit for erasing data. Memory cells are configured, for example, as transistors and store nonvolatile data.

[0028] By including such a memory cell, the semiconductor memory device 1 according to the embodiment is configured as, for example, a NAND-type nonvolatile memory.

[0029] The row decoder 520 decodes the row address RA. In addition, the row decoder 520 selects any block BLK based on the decoding result. In addition, the row decoder 520 applies a required voltage to the block BLK.

[0030] During a read operation, the sense amplifier module 530 senses data read from the memory cell array 510. Furthermore, the sense amplifier module 530 transmits read data RD to the data register 540. During a write operation, the sense amplifier module 530 transmits write data WD to the memory cell array 510.

[0031] The data register 540 includes multiple latch circuits. The latch circuits store write data WD and read data RRD. For example, during a write operation, the data register 540 temporarily stores write data WD received from the input / output circuit 310 and transmits it to the sense amplifier module 530. Furthermore, during a read operation, the data register 540 temporarily stores read data RD received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0032] The column decoder 550 decodes the column address CA, for example, during a write operation, a read operation, and an erase operation, and selects a latch circuit in the data register 540 based on the decoding result.

[0033] Furthermore, the circuit group arranged around the memory cell array 510 is also referred to as a peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may also include a status register 330, an address register 340, a command register 350, and a sequencer 360. Furthermore, the peripheral circuit may also include the input / output circuit 310, the logic control circuit 320, the ready / busy circuit 370, and the voltage generation circuit 380.

[0034] As described above, the semiconductor memory device 1 according to the embodiment includes the memory cell array 510 including a plurality of memory cells and the peripheral circuits for operating the plurality of memory cells.

[0035] Figure 2 1 is an equivalent circuit diagram showing an example of the configuration of a memory cell array 510 included in the semiconductor memory device 1 according to the embodiment.

[0036] As described above, the memory cell array 510 includes multiple blocks BLK. Each of the multiple blocks BLK includes multiple string units SU. Each of the multiple string units SU includes multiple memory strings MS. One end of each of the multiple memory strings MS is connected to peripheral circuits such as the sense amplifier module 530 via a bit line BL. The other end of each of the multiple memory strings MS is connected to the peripheral circuit via a common source line SL.

[0037] Memory string MS includes a drain select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC, and a source select transistor STS. Hereinafter, drain select transistor STD and source select transistor STS may be simply referred to as select transistors (STD, STS).

[0038] A memory cell MC is, for example, a field-effect transistor (FET) that includes a charge storage layer within its gate insulating layer. The threshold voltage of a memory cell MC varies depending on the amount of charge in the charge storage layer. By setting one or more threshold voltages, a memory cell MC can store one or more bits of data. Word lines WL are connected to the gate electrodes of each of the multiple memory cells MC corresponding to a memory string MS. These word lines WL are commonly connected to all memory strings MS within a block BLK.

[0039] The select transistors (STD, STS) are, for example, field-effect transistors. The gate electrodes of the select transistors (STD, STS) are connected to select gate lines (SGD, SGS), respectively. The drain select line SGD connected to the drain select transistor STD is provided corresponding to each string unit SU and is commonly connected to all memory strings MS in a string unit SU. The source select line SGS connected to the source select transistor STS is commonly connected to all memory strings MS in a block BLK.

[0040] One end of the word line WL and the select gate line (SGD, SGS) is connected to peripheral circuits such as the row decoder 520 .

[0041] (Example of Physical Structure of Semiconductor Memory Device)

[0042] Next, use Figure 3 and Figure 4 , the physical structure of the semiconductor memory device 1 according to the embodiment will be described.

[0043] Figure 3 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. Figure 3 (a) is a cross-sectional view of the semiconductor memory device 1 along the X direction. Figure 3 (b) is a schematic plan view showing the layout of the semiconductor memory device 1 .

[0044] However, in Figure 3 In (a), hatching is omitted for the sake of easy viewing of the accompanying drawings. Figure 3 In (a), in addition to showing the structure that does not necessarily exist in the same cross section, some upper layer wirings are omitted.

[0045] In this specification, the X and Y directions are both directions along the plane of the word line WL, with the X and Y directions being orthogonal to each other. The electrical extraction direction of the word line WL is sometimes referred to as the third direction, which is along the X direction. A direction intersecting the third direction is sometimes referred to as the second direction, which is along the Y direction. However, semiconductor memory device 1 may include manufacturing variations, so the second and third directions are not necessarily orthogonal. The direction in which multiple word lines WL are stacked is sometimes referred to as the first direction, which corresponds to the vertical direction of semiconductor memory device 1.

[0046] like Figure 3 As shown in FIG. 1 (a), a semiconductor memory device 1 includes a semiconductor substrate SB on which, from the bottom of the paper, an electrode film EL, a source line SL, a laminate LM, and a peripheral circuit CBA are provided. In the laminate LM, one or more select gate lines SGS, a plurality of word lines WL, and one or more select gate lines SGD are separately laminated.

[0047] A source line SL is arranged on the electrode film EL, with an insulating layer 60 interposed therebetween. Multiple plugs PG are arranged in the insulating layer 60, maintaining electrical continuity between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for externally supplying power and signals to the semiconductor memory device 1 are provided on the same layer as the electrode film EL. A select gate line SGS, multiple word lines WL, and a select gate line SGD are sequentially stacked on the source line SL to form a stacked body LM.

[0048] By the above configuration, the voltage generating circuit 380 (see Figure 1 ) A source potential is applied to the source line SL via the electrode film EL and the plug PG.

[0049] like Figure 3 As shown in Figures (a) and (b), a memory region MR is arranged in the center of the laminate LM in the X direction, and step regions SR are arranged at both ends in the X direction. These memory region MR and step regions SR are divided into multiple regions by multiple plate-like portions PT extending in the X direction, penetrating multiple word lines WL and the like.

[0050] Furthermore, a region disposed between the plate-like portions PT adjacent to each other in the Y direction and including the memory region MR and the step region SR corresponds to the aforementioned one block BLK (see Figure 2 As described above, the memory region MR includes a plurality of memory cells MC (see Figure 2 ), the above-mentioned block area BLK becomes the deletion unit of these data.

[0051] Furthermore, multiple separation layers SHE are arranged between adjacent plate-like portions PT in the Y direction, extending along the select gate line SGD and along the X direction. These separation layers SHE extend along the X direction across the entire memory region MR and reach a portion of the step region SR at both ends in the X direction. These separation layers SHE are, for example, insulating layers such as silicon oxide layers.

[0052] Thus, between the mutually adjacent plate-like portions PT, the region divided into the pattern of the selection gate line SGD by the separation layer SHE corresponds to the above-mentioned string unit SU (see Figure 2 ) is an example of the physical structure of .

[0053] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and select gate lines SGD and SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells MC are formed at the intersections of the pillars PL and the word lines WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional nonvolatile memory in which the memory cells MC are three-dimensionally arranged in the memory region MR.

[0054] Thus, the memory region MR is equivalent to the memory cell array 510 (see Figure 2 ) is an example of a physical structure. In addition, the pillar PL is equivalent to the above-mentioned memory string MS (refer to Figure 2 ) is an example of the physical structure of .

[0055] In the step region SR, multiple word lines WL and select gate lines SGD and SGS are processed and terminated in a stepped shape. At this point, as they move away from the memory region MR in the X direction, the multiple word lines WL and select gate lines SGD and SGS that constitute the terrace portion move from the upper layer to the lower layer, causing the terrace portion to descend toward the source line SL.

[0056] Furthermore, the separation layer SHE is processed into a stepped portion of the select gate line SGD extending from the memory region MR to the step region SR. This separates the select gate line SGD into multiple regions within a single block region BLK. In other words, by extending the separation layer SHE through the portion above the multiple word lines WL, the upper portion of the laminate LM is divided into a pattern corresponding to the multiple select gate lines SGD.

[0057] Contacts CC are located on each terrace of each level, each consisting of multiple word lines WL and select gate lines SGD and SGS. Each level has one contact CC connected to each word line WL and select gate line SGD and SGS. Each level has one contact CC connected to each word line WL and select gate line SGS. Each level has one contact CC connected to each select gate line SGD, separated by a separation layer SHE.

[0058] Here, in one block region BLK, a plurality of contacts CC are arranged on one side of the step region SR on both sides in the X direction. When viewed from one side in the X direction, for example, a plurality of contacts CC are arranged every three block regions BLK.

[0059] That is to say, in Figure 3 In the example (b), in the block area BLK at the top of the page, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, for example, in the stepped region SR on the left side of the page. Furthermore, in the block area BLK immediately below and two blocks below this block area BLK, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, on the right side of the page. Furthermore, in the block area BLK at the bottom of the page, multiple contacts CC are arranged in the stepped region SR on the left side of the page.

[0060] therefore, Figure 3 The contacts CC in the stepped regions SR at both ends in the X direction shown in (a) belong to different block regions BLK and are not actually located in the same cross section.

[0061] These contacts CC lead out the word lines WL and other layers stacked in multiple layers. More specifically, these contacts CC apply write and read voltages to memory cells MC contained in a storage region MR at the center of the word lines WL via the word lines WL at the same height as the memory cells MC.

[0062] In this specification, the direction in which terrace surfaces of word lines WL and the like processed into a staircase shape face is defined as the upper side of semiconductor memory device 1 .

[0063] A plurality of word lines WL, select gate lines SGD and SGS, pillars PL, and contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components.

[0064] The semiconductor substrate SB on the insulating layer 50 is, for example, a silicon substrate. The row decoder 520 including transistors TR and wiring, the sense amplifier module 530 (see FIG. 5 ) and the like are arranged on the surface of the semiconductor substrate SB. Figure 1 ) and other peripheral circuits CBA. Various voltages applied from the contacts CC to the memory cells MC are controlled by the peripheral circuits CBA electrically connected to these contacts CC. Thus, the peripheral circuits CBA control the electrical operation of the memory cells MC.

[0065] The peripheral circuit CBA is covered by an insulating layer 40. By joining the insulating layer 40 to an insulating layer 50 covering multiple word lines WL, etc., a semiconductor storage device 1 is formed that includes multiple word lines WL and selection gate lines SGD, SGS, pillars PL, and contacts CC that constitute the peripheral circuit CBA.

[0066] Figure 4 1 is a schematic diagram showing an example of the layout of various configurations in the memory region MR of the semiconductor memory device 1 according to the embodiment.

[0067] In more detail, Figure 4 (a) is a schematic diagram showing the detailed structure of the column PL. Figure 4 (b) and (c) are partial enlarged views of the storage area MR. Figure 4 (b) is a diagram omitting the bit line BL. Figure 4 (c) is a diagram showing the bit line BL. Figure 4 (d) is a schematic plan view showing a portion of the memory region MR.

[0068] like Figure 4 As shown in (d), as described above, the memory region MR between the plate-like portions PT adjacent to each other in the Y direction is separated into a plurality of sections by the plurality of separation layers SHE extending in the direction along the X direction.

[0069] Furthermore, between the plate-like portion PT and the separation layer SHE adjacent to each other in the Y direction, and between the separation layers SHE adjacent to each other in the Y direction, a plurality of pillars PL are arranged in a plurality of rows extending in the X direction. Figure 5 In the row (d), the plurality of columns PL are arranged in five rows R1 to R5. However, when viewed in the stacking direction of the stack LM, one end of the columns PL in the rows R1 and R5 adjacent to the separation layer SHE overlaps with the separation layer SHE.

[0070] In the arrangement of these columns PL, the columns PL belonging to adjacent columns R1 and R2, columns R2 and R3, columns R3 and R4, and columns R4 and R5 are arranged so that their Y-direction positions are staggered so that they do not overlap. On the other hand, the columns PL belonging to adjacent columns R1, R3, and R5, and columns R2 and R4, are arranged so that their Y-direction positions coincide with each other. Thus, the columns PL are arranged in a staggered pattern when viewed, for example, from the stacking direction of the laminate LM. More preferably, the columns PL are arranged with substantially equal spacing between them.

[0071] Furthermore, as described above, by arranging the multiple pillars PL in a manner that allows for interference between some of the pillars PL and the separation layer SHE, a periodic arrangement of the pillars PL, such as a staggered arrangement, can be maintained. This improves the machining accuracy of the pillars PL when forming the multiple pillars PL at a high density. Furthermore, as described above, the separation layer SHE, such as an insulating layer, does not affect the electrical properties of the pillars PL even if it comes into contact with them.

[0072] Above these pillars PL, for example, a plurality of bit lines BL extending in the Y direction are arranged at predetermined intervals in the X direction. More preferably, the plurality of bit lines BL are arranged at substantially equal intervals in the X direction.

[0073] Each pillar PL is electrically connected to any one of these bit lines BL. At this time, in order to be able to drive the memory cells MC belonging to each pillar PL individually, the pillars PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, and between the separation layers SHE adjacent in the Y direction, are respectively connected to different bit lines BL.

[0074] Here, the laminated body LM has a 2-Tier structure in which sacrificial layers corresponding to a plurality of word lines WL are laminated twice. In the 2-Tier laminated body LM, the staircase shapes of the pillars PL and the step region SR are also formed in two stages.

[0075] like Figure 4 As shown in (a), a MANOS structure including a semiconductor layer CN extending in the stacking direction of the stacked body LM and an insulating layer ME having a multilayer structure is formed inside the pillar PL. With this MANOS structure, a memory cell MC is formed at the intersection of the pillar PL and the word line WL, and select gates STD and STS are formed at the intersection of the pillar PL and the select gate lines SGD and SGS, respectively (see FIG. Figure 2 ).

[0076] Furthermore, one Y-direction end of the pillar PL in column R1, located between the plate-shaped portion PT and the isolation layer SHE, overlaps with the isolation layer SHE at the height of the select gate line SGD, resulting in a missing portion. Furthermore, the select gate line SGD surrounding the pillar PL in column R1 overlaps with the isolation layer SHE, resulting in a missing portion. However, the select transistor STD formed at the intersection of the pillar PL and the select gate line SGD is configured to function as the select transistor STD in the pillar PL in column R1 as well. The isolation layer SHE does not reach the height of the word line WL, preventing a missing portion from occurring in the pillar PL in column R1. Neither does a missing portion occur in the word line. Therefore, the memory cell MC formed at the intersection of the pillar in column R1 and the word line WL remains functional.

[0077] Similarly, one Y-direction end of the column PL in column R5, located between the two isolation layers SHE, overlaps with the isolation layer SHE at the height of the select gate line SGD, resulting in a missing portion. Furthermore, the select gate line SGD surrounding the column PL in column R5 overlaps with the isolation layer SHE, resulting in a missing portion. However, the select transistor STD formed at the intersection of the column PL and the select gate line SGD is configured to function as the select transistor STD in the column PL in column R5. The isolation layer SHE does not reach the height of the word line WL, preventing a missing portion from occurring in the column PL in column R5. Neither does a missing portion occur in the word line. Therefore, the memory cell MC formed at the intersection of the column R5 and the word line WL remains functional.

[0078] Furthermore, for example, in a two-tiered stacked body LM, the pillars PL include lower pillars LMH located in the lower portion of the stacked body LM, and upper pillars UMH located in the upper portion of the stacked body LM and connected to the lower pillars LMH. Plugs CH and VY are located sequentially from the pillar PL side at the upper ends of the pillars PL, and each pillar PL is connected to the upper bit line BL via these plugs CH and VY.

[0079] like Figure 4 As shown in FIG. 1( b ), the pillars PL have, for example, a circular shape when viewed from the stacking direction of the layered body LM. However, the pillars PL may have other shapes such as an oval or elliptical shape.

[0080] The plug CH at the upper end of the column PL has a longitudinal direction along the X direction, and has, for example, an elliptical shape when viewed from the stacking direction of the laminate LM. However, as long as it has a longitudinal direction along the X direction, the plug CH may have another shape, such as an oval or a rectangular shape with rounded corners. The length of the plug CH can be set, for example, to be at least 1.1 times and less than 2 times the length of the short side of the plug CH.

[0081] When viewed in the stacking direction of the laminate LM, the plug CH is smaller than the pillar PL and is arranged to fit within the upper surface of the pillar PL. Furthermore, the center point of the plug CH, when viewed in the stacking direction of the laminate LM, substantially coincides with the center point of the corresponding pillar PL.

[0082] On the other hand, the plug VY disposed on the upper surface of the plug CH has, for example, an elliptical shape having a longitudinal direction along the direction Y. That is, the plug VY extends in the direction in which the bit line BL extends.

[0083] Furthermore, the center point of the plug VY, as viewed in the stacking direction of the stacked body LM, is substantially aligned with the center point of the corresponding pillar PL and plug CH in the Y direction, but is offset in the X direction. The amount of offset between the center point of the plug VY and the center point of the corresponding pillar PL and plug CH differs for each pillar PL, so that the pillars PL disposed between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, and between the separation layers SHE adjacent in the Y direction, are connected to different bit lines BL.

[0084] like Figure 4 As shown in (c), it can be seen that if the bit line BL is connected to Figure 4 By having the above configuration, the pillars PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction and between the separation layers SHE adjacent in the Y direction are connected to different bit lines BL, respectively.

[0085] More specifically, the X-direction position of each plug VY is determined based on the X-direction position of the bit line BL to which it is connected among the plurality of bit lines BL. Therefore, as described above, the X-direction offset between the center point of the plug VY and the center points of the corresponding pillar PL and plug CH varies. This shift in center point allows the pillars PL arranged between the plate-like portion PT and the isolation layer SHE, and between isolation layers SHE, to be connected to different bit lines BL.

[0086] That is, in Figure 4 In the example shown in (c), between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL1, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL4, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL2, is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL5, is connected to bit line BL3 via plugs CH and VY.

[0087] In addition, Figure 4In the example shown in (c), between the isolation layers SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL5, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL2, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL4, is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL1, is connected to bit line BL3 via plugs CH and VY.

[0088] In this way, the plurality of bit lines BL are connected to any one of the pillars PL in each column R1 to R5 in a five-cycle arrangement. In other words, the pillars PL in the arrangement of the plurality of pillars PL belonging to any of the columns R1 to R5 are connected to every five bit lines BL in the plurality of bit lines BL arranged in the Y direction, the same number as the number of pillars PL arranged.

[0089] (Method for Manufacturing Semiconductor Memory Device)

[0090] Next, use Figure 5 , a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figure 5 This is a flowchart illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0091] like Figure 5 As shown in FIG. 1 , lower-layer wirings such as source lines SL are formed on a supporting substrate such as a silicon substrate (step S101 ).

[0092] Next, a plurality of sacrificial layers such as silicon nitride layers are stacked separately from one another above the source line SL to form a lower ONO structure, thereby forming a first stack (step S111). Furthermore, a portion of the first stack is processed into a step-like shape to form a lower step, which is then covered with an insulating layer 50 (step S112).

[0093] Furthermore, lower pillars LMH, which serve as the lower structure of the pillars PL, are formed on the first stacked layer (step S113 ). However, at this stage, the lower pillars LMH are filled with a sacrificial layer such as an amorphous silicon layer.

[0094] Next, a plurality of sacrificial layers such as silicon nitride layers are stacked separately from each other on the first stack to form an upper ONO structure, thereby forming a second stack (step S121). Furthermore, a portion of the second stack is processed into a step-like shape to form an upper step, which is then filled with an insulating layer 50 (step S122).

[0095] Furthermore, a memory hole, which becomes the upper structure of the pillar PL, namely, the upper pillar UMH, is formed in the second stacked layer (step S123 ) and the sacrificial layer filled in the lower pillar LMH is removed through the memory hole.

[0096] Next, a MANOS structure is formed on the lower pillars LMH and the upper pillars UMH, thereby forming pillars PL (step S131 ).

[0097] Next, a slit ST is formed through the 2-Tier stack (step S132). Furthermore, a removal solution such as hot phosphoric acid is flowed through the slit ST to remove the sacrificial layer of the stack (step S133). Furthermore, a source gas such as tungsten is flowed through the slit ST to form a plurality of word lines WL and the like in the portion where the sacrificial layer has been removed (step S134).

[0098] By such a replacement process, a 2-Tier structured stacked body LM is formed in which a plurality of word lines WL and the like are stacked separately from each other.

[0099] Next, an insulating layer or the like is filled into the slit ST to form the plate-shaped portion PT (step S135). Furthermore, a separation layer SHE is formed in the memory region MR, extending along the X direction and reaching the step region SR (step S136). Thus, one or more select gate lines SGD are formed in the upper portion of the laminate LM.

[0100] Next, holes that will later become plugs CH are formed in the layer above the laminate LM (step S141). The holes are elliptical when viewed from the stacking direction of the laminate LM. Furthermore, multiple contact holes that will later become contacts CC are formed in the step region SR (step S142).

[0101] Next, a conductive layer such as a tungsten layer is filled in these holes and contact holes, thereby forming plugs CH connected to the pillars PL and contacts CC connected to the word lines WL and select gate lines SGD and SGS (step S143).

[0102] Next, plugs VY and the like are formed at a level above plugs CH, each connected to plugs CH and contacts CC (step S144). Furthermore, bit lines BL are formed at a level above plugs VY, connected to plugs VY (step S145). Furthermore, upper-layer wiring is formed, for example, at the same level as bit lines BL, connected to contacts CC via plugs (step S146).

[0103] Next, a silicon substrate SB, on which peripheral circuits CBA are formed, is bonded to the topmost surface of the support substrate on which the laminated body LM, pillars PL, plugs CH, VY, bit lines BL, contacts CC, and upper-layer wiring are formed (step S151). The support substrate is then removed (step S152). Furthermore, plugs PG and an electrode film EL are sequentially formed on the side from which the support substrate has been removed (step S153).

[0104] As described above, the semiconductor memory device 1 according to the embodiment is manufactured.

[0105] in addition, Figure 5 The processing order shown is merely an example and can be modified as appropriate. For example, the processing of step S112 and the processing of step S113 can be interchanged, and the processing of step S122 and the processing of steps S123 and S131 can be interchanged. The processing of step S141 and the processing of step S142 can also be swapped.

[0106] (Summary)

[0107] To achieve high integration in semiconductor memory devices such as three-dimensional nonvolatile memories, the density of the pillars forming memory cells is being increased. Consequently, multiple pillars, such as five or more, are sometimes arranged in the region between the plate-like portion and the isolation layer, or between the isolation layers. However, connecting each pillar in the region between the plate-like portion and the isolation layer, or between the isolation layers, to a different bit line can make it difficult to adjust the relative positions of the pillars, plugs, and bit lines.

[0108] Figure 6 1 is a schematic diagram showing an example of the layout of various structures in the storage region MRx of the semiconductor storage device of the comparative example. Figure 6 (a) and (b) are partial enlarged views of the storage area MRx. Figure 6 (a) is a diagram in which the bit line BL is omitted. Figure 6 (b) is a diagram showing the bit line BL.

[0109] like Figure 6 As shown, the semiconductor memory device of the comparative example includes plugs CHx having, for example, a circular shape when viewed in the stacking direction of the stacked body. Meanwhile, in the comparative example, the pillars PL are also arranged in a staggered pattern. More specifically, they are arranged in five rows extending in the X direction within the region between the plate-like portion PT and the isolation layer SHE, or between the isolation layers SHE. Furthermore, in the comparative example, the center points of the pillars PL and the plugs CHx are also substantially aligned, while the X-direction positions of the plugs VY relative to these pillars PL and plugs CHx vary.

[0110] Thus, each pillar PL disposed between the plate portion PT and the isolation layer SHE or between isolation layers SHE can be connected to a different bit line BL. In other words, the plurality of bit lines BL are connected to any pillar PL in each column R1 to R5 in five cycles.

[0111] However, in a given row among the rows R1 to R5, it is difficult to ensure a sufficient connection area between the plug VY whose position in the X direction is determined by the position of the bit line BL and the plug CHx whose position in the X direction is determined by the position of the pillar PL. Figure 6 In the example, the connection area between the plugs CHx and VY on the pillar PL belonging to the column R5 and connected to the bit line BL3 is insufficient in each region between the plate portion PT and the isolation layer SHE and between the isolation layers SHE.

[0112] More specifically, in the pillars PL arranged between the plate-like portion PT and the separation layer SHE and belonging to row R5, the plugs VY are arranged extremely close to the upper side of the drawing, i.e., one side in the X direction, relative to the pillars PL and plugs CHx. This reduces the connection area between the plugs CHx and VY. Furthermore, in the pillars PL arranged between the separation layers SHE and belonging to row R5, the plugs VY are arranged extremely close to the lower side of the drawing, i.e., the other side in the X direction, relative to the pillars PL and plugs CHx. This reduces the connection area between the plugs CHx and VY.

[0113] Such a reduction in the connection area between the plugs CHx and VY is achieved, for example, when the arrangement of the pillars PL between the plate portion PT and the separation layer SHE and between the separation layers SHE is an odd number of rows. In the case where the bit lines BL connected to the pillars PL in the same number of periods as the arrangement of the pillars PL are arranged, the bit line BL in the middle of the bit lines BL, that is, in the middle of the bit lines BL connected to the pillars PL in the same number of periods as the arrangement of the pillars PL, is connected to the pillars PL in the odd number of rows. Figure 6 In the example, this may occur when the bit line BL3 is connected in the middle of the bit lines BL1 to BL5.

[0114] On the other hand, the plurality of plugs CH of the embodiment are, for example, elliptical in shape with a longitudinal direction along the X direction when viewed from the stacking direction of the stacked body LM. Figure 4 As shown in FIG. 5( a ) and the like, in the column PL belonging to row R5 , even when the plug VY is arranged extremely close to one side in the X direction relative to the column PL and the plug CH, a sufficient contact area between the plugs CH and VY is ensured.

[0115] According to the embodiment, the semiconductor memory device 1 includes: a plurality of pillars PL arranged in (2n+1) columns (n ​​is an integer greater than or equal to 1) extending along the X direction; and a plurality of plugs CH disposed at the upper ends of the pillars PL and electrically connected to the channel layers CN of the pillars PL. The plugs CH have a length direction intersecting the Y direction. This allows for more reliable connection of the high-density pillars PL to the bit lines BL. Consequently, the electrical characteristics and reliability of the semiconductor memory device 1 can be improved.

[0116] According to the semiconductor memory device 1 of the embodiment, the plurality of plugs CH have a length direction along the X direction. This allows the densely packed pillars PL to be more reliably connected to the bit lines BL.

[0117] In the semiconductor memory device 1 according to the embodiment, the plurality of plugs VY have a length along the Y direction and are arranged at positions overlapping with the bit lines BL to be connected, in the stacking direction of the stacked body LM. As described above, by having the plurality of plugs CH have a length along the X direction, sufficient contact area can be ensured with the plugs VY arranged corresponding to the bit lines BL, thereby achieving more reliable connection.

[0118] According to the semiconductor memory device 1 of the embodiment, the plurality of plugs CH have an outer shape smaller than that of the plurality of pillars PL, as viewed in the stacking direction of the stacked body LM, and are arranged at positions overlapping with the pillars PL to be connected, in the stacking direction of the stacked body LM. As described above, since the plurality of plugs CH have a length along the X-direction, as described above, the plugs CH arranged corresponding to the pillars PL and the plugs VY arranged corresponding to the bit lines BL can be connected more reliably while ensuring sufficient contact area.

[0119] According to the semiconductor memory device 1 of the embodiment, a plurality of pillars PL arranged in (2n+1) columns are disposed in the region between the plate-like portion PT and the isolation layer SHE adjacent to each other in the Y direction, or in the region between the isolation layers SHE. As described above, even when the plurality of pillars PL are arranged in an odd number of columns in the region between the plate-like portion PT and the isolation layer SHE, or in the region between the isolation layers SHE, the pillars PL can be more reliably connected to the bit lines BL.

[0120] According to the semiconductor memory device 1 of the embodiment, pillars PL belonging to the same arrangement among the plurality of pillars PL are connected to every (2n+1) bit lines BL among the plurality of bit lines BL arranged in parallel in the X direction. Thus, by configuring the pillars PL belonging to the same arrangement to be connected to the same number of bit lines BL as the number of bit lines BL in the arrangement of the pillars PL, it is possible to connect each pillar PL arranged in the region between the plate-like portion PT and the isolation layer SHE, or in the region between isolation layers SHE, to a different bit line BL.

[0121] Furthermore, in the above embodiment, the pillars PL are arranged in five rows extending in the X direction in the region between the plate-like portion PT and the separation layer SHE, and between the separation layers SHE. However, the arrangement of the pillars PL may be three rows, or even seven or more rows, as long as the number of rows is an odd number. As described above, by applying the configuration of the above embodiment to the pillars PL arranged in an odd number of rows, a sufficient connection area between the plugs CH and VY can be ensured in any bit line BL connected to the pillars PL with the same number of periods as the arrangement of the pillars PL.

[0122] In the above embodiment, the source lines SL are formed on the support substrate before the laminated body LM is formed. However, the source lines may be formed after lamination to the semiconductor substrate SB and removal of the support substrate.

[0123] In the above embodiment, the laminate LM has a two-tier structure. However, the number of tiers in the laminate may be one, or three or more.

[0124] In the above embodiment, the stepped region SR is arranged at the end of the laminate LM in the X direction. However, the central portion of the laminate may be hollowed out in a stepped manner to arrange the stepped region in the central portion of the laminate when viewed in the lamination direction.

[0125] (Variation)

[0126] Next, use Figure 7 A semiconductor memory device according to a modification of the embodiment will be described. In the semiconductor memory device according to the modification, the longitudinal direction of the plug CHa is different from that of the plug CH in the above-described embodiment.

[0127] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals and their description may be omitted.

[0128] Figure 7 1 is a schematic diagram showing an example of the layout of various configurations in the memory region MRa of a semiconductor memory device according to a modification of the embodiment.

[0129] In more detail, Figure 7 (a) and (b) are partial enlarged views of the storage area MRa. Figure 7 (a) is a diagram in which the bit line BL is omitted. Figure 7 (b) is a diagram showing the bit line BL. Figure 7 (c) is a schematic plan view showing a portion of the storage region MRa.

[0130] like Figure 7 As shown in (c), the layout of the pillars PL and the multiple bit lines BL above the pillars PL in the memory region MRa of the modified example is the same as that of the above-described embodiment. Specifically, in the regions between the plate-like portion PT and the isolation layer SHE, and between the isolation layers SHE, the multiple pillars PL are arranged in an odd number of columns, such as five, extending in the X direction, forming a staggered arrangement overall. Furthermore, above these pillars PL, multiple bit lines BL are arranged, separated from each other in the X direction and extending in the Y direction.

[0131] like Figure 7 As shown in (a) and (b) of FIG. 1 , in the semiconductor memory device of the modified example, the plurality of plugs CHa have, for example, an elliptical shape having a longitudinal direction intersecting both the X and Y directions. The longitudinal directions of the plurality of plugs CHa are preferably oriented at an angle of 30° to 60° relative to the plurality of bit lines BL extending along the Y direction.

[0132] Furthermore, the plurality of plugs CHa are not limited to being elliptical, and may have other shapes such as an oval or a rectangular shape with rounded corners.

[0133] In this manner, even in a semiconductor memory device with a modified example in which the plurality of plugs CHa have length directions oblique to both the X and Y directions, the pillars PL arranged between adjacent plate-shaped portions PT and isolation layers SHE in the Y direction, and between adjacent isolation layers SHE in the Y direction, can be connected to different bit lines BL. In this case, the plurality of bit lines BL are connected to any one pillar PL in each of the columns R1 to R5 in a five-cycle arrangement.

[0134] In the semiconductor memory device of this modification, the angle formed between the longitudinal directions of the plurality of plugs CHa and the plurality of bit lines BL is greater than or equal to 30° and less than or equal to 60°. This allows for a longer distance between adjacent plugs CHa in the X direction, facilitating exposure and etching processes during patterning of the plurality of plugs CHa. Furthermore, the increased distance between adjacent plugs CHa in the X direction reduces delays in the transmission speed of various signals passing through the plugs CHa.

[0135] The semiconductor memory device of the modification example exhibits the same effects as those of the semiconductor memory device 1 of the above-described embodiment except for the above-described features.

[0136] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are included within the scope of the invention described in the claims and their equivalents.

[0137] Description of Reference Numerals

[0138] 1…semiconductor memory device, BL…bit line, CH, CHa, VY…plug, CN…channel layer, LM…laminate, MC…memory cell, MR, MRa…storage region, PL…pillar, PT…plate portion, SR…step region, SGD, SGS…select gate line, SHE…isolation layer, STD, STS…select gate, WL…word line.

Claims

1. A semiconductor memory device, characterized in that: have: A laminated body is formed by laminating multiple conductive layers separately from each other; a plurality of pillars each having a semiconductor layer extending in the laminate in a first direction that is a lamination direction of the laminate, and arranged in (2n+1) columns in a second direction intersecting the first direction, where n is an integer greater than or equal to 1; a plurality of first plugs, respectively disposed at upper ends of the plurality of pillars and electrically connected to the semiconductor layer; and a plurality of bit lines extending along the second direction above the plurality of pillars and electrically connected to corresponding first plugs among the plurality of first plugs, The plurality of first plugs have a length direction in a direction intersecting the second direction when viewed from the first direction.

2. The semiconductor memory device according to claim 1, wherein An angle formed between the longitudinal directions of the plurality of first plugs and the plurality of bit lines is greater than or equal to 30° and less than or equal to 60°.

3. The semiconductor memory device according to claim 1, wherein The plurality of first plugs are elliptical when viewed from the first direction.

4. The semiconductor memory device according to claim 1, wherein A plurality of second plugs are further provided. The plurality of second plugs are arranged on upper ends of the plurality of first plugs and connect corresponding first plugs and bit lines among the plurality of first plugs and the plurality of bit lines.

5. The semiconductor memory device according to claim 4, wherein The plurality of second plugs have a length direction in the second direction and are arranged at positions overlapping with bit lines to be connected among the plurality of bit lines in the first direction.

6. The semiconductor memory device according to claim 5, wherein The plurality of first plugs have an outer shape smaller than that of the plurality of posts when viewed from the first direction, and are arranged at positions overlapping with posts to be connected among the plurality of posts in the first direction.

7. The semiconductor memory device according to claim 1, wherein Also features: a first plate-shaped portion extending within the laminate in the first direction and a third direction intersecting the first direction and the second direction; and The second plate-shaped portion extends within the laminate along the first direction and the third direction at a position separated from the first plate-shaped portion in the second direction. The plurality of pillars are arranged in a region between the first plate-shaped portion and the second plate-shaped portion.

8. The semiconductor memory device according to claim 1, wherein Also features: a first plate-shaped portion extending within the laminate in the first direction and a third direction intersecting the first direction and the second direction; a second plate-shaped portion extending within the laminate along the first direction and the third direction at a position separated from the first plate-shaped portion in the second direction; as well as a plurality of separation layers, penetrating at least the uppermost conductive layer of the plurality of conductive layers, extending along the third direction at positions separated from each other in the second direction in a region of the laminate between the first plate-shaped portion and the second plate-shaped portion; The plurality of pillars are arranged in a region between a separation layer adjacent to the first plate-shaped portion in the second direction among the plurality of separation layers and the first plate-shaped portion, or in a region between two separation layers adjacent to each other in the second direction among the plurality of separation layers.

9. The semiconductor memory device according to claim 8, wherein Among the plurality of pillars, pillars belonging to an arrangement adjacent to the plurality of separation layers in the second direction partially overlap with the adjacent separation layers when viewed from the first direction.

10. The semiconductor memory device according to claim 8, wherein The plurality of columns are arranged in 5 rows.

11. The semiconductor memory device according to claim 8, wherein The plurality of bit lines are arranged to be separated from each other in the third direction, Pillars belonging to the same arrangement among the plurality of pillars are connected to every (2n+1) bit lines among the plurality of bit lines arranged in parallel in the third direction.

12. The semiconductor memory device according to claim 11, wherein (2n+1) bit lines arranged in parallel along the third direction among the plurality of bit lines are respectively connected to pillars belonging to different arrangements among the plurality of pillars.

13. The semiconductor memory device according to claim 11, wherein The columns belonging to adjacent rows among the plurality of columns are arranged so that their center points do not overlap in the second direction when viewed from the first direction.

14. The semiconductor memory device according to claim 13, wherein When viewed from the first direction, the plurality of pillars are arranged in a staggered pattern.

15. A semiconductor memory device, characterized in that: have: A laminated body is formed by laminating multiple conductive layers separately from each other; A plurality of pillars each having a semiconductor layer extending in the laminate body in a first direction, i.e., a lamination direction of the laminate body; a plurality of first plugs, respectively disposed at upper ends of the plurality of pillars and electrically connected to the semiconductor layer; a plurality of second plugs, respectively disposed on upper ends of the plurality of first plugs and connected to the plurality of first plugs; a plurality of bit lines extending above the plurality of pillars along a second direction intersecting the first direction and electrically connected to corresponding second plugs in the plurality of second plugs; a first plate-shaped portion extending within the laminate body along the first direction and a third direction intersecting the first direction and the second direction; a second plate-shaped portion extending in the first direction and a third direction within the laminate at a position separated from the first plate-shaped portion along the second direction; and a plurality of separation layers, penetrating at least the uppermost conductive layer of the plurality of conductive layers, extending along the third direction at positions separated from each other in the second direction in a region of the laminate between the first plate-shaped portion and the second plate-shaped portion; The plurality of pillars are arranged in five rows in the second direction in a region between a separation layer adjacent to the first plate-shaped portion in the plurality of separation layers and the first plate-shaped portion, or in a region between two separation layers adjacent to each other in the second direction in the plurality of separation layers. The plurality of first plugs have a length direction in a direction intersecting the second direction when viewed from the first direction.

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