Three-dimensional memory element

Abstract

The invention provides a three-dimensional memory element. The three-dimensional memory element comprises a stacking structure and at least one channel structure, the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers which are alternately stacked. At least one channel structure penetrates through the stack structure, wherein the at least one channel structure includes a top portion and a bottom portion. A ratio of a first width of the bottom portion surrounded by one of the plurality of conductive layers to a second width of the top portion surrounded by another of the plurality of conductive layers is 0.85-0.95. The three-dimensional memory element provided by the invention can be a 3D AND flash memory element or a 3D NOR flash memory element with high capacity and high performance.

Description

Technical Field

[0001] The invention relates to a three-dimensional memory element and a manufacturing method thereof. Background Art

[0002] To meet the demand for high storage density, memory cells in memory devices are becoming smaller and more densely packed. Consequently, the morphology of memory devices has evolved from two-dimensional (2D) memory devices with planar gate structures to three-dimensional (3D) memory devices with channel structures. However, 3D memory devices with channel structures still face many challenges.

[0003] For example, in a three-dimensional memory device, a channel structure with a high aspect ratio has a relatively large size difference between its top and bottom. Consequently, the operating speed of multiple memory cells in the three-dimensional memory device varies depending on their location within the channel structure. Overall, such three-dimensional memory devices have relatively poor reliability. Summary of the Invention

[0004] The present disclosure provides a three-dimensional memory device having relatively high reliability.

[0005] A three-dimensional memory element according to one embodiment of the present disclosure includes a stacked structure and at least one channel structure. The stacked structure includes multiple alternating conductive layers and multiple insulating layers. The at least one channel structure extends through the stacked structure from a top surface to a bottom surface of the stacked structure, wherein the at least one channel structure includes a top portion and a bottom portion. A ratio of a first width of the bottom portion surrounded by one of the multiple conductive layers to a second width of the top portion surrounded by another of the multiple conductive layers is 0.85-0.95.

[0006] Another embodiment of the present disclosure includes a three-dimensional memory element comprising a stacked structure and multiple channel structures. The stacked structure includes multiple layers of word lines and multiple layers of insulating layers stacked alternately. The multiple channel structures extend through the stacked structure, wherein each of the multiple channel structures includes a top portion and a bottom portion. A ratio of a first width of the bottom portion surrounded by one layer of the multi-layer word lines to a second width of the top portion surrounded by another layer of the multi-layer word lines is 0.85-0.95.

[0007] The present disclosure provides a method for manufacturing a three-dimensional memory device, wherein the manufactured three-dimensional memory device can have relatively high reliability.

[0008] A method for manufacturing a three-dimensional memory device according to one embodiment of the present disclosure includes the following steps. First, a stacked structure layer is provided, wherein the stacked structure layer includes multiple alternating sacrificial layers and multiple first insulating layers. Next, a plurality of through-holes are formed, wherein the plurality of through-holes extend through the stacked structure layer. Next, a second insulating layer is formed in each of the plurality of through-holes, wherein the width of the second insulating layer surrounded by the bottommost layer of the plurality of sacrificial layers is smaller than the width of the second insulating layer surrounded by the topmost layer of the plurality of sacrificial layers. Next, a channel structure is formed in each of the plurality of through-holes, wherein each of the plurality of channel structures includes a top portion and a bottom portion. Next, the plurality of sacrificial layers and the second insulating layer adjacent to the plurality of sacrificial layers are removed to form a plurality of gate trenches, wherein the plurality of gate trenches expose a portion of the plurality of channel structures. Next, word lines are formed in each of the plurality of gate trenches to form multiple layers of the word lines. In the three-dimensional memory device manufactured according to one embodiment of the present disclosure, the ratio of the first width of the bottom portion surrounded by one layer of the multi-layer word line to the second width of the top portion surrounded by another layer of the multi-layer word line is 0.85-0.95.

[0009] Based on the foregoing, in a three-dimensional memory device provided by one embodiment of the present disclosure, the ratio of the first width of the bottom portion of the channel structure surrounded by the bottom layer of the multi-layer word line to the second width of the top portion of the channel structure surrounded by the top layer of the multi-layer conductive layer is 0.85-0.95. Based on this, multiple memory cells at different heights can have substantially the same memory cell size, resulting in similar operating speeds during operation, thereby ensuring relatively high reliability of the three-dimensional memory device of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1I FIG. 4 is a flow chart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0011] Figure 2A Drawing basis Figure 1D An enlarged schematic diagram of region R1.

[0012] Figure 2B Drawing basis Figure 1D An enlarged schematic diagram of region R2.

[0013] Figure 3A Drawing basis Figure 1I An enlarged schematic diagram of region R3.

[0014] Figure 3B Drawing basis Figure 1I An enlarged schematic diagram of region R4.

[0015] Figure 4A FIG. 1 is a partial perspective diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0016] Figure 4B FIG. 1 is a partial top view of a three-dimensional memory device according to an embodiment of the present disclosure.

[0017] Figure 4C FIG. 1 is a partial cross-sectional view of a driving circuit layer in a three-dimensional memory device according to an embodiment of the present disclosure.

[0018] Figure 5A FIG. 1 is a partial cross-sectional diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0019] Figure 5B FIG. 1 is a partial cross-sectional schematic diagram of a three-dimensional memory device according to another embodiment of the present disclosure.

[0020] Description of reference numerals:

[0021] 10, 20, 30: Three-dimensional memory elements

[0022] 10B: Memory block

[0023] 100: Stacked structure

[0024] 100a: stacked structure layer

[0025] 100T: Top surface

[0026] 110: First stacking structure

[0027] 110a: first stacked structure layer

[0028] 112a, 112a1, 112a2, 112a3: conductive layer

[0029] 114a, 114a1, 114a2: Insulation layer

[0030] 116, 500, 1121, 1123, CL: conductive layer

[0031] 120: Second stacking structure

[0032] 120a: second stacking structure layer

[0033] 122: First insulation layer

[0034] 122a: First insulating layer

[0035] 122aB, 122B, 124aB, CLB, ILB, WLB: bottom layer

[0036] 122aT, 122T, 124aT, CLT, ILT, WLT: top layer

[0037] 124a: Sacrificial layer

[0038] 130: Second insulation layer

[0039] 130a: Second insulating layer

[0040] 130aW, 130aW B , 130aW T , 200W B1 , 200W B2 , 200W T1 , 200W T2 :width

[0041] 200: Channel structure

[0042] 200B1, 200B2: bottom part

[0043] 200T1, 200T2: Top part

[0044] 210: Charge storage structure

[0045] 212: Tunneling layer

[0046] 214: Charge storage layer

[0047] 216: Barrier layer

[0048] 220: Channel layer

[0049] 230: Insulation column

[0050] 240: Conductive plug

[0051] 300: Separation structure

[0052] 302, 430, 600, IL: insulation layer

[0053] 304: Source line contact window

[0054] 400: driving circuit layer

[0055] 410: Transistor

[0056] 420: Wire

[0057] AR: Array Area

[0058] C1, C2: contact windows

[0059] CV: Via Window

[0060] EC: electrical connector

[0061] GTr: Gate channel

[0062] GSL: Ground Select Line

[0063] LBL: Local Bit Line

[0064] MCB, MCT: storage unit

[0065] PAD1, PAD2: pads

[0066] SB: Base

[0067] SL: Source line

[0068] SLIT: slit

[0069] SR: Step Area

[0070] SSL: Serial Select Line

[0071] STr: horizontal source line channel

[0072] R1, R2, R3, R4: Area

[0073] VC: Through-hole

[0074] WL: word line

[0075] X、 direction

[0076] Z: vertical direction DETAILED DESCRIPTION

[0077] The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description.

[0078] Figures 1A to 1I FIG. 4 is a flow chart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.

[0079] Please refer to Figure 1A , providing a stacked structure layer 100a. In some embodiments, the stacked structure layer 100a is disposed on a substrate SB. The substrate SB may be, for example, a semiconductor substrate. In some embodiments, the material of the substrate SB may include silicon, doped silicon, germanium, silicon germanium, semiconductor compounds, other suitable semiconductor materials, or a combination thereof. For example, the substrate SB may be a silicon substrate, but the present disclosure is not limited thereto. In some embodiments, a plurality of doped regions may be formed in the substrate SB according to design requirements. For example, a plurality of doped regions including a P-type well region (not shown) and an N-type deep well region (not shown) may be formed in the substrate SB, but the present disclosure is not limited thereto. In other embodiments, a buried oxide layer (not shown) may be further formed on the substrate SB.

[0080] In some embodiments, the stacked structure layer 100a is disposed above the substrate SB. The driving circuit layer is, for example, located between the stacked structure layer 100a and the substrate SB. Its structure and function will be described in detail in the following embodiments.

[0081] In this embodiment, the stacked structure layer 100 a includes a first stacked structure layer 110 a and a second stacked structure layer 120 a , and the second stacked structure layer 120 a is disposed on the first stacked structure layer 110 a .

[0082] In some embodiments, the method for forming the first stacked structure layer 110a includes the following steps, but the present disclosure is not limited thereto. First, a chemical vapor deposition process or other suitable process is performed to form a conductive layer 112a on the substrate SB. Next, a chemical vapor deposition process or other suitable process is performed to form an insulating layer 114a on the conductive layer 112a. Thereafter, the above steps are repeated to form a plurality of conductive layers 112a and a plurality of insulating layers 114a alternately stacked in the vertical direction Z on the substrate SB. In the present embodiment, the first stacked structure layer 110a includes a conductive layer 112a1, an insulating layer 114a1, a conductive layer 112a2, an insulating layer 114a2, and a conductive layer 112a3 alternately stacked in the vertical direction Z, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive layer 112a includes polysilicon, and the material of the insulating layer 114a includes silicon oxide.

[0083] In some embodiments, the method for forming the second stacked structure layer 120a includes the following steps, but the present disclosure is not limited thereto. First, a chemical vapor deposition process or other suitable process is performed to form a first insulating layer 122a on the first stacked structure layer 110a. Next, a chemical vapor deposition process or other suitable process is performed to form a sacrificial layer 124a on the first insulating layer 122a. Thereafter, the above steps are repeated to form a plurality of first insulating layers 122a and a plurality of sacrificial layers 124a alternately stacked in the vertical direction Z on the first stacked structure layer 110a. In this embodiment, the plurality of first insulating layers 122a include a topmost layer 122aT farthest from the first stacked structure layer 110a and a bottommost layer 122aB closest to the first stacked structure layer 110a, and the plurality of sacrificial layers 124a include a topmost layer 124aT farthest from the first stacked structure layer 110a and a bottommost layer 124aB closest to the first stacked structure layer 110a. In some embodiments, the first insulating layer 122a is made of silicon oxide, and the sacrificial layer 124a is made of silicon nitride. In this embodiment, the topmost layer of the second stacked structure layer 120a is the topmost layer 122aT of the multiple first insulating layers 122a, but the disclosure is not limited thereto.

[0084] Please refer to Figure 1B , forming a plurality of through-holes VC. The plurality of through-holes VC, for example, penetrate the stacked structure layer 100a in the vertical direction Z. In detail, in the present embodiment, each of the plurality of through-holes VC penetrates from the top surface of the second stacked structure layer 120a to the top surface of the first stacked structure layer 110a in the vertical direction Z. In some embodiments, the plurality of through-holes VC may extend into a portion of the substrate SB. In some embodiments, a portion of the stacked structure layer 100a may be removed by performing a patterning process to form a plurality of through-holes VC in the stacked structure layer 100a. The above-mentioned patterning process may include a photolithography process and an etching process, but the present disclosure is not limited thereto. In some embodiments, a portion of the substrate SB is removed.

[0085] Please refer to Figure 1C , each forming a second insulating layer 130a in a plurality of through-holes VC. In some embodiments, the method for forming the second insulating layer 130a includes the following steps, but the present disclosure is not limited thereto. First, an insulating layer (not shown) can be conformally formed on the second stacked structure layer 120a by performing a suitable deposition process. The above-mentioned insulating layer is formed in a plurality of through-holes VC. Then, an etching process can be performed to remove the insulating layer located on the top surface of the second stacked structure layer 120a. The above-mentioned residual insulating layer is conformally arranged in a plurality of through-holes VC to form the second insulating layer 130a. In some embodiments, the material of the second insulating layer 130a includes silicon oxide.

[0086] In this embodiment, the width 130aW of the second insulating layer 130a decreases as it approaches the bottom of the through hole VC, so that the channel structure 200 to be formed subsequently may have a similar width in the vertical direction Z, which will be described in detail in the following embodiments.

[0087] Please refer to Figure 1D , each forming a channel structure 200 in a plurality of through-holes VC. Channel structure 200 includes a charge storage structure 210, a channel layer 220, an insulating pillar 230, and a conductive plug 240. Insulating pillar 230 extends downward and may extend along a vertical direction Z. Conductive plug 240 is disposed on insulating pillar 230. Channel layer 220 surrounds insulating pillar 230 and conductive plug 240, and charge storage structure 210 surrounds channel layer 220. In some embodiments, the method of forming channel structure 200 includes the following steps, but the present disclosure is not limited thereto.

[0088] Step (1): Forming a charge storage structure 210

[0089] First, a tunneling material layer (not shown), a charge storage material layer (not shown), and a blocking material layer (not shown) can be sequentially and conformally formed on the second stacked structural layer 120a by performing a suitable deposition process. The tunneling material layer, charge storage material layer, and blocking material layer are formed in a plurality of through-holes (VC). Next, an etching process can be performed to remove the tunneling material layer, charge storage material layer, and blocking material layer located on the top surface of the second stacked structural layer 120a. The remaining tunneling material layer, charge storage material layer, and blocking material layer are conformally disposed in the plurality of through-holes (VC). Thus, a charge storage structure 210 is formed, each comprising a tunneling layer 212, a charge storage layer 214, and a blocking layer 216. In some embodiments, the charge storage structure 210 comprises an oxide-nitride-oxide (ONO) composite layer. Specifically, the material of the tunneling layer 212 may include silicon oxide, the material of the charge storage layer 214 may include silicon nitride, and the material of the blocking layer 216 may include silicon oxide, but the present disclosure is not limited thereto.

[0090] Step (2): Forming the channel layer 220

[0091] First, a channel material layer (not shown) can be conformally formed on the second stacked structure layer 120a by performing a suitable deposition process and a tempering process. The above-mentioned channel material layer is formed in each of the multiple through-holes VC. Next, an etching process can be performed to remove the channel material layer located on the top surface of the second stacked structure layer 120a. The above-mentioned residual channel material layer is conformally disposed in the multiple through-holes VC to form the channel layer 220. In some embodiments, the material of the channel layer 220 may include a doped or undoped semiconductor material. For example, the material of the channel layer 220 may include polysilicon, but the present disclosure is not limited thereto.

[0092] Step (3): Forming the insulating column 230

[0093] First, an insulating layer (not shown) can be formed on the second stacked structural layer 120a by performing a suitable deposition process. The insulating layer is then filled into the plurality of through-holes VC. Next, an etch-back process and / or a planarization process can be performed to remove the insulating layer on the top surface of the second stacked structural layer 120a and the portion of the insulating layer within each through-hole VC, thereby exposing a portion of the channel layer 220 on the sidewalls of the through-hole VC. Insulating pillars 230 are formed in the plurality of through-holes VC. In some embodiments, the material of the insulating pillars 230 includes silicon oxide.

[0094] Step (4): Forming the conductive plug 240

[0095] First, a suitable deposition process is performed to form a conductive plug material layer (not shown) on the second stacked structural layer 120a. This conductive plug material layer is then filled into the plurality of through-vias VC. Next, a planarization process is performed to remove the conductive plug material layer located on the top surface of the second stacked structural layer 120a. Thus, a conductive plug 240 is formed in each of the plurality of through-vias VC. The conductive plug 240 is electrically connected to the channel layer 220. In some embodiments, the conductive plug 240 is made of polysilicon, metal, or a combination thereof, but the present disclosure is not limited thereto.

[0096] After forming the channel structure 200, the second insulating layer 130a is interposed between the channel structure 200 and the stacked structure 100. As previously mentioned, the width 130aW of the second insulating layer 130a decreases as it approaches the bottom of the through hole VC.

[0097] In detail, Figure 2A and Figure 2B In the embodiment of the present invention, the width 130aW of the second insulating layer 130a surrounded by the bottom layer 124aB of the multi-layer sacrificial layer 124a is B smaller than the width 130aW of the second insulating layer 130a surrounded by the topmost layer 124aT of the multi-layer sacrificial layer 124a T .

[0098] Please refer to Figure 2A as well as Figure 2B , region R1 and region R2 respectively show the topmost layer 124aT and the bottommost layer 124aB in the multi-layer sacrificial layer 124a and the topmost layer 122aT and the bottommost layer 122aB in the multi-layer first insulating layer 122a, and the second insulating layer 130a surrounded by the multi-layer sacrificial layer 124a and the multi-layer first insulating layer 122a may have different widths in the vertical direction Z. In detail, the second insulating layer 130a may have different widths 130aW measured in the horizontal direction (including direction X and direction Y). The width 130aW of the second insulating layer 130a becomes smaller as it approaches the bottom of the through hole VC. In some embodiments, the characteristic of the second insulating layer 130a having different widths 130aW can be achieved by controlling the flow rate of gas in the deposition process, but the present disclosure is not limited thereto. In this embodiment, the width 130aW of the second insulating layer 130a surrounded by the bottommost layer 124aB in the multi-layer sacrificial layer 124a is B The width 130aW of the second insulating layer 130a surrounded by the topmost layer 124aT of the multi-layer sacrificial layer 124a is T The ratio is 0.10-0.90.

[0099] Please refer to Figure 1E, forming a plurality of slits SLITs in the stacked structure layer 100a. The plurality of slits SLITs, for example, extend downward in the stacked structure layer 100a (which may be in the vertical direction Z) and in a horizontal direction (in this embodiment, in the direction X). In some embodiments, a patterning process may be performed to remove portions of the stacked structure layer 100a to form the plurality of slits SLITs in the stacked structure layer 100a. The patterning process may include a photolithography process and an etching process, but the present disclosure is not limited thereto. In this embodiment, an etching process is used to sequentially remove portions of the second stacked structure layer 120a and the first stacked structure layer 110a, and the insulating layer 114a2 in the first stacked structure layer 110a may serve as an etch stop layer. Specifically, the etching process may stop after removing portions of the insulating layer 114a2, such that portions of the conductive layer 112a2 are exposed at the bottom of the plurality of slits SLITs. In addition, after portions of the multiple first insulating layers 122a in the second stacked structure layer 120a are removed, a multilayer insulating layer 122 is formed. The multi-layer insulation layer 122 includes a topmost layer 122T and a bottommost layer 122B.

[0100] Please refer to Figure 1F The insulating layers 114a1 and 114a2 in the first stacked structure layer 110a are removed from the bottoms adjacent to the multiple slits SLIT. Furthermore, a portion of the second insulating layer 130a and a portion of the conductive layer 112a surrounded by the insulating layers 114a1 and 114a2 are also removed. Furthermore, a portion of the charge storage structure 210 adjacent to a portion of the second insulating layer 130a is also removed. Through the above-described process, a horizontal source line channel STr is formed. The horizontal source line channel STr exposes a portion of the channel layer 220. Specifically, after forming the multiple slits SLIT, a protective layer (not shown) may be formed on the sidewalls of each slit SLIT. The protective layer covers the sidewalls of the multiple first insulating layers 122a and the multiple sacrificial layers 124a in the second stacked structure layer 120a exposed by the multiple slits SLIT, and covers the conductive layer 112a3 in the first stacked structure layer 120a exposed by the multiple slits SLIT. Then, an etching process is performed to remove the insulating layer 114a (insulating layers 114a1 and 114a2) and the conductive layer 112a2 in the first stacked structure layer 110a not covered by the protection layer and a portion of the charge storage structure 210 in the channel structure 200 to form a horizontal source line channel STr.

[0101] It is worth noting that the above-mentioned etching process may be, for example, a multi-stage etching process including the following steps, but the present disclosure is not limited thereto.

[0102] First, a first wet etching process using hydrofluoric acid is performed near the bottoms of the plurality of slits SLIT to simultaneously remove a portion of the second insulating layer 130a surrounded by the insulating layer 114a2, the insulating layer 114a2 in the first stacked structure layer 110a, and the blocking layer 216 adjacent to a portion of the second insulating layer 130a. As a result, the conductive layer 112a2 in the first stacked structure layer 110a and a portion of the charge storage layer 214 in the channel structure 200 are exposed.

[0103] Next, a second wet etching process is performed using phosphoric acid near the bottoms of the plurality of slits SLIT to simultaneously remove the conductive layer 112a2 in the first stacked structure layer 110a and a portion of the charge storage layer 214 in the channel structure 200. As a result, the insulating layer 114a1 in the first stacked structure layer 110a and a portion of the tunneling layer 212 in the channel structure 200 are exposed.

[0104] Thereafter, a third wet etching process using hydrofluoric acid is performed near the bottoms of the plurality of slits SLIT to simultaneously remove another portion of the second insulating layer 130a surrounded by the insulating layer 114a1, the barrier layer 216 adjacent to the other portion of the second insulating layer 130a, the insulating layer 114a1 in the first stacked structure layer 110a, and a portion of the tunneling layer 212 in the channel structure 200. Consequently, the outer surface of a portion of the channel layer 220 in the channel structure 200 is exposed, and the formed horizontal source line channels STr each expose the top surface of the conductive layer 1121 and the bottom surface of the conductive layer 1123.

[0105] Please refer to Figure 1G, forming a source line SL in the horizontal source line trench STr. In some embodiments, the method for forming the source line SL includes the following steps, but the present disclosure is not limited thereto. First, a conductive layer (not shown) can be formed on the second stacked structure layer 120a by performing a suitable deposition process. The above-mentioned conductive layer is filled in the multiple slits SLIT and the horizontal source line trench STr. Then, a back etching process can be performed to remove the conductive layer located on the top surface of the second stacked structure layer 120a and in the multiple slits SLIT. Therefore, a conductive layer 116 is formed in the horizontal source line trench STr. The above-mentioned back etching process can remove a portion of the conductive layer located in the horizontal source line trench STr and exposed by the multiple slits SLIT, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive layer 116 includes polysilicon, metal or a combination thereof, but the present disclosure is not limited thereto. It is worth noting that after the etch-back process, the conductive layer 116 in the horizontal source line trench STr and the conductive layers 1121 and 1123 in the first stacked structure layer 110a can be formed into the source line SL. In other words, the first stacked structure 110 is formed by stacking the conductive layers 1121, 116, and 1123 in this order.

[0106] Please refer to Figure 1H , the multi-layer sacrificial layer 124a in the second stacked structure layer 120a and the second insulating layer 130a adjacent thereto are removed to form a plurality of gate trenches GTr. In addition, a second insulating layer 130 is also formed. Each of the plurality of gate trenches GTr exposes a portion of the charge storage structure 210. In detail, an etching process can be performed, for example, to remove the multi-layer sacrificial layer 124a exposed by the plurality of slits SLIT. It is worth noting that the etching solution used in this etching process has a high etching selectivity for the multi-layer sacrificial layer 124a as well as for the second insulating layer 130a. Therefore, the second insulating layer 130a adjacent to the multi-layer sacrificial layer 124a is also removed in this etching process to form a plurality of gate trenches GTr. In this embodiment, the above-mentioned etching process is a wet etching process using phosphoric acid as an etching solution, but the present disclosure is not limited thereto.

[0107] In this embodiment, the etching selectivity of the second insulating layer 130 a to the blocking layer 216 of the charge storage structure 210 in the etching process is 2-10. Therefore, most of the blocking layer 216 is not removed in the etching process.

[0108] Please refer to Figure 1I, forming a conductive layer CL in a plurality of gate trenches GTr to form a second stacked structure 120. In some embodiments, the method for forming the conductive layer CL includes the following steps, but the present disclosure is not limited thereto. First, a conductive layer can be formed by performing a suitable deposition process. The above-mentioned conductive layer is filled in a plurality of slits SLIT and a plurality of gate trenches GTr. Then, a back etching process can be performed to remove the conductive layer located in the plurality of slits SLIT to form a multilayer conductive layer CL in the plurality of gate trenches GTr. In addition, a second stacked structure 120 is also formed. In other words, a second stacked structure 120 including a plurality of alternating stacked conductive layers CL and a first insulating layer 122 is formed. In some embodiments, the material of the conductive layer CL includes polysilicon, metal or a combination thereof, but the present disclosure is not limited thereto.

[0109] In this embodiment, the multi-layer conductive layer CL may include multi-layer word lines WL, string selection lines SSL, and ground selection lines GSL. The multi-layer word lines WL are stacked in the vertical direction Z and are located between the string selection lines SSL and the ground selection lines GSL. It is worth noting that although Figure 1I The multi-layer conductive layer CL is shown to include a series selection line SSL and a ground selection line GSL, but the present disclosure is not limited thereto. Based on this, after forming the multi-layer conductive layer CL, the memory cell can be defined by a channel structure 200 surrounded by a layer of word lines WL. For example, Figure 1I Memory cells MCT and MCB are shown as being each defined by a channel structure 200 surrounded by a topmost layer WLT and a bottommost layer WLB of word lines WL, but the present disclosure is not limited thereto. Furthermore, a string select transistor (not shown) and a ground select transistor (not shown) are each defined by a string select line SSL and a ground select line GSL surrounding a channel structure 200.

[0110] Because the width 130aW of the second insulating layer 130a decreases as it approaches the bottom of the via VC, the remaining space of the via VC can have a shape similar to a rectangular parallelepiped. In other words, the channel structure 200 can have a similar width in the vertical direction Z. Therefore, in this embodiment, there can be a small width difference between the bottom portion 200B and the top portion 200T of the channel structure 200. In other words, despite the relatively high aspect ratio of the via VC, multiple memory cells at different heights can have substantially the same memory cell size.

[0111] Please refer to Figure 3A as well as Figure 3BRegions R3 and R4 respectively represent the topmost layer CLT and the bottommost layer CLB of the multi-layer conductive layer CL and the topmost layer 122T and the bottommost layer 122B of the multi-layer insulating layer 122, and the channel structure 200 surrounded by the multi-layer conductive layer CL may have similar widths in the vertical direction Z. Specifically, in this embodiment, the width 200W of the bottom portion 200B1 of the channel structure 200 surrounded by the bottommost layer CLB of the multi-layer conductive layer CL is B1 The second width 200W of the top portion 200T1 of the channel structure 200 surrounded by the topmost layer CLT in the multi-layer conductive layer CL T1 The ratio is 0.85-0.95.

[0112] Please continue to refer to Figure 3A as well as Figure 3B Regions R3 and R4 also respectively represent the topmost WLT and the bottommost WLB of the multi-layer word lines WL, and the channel structures 200 surrounded by the multi-layer word lines WL may have similar widths in the vertical direction Z. Specifically, in this embodiment, the width 200W of the bottom portion 200B2 of the channel structure 200 surrounded by the bottommost WLB of the multi-layer word lines WL is B2 The second width 200W of the top portion 200T2 of the channel structure 200 surrounded by the topmost layer WLT of the multi-layer conductive layer WL is T2 The ratio is 0.85-0.95. Based on this, multiple memory cells at different heights can have substantially the same memory cell size, allowing them to have substantially the same operating speed when operated. For example, the memory cells MCT and MCB, which are farthest apart in the vertical direction Z, can have similar write speeds and / or erase speeds when operated.

[0113] Please continue to refer to Figure 1I, forming a plurality of separation structures 300 in the plurality of slits SLIT. In some embodiments, the method for forming the separation structures 300 includes the following steps, but the present disclosure is not limited thereto. First, an insulating layer 302 can be formed on the sidewalls of the plurality of slits SLIT by performing a suitable deposition process. Then, a source line contact window 304 can be filled into the plurality of slits SLIT by performing a suitable deposition process to form the separation structures 300. The insulating layer 302 is, for example, used to electrically isolate the source line contact window 304 from the conductive layer CL. The source line contact window 304 is, for example, electrically connected to the source line SL. In some embodiments, the material of the insulating layer 302 includes silicon oxide, and the material of the source line contact window 304 includes polysilicon, metal, or a combination thereof, but the present disclosure is not limited thereto. In this embodiment, the plurality of separation structures 300 each extend along a horizontal direction (which may be direction X). The two adjacent separation structures 300 described above can be used to define a memory block 10B, but the present disclosure is not limited thereto.

[0114] At this point, the manufacturing of the three-dimensional memory device 10 is completed. Although the manufacturing method of the three-dimensional memory device 10 of this embodiment is described using the above method as an example, the manufacturing method of the three-dimensional memory device disclosed in the present invention is not limited thereto.

[0115] Figure 4A FIG. 1 is a partial perspective diagram of a three-dimensional memory element according to an embodiment of the present disclosure. Figure 4B A partial top view of a three-dimensional memory device according to an embodiment of the present disclosure is shown, and Figure 4C FIG. 1 is a partial cross-sectional view of a driving circuit layer in a three-dimensional memory device according to an embodiment of the present disclosure. Figures 4A to 4C The embodiments of the present invention may respectively use the component numbers and part of the content of the aforementioned embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

[0116] Please also refer to Figure 1I 、 Figure 4A as well as Figure 4B The three-dimensional memory device 10 provided in the present disclosure may be a three-dimensional NAND flash memory with high capacity and high performance, but the present disclosure is not limited thereto. The three-dimensional memory device 10 of this embodiment includes a plurality of memory blocks 10B. It is worth noting that Figure 4A and Figure 4B The three-dimensional memory device 10 is shown as including three memory blocks 10B as an example, but the disclosure is not limited thereto.

[0117] In some embodiments, one of the plurality of memory blocks 10B may include a stack structure 100 and at least one channel structure 200. The plurality of memory blocks 10B may be defined by a plurality of partition structures 300, but the disclosure is not limited thereto.

[0118] The plurality of partition structures 300 are, for example, disposed on the substrate SB. In some embodiments, the plurality of partition structures 300 may extend in the direction X and may be used to define a plurality of memory blocks 10B of the three-dimensional memory device 10. For example, Figure 4A and Figure 4B As shown, two adjacent partition structures 300 can be used to define a memory block 10B, but the disclosure is not limited thereto.

[0119] like Figure 1I As shown, the stack structure 100 in the three-dimensional memory device 10 of this embodiment may include a first stack structure 110 and a second stack structure layer 120 , and the second stack structure 120 is disposed on the first stack structure 110 .

[0120] The first stacked structure 110 includes, for example, a conductive layer 1121, a conductive layer 116, and a conductive layer 1123 stacked in a vertical direction Z. In this embodiment, the conductive layers 1121, 116, and 1123 may collectively serve as the source line SL of the three-dimensional memory device 10. The materials included in the conductive layers 1121, 116, and 1123 may refer to the aforementioned embodiments and are not further described herein.

[0121] The second stacked structure 120, for example, includes multiple conductive layers CL and multiple insulating layers IL alternately stacked in a vertical direction Z. The multiple conductive layers CL may each extend in a plane defined by a direction X and a direction Y, and the directions X and Y are, for example, orthogonal to the vertical direction Z. In this embodiment, the multiple conductive layers CL may each have a length that decreases in the direction X along the vertical direction Z of the substrate SB, such that the multiple conductive layers CL have a stepped structure. The materials and structures of the multiple conductive layers CL can refer to the previous embodiments and are not further described here.

[0122] One of the multi-layer insulation layers IL, for example, includes a first insulation layer 122 and a second insulation layer 130, with the second insulation layer 130 positioned between the first insulation layer 122 and the at least one channel structure 200. The first insulation layer 122 and the second insulation layer 130, for example, extend horizontally in a direction away from the at least one channel structure 200 and cover a portion of a lower conductive layer in the multi-layer conductive layer CL. For example, the first insulation layer 122 and the second insulation layer 130 extend in a horizontal direction (including directions X and Y) and cover a portion of a lower word line in the multi-layer word line WL. The materials comprising each of the multi-layer insulation layers IL can be referred to in the previous embodiment and will not be further described here. In this embodiment, the first insulation layer 122 and the second insulation layer 130 comprise the same material, but the present disclosure is not limited thereto.

[0123] In this embodiment, the width 130WT of the second insulating layer 130 adjacent to the top portion 200T of the at least one channel structure 200 is greater than the width 130WB of the second insulating layer 130 adjacent to the bottom portion 200B of the at least one channel structure 200. In other words, the width 130W of the second insulating layer 130 decreases as it approaches the bottom of the channel structure 200.

[0124] For details, please refer to Figure 3A as well as Figure 3B Regions R3 and R4 respectively represent the topmost ILT and the bottommost ILB of the multi-layer insulation layer IL, and the width 130WT of the second insulation layer 130 in the topmost ILT is greater than the width 130WB of the second insulation layer 130 in the bottommost ILB. In this embodiment, the ratio of the width 130WB of the second insulation layer 130 in the bottommost ILB to the width 130WT of the second insulation layer 130 in the topmost ILT is 0.10-0.90.

[0125] At least one channel structure 200 extends downward (which may be in the vertical direction Z) and penetrates the stacked structure 100. That is, the at least one channel structure 200 penetrates from the top surface of the stacked structure 100 to the bottom surface of the stacked structure 100. The at least one channel structure 200 may include, for example, a cell string, and each memory cell in a cell string is electrically connected to a corresponding word line WL, but the present disclosure is not limited thereto. In this embodiment, each of the at least one channel structure 200 may include a charge storage structure 210, a channel layer 220, an insulating pillar 230, and a conductive plug 240, but the present disclosure is not limited thereto.

[0126] The charge storage structure 210 is disposed, for example, around the channel layer 220 and may be an outer structure of the channel structure 200. In some embodiments, the charge storage structure 210 may include a composite layer. For example, the charge storage structure 210 may include three dielectric layers stacked sequentially on the side surfaces of the channel layer 220. For example, the charge storage structure 210 may include an oxide-nitride-oxide (ONO) composite layer, but the present disclosure is not limited thereto. In other embodiments, the charge storage structure 210 may include an oxide-nitride-oxide-nitride-oxide (ONONO) composite layer or a composite layer including other structures. In this embodiment, the charge storage structure 210 includes a tunneling layer 212, a charge storage layer 214, and a blocking layer 216. The tunneling layer 212, the charge storage layer 214, and the blocking layer 216 surround the channel layer 220 in this order. The materials comprising the tunneling layer 212, the charge storage layer 214, and the blocking layer 216 can be referred to in the previous embodiments and will not be further described here.

[0127] Based on this, a plurality of memory cells can be defined by a channel structure 200 surrounded by a layer of word lines WL. For example, Figure 1I Memory cells MCT and MCB are each defined by a topmost word line WLT and a bottommost word line WLB surrounding a channel structure 200. In some embodiments, the memory cells can be operated using different methods to perform 1-bit or 2-bit operations. For example, when a voltage is applied to the channel structure 200, electrons can be transferred along the channel layer 220 and stored in the charge storage structure 210. Single-bit cell (SLC; 1-bit) or multi-bit cell (MLC; 2-bit or greater) operations can be performed on the memory cells, but the present disclosure is not limited thereto.

[0128] The channel layer 220 has, for example, a ring structure in the vertical direction Z. The materials included in the channel layer 220 can refer to the aforementioned embodiments and are not described in detail herein.

[0129] The insulating pillar 230 is, for example, surrounded by the channel layer 220 , ie, the insulating pillar 230 is, for example, disposed inside the channel layer 220 and, for example, extends in the vertical direction Z. The material of the insulating pillar 230 can refer to the above embodiment and is not described again here.

[0130] The conductive plug 240 is, for example, disposed on the insulating pillar 230 and is also surrounded by the channel layer 220. In some embodiments, the conductive plug 240 is electrically connected to the channel layer 220. The material of the conductive plug 240 can be referred to in the previous embodiment and will not be repeated here.

[0131] In some embodiments, the channel structure 200 surrounded by the multi-layer conductive layer CL may have similar widths in the vertical direction Z. Specifically, the channel structure 200 includes a top portion 200T1 and a bottom portion 200B1. The top portion 200T1 is the portion surrounded by the top layer of the multi-layer conductive layer CL (the string select line SSL in this embodiment), and the bottom portion 200B1 is the portion surrounded by the bottom layer of the conductive layer CL (the ground select line GSL in this embodiment). In some embodiments, the width 200W of the bottom portion 200B1 of the channel structure 200 surrounded by the ground select line GSL is B1 The width 200W of the top portion 200T1 of the channel structure 200 surrounded by the string selection line SSL T1 The ratio is 0.85-0.95.

[0132] Furthermore, in the present embodiment, the channel structures 200 surrounded by the multi-layer word lines WL may have similar widths in the vertical direction Z. In detail, the channel structure 200 further includes a top portion 200T2 and a bottom portion 200B2. The top portion 200T2 is a portion surrounded by at least one top layer of the multi-layer word lines WL, and the bottom portion 200B2 is a portion surrounded by at least one bottom layer of the multi-layer word lines WL. In the present embodiment, the top portion 200T2 is a portion surrounded by the topmost layer WLT of the multi-layer word lines WL, and the bottom portion 200B2 is a portion surrounded by the bottommost layer WLB of the multi-layer word lines WL. In the present embodiment, the width 200W of the bottom portion 200B2 of the channel structure 200 surrounded by the bottommost layer WLB of the multi-layer word lines WL is B2 The width 200W of the top portion 200T2 of the channel structure 200 surrounded by the topmost layer WLT of the multi-layer conductive layer WL is T2 The ratio is 0.85-0.95. Based on this, multiple memory cells at different heights can have substantially the same memory cell size, allowing them to have substantially the same operating speed when operated. For example, the memory cells MCT and MCB, which are farthest apart in the vertical direction Z, can have similar write speeds and / or erase speeds when operated.

[0133] Please refer to Figure 4A as well as Figure 4B The three-dimensional memory device 10 may include an array region AR and a stepped region SR. The aforementioned channel structure 200 is, for example, disposed in the array region AR. The stepped region SR can be used to electrically connect components (e.g., memory cells) located in the array region AR to the driver circuit layer 400. Specifically, in this embodiment, the three-dimensional memory device 10 further includes a driver circuit layer 400, a plurality of contact windows C1, a plurality of contact windows C2, and a plurality of electrical connectors EC.

[0134] The driving circuit layer 400 is, for example, disposed between the stacked structure 100 and the substrate SB. Figure 4C In this embodiment, the driving circuit layer 400 may include a plurality of transistors 410, a plurality of conductive lines 420, and a plurality of insulating layers 430. The plurality of transistors 410 may be, for example, complementary metal oxide semiconductor field effect transistors (CMOS). Therefore, the architecture of the three-dimensional memory element 10 shown in this embodiment may be referred to as a complementary metal oxide semiconductor field effect transistor under array (CMOS under array; CUA) architecture; however, the present disclosure is not limited thereto. In some embodiments, the transistors 410 may be electrically connected to the word lines WL through corresponding conductive lines 420 to control the corresponding word lines WL. In detail, the driving circuit layer 400 may, for example, include a word line decoder composed of a plurality of transistors 410, and the word line decoder may be electrically connected to the corresponding memory cell through the word line WL. In some embodiments, the word line decoder is configured to operate under the control of control logic (not shown). For example, the word line decoder may receive word line address data from the outside through the control logic. The word line decoder can be used, for example, to decode a word line address and apply a voltage provided by a voltage generator (not shown) to the corresponding word line WL according to the decoded word line address. The multi-layer insulation layer 430 can be used, for example, to electrically isolate the corresponding plurality of conductive lines 420 and / or the corresponding transistors 410 from the conductive lines 420.

[0135] Multiple contact windows C1, for example, are disposed in the stepped region SR and extend downward (which may be in the vertical direction Z), and are each electrically connected to a corresponding conductive layer CL. Multiple contact windows C2, for example, are disposed in the stepped region SR and extend downward (which may be in the vertical direction Z), and are electrically connected to the driver circuit layer 400. Multiple electrical connectors EC, for example, are disposed in the stepped region SR and extend horizontally (which may be in the direction Y), and are each electrically connected to a corresponding contact window C1 and contact window C2. Based on this, components (e.g., memory cells) located in the array region AR can be electrically connected to the driver circuit layer 400 via the multiple contact windows C1, multiple contact windows C2, and multiple electrical connectors EC.

[0136] In this embodiment, the three-dimensional memory device 10 may further include a plurality of local bit lines LBL.

[0137] A plurality of regional bit lines LBL are, for example, disposed in the array region AR and may extend horizontally (e.g., in direction Y). In some embodiments, each of the plurality of regional bit lines LBL is disposed on a corresponding channel structure 200. It is worth noting that, in this embodiment, each regional bit line LBL may be electrically connected to the corresponding channel structure 200 via a via CV. The via CV is electrically connected to a conductive plug 240 in the channel structure 200. In some embodiments, the material of the plurality of regional bit lines LBL may be the same as or similar to that of the multi-layer word lines WL.

[0138] Figure 5A A partial cross-sectional diagram of a three-dimensional memory device according to an embodiment of the present disclosure is shown, and Figure 5B FIG. 1 is a partial top view of a three-dimensional memory device according to another embodiment of the present disclosure.

[0139] Please refer to Figure 5A , Figure 5A The three-dimensional memory element 20 shown has a complementary metal oxide semiconductor field effect transistor under array (CMOS under array; CUA) architecture. The driving circuit layer 400 including the complementary metal oxide semiconductor field effect transistor is formed before the stack structure 100 is formed. That is, the complementary metal oxide semiconductor field effect transistor is located below the stack structure 100, which can be referred to the aforementioned embodiment and will not be described again here. In this embodiment, the three-dimensional memory element 20 may also include a conductive layer 500 and an insulating layer 600. The conductive layer 500 is, for example, disposed on the top surface of the stack structure 100. In some embodiments, the conductive layer 500 may include global bit lines, and the global bit lines are electrically connected to the corresponding multiple local bit lines LBL, but the present disclosure is not limited to this. The insulating layer 600 is, for example, disposed on the top surface of the stack structure 100 and covers the conductive layer 500. In some embodiments, the material of the conductive layer 500 may be the same as the material of the multiple local bit lines LBL, and the material of the insulating layer 600 may be the same as the material of the insulating layer IL.

[0140] Please refer to Figure 5B , Figure 5BThe three-dimensional memory element 30 shown has the architecture of a complementary metal oxide semiconductor field effect transistor bonded array (CMOS bonded array; CbA). In detail, a plurality of pads PAD1 are provided on the top surface 100T of the stacked structure 100, and a plurality of pads PAD2 are provided on the surface of the driving circuit layer 400 including complementary metal oxide semiconductor field effect transistors. The plurality of pads PAD1 and the plurality of pads PAD2 are bonded to each other. The driving circuit layer 400 including complementary metal oxide semiconductor field effect transistors is formed before the stacked structure 100 is formed. That is, the complementary metal oxide semiconductor field effect transistors are bonded to the stacked structure 100. In this embodiment, the plurality of pads PAD1 are electrically connected to the corresponding electrical connectors EC, and the plurality of pads PAD2 are electrically connected to the corresponding wires 420. Based on this, the stacked structure 100 and the driving circuit layer 400 can be electrically connected to each other through the pads PAD1 and the pads PAD2. In this embodiment, the three-dimensional memory device 30 may further include a conductive layer 500 and an insulating layer 600 , which may be described with reference to the above embodiments and will not be further described herein.

[0141] In other embodiments, the three-dimensional memory device disclosed herein may also have a CMOS next to array (CnA) architecture, with the stacked structure 100 and the driver circuit layer 400 including the CMOS field-effect transistors being adjacent to each other in the horizontal direction.

[0142] In summary, in the three-dimensional memory device provided by the present disclosure, the ratio of the first width of the bottom portion of the channel structure surrounded by the bottommost layer of the multi-layer word line to the second width of the top portion of the channel structure surrounded by the topmost layer of the multi-layer conductive layer is 0.85-0.95. Based on this, multiple memory cells at different heights can have substantially the same memory cell size, resulting in substantially the same operating speed during operation, thus ensuring relatively high reliability of the three-dimensional memory device provided by the present disclosure.

[0143] In addition, in the manufacturing method of the three-dimensional memory element provided by the present disclosure, a second insulating layer is formed in the plurality of through-holes before forming the channel structure in the plurality of through-holes. Furthermore, the width of the second insulating layer surrounded by the bottommost layer of the multi-layer sacrificial layer is smaller than the width of the second insulating layer surrounded by the topmost layer of the multi-layer sacrificial layer. Based on this, the width difference between the bottom and top portions of the subsequently formed channel structure can be reduced. Therefore, despite the relatively high aspect ratio of the through-hole, multiple memory cells at different heights can have substantially the same memory cell size. Therefore, the three-dimensional memory element provided by the present disclosure can have substantially the same operating speed when operated, so that it can have relatively high reliability.

Claims

1. A three-dimensional memory element, comprising: A stacked structure comprising multiple conductive layers and multiple insulating layers stacked alternately; as well as at least one channel structure extending through the stacked structure from a top surface of the stacked structure to a bottom surface of the stacked structure, wherein the at least one channel structure comprises a top portion and a bottom portion, A ratio of a first width of the bottom portion surrounded by one of the multiple conductive layers to a second width of the top portion surrounded by another of the multiple conductive layers is 0.85-0.

95. 2 . The three-dimensional memory element according to claim 1 , wherein the first width is a width of the bottom portion surrounded by a bottommost layer of the multi-layer conductive layer. 3 . The three-dimensional memory element according to claim 1 , wherein the second width is a width of the top portion surrounded by a topmost layer of the multi-layer conductive layer. 4 . The three-dimensional memory device according to claim 1 , wherein one of the multiple insulating layers comprises a first insulating layer and a second insulating layer, and the second insulating layer is located between the first insulating layer and the at least one channel structure. 5 . The three-dimensional memory element according to claim 4 , wherein the first insulating layer and the second insulating layer include the same material. 6 . The three-dimensional memory element according to claim 4 , wherein the second insulating layer horizontally extends away from the at least one channel structure and covers a portion of a lower conductive layer in the multi-layer conductive layer. 7 . The three-dimensional memory element according to claim 4 , wherein a width of the second insulating layer adjacent to the top portion of the at least one channel structure is greater than a width of the second insulating layer adjacent to the bottom portion of the at least one channel structure. 8 . The three-dimensional memory element according to claim 1 , further comprising a substrate located below the bottom portion of the at least one channel structure.

9. The three-dimensional memory element of claim 1, further comprising a substrate located above the top portion of the at least one channel structure.

10. A three-dimensional memory element, comprising: A stacked structure comprising alternately stacked multiple word lines and multiple insulating layers; as well as a plurality of channel structures extending downwardly through the stacked structure, wherein each of the plurality of channel structures includes a top portion and a bottom portion, A ratio of a first width of the bottom portion surrounded by one layer of the multi-layer word line to a second width of the top portion surrounded by another layer of the multi-layer word line is 0.85-0.

95. 11 . The three-dimensional memory element according to claim 10 , wherein the first width is a width of the bottom portion surrounded by a lowest layer in the multi-layer word line. 12 . The three-dimensional memory element of claim 10 , wherein the second width is a width of the top portion surrounded by a topmost layer in the multi-layer word line. 13 . The three-dimensional memory device according to claim 10 , wherein one of the multiple insulating layers comprises a first insulating layer and a second insulating layer, and the second insulating layer is located between the first insulating layer and one of the plurality of channel structures. 14 . The three-dimensional memory element according to claim 13 , wherein a ratio of a width of the second insulating layer in a bottommost layer of the multi-layer insulating layer to a width of the second insulating layer in a topmost layer of the multi-layer insulating layer is 0.10-0.

90. 15 . The three-dimensional memory device according to claim 13 , wherein the second insulating layer extends horizontally away from one of the plurality of channel structures and covers a portion of a lower word line in the multi-layer word line.

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