Memory element

Abstract

The invention provides a memory element. The memory element comprises a stacked structure, a first conductive type doped layer, a second conductive type doped layer, a first conductor plug and a second conductor plug, the stacked structure is located above the substrate, and the stacked structure comprises a plurality of conductor layers and a plurality of insulating layers which are alternately stacked. The first conductive type doping layer is located between the stacking structure and the substrate, and the projection area of the first conductive type doping layer is larger than that of the stacking structure. The second conductive type doped layer surrounds the first conductive type doped layer and forms a heterojunction with the first conductive type doped layer. The first conductor plug is electrically connected with the first conductive doping layer. The second conductor plug is electrically connected with the second conductive doping layer. The memory element may be a 3D AND flash memory.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory has the advantage of ensuring that stored data does not disappear even after power failure, and is therefore widely used in personal computers and other electronic devices. Currently, the more commonly used three-dimensional memories in the industry include NOR memory and NAND memory. In addition, another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays and has high integration and high area utilization, as well as the advantages of fast operation speed. Therefore, the development of three-dimensional memory devices has gradually become a current trend. However, many challenges associated with three-dimensional memory devices still exist. Summary of the Invention

[0003] The embodiments of the present invention provide a memory element and a manufacturing method thereof, which can reduce leakage current of the memory.

[0004] In an embodiment of the present invention, a memory element includes a stacked structure, a first conductive type doped layer, a second conductive type doped layer, a first conductor plug, and a second conductor plug. The stacked structure is located above a substrate, wherein the stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The first conductive type doped layer is located between the stacked structure and the substrate, and the projected area of ​​the first conductive type doped layer is larger than the projected area of ​​the stacked structure. The second conductive type doped layer surrounds the first conductive type doped layer and forms a heterojunction with the first conductive type doped layer. The first conductor plug is electrically connected to the first conductive type doped layer. The second conductor plug is electrically connected to the second conductive type doped layer.

[0005] In an embodiment of the present invention, a memory element includes: a first conductive type doped layer, a second conductive type doped layer, a stacked structure, a first intermediate partition wall, a second intermediate partition wall, a first outer partition wall, and a second outer partition wall. The first conductive type doped layer is located above a substrate and includes a first portion and a second portion separated from each other. The second conductive type doped layer is located above the substrate and forms a first heterojunction and a second heterojunction with the first portion and the second portion. The second conductive type doped layer includes a middle portion and a peripheral portion. The middle portion is located between the first portion and the second portion of the first conductive type doped layer. The peripheral portion surrounds the first portion and the second portion of the first conductive type doped layer. The stacked structure is located above the first portion of the first conductive type doped layer, above the middle portion of the second conductive type doped layer, and above the second portion of the first conductive type doped layer, wherein the stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately. The first intermediate partition wall extends through the stacked structure and is located between the first portion of the first conductive type doped layer and the middle portion of the second conductive type doped layer. The second intermediate partition wall extends through the stacked structure and is located between the second portion of the first conductive type doped layer and the middle portion of the second conductive type doped layer. A first outer partition wall extends through the stacked structure and reaches the first portion of the first conductivity-type doped layer and the outer portion of the second conductivity-type doped layer. A second outer partition wall extends through the stacked structure and reaches the second portion of the first conductivity-type doped layer and the outer portion of the second conductivity-type doped layer. The first outer partition wall and the first intermediate partition wall define a first cell of the stacked structure. The second outer partition wall and the second intermediate partition wall define a second cell of the stacked structure.

[0006] Based on the above, the memory element and the manufacturing method thereof according to the embodiments of the present invention can reduce leakage current by forming a heterojunction between the first conductive type doped layer and the second conductive type doped layer and applying and controlling voltage to disable the heterojunction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments.

[0008] Figure 1B Show Figure 1A A partial 3D view of the memory array in the middle section.

[0009] Figure 1C and Figure 1D Show Figure 1B Cross-sectional view of the tangent line I-I'.

[0010] Figure 1E Show Figure 1B 、 Figure 1C 、 Figure 1D Top view of the tangent line II-II'.

[0011] Figure 2A A top view of a memory chip according to an embodiment of the present invention is shown.

[0012] Figure 2B Show Figure 2A A top view of a local area.

[0013] Figure 2C Show Figure 2B An enlarged view of the first unit U1.

[0014] Figure 2D Show Figure 2C A stereogram of a local area.

[0015] Figure 2E Show Figure 2C Cross-sectional view along line III-III'.

[0016] Figure 2F Show Figure 2C A stereogram of a local area.

[0017] Figures 3A to 3E FIG. 1 is a schematic cross-sectional view illustrating a method for manufacturing a memory device according to an embodiment of the present invention.

[0018] Figures 4A to 4E for Figures 3A to 3E A stereogram of a local area.

[0019] Figures 5A to 5C Schematic cross-sectional views of various partition structures according to embodiments of the present invention are shown.

[0020] Figure 6A A top view of a memory chip according to another embodiment of the present invention is shown.

[0021] Figure 6B Show Figure 6A A top view of a local area.

[0022] Description of reference numerals:

[0023] 10. A (i) 、A (i+1) : Memory array

[0024] 12: Charge storage layer

[0025] 14: Tunneling layer

[0026] 16: Channel Column

[0027] 20: Storage unit

[0028] 24: Insulation filling layer

[0029] 28: Insulation column

[0030] 32a: Conductor column / source column

[0031] 32b: Conductor column / drain column

[0032] 36: Barrier layer

[0033] 38: Gate layer / word line / conductor layer

[0034] 40: Charge storage structure

[0035] 48: Base

[0036] 49: Internal connection structure

[0037] 50: Dielectric substrate / dielectric layer

[0038] 50s: Surface

[0039] 52: Middle layer

[0040] 53: Conductor layer

[0041] 53P: first conductivity type doped layer

[0042] 53N: Second conductivity type doped layer

[0043] 53I: Heterojunction

[0044] 54, 56: Insulation layer

[0045] 55: Dielectric layer

[0046] 57: Conductor Via Window

[0047] 60: Arrow

[0048] 109: Hole

[0049] 133: Separation channel

[0050] 142: Lining

[0051] 142': Insulation material

[0052] 144: Conductor layer

[0053] 146: Dielectric layer

[0054] 200D, 200E, 400: Local area

[0055] AR: Array Area

[0056] AG: Air Gap

[0057] B, B1, B1', B2, B2', B3, B3': Block

[0058] BLOCK (i) 、BLOCK (i+1) : Block

[0059] BL n BL n+1 : Bit line

[0060] C1, C2: Area

[0061] SP (i) n 、SP (i) n+1 、SP (i+1) n 、SP (i+1) n+1 :Source column

[0062] DP (i) n , DP (i) n+1 , DP (i+1) n , DP (i+1) n+1 :Source column

[0063] WL (i) m 、WL (i) m+1 、WL (i+1) m 、WL (i+1) m+1 :Word line

[0064] X, Y, Z: direction

[0065] CL1, CL1', CL2, CL2', CL3, CL3': conductors

[0066] SM1: First Element

[0067] SM2: Second Element

[0068] DVC, DVC1, DVC1', DVC2, DVC2', DVC3, DVC3', DVC4, DVC4': dummy structures

[0069] ER: fringe area

[0070] GSK, GSK1, GSK2: Gate stack structure

[0071] MC-1, MC-2: memory chips

[0072] MD: Middle part

[0073] OP1: First opening

[0074] OP2: Second opening

[0075] PP: peripheral part

[0076] P: Part

[0077] P1: Part 1

[0078] P2: Part 2

[0079] P1: Part 3

[0080] P2: Part 4

[0081] PC1, PC1', PC2, PC2', PC3, PC3': Conductor plug

[0082] SC: ladder structure

[0083] SK1: Stacked structure

[0084] SLT: Separated Structure

[0085] SLT1: First dividing wall

[0086] SLT2: Second dividing wall

[0087] SLT3: Third dividing wall

[0088] SR: Step Area

[0089] T, T1, T2, T3, T4: Block element

[0090] TM: Top Metal Layer

[0091] TV1, TV2, TV3, TV1', TV2', TV3': perforated

[0092] U1, U2: Unit

[0093] VC: Channel column structure

[0094] I-I', II-II', III-III': tangent

[0095] X, Y, Z: direction DETAILED DESCRIPTION

[0096] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments. Figure 1B Show Figure 1A A partial 3D view of the memory array in the middle section. Figure 1C and Figure 1D Show Figure 1B Cross-sectional view of the tangent line I-I'. Figure 1E Show Figure 1B 、 Figure 1C and Figure 1D Top view of the tangent line II-II'.

[0097] Figure 1A The vertical AND memory array 10 includes two blocks BLOCK arranged in rows and columns. (i) With BLOCK (i+1) Schematic diagram of the block. (i) Including memory array A (i) Memory array A (i) A row (for example, the m+1th row) has a common word line (for example, WL (i) m+1 ) of AND storage cells 20. Memory array A (i) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg DP (i) n With Dp (i) n+1 ), so that the AND memory cell 20 is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.

[0098] Memory array A (i) A row (eg, the nth row) has a common source column (eg, SP (i) n ) and a common drain column (such as DP (i) n ) of AND storage cells 20. Memory array A (i) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). Therefore, memory array A (i)AND memory cell 20 along a common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

[0099] exist Figure 1A In the block BLOCK (i) In the memory array A (i) The AND memory cells 20 in the nth row share a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). The AND storage cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ).

[0100] Common source column (such as SP (i) n ) is coupled to a common source line (eg, SL n ); a common drain column (eg DP (i) n ) is coupled to a common bit line (eg, BL n ). Common source column (such as SP (i) n+1 ) is coupled to a common source line (eg, SL n+1 ); a common drain column (eg DP (i) n+1 ) is coupled to a common bit line (eg, BL n+1 ).

[0101] Similarly, BLOCK (i+1) Including memory array A (i+1) , which is the same as in the block BLOCK (i) Memory array A in (i) Similar. Memory array A (i+1) A row (for example, the m+1th row) has a common word line (for example, WL (i+1) m+1 ) of AND storage cells 20. Memory array A (i+1) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i+1) m+1) and coupled to different source columns (eg SP (i+1) n With SP (i+1) n+1 ) and the drain column (eg DP (i+1) n With DP (i+1) n+1 ). Memory array A (i+1) A row (eg, the nth row) has a common source column (eg, SP (i +1) n ) and a common drain column (eg DP (i+1) n ) of AND storage cells 20. Memory array A (i+1) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i+1) m+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (eg Dp (i+1) n ). Therefore, memory array A (i+1) AND memory cell 20 along a common source column (eg SP (i+1) n ) and a common drain column (eg DP (i+1) n ) are logically configured into one row.

[0102] BLOCK (i+1) With BLOCK (i) Common source line (eg SL n With SL n+1 ) and bit lines (such as BL n With BL n+1 ). Therefore, the source line SL n and bit line BL n Coupled to block BLOCK (i) AND memory array A (i) The nth row of AND memory cells 20 is coupled to the block BLOCK (i+1) AND memory array A in (i+1) The nth row AND memory cell 20 in the same manner as the source line SL n+1 and bit line BL n+1 Coupled to block BLOCK (i) AND memory array A (i)The AND memory cell 20 in the n+1th row is coupled to the block BLOCK (i+1) AND memory array A in (i+1) The AND storage unit 20 in the n+1th row.

[0103] Please refer to Figures 1B to 1D Memory array 10 may be disposed on an interconnect structure of a semiconductor die, such as one or more active devices (e.g., transistors) formed on a semiconductor substrate. Therefore, dielectric substrate (or dielectric layer) 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed on a silicon substrate over a metal interconnect structure. Memory array 10 may include a stacked structure GSK, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a, a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.

[0104] Please refer to Figure 1B , a stacked structure GSK is formed on a dielectric substrate 50. The stacked structure GSK includes a plurality of gate layers (also called word lines or conductor layers) 38 and a plurality of insulating layers 54 vertically stacked on a surface 50s of the dielectric substrate 50. In the Z direction, these gate layers 38 are electrically isolated by insulating layers 54 disposed therebetween. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layers 38 of the step region SR may have a step structure SC. Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows (not shown) for connecting the gate layers 38 may land at the ends of the gate layers 38 to connect each layer of the gate layers 38 to each wire.

[0105] Please refer to Figures 1B to 1D Memory array 10 further includes a plurality of channel pillars 16. Channel pillars 16 extend continuously along the Z direction through stacked structure GSK and extend to conductive layer 53 between dielectric substrate 50 and stacked structure GSK. In some embodiments, channel pillars 16 may have an annular profile when viewed from above. Channel pillars 16 may be made of a semiconductor, such as undoped polysilicon. Conductive layer 53 may be made of doped polysilicon. In this embodiment, conductive layer 53 may be made of P-type doped polysilicon and N-type doped polysilicon, as described in detail below.

[0106] Please refer to Figures 1B to 1DThe memory array 10 further includes an insulating column 28, a plurality of first conductor columns 32a, and a plurality of second conductor columns 32b. In this example, the first conductor column 32a serves as a source column; the second conductor column 32b serves as a drain column. The first conductor column 32a, the second conductor column 32b, and the insulating column 28 each extend in a direction (i.e., the Z direction) perpendicular to the surface (i.e., the XY plane) of the gate layer 38. The first conductor column 32a and the second conductor column 32b are separated by the insulating column 28 and surrounded by the insulating filling layer 24. The first conductor column 32a and the second conductor column 32b are electrically connected to the channel column 16. The first conductor column 32a and the second conductor column 32b include doped polysilicon or metal material. The insulating column 28 is, for example, silicon nitride or silicon oxide, and the insulating filling layer 24 is, for example, silicon oxide.

[0107] Please refer to Figure 1C and Figure 1D The charge storage structure 40 is disposed between the channel pillar 16 and the plurality of gate layers (or conductor layers) 38. The charge storage structure 40 may include a tunneling layer (or energy gap engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 comprise silicon oxide. The charge storage layer 12 comprises silicon nitride, or other materials that can capture charge. In some embodiments, such as Figure 1C As shown, a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38. In other embodiments, such as Figure 1D As shown, the charge storage structure 40 (tunneling layer 14 , charge storage layer 12 and blocking layer 36 ) surrounds the gate layer 38 .

[0108] Please refer to Figure 1EThe charge storage structure 40, channel pillar 16, and source and drain pillars 32a and 32b are surrounded by a gate layer 38 and define a memory cell 20. The memory cell 20 can perform 1-bit or 2-bit operations using different operation methods. For example, when a voltage is applied to the source and drain pillars 32a and 32b, electrons can be transferred along the channel pillar 16 and stored in the charge storage structure 40 because the source and drain pillars 32a and 32b are connected to the channel pillar 16, thereby performing a 1-bit operation on the memory cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source and drain pillars 32a and 32b. For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32 a and drain pillars 32 b. This allows the memory cell 20 to perform single-bit cell (SLC, 1 bit) or multi-bit cell (MLC, greater than or equal to 2 bits) operations.

[0109] When operating, a voltage is applied to the selected word line (gate layer) 38, for example, a voltage higher than the corresponding starting voltage (V th ), the channel region of the channel column 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL n or BL n+1 (Shown in Figure 1B ) enters the drain column 32b and flows through the conductive channel region to the source column 32a (eg, in the direction indicated by arrow 60), and finally flows to the source line SL n or SL n+1 (Shown in Figure 1B ).

[0110] Figure 2A A top view of a memory chip according to an embodiment of the present invention is shown. Figure 2B Show Figure 2A The local area ( Figure 2A A top view of the dotted area). Figure 2C Show Figure 2B An enlarged view of the first unit U1. Figure 2D Show Figure 2C A stereoscopic view of a local area 200D. Figure 2E Show Figure 2C Cross-sectional view along line III-III'. Figure 2FShow Figure 2C A stereoscopic view of a local area 200E.

[0111] Please refer to Figure 2A and Figure 2B , the memory chip MC.1 is, for example, an AND memory element. The memory chip MC-1 may include a region C1 and a region C2. The region C1 may include a plurality of blocks T separated from each other. The blocks T may be arranged in an array having a plurality of rows and a plurality of columns. Figure 2A The block array is formed by 7 rows and 8 columns, however, the present invention is not limited thereto. Each block T in region C1 has multiple memory arrays. Region C2 includes peripheral circuits, such as complementary metal oxide semiconductor (CMOS) devices, disposed around the block array. Figure 2B A first unit U1 and a second unit U2 are shown. The first unit U1 includes a stacked structure GSK1 and a conductor layer 53. The second unit U2 includes a stacked structure GSK2 and a conductor layer 53. The stacked structure GSK1 and the conductor layer 53 of the first unit U1 may include blocks T1 and T2. The stacked structure GSK1 and the conductor layer 53 of the second unit U2 may include blocks T3 and T4.

[0112] The first unit U1 and the second unit U2 respectively include an array region AR, a step region SR and an edge region ER. Figures 2B to 2C The stacking structure GSK1 of the first unit U1 and the stacking structure GSK2 of the second unit U2 extend along the X direction from the array region AR to the step region SR. The stacking structure GSK1 of the first unit U1 and the stacking structure GSK2 of the second unit U2 are separated from each other.

[0113] The projected areas of the conductive layer 53 of the first unit U1 and the conductive layer 53 of the second unit U2 are respectively larger than the projected areas of the stacked structures GSK1 and GSK2. The conductive layer 53 of the first unit U1 and the conductive layer 53 of the second unit U2 each extend continuously from the array region AR through the step region SR to the edge region ER. In other words, the conductive layer 53 extends continuously from the edge region ER (leftmost) of the first unit U1 to the edge region ER (rightmost) of the second unit U2. Furthermore, the conductive layer 53 of the first unit U1 and the conductive layer 53 of the second unit U2 are connected to each other.

[0114] Please refer to Figures 2B to 2CThe stacked structure GSK1 of the first unit U1 and the stacked structure GSK2 of the second unit U2 are separated from each other and each extend along the X-direction from the array area AR to the step area SR. The conductive layer 53 of the first unit U1 and the conductive layer 53 of the second unit U2 are connected to each other and each extend along the X-direction, extending continuously from the array area AR through the step area SR to the edge area ER. In other words, the conductive layer 53 extends continuously from the edge area ER (leftmost) of the first unit U1 to the edge area ER (rightmost) of the second unit U2. From a top view, the stacked structure GSK1 of the first unit U1 is surrounded by the conductive layer 53. The stacked structure GSK2 of the second unit U2 is surrounded by the conductive layer 53.

[0115] Please refer to Figure 2D , the conductor layer 53 is located on the substrate 48. To further illustrate, the conductor layer 53 is located between the stacked structure GSK1 and the dielectric layer 50, and extends laterally to protrude from the stepped region SR of the stacked structure GSK1. The conductor layer 53 of the embodiment of the present invention includes a doped semiconductor layer, such as a doped polysilicon layer. The conductor layer 53 of the embodiment of the present invention includes a first conductive type doped layer 53P and a second conductive type doped layer 53N. The first conductive type doped layer 53P can be grounded, and is adjacent to and in contact with the second conductive type doped layer 53N, and forms a heterojunction 53I. The first conductive type doped layer 53P extends from the array region AR to the stepped region SR and to a portion of the edge region ER, and is located between the stacked structure GSK1 and the dielectric layer 50. In other words, the first conductive type doped layer 53P is located below the stacked structure GSK1 and extends laterally to protrude from the stepped structure SC of the stacked structure GSK1. The second conductive type doped layer 53N is located in another portion of the edge region ER, located on the dielectric layer 50, and laterally surrounds the first conductive type doped layer 53P. Figure 2C shown.

[0116] Reference Figure 2B In the embodiment of the present invention, the first conductive type doping layer 53P includes a plurality of portions P separated from each other. The second conductive type doping layer 53N surrounds the plurality of portions P. Figure 2B In the embodiment, the first conductive type doped layer 53P includes a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4. The second conductive type doped layer 53N surrounds the first portion P1, the second portion P2, the third portion P3, and the fourth portion P4. The first unit U1 includes the first portion P1 and the second portion P2 of the first conductive type doped layer 53P. The second unit U2 includes the third portion P3 and the fourth portion P4 of the first conductive type doped layer 53P. The second conductive type doped layer 53N of the first unit U1 surrounds the first portion P1 and the second portion P2. The second conductive type doped layer 53N of the second unit U1 surrounds the third portion P3 and the fourth portion P4.

[0117] The second conductive type doped layer 53N of the first unit U1 and the second unit U2 each includes a middle portion MP and a peripheral portion PP. In the first unit U1, the middle portion MP is located between the first portion P1 and the second portion P2 of the first conductive type doped layer 53P. In other words, the second conductive type doped layer 53N divides the first conductive type doped layer 53P into two parts, namely the first portion P1 and the second portion P2, via its middle portion MP. The middle portion MP of the second unit U2 is located between the third portion P3 and the fourth portion P4 of the first conductive type doped layer 53P. In other words, the second conductive type doped layer 53N divides the first conductive type doped layer 53P into two parts, namely the third portion P3 and the fourth portion P4, via its middle portion MP. The peripheral portion PP of the first unit U1 surrounds the first portion P1 and the second portion P2 of the first conductive type doped layer 53P. The peripheral portion PP of the second unit U2 surrounds the third portion P3 and the fourth portion P4 of the first conductive type doped layer 53P and is connected to each other.

[0118] The first unit U1 and the second unit U2 each include a plurality of partition structures SLT and SLT', which are long trenches. The partition structure SLT divides part of the stacked structure GSK1, defining a block T1 and a plurality of blocks B1, B2 and B3 in the block T3. Similarly, the partition structure SLT' defines a block T2 and a plurality of blocks B1', B2' and B3' in the block T4. For simplicity, Figure 2C The first unit U1 is taken as an example for further explanation.

[0119] exist Figure 2C In the embodiment, the partition structure SLT includes a plurality of first partition walls SLT1, a second partition wall SLT2 and a third partition wall SLT3. The plurality of first partition walls SLT1 are located between the second partition wall SLT2 and the third partition wall SLT3. Therefore, the plurality of first partition walls SLT1 are also referred to as a plurality of first inner partition walls SLT1. The second partition wall SLT2 is close to the center of the first unit U1, and is therefore also referred to as the first intermediate partition wall SLT2. The third partition wall SLT3 is outside the plurality of first inner partition walls SLT1, and is therefore also referred to as the first outer partition wall SLT3. In some viewpoints, the first outer partition wall SLT3 and the first intermediate partition wall SLT2 define the stacking structure GSK1 as a first element T1. The second outer partition wall SLT3' and the second intermediate partition wall SLT2' define the stacking structure GSK1 as a second element T2.

[0120] In some embodiments, the plurality of first partition walls SLT1, second partition walls SLT2, and third partition walls SLT3 are separated and unconnected from one another and are substantially parallel, for example, extending in the X direction and arranged in the Y direction. In some embodiments, the X direction is also referred to as the first direction, the Y direction is also referred to as the second direction, and the Z direction is also referred to as the third direction.

[0121] The first block T1 is divided into a plurality of blocks B by a plurality of first partition walls SLT1, a second partition wall SLT2 and a third partition wall SLT3. Figure 2C In FIG, the first block element T1 includes three blocks B1, B2 and B3, however, the embodiment of the present invention is not limited thereto.

[0122] The second partition wall SLT2 is located between the first portion P1 of the first conductivity-type doped layer 53P and the second conductivity-type doped layer 53N. A sidewall sw1 of the second partition wall SLT2 is adjacent to and in contact with the first portion P1 of the first conductivity-type doped layer 53P. A sidewall sw2 of the second partition wall SLT2 is adjacent to and in contact with the middle portion MP of the second conductivity-type doped layer 53N. Furthermore, sidewalls sw3 and sw4 at both ends of the second partition wall SLT2 may be adjacent to or connected to the heterojunction 53I.

[0123] Similarly, the partition structure SLT' includes a plurality of first partition walls SLT1', a second partition wall SLT2', and a third partition wall SLT3'. Each of these partition walls is similar to the plurality of first partition walls SLT1, second partition walls SLT2, and third partition walls SLT3, and will not be further described here. The second partition wall SLT2 of the first block T1 and the second partition wall SLT2' of the second block T2 are separated by the middle portion MP of the second conductive type doped layer 53N.

[0124] In addition, the stacked structure GSK1 includes multiple channel column structures VC, first dummy columns DVC1, and multiple second dummy columns DVC2 extending along the Z direction. The multiple channel column structures VC are located within the stacked structure GSK1 in blocks B1, B2, and B3, and are separated from each other by multiple first partition walls SLT1. Similarly, the multiple channel column structures VC' are located within the stacked structure GSK1 in blocks B1', B2', and B3', and are separated from each other by multiple first partition walls SLT1'.

[0125] On both sides of the second partition wall SLT2 are multiple first dummy columns DVC1 and multiple second dummy columns DVC2, which are separated from each other. The multiple first dummy columns DVC1 extend along the Z direction through the stacked structure GSK1 above the first portion P1 of the first conductive type doped layer 53P. The multiple second dummy columns DVC2 extend along the Z direction through the stacked structure GSK1 above the middle portion MP of the second conductive type doped layer 53N. The multiple first dummy columns DVC1 and the multiple second dummy columns DVC2 are separated by the second partition wall SLT2. Similarly, on both sides of the second partition wall SLT2' are multiple first dummy columns DVC1' and multiple second dummy columns DVC2'. The multiple first dummy columns DVC1' and the multiple second dummy columns DVC2' are separated by the second partition wall SLT2'. The multiple first dummy columns DVC1' extend through the stacked structure GSK1 above the second portion P2 of the first conductive type doped layer 53P.

[0126] Multiple third dummy columns DVC3 and multiple fourth dummy columns DVC4 are provided on both sides of the third partition wall SLT3, separating them from one another. The multiple third dummy columns DVC3 and multiple fourth dummy columns DVC4 extend through the stacked structure GSK1 above the first portion P1 of the first conductive type doped layer 53P. Similarly, multiple third dummy columns DVC3' and multiple fourth dummy columns DVC4' are provided on both sides of the third partition wall SLT3', separating them from one another. The multiple third dummy columns DVC3' and multiple fourth dummy columns DVC4' extend through the stacked structure GSK1 above the second portion P2 of the first conductive type doped layer 53P.

[0127] Reference Figure 2C In the embodiment of the present invention, the ends of each of the separation structures SLT and SLT' extending in the X-direction do not extend to the heterojunction 53I between the first conductivity-type doped layer 53P and the second conductivity-type doped layer 53N, and do not extend to the second conductivity-type doped layer 53N. Therefore, the first portion P1 and the second portion P2 of the first conductivity-type doped layer 53P are not cut into multiple separate segments by the separation structures SLT and SLT', and thus the first portion P1 and the second portion P2 of the first conductivity-type doped layer 53P remain continuous layers. Similarly, the ends of the separation structures SLT and SLT' do not extend to the peripheral portion PP of the second conductivity-type doped layer 53N. The middle portion MP and the peripheral portion PP of the second conductivity-type doped layer 53N remain connected to each other, and thus the second conductivity-type doped layer 53N remains a continuous layer.

[0128] Reference Figure 2C and 2DIn an embodiment of the present invention, the first portion P1 and the second portion P2 of the first conductive type doped layer 53P are each electrically connected to the first conductor plugs PC1 and PC1' disposed on the periphery of the stepped structure SC. The first conductor plugs PC1 and PC1' are each electrically connected to the first conductive wires CL1 and CL1' disposed thereon. The first conductive wires CL1 and CL1' are electrically connected to the first through-vias TV1 and TV1'. The first through-vias TV1 and TV1' are disposed outside the lowest step of the stepped structure SC and therefore do not overlap with the stepped structure SC. The first through-vias TV1 and TV1' pass through the first portion P1 and the second portion P2 of the first conductive type doped layer 53P, respectively, and are each connected to the top metal layer TM, and are further electrically connected to the first component SM1 disposed above the substrate 48. That is, the first portion P1 of the first conductive type doped layer 53P is electrically connected to the first component SM1 via the first conductor plug PC1, the first conductive wire CL1, and the first through-via TV1. The second portion P2 of the first conductive type doped layer 53P is electrically connected to another first element (not shown) above the substrate 48 through the first conductive plug PC1 ′, the first conductive line CL1 ′, and the first through-via TV1 ′.

[0129] The peripheral portion PP of the second conductive type doped layer 53N is electrically connected to the second conductor plugs PC2 and PC2' arranged on the periphery of the first part P1 and the second part P2 of the first conductive type doped layer 53P. The second conductor plugs PC2 and PC2' are electrically connected to the second conductive wires CL2 and CL2' arranged above them, respectively. The second conductive wires CL2 and CL2' are electrically connected to the second through-holes TV2 and TV2' arranged in the peripheral portion PP of the second conductive type doped layer 53N. The second through-holes TV2 and TV2' pass through the second conductive type doped layer 53N, and are respectively connected to the top metal layer TM, and are further electrically connected to the second element SM2 arranged above the substrate 48. That is, the second conductive type doped layer 53N is electrically connected to the second element SM2 above the substrate 48 via the second conductor plugs PC2 and PC2', the second conductive wires CL2 and CL2' and the second through-holes TV2 and TV2'. Figure 2C In the embodiment, the peripheral portion PP of the second conductive type doped layer 53N is electrically connected to the second conductive plugs PC2 and PC2' disposed on the periphery of the first conductive type doped layer 53P. Figure 2C In the embodiment, two second conductor plugs PC2, two second conductor plugs PC2' and their connected two second conductors CL2 and two second conductors CL2', two second through-holes TV2 and two second through-holes TV2' are used as an example. However, the present invention is not limited thereto. In other embodiments, more components may be included.

[0130] In an embodiment of the present invention, a P-type doped layer 53P contacts an N-type doped layer 53N to form a heterojunction 53I. A voltage V1 can be applied to the first conductive type doped layer 53P via the first element SM1, the first conductor plug PC1, the first conductive line CL1, and the first through-hole TV1. A voltage V2 can be applied to the second conductive type doped layer 53N via the second element SM2, the second conductor plug PC2, the first conductive line CL1, and the second through-hole TV2. By controlling the voltage difference ΔV between voltages V1 and V2 to be less than the turn-on voltage Vth of the heterojunction 53I (i.e., ΔV < Vth), the heterojunction 53I can be rendered non-conductive, thereby closing the leakage current path and reducing leakage current in the memory device.

[0131] Each of the plurality of third conductor plugs PC3 and PC3' is located on the stepped region SR of one of the blocks (e.g., blocks B2 and B2') of the stacked structure GSK1 and is connected to one of the plurality of conductor layers 38. Each of the third through-vias TV3 and TV3' is located on the stepped region SR of another adjacent block (e.g., blocks B1 and B1') of the stacked structure GSK1 and passes through the stacked structure GSK1 to connect to a third component above the substrate 48. Each of the third conductive lines CL3 and CL3' is connected to the third conductive plugs PC3 and PC3' and the third through-vias TV3 and TV3', respectively. One of the plurality of conductor layers 38 is connected to a third component via the third conductive plug PC3 or PC3', the third conductive line CL3 or CL3', and the third through-via TV3 or TV3'.

[0132] Figures 3A to 3E FIG. 1 is a schematic cross-sectional view illustrating a method for manufacturing a memory device according to an embodiment of the present invention. Figures 4A to 4E for Figures 3A to 3E A stereoscopic view of a local area 400.

[0133] Please refer to Figure 3A and Figure 4A , providing a substrate 48. The substrate 48 includes an array region AR, a step region SR and an edge region ER. The substrate 48 may include a semiconductor substrate, such as a silicon substrate. The substrate 48 includes components such as active elements (such as PMOS, NMOS, CMOS, JFET, BJT or diode components) or passive elements. An internal connection structure 49 is formed on the array region AR, the step region SR and the edge region ER of the substrate 48. The internal connection structure 49 may include components such as an inner dielectric layer, a contact window, a wire, an interlayer dielectric layer and a dielectric window. The material of the inner dielectric layer and the interlayer dielectric layer is, for example, a silicon oxide layer. Then, a dielectric layer 50 is formed on the internal connection structure 49. The material of the dielectric layer 50 is, for example, silicon oxide. In some embodiments, the dielectric layer 50 may also be referred to as a dielectric substrate 50.

[0134] Next, please continue to refer to Figure 3A and Figure 4A A blanket conductive layer 53 is formed on the dielectric layer 50 in the array region AR and the stepped region SR. The conductive layer 53 also extends to the edge region ER. The conductive layer 53 includes a first conductivity type doped layer 53P and a second conductivity type doped layer 53N.

[0135] The first conductivity-type doped layer 53P is, for example, a P-type doped layer 53P, and the second conductivity-type doped layer 53N is, for example, an N-type doped layer 53N. The P-type doped layer 53P is, for example, a P-type polysilicon layer. The N-type doped layer 53N is, for example, an N-type polysilicon layer. The P-type doped layer 53P may include a first portion P1 and a second portion P2. The conductive layer 53 may be formed by chemical vapor deposition of a conductive material, followed by forming a patterned implantation mask on the substrate 48 and performing an ion implantation process to form the P-type doped layer 53P and the N-type doped layer 53N, respectively.

[0136] Please refer to Figure 3B and Figure 4B , a stacking structure SK1 is formed on the conductive layer 53, and the stacking structure SK1 is patterned to form a step structure SC in the step region SR. In the present embodiment, the stacking structure SK1 is composed of an insulating layer 54 and an intermediate layer 52 stacked in sequence on the conductive layer 53. In other embodiments, the stacking structure SK1 may be composed of an intermediate layer 52 and an insulating layer 54 stacked in sequence on the conductive layer 53. The material of the insulating layer 54 is, for example, silicon oxide. The material of the intermediate layer 52 is, for example, silicon nitride. The intermediate layer 52 can serve as a sacrificial layer and be partially removed in subsequent processes. In the present embodiment, the stacking structure SK1 has 4 layers of insulating layers 54 and 5 layers of intermediate layers 52, but the present invention is not limited thereto. In other embodiments, more layers of insulating layers 54 and more layers of intermediate layers 52 can be formed depending on actual needs. Thereafter, photolithography and etching processes and trimming processes are performed to form the step structure SC.

[0137] A dielectric layer 55 (e.g., Figure 2E As shown in FIG. 5 , the dielectric layer 55 is formed by, for example, forming a dielectric material to cover the step structure SC. The dielectric layer 55 is then planarized using, for example, a chemical mechanical polishing process. For clarity, the dielectric layer 55 is not shown in FIG. Figure 3B and Figure 4B middle.

[0138] Reference Figure 3C, then, a plurality of channel column structures VC and VC' are formed in the stacked structure SK1. The methods for forming the plurality of channel column structures VC and VC' are similar. For the sake of brevity, only the plurality of channel column structures VC are used for illustration. First, a plurality of openings are formed in the stacked structure SK1. The openings expose the P-type doping layer 53P of the conductor layer 53. The etching process may be a dry etching process, a wet etching process or a combination thereof. The dry etching process is, for example, a plasma etching process. In this embodiment, the opening has a circular outline when viewed from above, but the present invention is not limited thereto. In other embodiments, the opening may have outlines of other shapes, such as a polygon (not shown). Then, in some implementations, a tunneling layer 14 and a channel column 16 are formed in the opening, such as Figure 1D as well as Figure 1E As shown. The tunneling layer 14 can also be formed later. For the sake of simplicity, Figure 3C The channel pillar 16 and the tunneling layer 14 are not shown.

[0139] Reference Figure 1D as well as Figure 1E The tunneling layer 14 and the channel pillar 16 may extend through the stacked structure SK1 and not through the conductive layer 53, but the present invention is not limited thereto. The channel pillar 16 may be, for example, annular in shape when viewed from above, and may be continuous in its extension direction (e.g., in a direction perpendicular to the surface of the substrate 48). In other words, the channel pillar 16 is integral in its extension direction and is not divided into a plurality of disconnected portions. In some embodiments, the channel pillar 16 may have a circular profile when viewed from above, but the present invention is not limited thereto. In other embodiments, the channel pillar 16 may have other shapes (e.g., polygonal) when viewed from above.

[0140] Reference Figure 1D as well as Figure 1E , an insulating filling material is filled on the stacked structure SK1 and in the opening. The insulating filling material is, for example, low-temperature silicon oxide. The insulating filling material filled in the opening forms an insulating filling layer 24 and leaves a circular pore in the center of the insulating filling layer 24. Then, an anisotropic etching process is performed to expand the circular pore to form a hole 109. An insulating material is formed on the insulating filling layer 24 and in the hole 109. Then, an anisotropic etching process is performed to remove part of the insulating material to form an insulating column 28 in the hole 109. The material of the insulating column 28 is different from the material of the insulating filling layer 24. The material of the insulating column 28 is, for example, silicon nitride.

[0141] Reference Figure 1D as well as Figure 1EA patterning process, such as photolithography and etching, is then performed to form a hole (not shown) in the insulating filler layer 24. During the etching process, the conductive layer 53 can be used as an etch stop layer. Thus, the formed hole extends from the stacked structure SK1 until the conductive layer 53 is exposed. The outline of the hole pattern defined by the patterning process can be tangential to the outline of the insulating pillar 28. The outline of the hole pattern defined by the patterning process can also exceed the outline of the insulating pillar 28 (not shown).

[0142] Reference Figure 1D as well as Figure 1E Then, conductive pillars 32a and 32b are formed in the hole. Conductive pillars 32a and 32b can serve as source and drain pillars, respectively, and are electrically connected to channel pillar 16. Conductive pillars 32a and 32b can be formed by forming a conductive layer on insulating filler layer 24 and in the hole, and then etching back. Conductive pillars 32a and 32b are, for example, doped polysilicon.

[0143] Reference Figure 3C as well as Figure 4C , photolithography and etching processes are performed to form a plurality of first openings OP1. Afterwards, insulating materials are filled into the plurality of first openings OP1 to form an insulating layer 56 of perforations TV1, TV2, TV3 and TV1', TV2', TV3'. The insulating material is, for example, silicon oxide. In addition, a plurality of dummy structures DVC and DVC' are formed in the stacked structure SK1. The plurality of dummy structures DVC and DVC' may be insulating materials. The plurality of dummy structures DVC and DVC' may include the aforementioned plurality of first dummy structures DVC1 and DVC1', a plurality of second dummy structures DVC2 and DVC2', a plurality of third dummy structures DVC3 and DVC3', and a plurality of fourth dummy structures DVC4 and DVC4'.

[0144] Please refer to Figure 3D and Figure 4D Afterwards, the stacked structure SK1 and the conductive layer 53 are patterned to form the separation trenches 133. During the etching process, the dielectric layer 50 or the conductive layer 53 can be used as an etch stop layer to expose the dielectric layer 50 or the conductive layer 53 in the separation trenches 133. The etching process can be a dry etching process, such as a plasma etching process.

[0145] Please refer to Figure 3D and Figure 4D , a replacement process is performed on the multi-layer intermediate layer 52. First, an etching process, such as a wet etching process, is performed to remove a portion of the multi-layer intermediate layer 52 to form a plurality of horizontal openings (not shown). The multi-layer charge storage layer 12, the multi-layer blocking layer 36, and the multi-layer conductor layer 38 are formed in the plurality of horizontal openings. Figure 1DAs shown. Charge storage layer 12 is, for example, silicon nitride. Blocking layer 36 is, for example, a high-k material having a dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. Conductor layer 38 is, for example, tungsten. In some embodiments, a barrier layer (not shown) is further formed before forming the multilayer conductor layer 38. The barrier layer is, for example, made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0146] Please refer to Figure 1D The charge storage layer 12, blocking layer 36, barrier layer, and conductor layer 38 are formed, for example, by sequentially forming a storage material, a blocking material, a barrier material, and a conductor material within the separation trenches 133 and the horizontal openings. An etch-back process is then performed to remove the storage material, blocking material, barrier material, and conductor material within the plurality of separation trenches 133. The tunneling layer 14, charge storage layer 12, and blocking layer 36 are collectively referred to as a charge storage structure 40. Thus, a gate stack structure GSK (GSK1) is formed. The gate stack structure GSK (GSK1) is disposed on a substrate 48 and includes multiple layers of conductor layers 38 and multiple layers of insulating layers 54 stacked alternately with one another.

[0147] Please refer to Figure 3D and Figure 4D , then, a separation structure SLT, SLT' is formed in the separation trench 133. The separation structure SLT, SLT' includes a plurality of first separation walls SLT1, SLT1', a plurality of second separation walls SLT2, SLT2' and a plurality of third separation walls SLT3, SLT3'. The separation structure SLT, SLT' can be a single layer or a multi-layer, such as Figures 5A to 5C shown.

[0148] Please refer to Figure 3D 、 Figure 4D and Figure 5A In some embodiments, the method for forming the separation structure SLT or SLT' is as follows. An insulating liner and a conductive material are filled on the gate stack structure GSK and in the separation trench 133. The insulating liner is, for example, silicon oxide. The conductive material is, for example, polysilicon. Then, the excess insulating liner material and the conductive material on the gate stack structure GSK and the edge region ER are removed by an etch-back process or a planarization process to form a liner 142 and a conductive layer 144. Thereafter, a dielectric material is formed on the substrate 48, and then an etch-back process or a planarization process can be performed to planarize the dielectric material to form a dielectric layer 146. The liner 142, the conductive layer 144 and a portion of the dielectric layer 146 form the separation structure SLT or SLT', as shown in FIG. Figure 5A shown.

[0149] In some embodiments, the separation structure SLT or SLT′ may also be completely filled with the insulating material 142′ without any conductive material, such as Figure 5B In some other embodiments, the separation structure SLT or SLT' may also be a liner 142, and the liner 142 covers the air gap AG without any conductive material, such as Figure 5C shown.

[0150] Reference Figure 3E and Figure 4E A conductive via 57 is formed in the insulating layer 56 between the through-holes TV1, TV2, TV3, and TV1', TV2', and TV3', and conductive plugs PC1, PC2, PC3, and PC1', PC2', and PC3' are formed. The conductive via 57 is located in the insulating layer 56 and extends through the insulating layer 56 and the dielectric layer 50, landing on the topmost conductive layer TM of the interconnect structure 49 and electrically connecting thereto. The conductive plugs PCI / PC1', PC2 / PC2', and PC3 / PC3' land on the first conductive type doped layer 53P, the second conductive type doped layer 53N, and the conductive layer 38, respectively. The conductive via 57 is formed by, for example, performing a photolithography and etching process to form a second opening OP2 in the insulating layer 56. The second opening OP2 penetrates the insulating layer 56 and the dielectric layer 50, exposing the topmost conductive layer TM of the interconnect structure 49. Next, a conductive material is formed on substrate 48 and filled into second opening OP2. The conductive material can be, for example, tungsten or polysilicon. A planarization process, such as chemical mechanical polishing, is then performed to remove the conductive material outside the via. Conductive plugs PC1 / PC1', PC2 / PC2', and PC3 / PC3' can be formed using a similar method to that used to form conductive via 57, or any other known method.

[0151] Reference Figure 2C and Figure 2D A dielectric layer (not shown) and a conductive layer are formed over the through-holes TV1, TV2, TV3, TV1', TV2', TV3', and the conductor plugs PC1, PC2, PC3, PC1', PC2', PC3'. Photolithography and etching processes are then performed to pattern the conductive layer to form the conductive lines CL1, CL2, and CL3. In this embodiment, the conductive lines CL1, CL2, and CL3 extend in the same direction. In another embodiment, the conductive lines CL1, CL2, and CL3 extend in different directions.

[0152] The present invention can be used in 3D AND flash memory, as well as 3D NOR flash memory and 3D NAND flash memory. The structure of 3D NOR flash memory can be as follows: Figure 2A and Figure 2BAs shown. The 3D NAND flash memory chip MC-2 can be Figure 6A and Figure 6B As shown, Figure 6B Show Figure 6A The local area ( Figure 6A A top view of the dotted area).

[0153] Furthermore, the present invention can be applied to various flash memories, such as floating gate (FG) type, charge trapping (CT) type, CMOS near array type, CMOS under array type, and CMOS bonding array type.

[0154] Based on the above, in embodiments of the present invention, a first conductivity-type doped layer and a second conductivity-type doped layer are formed below the stacked structure to create a heterojunction (PN junction) therebetween. By applying a voltage, the heterojunction is rendered inoperable, thereby reducing leakage current in the memory device. Therefore, the method of embodiments of the present invention can improve device reliability.

Claims

1. A memory element comprising: a stacked structure located above the substrate, wherein the stacked structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately; a first conductive type doped layer, located between the stacked structure and the substrate, wherein a projected area of ​​the first conductive type doped layer is larger than a projected area of ​​the stacked structure; a second conductive type doped layer, surrounding the first conductive type doped layer and forming a heterojunction with the first conductive type doped layer; a first conductor plug electrically connected to the first conductive type doped layer; as well as The second conductor plug is electrically connected to the second conductive type doped layer.

2. The memory element according to claim 1 , further comprising: a first through-hole, located at the periphery of the stacked structure, passing through the first conductive type doped layer, and electrically connected to the first element above the substrate; as well as A first conductive wire connects the first conductive plug and the first through-hole, wherein the first conductive type doped layer is electrically connected to the first element via the first conductive plug, the first conductive wire, and the first through-hole.

3. The memory element according to claim 1 , further comprising: a second through-hole, located at a periphery of the first conductive type doped layer, passing through the second conductive type doped layer, and electrically connected to a second element above the substrate; as well as The second conductive wire connects the second conductive plug and the second through-hole, wherein the second conductive type doped layer is electrically connected to the second element via the second conductive plug, the second conductive wire and the second through-hole.

4. The memory element according to claim 1 , further comprising: The first partition wall extends through the stack structure and the first conductive type doped layer to divide the stack structure into a first block and a second block.

5. The memory element according to claim 4 , further comprising: a second partition wall extending through the stacked structure and located between the first conductive type doped layer and the second conductive type doped layer; as well as The third partition wall extends through the stacked structure and the first conductive type doped layer, wherein the first partition wall is located between the second partition wall and the third partition wall.

6. The memory element according to claim 5, further comprising: A plurality of first channel column structures and a plurality of second channel column structures extend through the stacked structures of the first block and the second block respectively, and are separated by the first partition wall.

7. A memory element comprising: A first conductive type doped layer is located above the substrate and includes a first portion and a second portion separated from each other; A second conductive type doped layer is located above the substrate and surrounds the first portion and the second portion, the second conductive type doped layer comprising: a middle portion, located between the first portion and the second portion of the first conductive type doped layer; a peripheral portion surrounding the first portion and the second portion of the first conductive type doped layer; a stacked structure located above the first portion of the first conductivity-type doped layer, above the middle portion of the second conductivity-type doped layer, and above the second portion of the first conductivity-type doped layer, wherein the stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately; and a pair of intermediate dividing walls extending through the stacked structure, One side of the first intermediate partition wall of the pair of intermediate partition walls is adjacent to the first part of the first conductive type doped layer, one side of the second intermediate partition wall of the pair of intermediate partition walls is adjacent to the second part of the first conductive type doped layer, and the other side of the first intermediate partition wall and the other side of the second intermediate partition wall are adjacent to the middle part of the second conductive type doped layer.

8. The memory element according to claim 7, further comprising: a first outer partition wall extending through the stack structure and extending to the first portion of the first conductivity-type doped layer; a second outer partition wall extending through the stacked structure and extending to the second portion of the first conductive type doped layer; and The first outer partition wall and the first middle partition wall define the stacking structure into a first unit, and the first outer partition wall and the first middle partition wall are separated from each other and not connected; the second outer partition wall and the second middle partition wall define the stacking structure into a second unit, and the second outer partition wall and the second middle partition wall are separated from each other and not connected.

9. The memory element according to claim 7, further comprising: a plurality of first conductor plugs, located outside the stacked structure and respectively landing on the first portion and the second portion of the first conductive type doped layer; as well as The second conductor plug is located at the periphery of the first conductive type doped layer and lands on the second conductive type doped layer.

10. The memory element according to claim 9, further comprising: a plurality of first through holes, located outside the stacked structure, passing through the first portion and the second portion of the first conductive type doped layer, and electrically connecting to a plurality of first elements above the substrate respectively; as well as A plurality of first conductive wires connect the plurality of first conductor plugs and the plurality of first through-holes, wherein the first portion and the second portion of the first conductive type doped layer are electrically connected to corresponding first elements via corresponding first conductor plugs, corresponding first conductive wires and corresponding first through-holes respectively.

11. The memory element according to claim 9, further comprising: a second through-hole, located at a periphery of the first conductive type doped layer, passing through the periphery of the second conductive type doped layer, and electrically connected to a second element above the substrate; as well as The second conductive wire connects the second conductive plug and the second through-hole, wherein the second conductive type doped layer is electrically connected to the second element via the second conductive plug, the second conductive wire and the second through-hole. 12 . The memory element according to claim 7 , wherein the first portion of the first conductivity type doped layer is continuous; and the second portion of the first conductivity type doped layer is continuous. 13 . The memory element according to claim 7 , wherein the middle portion and the peripheral portion of the second conductivity-type doped layer are respectively continuous and connected to each other.

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