Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a gate structure including conductive layers and insulating layers alternately stacked; support structures respectively located at apexes of a polygon defined on an upper surface of the gate structure, and each of the support structures includes a pillar extending through the gate structure and a protruding portion protruding from the pillar toward the conductive layer; and a contact structure extending through the gate structure inside the polygon and electrically connected to a first of the conductive layers, in which the protrusion portion may include a first protrusion portion in contact with the contact structure and a second protrusion portion below the contact structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a unit memory cell. Recently, as improvements in the integration density of semiconductor devices in which memory cells are formed in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices have been proposed, in which memory cells are stacked on a substrate. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure including alternatingly stacked conductive layers and insulating layers; support structures (also referred to as support members) respectively located at the vertices of a polygon defined on the upper surface of the gate structure, and each support structure includes a column extending through the gate structure and a protrusion protruding from the column toward the conductive layer; and a contact structure extending through the gate structure inside the polygon and electrically connected to a first conductive layer among the conductive layers, wherein the protrusion may include a first protrusion in contact with the contact structure and a second protrusion located below the contact structure.

[0004] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure comprising alternatingly stacked conductive layers and insulating layers; support structures, respectively located at vertices of a polygon defined on an upper surface of the gate structure, and each support structure comprising a column extending through the gate structure and a protrusion protruding from the column toward the conductive layer; and a contact structure extending through the gate structure inside the polygon and electrically connected to a first conductive layer among the conductive layers, wherein the support structures arranged along the periphery of the polygon may be spaced apart from each other, and the contact structure may contact the protrusion of the support structure.

[0005] In an embodiment, a method for manufacturing a semiconductor device may include the following steps: forming a stack comprising a first material layer and a second material layer alternately stacked; forming a sacrificial support structure extending through the stack and respectively located at the vertices of a polygon defined on an upper surface of the stack; forming a sacrificial contact structure extending through the stack inside the polygon and comprising a lower region, an upper region, and an arched region located between the lower region and the upper region, the width of the arched region being greater than the width of the lower region and the width of the upper region; forming a first opening by removing the sacrificial support structure; forming a second opening by selectively etching the first material layer through the first opening so that the lower region of the sacrificial contact structure is exposed; forming a support structure in the first opening and the second opening; replacing the first material layer with a conductive layer; and replacing the sacrificial contact structure with a contact structure.

[0006] These and other features and advantages of embodiments of the present disclosure will become better understood by those skilled in the art after reading the following detailed description of the various embodiments illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1D is a simplified schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figures 2A to 2D is a simplified schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B is a simplified schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 7A to 7D 、 Figure 8A and Figure 8B is a simplified schematic diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 9 are diagrams for describing a modified example of the method for manufacturing the semiconductor device according to the embodiment of the present disclosure.

[0013] Figure 10A and Figure 10Bis a simplified schematic diagram for describing a modified example of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 11 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 12 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0017] By three-dimensionally stacking memory cells, the integration density of a semiconductor device can be improved, and a semiconductor device having a stable structure and improved reliability can also be provided.

[0018] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0019] Figures 1A to 1D is a simplified schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0020] Reference Figures 1A to 1D The semiconductor device may include a gate structure GST, a support structure 13, and a contact structure CT. The gate structure GST may include conductive layers 11 and insulating layers 12 alternately stacked. In an embodiment, the conductive layers 11 may be gate lines such as word lines, source select lines, or drain select lines. The conductive layers 11 may each include a conductive material such as, for example, polysilicon, tungsten, or molybdenum. The insulating layer 12 is used to insulate the stacked conductive layers 11 from each other. Each conductive layer 11 may include an insulating material such as, for example, oxide, nitride, or air gap.

[0021] The support structure 13 may extend vertically through the gate structure GST in a third direction III. The third direction III refers to the stacking direction of the conductive layer 11 and the insulating layer 12. In a plan view, the support structure 13 may be arranged in a first direction I and a second direction II intersecting the first direction I. As an example, a polygon may be defined on the upper surface of the gate structure GST, and the support structures 13 may be respectively located at the vertices of the polygon. The support structures 13 arranged along the periphery of the polygon may be spaced apart from each other. Here, the polygon may be a square. Figure 1C and Figure 1D , the four support structures 13 may be located at the four vertices of the square, respectively. The four support structures 13 arranged along the perimeter of the square may be spaced apart from each other. The four support structures 13 may be arranged at the four vertices of the square, and their sizes may be such that they may not contact each other.

[0022] Each support structure 13 may include a column 13A and a protrusion 13B. The column 13A refers to a slender column extending along the third direction III. The protrusion 13B may protrude laterally (e.g., horizontally) from the side wall of the column 13A. The cross-section of the column 13A may have a circular shape. However, the embodiment is not limited thereto, and in a variation of the described embodiment, the cross-section may be rectangular or elliptical. Multiple protrusions 13B may be connected to one column 13A, and the protrusions 13B may be positioned corresponding to the conductive layer 11. The protrusions 13B may protrude toward their corresponding conductive layer 11. The protrusions 13B may be spaced apart from each other at regular intervals along the third direction III.

[0023] like Figure 1A As shown in the embodiment of FIG, the contact structure CT may be located between the support structures 13. As an example, the contact structure CT may be located within a polygon defined by the support structures 13 and may be positioned corresponding to the center of the polygon (see FIG. Figure 1C ). In a plan view, the center of the contact structure CT may coincide with the center of the polygon, or the center of the polygon may be located in an area covered by the contact structure CT. The contact structure CT may vertically extend through the gate structure GST in the third direction III and may be electrically connected to the first conductive layer 11A in the conductive layer 11. As an example, a plurality of contact structures CT having different depths may be connected to the conductive layer 11, respectively. In a cross section, the contact structure CT may have a tapered shape or an arched shape. For example, as Figure 1A As shown, the cross-section of the contact structure CT may decrease in a direction opposite to the stacking direction of the gate structure GST.

[0024] The contact structure CT may include a contact plug 15 and an insulating spacer 14 surrounding a sidewall of the contact plug 15. The contact plug 15 may be electrically connected to the first conductive layer 11A. The insulating spacer 14 may insulate conductive layers above the first conductive layer 11A and the contact plug 15 from each other.

[0025] The contact structure CT may be in contact with the surrounding support structure 13. For example, Figure 1C As best shown in FIG, the contact structure CT located at the center of the polygon can contact the support structure 13 located at the vertex of the polygon. Depending on whether the protrusion 3B contacts the contact structure CT, the protrusion 13B can be divided into a first protrusion 13B1 or a second protrusion 13B2. The first protrusion 13B1 and the second protrusion 13B2 can have different shapes. For example, the second protrusion 13B2 can have a normal shape (e.g., a symmetrical shape such as a circular shape or an elliptical shape) that does not include the groove G, and the first protrusion 13B1 can have an abnormal shape that includes the groove G.

[0026] First protrusions 13B1 may be located within a first height range LV1 corresponding to contact structures CT. Contact structures CT may be located between first protrusions 13B1, and first protrusions 13B1 and contact structures CT may contact each other. First protrusions 13B1 may each include a groove G surrounding the sidewalls of contact structures CT and may have an asymmetrical shape with a portion recessed by the groove G. Contact structures CT may fill the groove G.

[0027] Second protrusion 13B2 may be located in a second height range LV2 that does not correspond to contact structure CT and may be located below contact structure CT. Because contact structure CT does not exist between second protrusions 13B2 in second height range LV2, second protrusion 13B2 does not include a groove. Therefore, second protrusion 13B2 may have a normal shape and may have a symmetrical shape such as a circular shape or an elliptical shape.

[0028] According to the above structure, the distance between support structures 13 can be adjusted by protrusions 13B. Even if pillars 13A are spaced apart by a first distance X1, the distance between support structures 13 can be narrowed to a second distance X2 by protrusions 13B. Therefore, the support force for the stack can be increased during the manufacturing process, and tilting or collapse of the stack can be reduced.

[0029] In addition, by increasing the width W of first protruding portion 13B1 and second protruding portion 13B2, second distance X2 can be narrowed, and the supporting force can be further increased. However, the value of width W should be determined in consideration of distance Y between adjacent support structures 13. When width W is increased so that adjacent support structures 13 contact each other along the perimeter of the polygon, first conductive layer 11A outside the polygon and first conductive layer 11A inside the polygon may be electrically disconnected from each other. Therefore, protruding portions 13B should be spaced apart from each other so that first conductive layer 11A is continuously connected to each other outside and inside the polygon, and width W should be increased within a range that ensures distance Y.

[0030] Figures 2A to 2D 1 is a simplified schematic diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure. Detailed descriptions of the aforementioned contents may be omitted.

[0031] Reference Figures 2A to 2D, the semiconductor device may include a gate structure GST, a contact structure CT, and a support structure 23. The gate structure GST may include stacked conductive layers 21A to 21C, and the contact structure CT may extend through the gate structure GST in a third direction III (i.e., a vertical direction). The support structure 23 may include a pillar 23A and protrusions 23B1, 23B2, and 23B3. The cross-section of the pillar 23A may have a circular shape. However, the embodiment is not limited thereto, and in variations of the described embodiment, the cross-section may be rectangular or elliptical.

[0032] As an example, the contact structure CT may have a cross section with an arcuate shape. More specifically, as Figure 2A As shown, the contact structure CT may include a lower region LR, an arched region BR, and an upper region UR. The lower region LR may include the lower surface of the contact structure CT, the upper region UR may include the upper surface of the contact structure CT, and the arched region BR may be located between the upper region UR and the lower region LR. The lower region LR may have a first width R1, the upper region UR may have a second width R2, and the arched region BR may have a third width R3. Here, the third width R3 may be greater than the first width R1 and the second width R2.

[0033] The protrusion portions 23B1, 23B2, and 23B3 may include grooves G1, G2, and G3 having different depths according to regions. Figure 2B , in the lower region LR, the contact structure CT may have a first width R1, and the first protrusion portion 23B1 may include a first groove G1 having a first depth D1. Figure 2C , in the upper region UR, the contact structure CT may have a second width R2, and the second protrusion portion 23B2 may include a second groove G2 having a second depth D2. Figure 2D , in the bow region BR, the contact structure CT may have a third width R3, and the third protrusion portion 23B3 may include a third groove G3 having a third depth D3.

[0034] Here, the second width R2 may be greater than the first width R1, and the second depth D2 may be greater than the first depth D1. The third width R3 may be greater than the first and second widths R1 and R2, and the third depth D3 may be greater than the first and second depths D1 and D2.

[0035] According to the above structure, the contact structure CT can have an arcuate cross-section and can contact the surrounding support structure 23 regardless of the width of the various regions of the contact structure CT. The first to third protruding portions 23B1, 23B2, and 23B3 can include first to third grooves G1, G2, and G3, respectively, and the depths of the grooves can vary depending on the width of the contact structure CT. The entire sidewall of the contact structure CT can have a continuous curved profile that protrudes in the arcuate region BR located between the lower region LR and the upper region UR.

[0036] Figure 3A and Figure 3B is a simplified schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A It is along Figure 3B Hereinafter, any contents repeated with those previously described may be omitted.

[0037] Reference Figure 3A and Figure 3B The semiconductor device may include a conductive layer 31, an insulating layer 32, a contact structure CT, and a support structure 33. The support structures 33 may each include a pillar 33A and a protrusion 33B. The contact structure CT may include a contact plug 35 and an insulating spacer 34 surrounding the contact plug 35. The insulating spacer 34 may include a sidewall pattern 34A and a protrusion pattern 34B. The protrusion pattern 34B may protrude from the sidewall pattern 34A toward the conductive layer 31. The protrusion pattern 34B may be positioned corresponding to the protrusion 33B and may be in contact with the protrusion 33B.

[0038] The support structures 33 may be arranged at the vertices of the polygon, and the contact structure CT may be located at the center of the polygon. The contact structure CT may contact the surrounding support structures 33. The contact structure CT may have a shape whose width is increased by the protrusion pattern 34B. The protrusion pattern 34B can increase the distance between the contact plug 35 and the conductive layer 31, and can ensure a breakdown voltage.

[0039] Figure 4 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0040] Reference Figure 4 The semiconductor device may include a peripheral circuit PC, a bonding structure BS, and a memory cell array CA. The bonding structure BS may be located between the peripheral circuit PC and the memory cell array CA and may include a bonding layer BL and a bonding pad BP that electrically connect the peripheral circuit PC and the memory cell array CA to each other.

[0041] The memory cell array CA may include a gate structure GST, a contact structure CT, and a support structure 43. The memory cell array CA may also include at least one of a channel structure CH, a source structure 49, a first interconnection structure IC1, a first interlayer insulating layer IL1, and a third interlayer insulating layer IL3.

[0042] The gate structure GST may include conductive layers 41 and insulating layers 42 alternately stacked. A source structure 49 may be located on the gate structure GST. A third interlayer insulating layer IL3 may be located on the source structure 49. The third interlayer insulating layer IL3 may be located on any remaining section of the gate structure GST not covered by the source structure 49. A channel structure CH may extend vertically through the gate structure GST and slightly into the source structure 49. The channel structure CH may include a channel layer 46, a memory layer 47 surrounding the channel layer 46, and an insulating core 48 located in the channel layer 46. A first interconnect structure IC1 may be connected to the channel structure CH and / or the contact structure CT. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1 and may include at least one vertically extending through-hole and at least one line extending parallel to the gate structure GST.

[0043] The support structure 43 may extend vertically through the gate structure GST. The support structure 43 may include a protrusion portion protruding toward the conductive layer 41. The contact structure CT may be located between the support structures 43. The contact structure CT may include an insulating spacer 44 and a contact plug 45. The contact structure CT may contact the surrounding support structures 43. Figure 3A and Figure 3B As described, the insulating spacer 44 may also include a protrusion pattern.

[0044] The peripheral circuit PC may include a transistor TR on the substrate 40. As an example, the peripheral circuit PC may be a page buffer, a row decoder, a logic circuit, etc. The second interconnect structure IC2 may be connected to the peripheral circuit PC and may be located in the second interlayer insulating layer IL2.

[0045] According to the above structure, the memory cell array CA and the peripheral circuit PC can be electrically connected to each other through the bonding structure BS. The support structure 43 includes the protruding portion, and thus, structural stability can be ensured in the manufacturing process.

[0046] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 7A to 7D 、 Figure 8A and Figure 8B is a simplified schematic diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A It's a floor plan. Figure 5B 、 Figure 6B 、 Figure 7B and Figure 8B Along the Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A A cross-sectional view taken along line AA'.

[0047] Reference Figure 5A and Figure 5B , a stack ST including alternately stacked first material layers 51 and second material layers 52 may be formed. The first material layers 51 may each include a material having a high etching selectivity relative to the second material layers 52. The first material layers 51 may be used to form gate lines. As an example, the first material layers 51 may each include a sacrificial material such as a nitride or a conductive material such as polysilicon or a metal. The second material layers 52 are used to insulate the stacked gate lines from each other and may each include an insulating material such as, for example, an oxide, a nitride, or an air gap.

[0048] Subsequently, first openings OP1 may be formed through the stack ST. The first openings OP1 may be arranged in a first direction I and a second direction II. In a plane defined by the first direction I and the second direction II, the first openings OP1 may be located at vertices of a polygon. In a plan view, the first openings OP1 may each have a shape such as a circular shape or an elliptical shape. The first openings OP1 may have a first width W1. The first openings OP1 may be arranged along the perimeter of the polygon and may be spaced apart from each other.

[0049] Subsequently, sacrificial support structures 53 may be formed in each of the first openings OP1. The sacrificial support structures 53 may extend through the stack ST. The sacrificial support structures 53 may each have a conical or arcuate cross-section. The sacrificial support structures 53 may each include a material having an etching selectivity relative to the first material layer 51 and the second material layer 52. As an example, the sacrificial support structures 53 may each include a carbon layer.

[0050] For example, when forming the first opening OP1, a channel hole, a slit, etc. may be formed together. In this case, when forming the sacrificial support structure 53, a sacrificial channel layer may be formed in the channel hole, and a sacrificial slit layer may be formed in the slit. In addition, after selectively removing the sacrificial channel layer, a channel structure may be formed.

[0051] Subsequently, a contact hole CTH may be formed in the stack ST. For example, a plurality of contact holes CTH having different depths may be formed to expose the first material layer 51. The contact hole CTH may be located between the first openings OP1. For example, the contact hole CTH may be located at the center of a polygon and may be spaced apart from the first openings OP1. The contact hole CTH may have a tapered or arcuate cross-section. The contact hole CTH may have a second width W2 greater than the first width W1.

[0052] Reference Figure 6A and Figure 6B , a sacrificial contact structure S_CT may be formed in the contact hole CTH. After forming an insulating liner 54 in the contact hole CTH, a sacrificial layer 55 may be formed in the insulating liner 54. The insulating liner 54 may include an insulating material such as, for example, oxide. The sacrificial layer 55 may include a material having a high etching selectivity with respect to the insulating liner 54, and may include tungsten.

[0053] Reference 7A to 7D , the sacrificial support structure 53 may be replaced by a support structure 56. The support structure 56 may have a shape different from that of the sacrificial support structure 53 and may include a plurality of protrusions 56B. Here, the protrusions 56B may be used to stably support the stack ST.

[0054] First, refer to Figure 7A and Figure 7B By removing the sacrificial support structure 53, the first opening OP1 can be reopened. Subsequently, the second material layer 52 exposed through the first opening OP1 can be selectively etched. As a result, the width of the first opening OP1 can be increased to a third width W3, and irregularities can be formed on the inner wall of the first opening OP1. The first material layer 51 can protrude into the first opening OP1.

[0055] The depth to which the second material layer 52 is etched may be determined by taking into account the width of the pillar formed in a subsequent process. The width W3 of the first opening OP1 defined by etching the second material layer 52 may correspond to the width of the pillar. When more of the second material layer 52 is etched, the width of the pillar increases, and when less of the second material layer 52 is etched, the width of the pillar decreases. Therefore, the depth to which the second material layer 52 is etched may be determined by taking into account the shape of the support member formed in a subsequent process.

[0056] Then, refer to Figure 7A and Figure 7C , the second opening OP2 can be formed by selectively etching the first material layer 51 exposed by the first opening OP1. The second opening OP2 can be used to define the area where the protrusion portion of the support structure is formed in a subsequent process. Therefore, the depth to which the first material layer 51 is etched can be determined in consideration of the width of the protrusion portion.

[0057] In order for the support structure to stably support the stack ST, the protrusion should have a sufficient width. However, adjacent support structures should be spaced apart from each other, and the protrusions should not be connected to each other. Therefore, the width of the second opening OP2 should be adjusted so that a protrusion with an appropriate width can be formed.

[0058] To this end, the first material layer 51 may be etched at a depth where the sacrificial contact structure S_CT is exposed. In this case, the second opening OP2 may have a sufficient width. In addition, adjacent second openings OP2 may not be connected to each other, and the first material layer 51 may remain between adjacent second openings OP2.

[0059] When the sacrificial contact structure S_CT has a variable width depending on the height, the depth of the first material layer 51 that should be etched to expose the sacrificial contact structure S_CT may differ from one another depending on the height. As an example, when the sacrificial contact structure S_CT has a tapered or bowed shape, the sacrificial contact structure S_CT may have a width in its lower region that is smaller than that in its remaining region. The sacrificial contact structure S_CT may have a minimum width in its lower surface and a maximum width in its bowed region or upper region. At the height where the sacrificial contact structure S_CT has the minimum width, the distance between the sacrificial contact structure S_CT and the first opening OP1 may be maximum, and the etching depth of the first material layer 51 required to expose the sacrificial contact structure S_CT may be relatively large. At the height where the sacrificial contact structure S_CT has the maximum width, the distance between the sacrificial contact structure S_CT and the first opening OP1 may be minimum, and the etching depth of the first material layer 51 required to expose the sacrificial contact structure S_CT may be relatively small.

[0060] Therefore, the first material layer 51 may be etched based on the etching depth of the first material layer 51 at the height where the sacrificial contact structure S_CT has the minimum width. As an example, the first material layer 51 may be etched at a depth at which the lower region of the sacrificial contact structure S_CT is exposed. In this case, the upper region and the bow region of the sacrificial contact structure S_CT and the lower region of the sacrificial contact structure S_CT may be exposed.

[0061] As the first material layer 51 is etched, the second opening OP2A may be formed at a height corresponding to the sacrificial contact structure S_CT, and the second opening OP2B may be formed at a height not corresponding to the sacrificial contact structure S_CT.

[0062] The sacrificial contact structure S_CT may be exposed through the second opening OP2A, and the area of ​​the sacrificial contact structure S_CT exposed in each of the lower region, the upper region, and the bow region may be different from each other. The area of ​​the sacrificial contact structure S_CT exposed in the lower region may be smaller, and the area of ​​the sacrificial contact structure S_CT exposed in the bow region may be larger.

[0063] The second openings OP2B may be located below the sacrificial contact structures S_CT. Because the second openings OP2B do not expose the sacrificial contact structures S_CT, the second openings OP2B may each have a normal shape, such as a circular shape or an elliptical shape. By increasing the depth of the second openings OP2B, the width of the protrusion formed in a subsequent process may be increased, and a greater supporting force may be ensured.

[0064] Then, refer to Figure 7A and Figure 7D , support structures 56 may be formed in the first opening OP1 and the second opening OP2. Each support structure 56 may include a column 56A located in the first opening OP1 and a protrusion 56B located in the second opening OP2.

[0065] Among the protrusions 56B, protrusions 56B1 located at a height corresponding to the sacrificial contact structure S_CT may contact the sacrificial contact structure S_CT and may include grooves surrounding the sidewalls of the sacrificial contact structure S_CT. Due to the grooves, each protrusion 56B1 may have an asymmetrical shape. Furthermore, the sizes of the grooves in each of the lower region, upper region, and arcuate region may differ from one another. The grooves in the protrusions 56B1 corresponding to the lower region may be relatively small, while the grooves in the protrusions 56B1 corresponding to the arcuate region may be relatively large.

[0066] The protrusions 56B2 located at a height not corresponding to the sacrificial contact structure S_CT among the protrusions 56B may be located below the sacrificial contact structure S_CT and may not include a groove. Because the protrusions 56B2 do not include a groove, each protrusion 56B2 may have a normal shape such as a circular shape or an elliptical shape.

[0067] Reference Figure 8A and Figure 8B , the first material layer 51 can be replaced with a conductive layer 57. As an example, the first material layer 51 can be removed by a slit penetrating the stack ST, and the conductive layer 57 can be formed in the area where the first material layer 51 is removed. Through this process, a gate structure including the conductive layer 57 and the second material layer 52 alternately stacked is formed.

[0068] Subsequently, the contact hole CTH may be reopened by removing the sacrificial layer 55. The insulating liner 54 may be exposed through the reopened contact hole CTH. Subsequently, the insulating liner 54 may be etched to form an insulating spacer 54A on the inner wall of the contact hole CTH. Subsequently, a contact plug 58 may be formed in the contact hole CTH.

[0069] According to the above-described manufacturing method, the support structure 56 including the protruding portion 56B can be formed by etching the first material layer 51 to form the second opening OP2. Therefore, when the first material layer 51 is replaced by the conductive layer 57, the support structure 56 can stably support the stack ST. Even at a height where the sacrificial contact structure S_CT does not exist, the stack ST can be stably supported by the protruding portion 56B.

[0070] In addition, since the second opening OP2 is formed by etching the first material layer 51 to expose the lower region of the sacrificial contact structure S_CT having a relatively small width, the second opening OP2 having a sufficient width may be formed, and the protrusion portion 56B having a sufficient width may be formed.

[0071] Figure 9 1 is a diagram for describing a modified example of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0072] Figure 9 is the same as above Figure 7B The corresponding figure. Figure 7B In the embodiment, the second material layer 52 exposed through the first opening OP1 is selectively etched, but this may be modified. As an example, the first material layer 51 and the second material layer 52 may be etched simultaneously. In this case, irregularities may not be formed in the first opening OP1, and the sidewalls of the first material layer 51 and the second material layer 52 may be aligned with each other.

[0073] Other processes may be the same or similar to the above processes.

[0074] Figure 10A and Figure 10B 1 is a simplified schematic diagram for describing a modified example of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0075] Figure 10A and Figure 10B is the same as above Figure 5B and Figure 6B The corresponding simplified schematic diagram. Figure 5B In the embodiment, the sacrificial contact structure S_CT is formed after the contact hole CTH is formed, but this may be modified. As an example, the shape of the contact hole CTH may be changed.

[0076] Reference Figure 10A , the opening OP may be formed by etching the first material layer 51 through the contact hole CTH. Thus, irregularities may be formed on the inner wall of the contact hole CTH, and the second material layer 52 may protrude into the contact hole CTH.

[0077] Reference Figure 10B , an insulating liner 54 and a sacrificial layer 55 may be formed in the contact hole CTH. The insulating liner 54 may extend along the inner surface of the contact hole CTH while filling the opening OP. Therefore, the insulating spacer 54A formed in a subsequent process may include a sidewall pattern and a protrusion pattern.

[0078] Other processes may be the same or similar to the above processes.

[0079] The structures and manufacturing methods according to the above-described embodiments can be applied to semiconductor devices having various structures. Figure 11 and Figure 12 A schematic configuration of a semiconductor device to which the above-described embodiment is applied is shown.

[0080] Figure 11 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0081] Reference Figure 11 , the semiconductor device may include a substrate SUB, a peripheral circuit PC, and a memory cell array CA. Here, the peripheral circuit PC and the memory cell array CA may be formed on the same substrate.

[0082] The substrate SUB may include a semiconductor material. As an example, the semiconductor material may include at least one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI compound semiconductor. Here, the Group IV semiconductor may include single crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). The Group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. The Group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0083] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include an organic material. As an example, the substrate SUB may include graphene.

[0084] The substrate SUB may be a bulk wafer or an epitaxial layer grown by a selective epitaxial growth (SEG) method. The substrate SUB may be a layer formed by a metal induced lateral crystallization (MILC) method and may partially include metal. The substrate SUB may have a single crystal state, a polycrystalline state, or an amorphous state. The substrate SUB may include Group II, Group III, Group IV, Group V, or Group VI impurities. As an example, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0085] The peripheral circuit PC may be located between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, and the like. As an example, the peripheral circuit PC may include an N-channel metal oxide semiconductor (NMOS) transistor, a P-channel metal oxide semiconductor (PMOS) transistor, a resistor, a capacitor, and the like. The peripheral circuit PC may also include an interconnect structure. The interconnect structure may serve as a path for transmitting an operating voltage and may include contact plugs, wiring, and the like.

[0086] The memory cell array CA may include memory cells. As an example, the memory cell array CA may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. As an example, the memory cell array CA may include memory cells connected between word lines and bit lines. The memory cell array CA may also include an interconnect structure.

[0087] Figure 12 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0088] Reference Figure 12 The semiconductor device may include a substrate SUB, a peripheral circuit PC, a bonding structure BS, and a memory cell array CA. Here, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded to each other. The semiconductor device may also include a support base SP_B.

[0089] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. As an example, a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC can be manufactured separately and then electrically connected to each other via a bonding structure BS. After the first wafer and the second wafer are bonded to each other, the support base SP_B of the first wafer can be at least partially removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0090] The support base SP_B may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. The support base SP_B may be a bulk wafer, an epitaxial layer grown by a selective epitaxial growth (SEG) method, or a layer formed by a metal-induced lateral crystallization (MILC) method. The support base SP_B may have a single crystal state, a polycrystalline state, or an amorphous state. The support base SP_B may include Group II, Group III, Group IV, Group V, or Group VI impurities.

[0091] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC to each other. As an example, the bonding structure BS can bond the memory cell array CA and the peripheral circuit PC to each other through a wafer-to-wafer bonding method, a chip-to-wafer bonding method, a chip-to-chip bonding method, etc. The bonding structure BS may include a bonding pad, a bonding layer, a bonding interface, etc. The bonding pad may include a metal such as copper or aluminum and / or an alloy thereof. The bonding interface may include a non-metal-non-metal interface, a metal-metal interface, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected to each other through the bonding structure BS.

[0092] For reference, the interconnect structures included in the memory cell array CA and / or the peripheral circuit PC may also be directly connected to each other without requiring bonding pads. As an example, a bonding layer included in the memory cell array CA and a bonding layer included in the peripheral circuit PC may be bonded to each other to form a bonding interface, and the interconnect structures included in the memory cell array CA and the interconnect structures included in the peripheral circuit PC may be directly connected to each other. Thus, contact plugs, wiring, etc. formed on different wafers can be electrically connected to each other without requiring separate bonding pads.

[0093] Other configurations can refer to the above Figure 11 The configurations described are the same or similar.

[0094] The semiconductor device may also have the above reference Figure 11 and Figure 12 The described embodiments may be combined with each other or may have partially modified structures. Figure 11 and Figure 12 In the described embodiment, the positions of the memory cell array CA and the peripheral circuit PC may be changed. Figure 11 In the described embodiments, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally bonded. As an example, a portion of the peripheral circuit PC may be located in the memory cell array CA.

[0095] Although embodiments according to the technical concepts of the present disclosure have been described above with reference to the accompanying drawings, this is merely for the purpose of describing embodiments according to the concepts of the present disclosure, and the present disclosure is not limited to the aforementioned embodiments. Without departing from the technical concepts of the present disclosure as defined in the following claims, those skilled in the art may make various types of substitutions, modifications, changes, and combinations of the embodiments, and such substitutions, modifications, changes, and combinations should be construed as falling within the scope of the present disclosure. Furthermore, these embodiments may be combined to form additional embodiments.

[0096] CROSS-REFERENCE TO RELATED APPLICATIONS

[0097] This patent application claims priority from Korean Patent Application No. 10-2024-0036920, filed on March 18, 2024, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate structure comprising alternately stacked conductive layers and insulating layers; support structures, the support structures being respectively located at vertices of a polygon defined on an upper surface of the gate structure, and each support structure including a pillar extending through the gate structure and a protrusion protruding from the pillar toward the conductive layer; as well as a contact structure extending through the gate structure within the polygon and electrically connected to a first conductive layer of the conductive layers, The protruding portion includes a first protruding portion in contact with the contact structure and a second protruding portion located below the contact structure.

2. The semiconductor device according to claim 1, wherein The contact structure is positioned to correspond to the center of the polygon.

3. The semiconductor device according to claim 1, wherein Each of the first protrusion portions includes a groove surrounding a sidewall of the contact structure and has an asymmetrical shape.

4. The semiconductor device according to claim 3, wherein Each of the second protrusion portions has a shape that does not include the groove.

5. The semiconductor device according to claim 3, wherein The contact structure fills the groove of the first protruding portion. The semiconductor device according to claim 3 , wherein: The grooves of the plurality of first protrusion portions have different depths.

7. The semiconductor device according to claim 1, wherein The support structures arranged along the perimeter of the polygon are spaced apart from each other.

8. The semiconductor device according to claim 1, wherein The contact structure includes a lower region, an upper region, and an arcuate region between the lower region and the upper region, and a width of the arcuate region is greater than a width of the lower region and a width of the upper region.

9. The semiconductor device according to claim 8, wherein Each of the first protruding portions includes a groove surrounding a sidewall of the contact structure, and a depth of the groove of the first protruding portion corresponding to the arcuate region is greater than a depth of the groove of the first protruding portion corresponding to the lower region.

10. The semiconductor device according to claim 1, wherein Each of the second protrusion portions has a circular shape or an oval shape in a plan view.

11. The semiconductor device according to claim 1, wherein The contact structure comprises: a contact plug electrically connected to the first conductive layer; and An insulating spacer surrounds a sidewall of the contact plug.

12. The semiconductor device according to claim 11, wherein The insulating spacer includes a protrusion pattern protruding toward the conductive layer.

13. The semiconductor device according to claim 12, wherein The protrusion pattern and the first protrusion portion contact each other.

14. The semiconductor device according to claim 1, further comprising: Peripheral circuits; as well as A bonding structure is located between the peripheral circuit and the gate structure and electrically connects the peripheral circuit and the contact structure to each other.

15. A semiconductor device comprising: a gate structure comprising alternately stacked conductive layers and insulating layers; support structures, the support structures being respectively located at vertices of a polygon defined on an upper surface of the gate structure, and each support structure including a pillar extending through the gate structure and a protrusion protruding from the pillar toward the conductive layer; as well as a contact structure extending through the gate structure within the polygon and electrically connected to a first conductive layer of the conductive layers, The support structures arranged along the periphery of the polygon are spaced apart from each other, and the contact structure contacts the protruding portions of the support structures.

16. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a laminate comprising alternatingly stacked layers of a first material and a second material; forming sacrificial support structures extending through the stack and respectively located at vertices of polygons defined on an upper surface of the stack; forming a sacrificial contact structure extending through the stack within the polygonal interior and comprising a lower region, an upper region, and an arcuate region between the lower region and the upper region, the arcuate region having a width greater than both the lower region and the upper region; forming a first opening by removing the sacrificial support structure; forming a second opening by selectively etching the first material layer through the first opening to expose the lower region of the sacrificial contact structure; forming a support structure in the first opening and the second opening; replacing the first material layer with a conductive layer; as well as The sacrificial contact structure is replaced with a contact structure.

17. The manufacturing method according to claim 16, further comprising the following steps: Before forming the second opening, the second material layer is etched through the first opening.

18. The manufacturing method according to claim 16, further comprising the following steps: Before forming the second opening, the first material layer and the second material layer are etched through the first opening.

19. The manufacturing method according to claim 16, wherein: The step of forming the sacrificial contact structure comprises the following steps: forming a contact hole in the stack; forming an insulating liner in the contact hole; and A sacrificial layer is formed in the insulating liner.

20. The manufacturing method according to claim 19, wherein: The step of replacing the sacrificial contact structure with the contact structure comprises the following steps: removing the sacrificial layer; forming insulating spacers by etching the insulating liner; and A contact plug is formed in the contact hole.

21. The manufacturing method according to claim 16, wherein: The support structure is in contact with the sacrificial contact structure.

22. The manufacturing method according to claim 16, wherein: The support structures are respectively located at the vertices of the polygon, and the support structures arranged along the periphery of the polygon are spaced apart from each other.

23. The manufacturing method according to claim 16, wherein: Each of the support structures includes a post positioned in the first opening and a protruding portion positioned in the second opening.

24. The manufacturing method according to claim 23, wherein: The protrusion comprises: a first protrusion portion that contacts the sacrificial contact structure and has an asymmetrical shape including a groove surrounding a sidewall of the sacrificial contact structure; and A second protrusion portion is located below the sacrificial contact structure and has a shape that does not include the groove.

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