Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. According to one embodiment, a semiconductor memory device includes a first chip and a second chip bonded to the first chip. The second chip has a stacked body, a columnar body, a semiconductor layer, a first wiring, and a second wiring. The columnar body includes a first end portion that reaches at least a first end of the laminated body. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion disposed along the first end of the stacked body, and a second portion covering the first end of the columnar body. The first semiconductor portion and the second semiconductor portion include an impurity that forms a p-type semiconductor. The third semiconductor portion includes an impurity that forms an n-type semiconductor. The first gate electrode layer includes a portion overlapping the first semiconductor portion when viewed from the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known (for example, see Japanese Patent Application Laid-Open No. 2022-41054). Summary of the Invention

[0003] In one embodiment, a semiconductor memory device includes a first chip and a second chip. The second chip is bonded to the first chip. The second chip includes a laminate, a columnar body, a semiconductor layer, a first wiring, and a second wiring. The laminate includes multiple gate electrode layers and multiple insulating layers. The multiple gate electrode layers and the multiple insulating layers are alternately stacked one after another in a first direction. The laminate has a first end, which is the opposite side of the first chip, that is, the end on the first side in the first direction. The columnar body extends through the laminate in the first direction. The columnar body has a first end that reaches at least the first end of the laminate. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion arranged along the first end of the laminate and a second portion covering the first end of the columnar body. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first and second semiconductor portions contain impurities that form a p-type semiconductor. The third semiconductor portion contains impurities that form an n-type semiconductor. The first gate electrode layer closest to the first end of the laminate, among the plurality of gate electrode layers, includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 This is a block diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0005] Figure 2 This is a diagram showing an equivalent circuit of a portion of the memory cell array according to the first embodiment.

[0006] Figure 3 This is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0007] Figure 4 It will Figure 3 The semiconductor memory device shown is a cross-sectional view showing an enlarged view of a region circled by line F4.

[0008] Figure 5 yes Figure 4 A cross-sectional view of the semiconductor memory device shown is taken along line F5 - F5 .

[0009] Figure 6 yes Figure 3 A cross-sectional view of the semiconductor memory device shown is taken along line F6 - F6 .

[0010] Figure 7 It is a cross-sectional view of the semiconductor layer for explaining the first embodiment.

[0011] Figure 8 yes Figure 7 This is a cross-sectional view of the structure shown along the line F8-F8.

[0012] Figure 9 It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0013] Figure 10 It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0014] Figure 11 It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0015] Figure 12 It is a diagram for explaining a read operation of the semiconductor memory device according to the first embodiment.

[0016] Figure 13 This is a cross-sectional view for explaining a read operation of the semiconductor memory device according to the first embodiment.

[0017] Figure 14 It is a diagram for explaining a write operation of the semiconductor memory device according to the first embodiment.

[0018] Figure 15 This is a diagram for explaining the erasing operation of the semiconductor memory device according to the first embodiment.

[0019] Figure 16 This is a cross-sectional view for explaining the erasing operation of the semiconductor memory device according to the first embodiment.

[0020] Figure 17 This is a cross-sectional view showing a portion of a semiconductor memory device according to a second embodiment.

[0021] Figure 18 This is a cross-sectional view showing a portion of a semiconductor memory device according to a third embodiment.

[0022] Figure 19 yes Figure 18A cross-sectional view of the structure shown along line F19-F19.

[0023] Figure 20 It is a plan view showing a portion of a semiconductor memory device according to a fourth embodiment.

[0024] Figure 21 It is a plan view showing a portion of the semiconductor memory device according to the fifth embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having identical or similar functions are denoted by the same reference numerals. Furthermore, duplicate descriptions of these components may be omitted. In the following description, reference numerals or letters may be omitted if they are not necessary to distinguish between reference numerals or letters.

[0026] In this application, the definitions of terms are as follows. "Parallel", "orthogonal" or "same" may include "approximately parallel", "approximately orthogonal" or "approximately the same" respectively. "Connected" is not limited to mechanical connection, and may include electrical connection. That is, "connected" is not limited to the situation where multiple elements are directly connected, and may include the situation where multiple elements are connected with other elements interposed therebetween. "Overlap" is not limited to the situation where multiple elements are in contact with each other, and may include the situation where multiple elements are separated (when viewed from a certain direction, the projections of multiple elements overlap with each other).

[0027] The +X direction, -X direction, +Y direction, -Y direction, +Z direction and -Z direction are defined as follows. The +X direction is the direction in which the word line WL is extended (see Figure 3 ). -X direction is the opposite direction of +X direction. When there is no need to distinguish between +X direction and -X direction, it is referred to as X direction. +Y direction is the direction intersecting (for example, orthogonal to) X direction. +Y direction is the extending direction of bit line BL (refer to Figure 6 ). -Y direction is the opposite direction of +Y direction. When there is no need to distinguish between +Y direction and -Y direction, it is referred to as Y direction. +Z direction is the direction intersecting (for example, orthogonal to) X direction and Y direction. +Z direction is the direction from the bit line BL described below toward the stacked body 40 (refer to Figure 3 ). The -Z direction is the opposite direction of the +Z direction. When there is no need to distinguish between the +Z direction and the -Z direction, it is referred to as the Z direction for short. In this application, the +Z direction side is sometimes referred to as "upper" and the -Z direction side is sometimes referred to as "lower". However, these expressions are only for the convenience of explanation and are not used to define the direction of gravity. The Z direction is an example of the "first direction". The X direction is an example of the "second direction". In addition, in the drawings described below, illustrations of structures that are not related to the description are sometimes omitted.

[0028] (First embodiment)

[0029] <1. Structure of a Semiconductor Memory Device>

[0030] Figure 1 This is a block diagram showing a portion of a semiconductor memory device 1. Semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device. Semiconductor memory device 1 is a NAND flash memory. Semiconductor memory device 1 can be connected to an external host device. Semiconductor memory device 1 serves as storage space for the host device. Semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0031] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer greater than or equal to 1). A block BLK is a collection of memory cell transistors. A block BLK serves as a unit for erasing data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0032] The command register 12 stores the command CMD received by the semiconductor memory device 1 from the host device. The address register 13 stores the address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes data write, read, or erase operations based on the command CMD stored in the command register 12.

[0033] The driver module 15 includes a voltage generation circuit that generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage on each bit line. During this operation, the sense amplifier module 17 transmits the determination result as read data DAT to the host device.

[0034] <2. Electrical Structure of Memory Cell Array>

[0035] Figure 2 1 is a diagram showing an equivalent circuit of a portion of the memory cell array 11 . Figure 2 1 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, five strings STR0 to STR4).

[0036] Each string STR includes multiple NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes multiple memory cell transistors MT0 to MTn (n is an integer greater than or equal to 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0037] In each NAND string NS, memory cell transistors MT0-MTn ​​are connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to one of the word lines WL0-WLn. In each memory cell transistor MT, charge is stored in the charge storage unit according to the voltage applied to the control gate via the word line WL, thereby storing data in a nonvolatile manner.

[0038] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0-MTn. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0-SGD4. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.

[0039] The drain of source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of source-side select transistor STS is connected to source line SL. The control gate of source-side select transistor STS is connected to source-side select gate line SGS. When a specified voltage is applied to source-side select gate line SGS, source-side select transistor STS connects NAND string NS to source line SL.

[0040] In the same block BLK, the control gates of memory cell transistors MT0-MTn ​​are commonly connected to their corresponding word lines WL0-WLn. In the same string STR, the control gates of drain-side select transistors STD are commonly connected to their corresponding drain-side select gate line SGD. The control gates of source-side select transistors STS are commonly connected to source-side select gate line SGS. In the memory cell array 11, bit line BL is shared by NAND strings NS assigned the same column address within multiple strings STR.

[0041] <3. Structure of a Semiconductor Memory Device>

[0042] Next, the structure of semiconductor memory device 1 will be described.

[0043] Figure 3 2 is a cross-sectional view showing a portion of a semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0044] <3.1 First Chip>

[0045] The first chip 2 is a circuit chip including a peripheral circuit and includes, for example, a semiconductor substrate 21 , a peripheral circuit 22 , an insulating portion 23 , and a plurality of pads 24 .

[0046] The semiconductor substrate 21 is, for example, a substrate serving as a base for the first chip 2. At least a portion of the semiconductor substrate 21 is in a plate shape extending along the directions X and Y. The semiconductor substrate 21 is formed of, for example, a semiconductor material such as silicon.

[0047] The peripheral circuit 22 is a circuit for enabling the memory cell array 11 to function. The peripheral circuit 22 includes a plurality of transistors 22a and a plurality of wirings 22b. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. An insulating portion 23 covers the peripheral circuit 22. A plurality of bonding pads 24 are provided on the surface of the insulating portion 23. Each bonding pad 24 is electrically connected to the peripheral circuit 22.

[0048] <3.2 Second Chip>

[0049] The second chip 3 is an array chip including the memory cell array 11. The second chip 3 includes, for example, the memory cell array 11, an insulating portion 31, a plurality of bonding pads 32, and an insulating portion 33. Here, the insulating portion 31, the plurality of bonding pads 32, and the insulating portion 33 are described; the memory cell array 11 will be described later.

[0050] The insulating portion 31 covers the memory cell array 11 from the -Z direction. A plurality of bonding pads 32 are provided on the surface of the insulating portion 31. Each bonding pad 32 is electrically connected to a wiring (e.g., wiring 71 or wiring 72) included in a wiring portion 70 of the memory cell array 11, described below. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the plurality of bonding pads 24 of the first chip 2 and the plurality of bonding pads 32 of the second chip 3 so that they face each other. The insulating portion 33 covers the memory cell array 11 from the +Z direction.

[0051] <4. Memory Cell Array>

[0052] Next, the memory cell array 11 will be described.

[0053] like Figure 3As shown, the memory cell array 11 includes an array area AR and a wiring area FR. In the array area AR, a plurality of storage pillars MH are provided. The array area AR is an area capable of storing data. In the wiring area FR, a plurality of contacts CC are provided. The wiring area FR is an area for connecting the plurality of conductive layers 41 described below to the wiring portion 70. The wiring areas FR are, for example, respectively provided on both sides of the array area AR in the X direction. No storage pillars MH are provided in the wiring area FR. In the wiring area FR, the ends of the plurality of conductive layers 41 are arranged, for example, in a stepped manner. Alternatively, the wiring area FR may also have a through contact that penetrates the conductive layer 41 as a contact CC. In addition, in the wiring area FR, a support body HR is provided for supporting the plurality of insulating layers 42 in the replacement step described below.

[0054] like Figure 3 As shown, the memory cell array 11 includes, for example, a laminate 40, a semiconductor layer 50, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the conductive layer, a wiring portion 70, a support body HR, and a plurality of dividing portions 80 (see FIG. Figure 6 ).

[0055] <4.1 Laminated body>

[0056] First, the layered body 40 will be described.

[0057] Figure 4 It will Figure 3 The illustrated cross-sectional view of the semiconductor memory device 1 is an enlarged view of the area encircled by line F4. The laminate 40 has a first end 40e1. The first end 40e1 is located on the opposite side of the first chip 2, i.e., on the +Z direction side. For example, the first end 40e1 is located on the opposite side of the semiconductor substrate 21, i.e., on the +Z direction side. Furthermore, the laminate 40 includes, for example, a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating layer 43. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one above the other in the Z direction.

[0058] The conductive layers 41 extend along the X and Y directions. Each conductive layer 41 is formed of a conductive material such as tungsten or molybdenum. The conductive layer 41 is an example of a "gate electrode layer."

[0059] Among the multiple conductive layers 41, one or more (e.g., multiple) of the conductive layers 41 located at the bottom function as drain-side select gate lines SGD. Drain-side select gate lines SGD are provided in common with multiple memory pillars MH arranged in the X or Y direction. The intersection of drain-side select gate lines SGD and channel layers 62 (described below) of each memory pillar MH functions as the drain-side select transistor STD.

[0060] Among the multiple conductive layers 41, one or more (e.g., multiple) conductive layers 41 located at the top function as source-side select gate lines SGS. Source-side select gate lines SGS are provided in common with multiple memory pillars MH arranged in the X or Y direction. The intersection of source-side select gate lines SGS and the channel layer 62 of each memory pillar MH functions as the source-side select transistor STS.

[0061] Among the multiple conductive layers 41, at least a portion of the remaining conductive layers 41 disposed between the conductive layers 41 functioning as the drain-side select gate line SGD and the source-side select gate line SGS functions as word lines WL. Word lines WL are provided in common with the multiple memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection of word lines WL and the channel layer 62 of each memory pillar MH functions as a memory cell transistor MT. Memory cell transistors MT will be described in detail below.

[0062] In this embodiment, the plurality of conductive layers 41 include a conductive layer 41A, a conductive layer 41B, and a conductive layer 41C.

[0063] Conductive layer 41A is the uppermost conductive layer 41 among the plurality of conductive layers 41. Conductive layer 41A is the conductive layer 41 closest to the first end 40e1 of the laminate 40 among the plurality of conductive layers 41. Conductive layer 41A is an example of a "first gate electrode layer."

[0064] Conductive layer 41B is one of the multiple conductive layers 41. Conductive layer 41B, for example, functions as the topmost word line WL among the multiple word lines WL. Conductive layer 41B, for example, is the conductive layer 41 closest to the source-side select gate line SGS among the multiple word lines WL. Alternatively, conductive layer 41B may function as the drain-side select gate line SGD or the source-side select gate line SGS. Conductive layer 41B is an example of a "second gate electrode layer."

[0065] Conductive layer 41C is conductive layer 41 adjacent to conductive layer 41B in the Z direction. Conductive layer 41C is, for example, the next conductive layer 41 located below conductive layer 41B. Conductive layer 41C functions as, for example, word line WL. Alternatively, conductive layer 41C may function as drain-side select gate line SGD or source-side select gate line SGS. Conductive layer 41C is an example of a "third gate electrode layer."

[0066] Insulating layer 42 is provided between two conductive layers 41 adjacent in the Z direction. Insulating layer 42 is an interlayer insulating film that insulates the two conductive layers 41. Insulating layer 42 extends along the X and Y directions. Insulating layer 42 is formed, for example, from a film containing silicon and oxygen. Insulating layer 42 is formed by supplying raw material gases, causing them to undergo a chemical reaction while being deposited. Insulating layer 42 is formed, for example, by chemical vapor deposition (CVD). Insulating layer 42 may contain carbon, etc., mixed in due to chemical reactions during the film formation process.

[0067] The plurality of insulating layers 42 include an insulating layer 42A. Insulating layer 42A is provided between conductive layer 41B (second gate electrode layer) and conductive layer 41C (third gate electrode layer). Insulating layer 42A is an interlayer insulating film that insulates conductive layers 41B and 41C. Insulating layer 42A is an example of a "first insulating layer."

[0068] Insulating layer 43 is provided above conductive layer 41A (first gate electrode layer). It is positioned between conductive layer 41A (first gate electrode layer) and first end 40e1 of laminate 40. The end of insulating layer 43 on the +Z direction forms first end 40e1 of laminate 40. Insulating layer 43 extends along the X and Y directions. Insulating layer 42 is formed, for example, from a film containing silicon and oxygen.

[0069] Insulating layer 43 is, for example, a thermally oxidized film. Insulating layer 43 is formed by heating a silicon layer in an oxygen atmosphere, oxidizing part or all of the silicon layer. Compared to insulating layer 42, insulating layer 43 contains a lower content of materials other than silicon and oxygen (e.g., carbon). Insulating layer 43 differs from insulating layer 42 in composition (e.g., film quality). Insulating layer 43 is a film with higher voltage resistance than insulating layer 42. Insulating layer 43 is an example of a "second insulating layer."

[0070] In this embodiment, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness (e.g., minimum thickness) T1 of the insulating layer 42 in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half the thickness (e.g., minimum thickness) T1 of the insulating layer 42 in the Z direction. In this embodiment, the "thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction" corresponds to the distance (e.g., shortest distance) in the Z direction between the conductive layer 41A and the first semiconductor portion 51 described below.

[0071] In another aspect, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness T3 of the conductive layer 41A in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half the thickness T3 of the conductive layer 41A in the Z direction. In another aspect, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is thinner than the thickness T4 of the conductive layer 41B in the Z direction. For example, the thickness (e.g., minimum thickness) T2 of the insulating layer 43 in the Z direction is less than half the thickness T4 of the conductive layer 41B in the Z direction.

[0072] <4.2 Semiconductor Layer (Source Line)>

[0073] The semiconductor layer 50 is provided on the first end 40e1 of the laminate 40. The semiconductor layer 50 extends in the X and Y directions. The semiconductor layer 50 is formed of a material containing silicon. The semiconductor layer 50 functions as the source line SL. The semiconductor layer 50 will be described in detail below.

[0074] <4.3 Storage Column>

[0075] A plurality of memory pillars MH are arranged in the X direction and the Y direction (refer to Figure 3 Each memory pillar MH extends through the laminate 40 in the Z direction and penetrates the laminate 40. The memory pillar MH is an example of a "columnar body."

[0076] Figure 5 yes Figure 4 The memory pillar MH includes, for example, a memory film (multilayer film) 61, a channel layer 62, an insulating portion 63, a cavity portion (air gap) 64, and a cap portion 65 (see FIG. Figure 4 ).

[0077] The memory film 61 is provided on the outer peripheral side of the channel layer 62. The memory film 61 is located between the plurality of conductive layers 41 and the channel layer 62. The memory film 61 includes, for example, a bulk insulating film 61a, a charge trapping film 61b, and a tunnel insulating film 61c.

[0078] The block insulating film 61a is provided between the plurality of conductive layers 41 and the charge capture film 61b. The block insulating film 61a is an insulating film that suppresses reverse tunneling. Reverse tunneling refers to the phenomenon in which charge returns from the word line WL to the charge capture film 61b. The block insulating film 61a is formed in a ring shape and extends in the Z direction. The block insulating film 61a is provided, for example, across the entire length of the storage column MH in the Z direction except for the first end MHe1 of the storage column MH described below. The block insulating film 61a is, for example, a laminated structure film formed by laminating a plurality of insulating films such as a film containing silicon and oxygen, or a film containing metal and oxygen. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 61a may also contain a high dielectric constant material (high-k material) such as silicon nitride or hafnium oxide.

[0079] The charge capture film 61b is located between the block insulating film 61a and the tunnel insulating film 61c. The charge capture film 61b is formed in a ring shape and extends in the Z direction. The charge capture film 61b is provided, for example, across the entire length of the storage column MH in the Z direction except for the first end MHe1 of the storage column MH. The charge capture film 61b is a functional film having many crystal defects (capture energy levels) and capable of capturing charges at the crystal defects. The charge capture film 61b is formed, for example, of a film containing silicon and nitrogen. In the charge capture film 61b, the portion adjacent to each word line WL is an example of a "charge storage portion" that can store information by storing charges.

[0080] The tunnel insulating film 61c is provided between the channel layer 62 and the charge trapping film 61b. The tunnel insulating film 61c is, for example, annular along the outer circumference of the channel layer 62 and extends in the Z direction along the channel layer 62. For example, the tunnel insulating film 61c is provided across the entire length of the memory pillar MH in the Z direction, excluding the first end portion MHe1 of the memory pillar MH. The tunnel insulating film 61c serves as a potential barrier between the channel layer 62 and the charge trapping film 61b. The tunnel insulating film 61c is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0081] Channel layer 62 is provided inside memory film 61. Channel layer 62 is formed in a ring shape. Channel layer 62 extends in the Z direction. For example, channel layer 62 is provided across the entire length of memory pillar MH in the Z direction. Channel layer 62 is formed of a semiconductor material such as polycrystalline silicon. Channel layer 62 may also be doped with impurities. When a voltage is applied to word line WL, channel layer 62 forms a channel, electrically connecting bit line BL and source line SL.

[0082] Thus, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed via the end of the word line WL adjacent to the memory pillar MH, the block insulating film 61a, the charge trapping film 61b, the tunnel insulating film 61c, and the channel layer 62. Furthermore, as a charge storage portion, the memory film 61 may include a floating gate charge storage portion (floating gate electrode) instead of the charge trapping film 61b. The floating gate electrode is formed, for example, of polysilicon containing impurities.

[0083] The insulating portion 63 is provided inside the channel layer 62. At least a portion of the interior of the channel layer 62 is embedded in the insulating portion 63. The insulating portion 63 is formed of a film containing silicon and oxygen. In this embodiment, the insulating portion 63 is formed in a ring shape along the inner peripheral surface of the channel layer 62 in such a manner that a cavity portion (air gap) 64 is formed inside. In addition, the cavity portion 64 may not exist. The insulating portion 63 extends in the Z direction. The insulating portion 63 is provided, for example, across most of the storage column MH in the Z direction except for the lower end portion of the storage column MH (refer to Figure 4 ).

[0084] Next, back to Figure 4 , the cover portion 65 will be described. The cover portion 65 is provided below the insulating portion 63. The cover portion 65 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 65 may also be doped with impurities. The cover portion 65 is arranged on the inner peripheral side of the lower end portion of the storage film 61 and is formed integrally with the channel layer 62. The cover portion 65 and the lower end portion of the channel layer 62 together form the lower end portion of the storage column MH. The contact CH is connected to the cover portion 65 from the -Z direction side.

[0085] Next, the first end MHe1 of the storage column MH is described. In the present embodiment, the first end MHe1 of the storage column MH protrudes from the first end 40e1 of the laminate 40 toward the +Z direction side. The first end MHe1 of the storage column MH is in contact with the semiconductor layer 50. At the first end MHe1 of the storage column MH, there is no storage film 61, and the channel layer 62 is exposed to the outside of the storage column MH. The channel layer 62 of the storage column MH is in contact with the semiconductor layer 50 at a position of the first end MHe1 that is closer to the +Z direction side than the first end 40e1 of the laminate 40. The first end MHe1 of the storage column MH is an example of a “first end”. In addition, the first end MHe1 of the storage column MH does not necessarily have to protrude from the first end 40e1 of the laminate 40 toward the +Z direction side. The first end MHe1 of the storage column MH only needs to reach at least the first end 40e1 of the laminate 40. For example, the first end portion MHe1 of the memory pillar MH may be in contact with the semiconductor layer 50 at the same position as the first end 40 e 1 of the laminate 40 .

[0086] <4.4 bit lines>

[0087] Next, back to Figure 3 Next, the bit lines BL are described. The bit lines BL are used to select one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below (on the -Z direction) the laminate 40. The multiple bit lines BL are spaced apart in the X direction and arranged in the X direction. Each bit line BL extends in the Y direction. Each bit line BL passes below the corresponding memory pillar MH and extends.

[0088] Each bit line BL is connected to the channel layer 62 of the memory pillar MH via the contact VY and the contact CH. Thus, a memory cell transistor MT can be arbitrarily selected from a plurality of memory cell transistors MT arranged three-dimensionally by combining word lines WL and bit lines BL.

[0089] <4.5 Contacts for Conductive Layer>

[0090] like Figure 3 As shown, contacts CC are electrical connection portions that electrically connect conductive layer 41 to wiring 72 (described below) included in wiring portion 70. Multiple contacts CC are arranged, for example, corresponding to wiring regions FR of memory cell array 11. Multiple contacts CC extend in the Z direction and are connected to different conductive layers 41, respectively.

[0091] <4.6 Wiring>

[0092] Next, the wiring portion 70 will be described. The wiring portion 70 is, for example, disposed between the laminate 40 and the semiconductor substrate 21. The wiring portion 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, a plurality of wirings 72, a plurality of wirings 75 ( Figure 6 Only one is shown in the figure) and multiple wirings 76 ( Figure 6 Only one is shown in the figure). The wiring 75 and the wiring 76 will be described below.

[0093] Wiring 71 is an electrical connection portion that electrically connects bit lines BL to pads 32. Multiple wirings 71 are arranged, for example, below the bit lines BL. Each wiring 71 extends, for example, in the X or Y direction. A via V1 is provided between wiring 71 and the bit lines BL to electrically connect them.

[0094] Wiring 72 is an electrical connection portion that electrically connects conductive layer contact CC to pad 32. Wiring 72 is electrically connected to conductive layer 41 via conductive layer contact CC. A voltage is applied to wiring 72 to select conductive layer 41 (word line WL, drain-side select gate line SGD, or source-side select gate line SGS).

[0095] <4.7 Support>

[0096] Next, the support body HR will be described. The support body HR is provided in the wiring region FR. The support body HR penetrates the laminate 40 in the Z direction in the wiring region FR. The support body HR is, for example, a columnar body having the same structure as the storage column MH. Furthermore, the support body HR may also be formed of an insulating portion. The support body HR supports the plurality of insulating layers 42 in the replacement step described below.

[0097] <5.Breaking part>

[0098] Next, the dividing portion 80 will be described.

[0099] Figure 6 yes Figure 3 A cross-sectional view of semiconductor memory device 1 along line F6-F6 is shown. In this embodiment, multiple dividing portions 80 are provided in laminate 40. The multiple dividing portions 80 are spaced apart in the Y direction. Each of the multiple dividing portions 80 extends through laminate 40 in the Z direction, dividing one or more conductive layers 41, including the bottommost layer, along the Y direction. The multiple dividing portions 80 include, for example, multiple dividing portions ST and multiple dividing portions SHE.

[0100] <5.1 Breaking part ST>

[0101] The dividing portion ST is a wall portion that divides the laminate 40 along the Y direction. Multiple dividing portions ST are spaced apart in the Y direction. The dividing portion ST extends in the Z direction, penetrating the laminate 40, and also extends in the X direction. In other words, the dividing portion ST is a wall portion extending along both the Z and X directions. The dividing portion ST divides each conductive layer 41 included in the laminate 40 along the Y direction. For example, the dividing portion ST includes an insulating portion STa and a conductive portion STb.

[0102] The insulating portion STa extends in the Z direction and penetrates the laminated body 40. The insulating portion STa separates the plurality of conductive layers 41 included in the laminated body 40 along the Y direction. The insulating portion STa is formed of, for example, a film containing silicon and oxygen.

[0103] The conductive portion STb is provided within the insulating portion STa. It extends in the Z direction, penetrating the laminate 40. The upper end of the conductive portion STb contacts the semiconductor layer 50 (source line SL). The conductive portion STb is formed of a conductive material such as tungsten or molybdenum. For example, the conductive portion STb can also function as an electrical connection between the semiconductor layer 50 (source line SL) and wiring within the memory cell array 11.

[0104] Furthermore, the dividing portion ST may be formed of only one of the insulating portion STa and the conductive portion STb. For example, the dividing portion ST may be formed of only an insulator or only a conductor.

[0105] <5.2 Breaking part SHE>

[0106] The partition portion SHE is shallower in the Z direction than the partition portion ST and is a wall portion that divides the lower end of the laminate 40 along the Y direction. Multiple partition portions SHE are spaced apart in the Y direction. In this embodiment, multiple (e.g., four) partition portions SHE are present between two adjacent partition portions ST in the Y direction. The partition portion SHE is provided at the lower end of the laminate 40, extending midway through the laminate 40 in the Z direction and also extending in the X direction. In other words, the partition portion SHE is a wall portion extending along both the Z and X directions.

[0107] The dividing portion SHE penetrates a portion of the conductive layers 41, including the bottommost layer, among the plurality of conductive layers 41, dividing this portion of the conductive layers 41 along the Y direction. For example, the dividing portion SHE penetrates all conductive layers 41 that function as the drain-side select gate line SGD. On the other hand, the dividing portion SHE does not reach the conductive layer 41 that functions as the word line WL. The dividing portion SHE only divides the conductive layer 41 that functions as the drain-side select gate line SGD along the Y direction. The dividing portion SHE is formed, for example, of a film containing silicon and oxygen.

[0108] <6. Structure Related to the Semiconductor Layer (Source Line)>

[0109] Next, the structure related to the semiconductor layer 50 will be described.

[0110] Figure 7 It is a cross-sectional view for explaining the semiconductor layer 50 . Figure 7 In the figure, for the sake of convenience, only two memory pillars MH are shown between two adjacent segmentation portions ST (ST1, ST2) in the Y direction. Figure 6 As shown, among the plurality of partitioning portions ST, a plurality of memory pillars MH are present between two partitioning portions ST (ST1, ST2) adjacent in the Y direction. The partitioning portion ST1 is an example of a "first partitioning portion." The partitioning portion ST2 is an example of a "second partitioning portion."

[0111] like Figure 7 As shown, the semiconductor layer 50 is provided along the first end 40e1 of the laminate 40. In this embodiment, the semiconductor layer 50 is provided on the first end 40e1 of the laminate 40. The semiconductor layer 50 includes, for example, a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53.

[0112] <6.1 Semiconductor Division 1>

[0113] The first semiconductor portion 51 is a portion connected to the first end portions MHe1 of the plurality of memory pillars MH. The first semiconductor portion 51 extends in the Y direction, for example, so as to cover the first end portions MHe1 of the plurality of memory pillars MH. In addition, in this embodiment, the first semiconductor portion 51 extends linearly in the X direction (see FIG. Figure 8 ). The first semiconductor portion 51 includes, for example, a first portion 51 a and a plurality of second portions 51 b.

[0114] The first portion 51a is provided along the first end 40e1 of the laminate 40. For example, the first portion 51a is provided on the first end 40e1 of the laminate 40. For example, the first portion 51a is in a layered form along the X and Y directions on the first end 40e1 of the laminate 40. The first portion 51a is arranged between the plurality of second portions 51b in the X and Y directions, connecting the plurality of second portions 51b. In addition, the end portion of the first portion 51a on the +Y direction side is connected to the second semiconductor portion 52 in the Y direction. The end portion of the first portion 51a on the -Y direction side is connected to the third semiconductor portion 53 in the Y direction.

[0115] When viewed from the Z direction, the plurality of second portions 51b are provided in one-to-one correspondence with the plurality of memory pillars MH (see Figure 8 ). Each second portion 51b covers the first end portion MHe1 of the storage column MH from the +Z direction side. In the present embodiment, the first end portions MHe1 of the plurality of storage columns MH protrude from the first end 40e1 of the laminate 40 toward the +Z direction side. In the present embodiment, each second portion 51b bulges from the first portion 51a toward the +Z direction side and covers the first end portion MHe1 of the storage column MH from the +Z direction side.

[0116] The first semiconductor portion 51 contains an impurity that forms a p-type semiconductor (an impurity that serves as an acceptor) and has a p-type (for example, p - An "acceptor" is an element with fewer valence electrons than a tetravalent element, such as a trivalent element. An example of an acceptor is boron (B).

[0117] <6.2 Second Semiconductor Unit>

[0118] The second semiconductor portion 52 is connected to the wiring 75 of the wiring portion 70. The second semiconductor portion 52 is located, for example, on the +Y direction side relative to the first semiconductor portion 51. The second semiconductor portion 52 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the second semiconductor portion 52 is provided on the first end 40e1 of the laminate 40. The second semiconductor portion 52 includes, for example, a first portion 52a and a second portion 52b.

[0119] The first portion 52a is provided along the first end 40e1 of the laminate 40. For example, the first portion 52a is provided at the first end 40e1 of the laminate 40. The thickness of the first portion 52a in the Z direction is the same as the thickness of the first portion 51a of the first semiconductor portion 51 in the Z direction.

[0120] The second portion 52b covers the first end STe1 of the first dividing portion ST1 from the +Z direction side. In this embodiment, the first end STe1 of the first dividing portion ST1 protrudes from the first end 40e1 of the laminate 40 toward the +Z direction side. In this embodiment, the second portion 52b bulges toward the +Z direction side from the first portion 52a and covers the first end STe1 of the first dividing portion ST1 from the +Z direction side.

[0121] In this embodiment, the second semiconductor portion 52 overlaps at least a portion of the dividing portion ST1 when viewed from the Z direction. The second semiconductor portion 52 extends linearly in the X direction along the dividing portion ST1 (see FIG. Figure 8 ).

[0122] The second semiconductor portion 52 contains an impurity that forms a p-type semiconductor (an impurity that serves as an acceptor) and has a p-type (for example, p + In this embodiment, the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51. The impurities forming the second semiconductor portion 52 may be the same as or different from the impurities forming the first semiconductor portion 51.

[0123] <6.3 3rd Semiconductor Division>

[0124] The third semiconductor portion 53 is connected to the wiring 76 of the wiring portion 70. The third semiconductor portion 53 is located, for example, on the -Y direction side relative to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the third semiconductor portion 53 is provided on the first end 40e1 of the laminate 40. The third semiconductor portion 53 includes, for example, a first portion 53a and a second portion 53b.

[0125] The first portion 53a is provided along the first end 40e1 of the laminate 40. For example, the first portion 53a is provided at the first end 40e1 of the laminate 40. The thickness of the first portion 53a in the Z direction is the same as the thickness of the first portion 51a of the first semiconductor portion 51 in the Z direction.

[0126] The second portion 53b covers the first end STe1 of the second segment ST2 from the +Z direction side. In this embodiment, the first end STe1 of the second segment ST2 protrudes from the first end 40e1 of the laminate 40 toward the +Z direction side. In this embodiment, the second portion 53b rises from the first portion 53a toward the +Z direction side and covers the first end STe1 of the second segment ST2 from the +Z direction side.

[0127] In this embodiment, the third semiconductor portion 53 overlaps at least a portion of the dividing portion ST2 when viewed from the Z direction. The third semiconductor portion 53 extends linearly in the X direction along the dividing portion ST2 (see FIG. Figure 8 ).

[0128] The third semiconductor portion 53 contains an impurity that forms an n-type semiconductor (an impurity that serves as a donor) and has an n-type (for example, n + A "donor" is an element having more valence electrons than a tetravalent element, such as a pentavalent element. An example of a donor is phosphorus (P).

[0129] <6.4 Inversion Layer>

[0130] In this embodiment, the conductive layer 41A (the uppermost conductive layer 41 among the plurality of conductive layers 41) overlaps with the semiconductor layer 50 when viewed from the Z direction. The conductive layer 41A includes, for example, a first portion 41Aa, a second portion 41Ab, and a third portion 41Ac. The first portion 41Aa overlaps with the first semiconductor portion 51 of the semiconductor layer 50 when viewed from the Z direction. The second portion 41Ab overlaps with the second semiconductor portion 52 of the semiconductor layer 50 when viewed from the Z direction. The third portion 41Ac overlaps with the third semiconductor portion 53 of the semiconductor layer 50 when viewed from the Z direction. In addition, the term "overlapping with XX" as used in this application is not limited to overlapping with the entire region of XX, but may include overlapping with at least a portion of XX.

[0131] In this embodiment, when a voltage is applied to the conductive layer 41A, an inversion layer 50r is formed in a portion of the semiconductor layer 50. The inversion layer 50r is formed, for example, at the end portion on the -Z direction side of the first semiconductor portion 51. The inversion layer 50r extends in the X and Y directions along the first end 40e1 of the laminate 40. The inversion layer 50r is in contact with the channel layer 62 of the memory column MH and is also in contact with the third semiconductor portion 53. After the inversion layer 50r is formed, electrons can move between the channel layer 62 of the memory column MH and the third semiconductor portion 53.

[0132] <6.5 1st Wiring>

[0133] Next, the wiring 75 will be described. Hereinafter, for ease of explanation, the wiring 75 will be referred to as the "first wiring 75." The first wiring 75 is electrically connected to the second semiconductor portion 52. In this embodiment, the first wiring 75 is provided on the second semiconductor portion 52 and is in contact with the second semiconductor portion 52 from the +Z direction. For example, the first wiring 75 is in contact with the first portion 52a and the second portion 52b of the second semiconductor portion 52.

[0134] Figure 8 yes Figure 7 This is a cross-sectional view of the structure shown along the line F8-F8. Figure 8 Similarly, for the sake of convenience, only a portion of the memory pillars MH is shown between two adjacent segmentation portions ST (ST1, ST2) in the Y direction. Figure 8 For the sake of convenience, the insulating portion 33 is omitted and the first semiconductor portion 51, the second semiconductor portion 52, the third semiconductor portion 53, the wiring 75 and the wiring 76 are shown in solid lines. Figure 19 、 Figure 20 、 Figure 21 The same is true in Chinese.

[0135] like Figure 8 As shown, the first wiring 75 extends linearly in the X direction along the second semiconductor portion 52. The arrangement of the first wiring 75 is not limited to the example described above. For example, the first wiring 75 may be provided below the laminate 40 and electrically connected to the second semiconductor portion 52 via the conductive portion STb of the dividing portion ST1.

[0136] <6.6 Second Wiring>

[0137] Next, the wiring 76 will be described. Hereinafter, for ease of explanation, the wiring 76 will be referred to as the "second wiring 76." The second wiring 76 is electrically connected to the third semiconductor portion 53. In this embodiment, the second wiring 76 is electrically insulated from the first wiring 75. In this embodiment, the second wiring 76 is provided on the third semiconductor portion 53 and is in contact with the third semiconductor portion 53 from the +Z direction. For example, the second wiring 76 is in contact with the first portion 53a and the second portion 53b of the third semiconductor portion 53. The second wiring 76 extends linearly in the X direction along the third semiconductor portion 53.

[0138] The arrangement of the second wiring 76 is not limited to the above example. For example, the second wiring 76 may be provided below the laminate 40 and electrically connected to the third semiconductor portion 53 via the conductive portion STb of the dividing portion ST2.

[0139] <6.7 Insulation>

[0140] Back to Figure 7Next, the insulating portion 33 will be described. The insulating portion 33 is provided between the first wiring 75 and the second wiring 76 to electrically insulate the first wiring 75 from the second wiring 76. Furthermore, the insulating portion 33 is provided between the second semiconductor portion 52 and the third semiconductor portion 53 to electrically insulate the second semiconductor portion 52 from the third semiconductor portion 53.

[0141] <7. Manufacturing Method>

[0142] Next, a method for manufacturing semiconductor memory device 1 will be described.

[0143] Figures 9 to 11 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor memory device 1. First, a semiconductor substrate 101 is prepared. The semiconductor substrate 101 is formed of silicon. Next, an insulating layer 43 (see FIG. 1 ) is formed on the surface of the semiconductor substrate 101. Figure 9 In this embodiment, an oxidizing agent is supplied to the surface of the semiconductor substrate 101 while heating the surface, thereby forming the insulating layer 43 as a thermal oxide film on the surface of the semiconductor substrate 101 .

[0144] Then, the insulating layer 111 and the insulating layer 42 are alternately stacked one by one on the insulating layer 43 (see Figure 9 (b) in FIG. 4 ). Thus, a laminate 40A is formed. The insulating layer 111 is a sacrificial layer that will be replaced by the conductive layer 41 in a subsequent step. The insulating layer 111 is formed of a material containing silicon and nitrogen, for example.

[0145] Next, the memory pillars MH and the partitioning portions ST are formed on the laminate 40A (see Figure 9 (c) in FIG. 1 ). The first end MHe1 of the memory pillar MH and the first end STe1 of the dividing portion ST are formed within the semiconductor substrate 101. In this embodiment, the replacement step is performed by using the trench provided when forming the dividing portion ST, thereby replacing the insulating layer 111 with the conductive layer 41. Thus, the laminate 40 is formed from the laminate 40A.

[0146] The above steps form the second chip 3. Furthermore, the first chip 2 is formed through other steps. The second chip 3 is then attached to the first chip 2 in an upside-down position. For example, by bonding the bonding pads 32 of the second chip 3 to the bonding pads 24 of the first chip 2, the first chip 2 and the second chip 3 are integrated.

[0147] Then, at least a portion of the semiconductor substrate 101 is removed from the second chip 3 (see Figure 10(d) in the figure). Here, for example, etching is performed. In addition, other processing besides etching may also be performed. In addition, both etching and the other steps may be performed. In this embodiment, the entire semiconductor substrate 101 except the insulating layer 43 is removed. In addition, the storage film 61 is removed at the first end MHe1 of the storage column MH by etching. Thus, the channel layer 62 is exposed at the first end MHe1 of the storage column MH. In addition, the insulating portion STa is removed at the first end STe1 of the dividing portion ST by etching. Thus, the conductive portion STb is exposed at the first end STe1 of the dividing portion ST.

[0148] Next, a semiconductor layer 120 is formed on the insulating layer 43 (see Figure 10 (e) in FIG). The semiconductor layer 120 contains impurities that form a p-type semiconductor. In this embodiment, the semiconductor layer 120 is formed as a p - The semiconductor layer 120 is formed of, for example, silicon doped with impurities. Alternatively, the semiconductor layer 120 may be formed by implanting impurities after film formation.

[0149] Semiconductor layer 120 includes a first portion 121, a second portion 122, and a third portion 123. First portion 121 corresponds to first semiconductor portion 51 of semiconductor layer 50. Second portion 122 corresponds to second semiconductor portion 52 of semiconductor layer 50. Third portion 123 corresponds to third semiconductor portion 53 of semiconductor layer 50.

[0150] Then, a mask M1 covering the first portion 121 and the third portion 123 of the semiconductor layer 120 is formed by, for example, photolithography (see FIG. Figure 10 (f)). Next, with the mask M1 in place, an impurity for forming a p-type semiconductor is additionally implanted into the second portion 122 of the semiconductor layer 120. Thus, the second portion 122 of the semiconductor layer 120 is formed into a p-type semiconductor. + type semiconductor.

[0151] Then, a mask M2 (see FIG. 1 ) covering the first portion 121 and the second portion 122 of the semiconductor layer 120 is formed by photolithography, for example. Figure 11 (g)). Next, with the mask M2 in place, an impurity for forming an n-type semiconductor is additionally implanted into the third portion 123 of the semiconductor layer 120. Thus, the third portion 123 of the semiconductor layer 120 is formed into an n-type semiconductor. + type semiconductor.

[0152] Then, activation annealing (eg, laser annealing) is performed. As a result, the first portion 121 of the semiconductor layer 120 becomes the first semiconductor portion 51. The second portion 122 of the semiconductor layer 120 becomes the second semiconductor portion 52. The third portion 123 of the semiconductor layer 120 becomes the third semiconductor portion 53.

[0153] Next, a conductive material (for example, a metal material) is supplied onto the semiconductor layer 50 to form a conductive layer 130 (see FIG. Figure 11 Then, unnecessary portions are removed from the conductive layer 130 by patterning, and the first wiring 75 and the second wiring 76 are formed from the conductive layer 130 (see Figure 11 (i) in FIG. Next, insulating portion 33 is provided so as to be embedded between first wiring 75 and second wiring 76. Thereafter, upper-layer wiring included in wiring portion 70 is formed. Thus, semiconductor memory device 1 is completed.

[0154] Furthermore, the method for manufacturing the semiconductor memory device 1 is not limited to the example described above. For example, the insulating layer 43 may be formed after the first chip 2 and the second chip 3 are bonded together and the semiconductor substrate 101 is removed from the second chip 3. Furthermore, part or all of the semiconductor layer 50 may be formed before the first chip 2 and the second chip 3 are bonded together. For example, part or all of the semiconductor layer 50 may be formed as part of the semiconductor substrate 101 before the insulating layer 43 is formed. In this case, for example, the semiconductor layer 50 may be formed from the remaining portion of the semiconductor substrate 101 by bonding the first chip 2 and the second chip 3 together and removing an unnecessary portion of the semiconductor substrate 101.

[0155] <8. Action Example>

[0156] Next, an operation example of the semiconductor memory device 1 will be described. Unless otherwise specified, the following control is executed by the control circuit (sequencer) 14.

[0157] <8.1 Reading Operation>

[0158] First, the read operation will be described.

[0159] Figure 12 This diagram is used to illustrate a read operation. Here, the memory cell transistor MT from which data is read is referred to as the "selected memory cell transistor MT." The word line WL corresponding to the selected memory cell transistor MT is referred to as the "selected word line WL." On the other hand, the memory cell transistor MT not from which data is read is referred to as the "unselected memory cell transistor MT." The word lines WL corresponding to the unselected memory cell transistors MT are referred to as the "unselected word lines WL." Furthermore, the bit line BL refers to the bit line BL corresponding to the selected memory cell transistor MT.

[0160] like Figure 12 As shown, at time point t10, the first wiring 75, the second wiring 76, the source side selection gate line SGS, the selection word line WL, the non-selection word line WL, the drain side selection gate line SGD and the bit line BL have a ground potential Vss (for example, 0V) through the control of the control circuit 14.

[0161] From time t11 on, the control circuit 14 maintains the voltage of the bit line BL at voltage Vbl. Voltage Vbl is higher than voltage Vss. Furthermore, from time t11 on, the control circuit 14 maintains the voltage of the second wiring 76 at voltage Vcelsrc. Voltage Vcelsrc is lower than voltage Vbl. Application of voltages Vbl and Vcelsrc continues, for example, until time t15.

[0162] The control circuit 14 applies a voltage Vsgs to the source side selection gate line SGS from time t12. The voltage Vsgs is a voltage that turns the source side selection transistor STS into an on state (conducting state). In addition, the voltage Vsgs is applied to the conductive layer 41A to form an inversion layer 50r in the semiconductor layer 50 (see Figure 13 ) voltage.

[0163] Alternatively, a voltage higher than the voltage applied to the other conductive layer 41 serving as the source-side select gate line SGS may be applied to the conductive layer 41A to form the inversion layer 50r in the semiconductor layer 50. In this embodiment, the insulating layer 43 is relatively thin, so even if a relatively low voltage is applied to the conductive layer 41A, the inversion layer 50r can be formed in the semiconductor layer 50. Therefore, the voltage Vsgs applied to the conductive layer 41A is the same as the voltage Vsgs applied to the other conductive layer 41 serving as the source-side select gate line SGS.

[0164] Furthermore, the control circuit 14 applies voltage Vsgd to the drain-side select gate line SGD from time t12. Voltage Vsgd is a voltage that turns on the drain-side select transistor STD. Furthermore, the control circuit 14 applies voltage Vpass_read to the unselected word line WL from time t12. Voltage Vpass_read is a voltage that turns on the unselected memory cell transistor MT regardless of the threshold state of the unselected memory cell transistor MT. Application of voltages Vsgs, Vsgd, and Vpass_read continues, for example, until time t15.

[0165] Between time t13 and time t14, the control circuit 14 applies voltage Vcgr to the selected word line WL. Application of voltage Vcgr maintains the selected memory cell transistor MT, which has a threshold voltage greater than voltage Vcgr, in an off state (non-conducting state). The selected memory cell transistor MT, which has a threshold voltage less than voltage Vcgr, enters an on state (conducting state). In this state, the sense amplifier module 17 determines whether current is flowing in the channel layer 62 of the memory column MH based on the voltage of the bit line BL. This allows data to be read.

[0166] Figure 13 This is a cross-sectional view for explaining the read operation of the semiconductor memory device 1. During the read operation, as described above, voltage Vsgs is applied to the conductive layer 41A, forming an inversion layer 50r in the semiconductor layer 50. Therefore, when the selected memory cell transistor MT is turned on (conductive), electrons move between the channel layer 62 of the memory pillar MH and the second wiring 76 via the inversion layer 50r and the third semiconductor portion 53. As a result, current flows between the bit line BL and the second wiring 76.

[0167] <8.2 Writing Operation>

[0168] Next, the writing operation will be described.

[0169] Figure 14 This diagram is used to illustrate a write operation. Here, the memory cell transistor MT to which data is written is referred to as the "selected memory cell transistor MT." The word line WL corresponding to the selected memory cell transistor MT is referred to as the "selected word line WL." On the other hand, the memory cell transistor MT not to which data is written is referred to as the "unselected memory cell transistor MT." The word lines WL corresponding to the unselected memory cell transistors MT are referred to as the "unselected word lines WL." Furthermore, the bit line BL refers to the bit line BL corresponding to the selected memory cell transistor MT.

[0170] like Figure 14 As shown, at time point t20, the first wiring 75, the second wiring 76, the source side selection gate line SGS, the selection word line WL, the non-selection word line WL, the drain side selection gate line SGD and the bit line BL have a ground potential Vss (for example, 0V) through the control of the control circuit 14.

[0171] The control circuit 14 applies voltage Vsgd to the drain-side selection gate line SGD from time t21. Voltage Vsgd is a voltage that turns on the drain-side selection transistor STD. Application of voltage Vsgd continues until, for example, time t25.

[0172] Starting at time t22, the control circuit 14 applies voltage Vpass to the selected word line WL and the unselected word lines WL. Vpass is a voltage high enough to turn on the memory cell transistor MT, but low enough not to cause a write operation to the memory cell transistor MT. Application of voltage Vpass to the unselected word lines WL continues until, for example, time t25.

[0173] Between time t23 and time t24, the control circuit 14 applies voltage Vpgm to the selected word line WL. Voltage Vpgm is a voltage higher than voltage Vpass. Voltage Vpgm is a voltage for writing data to the memory cell transistor MT (changing the threshold state of the memory cell transistor MT). Application of voltage Vpgm creates a large potential difference between the selected word line WL and the channel layer 62 of the memory cell transistor MT due to voltage Vpgm and voltage Vss. As a result, electrons are injected into the selected memory cell transistor MT, allowing data to be written.

[0174] <8.3 Erase Operation>

[0175] Next, the erasing operation will be described.

[0176] Figure 15 is a diagram used to illustrate the erasing action. Figure 15 As shown, at time t30, the first wiring 75 and word line WL have a ground potential Vss (e.g., 0 V) ​​under the control of the control circuit 14. Furthermore, the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL are in a floating state under the control of the control circuit 14.

[0177] Between time t31 and time t32, the control circuit 14 applies voltage Vera to the first wiring 75. Voltage Vera is greater than voltage Vss. As a result, the voltages of the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL rise to a voltage close to voltage Vera (≈Vera). This generates holes in the second semiconductor portion 52, which are then supplied to the memory cell transistor MT. This removes electrons from the memory cell transistor MT, erasing the data.

[0178] From time t32, the control circuit 14 discharges the first wiring 75. As a result, the voltages of the second wiring 76, the source select gate line SGS, the drain select gate line SGD, and the bit line BL, which had previously risen to a voltage close to voltage Vera (≈Vera), drop to voltage Vss.

[0179] Figure 16This is a cross-sectional view for explaining the erase operation of the semiconductor memory device 1. During the erase operation, as described above, holes are generated in the second semiconductor portion 52, and the generated holes are supplied to the memory cell transistor MT via the first semiconductor portion 51 and the channel layer 62 of the memory pillar MH. As a result, electrons are removed from the memory cell transistor MT, and data is erased.

[0180] 9. Advantages

[0181] As a comparative example, a configuration can be envisioned in which holes are supplied by GIDL (Gate Induced Drain Leakage) current during an erase operation. In this configuration, impurities such as phosphorus need to be injected into the deeper portion of the channel layer 62 of the memory pillar MH and amorphized by annealing. However, it is not easy to inject impurities into the deeper portion of the channel layer 62 and amorphize by annealing. Therefore, during an erase operation, the GIDL current may be insufficient. As a result, the electrical characteristics of the semiconductor memory device may sometimes degrade.

[0182] On the other hand, the semiconductor memory device 1 of this embodiment includes a semiconductor layer 50, a first wiring 56, and a second wiring 57. The semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53. The first semiconductor portion 51 includes a first portion 51a arranged along the first end 40e1 of the laminate 40, and a second portion 51b covering the first end portion MHe1 of the memory column MH. The second semiconductor portion 52 is connected to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51. The first wiring 56 is electrically connected to the second semiconductor portion 52. The second wiring 57 is electrically connected to the third semiconductor portion 53. The first semiconductor portion 51 and the second semiconductor portion 52 contain impurities that form a p-type semiconductor. The third semiconductor portion 53 contains impurities that form an n-type semiconductor. The conductive layer 41A includes a portion 41Aa that overlaps with the first semiconductor portion 51 when viewed from the Z direction.

[0183] According to this configuration, during the erasing operation, holes are generated in the second semiconductor portion 52, which is a p-type semiconductor, and supplied to the memory cell transistor MT. Therefore, insufficient erasing operation can be suppressed, and the electrical characteristics of the semiconductor memory device 1 can be improved.

[0184] In this embodiment, the third semiconductor portion 53 is provided on the first end 40e1 of the laminate 40. This configuration facilitates electron movement between the inversion layer 50r formed near the first end 40e1 of the laminate 40 in the first semiconductor portion 51 and the third semiconductor portion 53. This further improves the electrical characteristics of the semiconductor memory device 1.

[0185] In this embodiment, the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51. This configuration facilitates the generation of holes through the second semiconductor portion 52 and their supply to the memory cell transistor MT. For example, if the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51, the contact resistance between the second semiconductor portion 52 and the wiring 75 decreases, making it easier for holes to be generated. Consequently, the electrical characteristics of the semiconductor memory device 1 can be further improved. Furthermore, considering only operation, the impurity concentration of the second semiconductor portion 52 does not necessarily have to be higher than the impurity concentration of the first semiconductor portion 51.

[0186] In this embodiment, the distance in the Z direction between the conductive layer 41A and the first semiconductor portion 51 is smaller than the thickness T1 of the insulating layer 42A in the Z direction. This configuration facilitates the formation of the inversion layer 50r in the semiconductor layer 50 even when a low voltage is applied to the conductive layer 41A. This further improves the electrical characteristics of the semiconductor memory device 1.

[0187] In this embodiment, the shortest distance between the conductive layer 41A and the first semiconductor portion 51 is less than or equal to half the thickness T1 of the insulating layer 42A in the Z direction. This configuration facilitates the formation of the inversion layer 50r in the semiconductor layer 50 even when a low voltage is applied to the conductive layer 41A. This further improves the electrical characteristics of the semiconductor memory device 1.

[0188] In this embodiment, the composition of insulating layer 43 is different from that of insulating layer 42. This configuration makes it easier to ensure the required withstand voltage even when insulating layer 43 is thin, thereby further improving the electrical characteristics of semiconductor memory device 1.

[0189] In this embodiment, the second semiconductor portion 52 overlaps at least a portion of the partition portion ST1 when viewed from the Z direction. With this configuration, the second semiconductor portion 52 is formed in an area where no memory pillars MH are located. This facilitates achieving at least one of the advantages of miniaturization and high-density packaging of the semiconductor memory device 1.

[0190] In this embodiment, the third semiconductor portion 53 overlaps at least a portion of the dividing portion ST2 when viewed from the Z direction. With this configuration, the third semiconductor portion 53 is formed in an area where the memory pillars MH are not located. This facilitates achieving at least one of the advantages of miniaturization and high-density packaging of the semiconductor memory device 1.

[0191] (Second embodiment)

[0192] Next, the second embodiment will be described. The second embodiment differs from the first embodiment in that the dividing portion ST does not have a conductive portion STb. Except for the configuration described below, the other configurations are the same as those of the first embodiment.

[0193] Figure 17 This is a cross-sectional view showing a portion of a semiconductor memory device 1A according to a second embodiment. In this embodiment, the dividing portion ST does not include the conductive portion STb. The dividing portion ST is formed entirely of the insulating portion STa. The end of the dividing portion ST on the +Z direction side coincides with the first end 40e1 of the laminate 40. Therefore, the second semiconductor portion 52 does not include the second portion 52b. The second semiconductor portion 52 is layered along the X and Y directions. Similarly, the third semiconductor portion 53 does not include the second portion 53b. The third semiconductor portion 53 is layered along the X and Y directions.

[0194] According to this configuration, a migration path for electrons and holes can be formed through the semiconductor layer 50 , thereby improving the electrical characteristics of the semiconductor memory device 1A.

[0195] (Third embodiment)

[0196] Next, the third embodiment will be described. The third embodiment differs from the second embodiment in that the second semiconductor portion 52 is disposed in a region that does not overlap with the partitioning portion ST in the Z direction. Except for the configuration described below, the other configurations are the same as those of the second embodiment.

[0197] Figure 18 This is a cross-sectional view showing a portion of a semiconductor memory device 1B according to the second embodiment. In this embodiment, the semiconductor layer 50 includes a first semiconductor portion 51 and a second semiconductor portion 52 (see FIG. Figure 19 ), semiconductor portion 53A and semiconductor portion 53B.

[0198] In this embodiment, the semiconductor portion 53A and the semiconductor portion 53B each contain an impurity that forms an n-type semiconductor (an impurity that serves as a donor), and have an n-type (for example, n + The semiconductor portion 53A and the semiconductor portion 53B are both examples of the "third semiconductor portion". When viewed from the Z direction, the semiconductor portion 53A overlaps with at least a portion of the dividing portion ST1. The semiconductor portion 53A extends linearly in the X direction along the dividing portion ST1 (see FIG. Figure 19 ). When the semiconductor portion 53B is viewed from the Z direction, it overlaps with at least a portion of the dividing portion ST2. The semiconductor portion 53B extends linearly in the X direction along the dividing portion ST2 (see Figure 19 ).

[0199] In this embodiment, the wiring portion 70 includes a wiring 76A and a wiring 76B. The wiring 76A is arranged away from the semiconductor portion 53A in the Z direction. For example, the wiring 76A is arranged at a height that does not affect the bit line BL. A through hole 202A is provided between the wiring 76A and the semiconductor portion 53A. The through hole 202A is a conductive portion extending in the Z direction. In this embodiment, the through hole 202A extends in the Z direction and extends linearly in the X direction along the disconnection portion ST1. The wiring 76A is electrically connected to the semiconductor portion 53A via the through hole 202A. In addition, in addition to the above example, the through hole 202A may not be provided. The wiring 76A may also be provided on the semiconductor portion 53A.

[0200] Similarly, the wiring 76B is arranged away from the semiconductor portion 53B in the Z direction. For example, the wiring 76B is arranged at a height that does not affect the bit line BL. A through hole 202B is provided between the wiring 76B and the semiconductor portion 53B. The through hole 202B is a conductive portion extending in the Z direction. In this embodiment, the through hole 202B extends in the Z direction and extends linearly in the X direction along the dividing portion ST2. The wiring 76B is electrically connected to the semiconductor portion 53B via the through hole 202B. In addition, in addition to the above example, the through hole 202B may not be provided. The wiring 76B may also be provided on the semiconductor portion 53B.

[0201] Figure 19 yes Figure 18 A cross-sectional view of the structure shown along line F19-F19. In this embodiment, regarding the array area AR, the memory cell array 11 includes a first array area AR1 and a second array area AR2. The memory cell array 11 has a non-array area NAR between the first array area AR1 and the second array area AR2. The non-array area NAR is an area where no memory pillars MH are arranged. For example, the non-array area NAR is an area where no memory pillars MH exist beyond the arrangement interval of the memory pillars MH in the array area AR. The memory cell array 11 may also have multiple non-array areas NAR arranged at regular intervals.

[0202] In this embodiment, the semiconductor layer 50 includes a second semiconductor portion 52 in at least a portion of the non-array region NAR. The wiring 75 is arranged away from the second semiconductor portion 52 in the Z direction. For example, the wiring 75 is arranged at a height that does not interfere with the bit line BL. A through-hole 201 is provided between the wiring 75 and the second semiconductor portion 52. The through-hole 201 is a conductive portion extending in the Z direction. The wiring 75 is electrically connected to the semiconductor portion 53A via the through-hole 201. In addition to the above example, the through-hole 201 may not be provided. The wiring 75 may also be provided on the second semiconductor portion 52.

[0203] This configuration allows for electron and hole migration paths to be formed through the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1B. Furthermore, in the third embodiment, the third semiconductor portion (semiconductor portions 53A and 53B) is disposed in the array region AR, and the second semiconductor portion 52 is disposed in the non-array region NAR. Alternatively, the second semiconductor portion 52 may be disposed in the array region AR, and the third semiconductor portion 53 may be disposed in the non-array region NAR. Furthermore, both the second semiconductor portion 52 and the third semiconductor portion 53 may be disposed in the non-array region NAR.

[0204] (Fourth embodiment)

[0205] Next, the fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that the second semiconductor portion 52 is disposed in the wiring region FR. Except for the configuration described below, the other configurations are the same as those of the third embodiment.

[0206] Figure 20 This is a plan view showing a portion of a semiconductor memory device 1C according to Embodiment 4. In this embodiment, a semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52, a semiconductor portion 53A, and a semiconductor portion 53B.

[0207] At least a portion of the semiconductor portion 53A is disposed in the array region AR. At least a portion of the semiconductor portion 53B is disposed in the array region AR. Meanwhile, the second semiconductor portion 52 is disposed in the wiring region FR. The wiring region FR is an area where no memory pillars MH are disposed. For example, the second semiconductor portion 52 is disposed between two supports HR.

[0208] With this configuration, a path for electron and hole migration can be formed through the semiconductor layer 50, thereby improving the electrical characteristics of the semiconductor memory device 1C. Furthermore, in this embodiment, the second semiconductor portion 52 is formed in an area where the memory pillars MH are not disposed. This facilitates achieving at least one of the advantages of miniaturization and high-density packaging of the semiconductor memory device 1C. Furthermore, in addition to the examples described above, the third semiconductor portion 53 may be disposed in the wiring region FR, or both the second semiconductor portion 52 and the third semiconductor portion 53 may be disposed in the wiring region FR.

[0209] (Fifth embodiment)

[0210] Next, the fifth embodiment will be described. The fifth embodiment differs from the third embodiment in that the second semiconductor portion 52 overlaps the dummy memory pillar DMH in the Z direction. Except for the configuration described below, the other configurations are the same as those of the third embodiment.

[0211] Figure 21This is a top view of a portion of a semiconductor memory device 1D according to a fifth embodiment. In this embodiment, the second semiconductor portion 52 is arranged in an area overlapping with a dummy memory pillar DMH in the array area AR. The dummy memory pillar DMH is a memory pillar MH that is not used to store valid data. For example, the dummy memory pillar DMH is arranged at a position overlapping with the partition portion SHE in the Z direction and is not connected to the bit line BL.

[0212] According to this structure, a movement path of electrons and holes can be formed through the semiconductor layer 50, and the electrical characteristics of the semiconductor memory device 1D can be improved. In addition, in this embodiment, the second semiconductor portion 52 is formed using the area where the storage column MH is not configured. As a result, it is easy to achieve at least one of the advantages of miniaturization and high-density installation of the semiconductor memory device 1D. In addition, in addition to the above example, the third semiconductor portion 53 can be configured in the area overlapping with the dummy storage column DMH, or both the second semiconductor portion 52 and the third semiconductor portion 53 can be configured in the area overlapping with the dummy storage column DMH.

[0213] Although several embodiments have been described above, the embodiments are not limited to the examples described above. For example, a plurality of embodiments may be combined to realize the present invention.

[0214] According to at least one embodiment described above, a semiconductor memory device includes a first chip and a second chip. The second chip includes a laminate, a columnar body, a semiconductor layer, a first wiring, and a second wiring. The laminate includes multiple gate electrode layers and multiple insulating layers. The multiple gate electrode layers and the multiple insulating layers are alternately stacked one after another in a first direction. The laminate has a first end, which is the opposite side of the first chip, that is, the end on the first side in the first direction. The columnar body extends through the laminate in the first direction. The columnar body has a first end that reaches at least the first end of the laminate. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion arranged along the first end of the laminate and a second portion covering the first end of the columnar body. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first and second semiconductor portions contain impurities that form a p-type semiconductor. The third semiconductor portion contains impurities that form an n-type semiconductor. Among the plurality of gate electrode layers, the first gate electrode layer closest to the first end of the laminate includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. This configuration can improve the electrical characteristics of the semiconductor memory device.

[0215] While several embodiments of the present invention have been described, these embodiments are provided for illustrative purposes only and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention, and are also intended to be included within the scope of the invention set forth in the claims and their equivalents.

[0216] [Explanation of Symbols]

[0217] 1,1A,1B,1C,1D semiconductor memory devices

[0218] 2. Chip 1

[0219] 3. Second chip

[0220] 21 semiconductor substrate

[0221] 40 laminated body

[0222] 40e1 First end of the laminate

[0223] 41 conductive layer (gate electrode layer)

[0224] 41A conductive layer (first gate electrode layer)

[0225] 41B conductive layer (second gate electrode layer)

[0226] 41C conductive layer (third gate electrode layer)

[0227] 42 Insulation layer

[0228] 42A 1st insulation layer

[0229] 43 Insulation layer (second insulation layer)

[0230] 50 semiconductor layer

[0231] 51 1st Semiconductor Department

[0232] 51a Part 1

[0233] 51b Part 2

[0234] 52 Semiconductor Division 2

[0235] 53 3rd Semiconductor Division

[0236] 56 1st wiring

[0237] 57 2nd wiring

[0238] MH storage column (column)

[0239] MHe1 The first end of the storage column.

Claims

1. A semiconductor memory device comprising: chip 1; and A second chip is bonded to the first chip; and The second chip has: A laminate comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately laminated one by one in a first direction, and the laminate has a first end, which is an opposite side of the first chip, that is, an end on a first side in the first direction; a columnar body extending in the first direction through the laminate and having a first end portion reaching at least the first end of the laminate; a semiconductor layer comprising a first semiconductor portion, a second semiconductor portion connected to the first semiconductor portion, and a third semiconductor portion connected to the first semiconductor portion, wherein the first semiconductor portion includes a first portion arranged along the first end of the laminate and a second portion covering the first end of the columnar body; a first wiring electrically connected to the second semiconductor portion; and a second wiring electrically connected to the third semiconductor portion; The first semiconductor portion and the second semiconductor portion contain impurities that form a p-type semiconductor. The third semiconductor portion contains impurities that form an n-type semiconductor. A first gate electrode layer closest to the first end of the laminate among the plurality of gate electrode layers includes a portion overlapping with the first semiconductor portion when viewed from the first direction.

2. The semiconductor memory device according to claim 1, wherein The third semiconductor portion is provided on the first end of the laminate.

3. The semiconductor memory device according to claim 1 or 2, wherein The second semiconductor portion contains more impurities forming a p-type semiconductor than the first semiconductor portion.

4. The semiconductor memory device according to claim 1 or 2, wherein The plurality of gate electrode layers include a second gate electrode layer and a third gate electrode layer adjacent to the second gate electrode layer in the first direction. The plurality of insulating layers include a first insulating layer disposed between the second gate electrode layer and the third gate electrode layer, and A distance between the first gate electrode layer and the first semiconductor portion in the first direction is smaller than a thickness of the first insulating layer in the first direction.

5. The semiconductor memory device according to claim 4, wherein A distance between the first gate electrode layer and the first semiconductor portion in the first direction is less than or equal to half of a thickness of the first insulating layer in the first direction. The semiconductor memory device according to claim 4 , wherein The laminate includes a second insulating layer disposed between the first gate electrode layer and the first end of the laminate, and the second insulating layer has a composition different from that of the first insulating layer.

7. The semiconductor memory device according to claim 6, wherein The first insulating layer is an insulating layer formed by supplying a raw material gas. The second insulating layer is a thermal oxide film.

8. The semiconductor memory device according to claim 1 or 2, further comprising a first dividing portion extending through the laminate in the first direction and dividing the plurality of gate electrode layers along a second direction intersecting the first direction; and The second semiconductor portion overlaps with at least a portion of the first dividing portion when viewed from the first direction.

9. The semiconductor memory device according to claim 1 or 2, further comprising a second dividing portion extending through the laminate in the first direction and dividing the plurality of gate electrode layers along a second direction intersecting the first direction; and The third semiconductor portion overlaps with at least a portion of the second dividing portion when viewed from the first direction.

10. A method for manufacturing a semiconductor memory device, The first layer and the second layer are alternately stacked in a first direction on the semiconductor substrate to form a stacked body; forming a columnar body extending in the first direction through the laminate and including a first end portion reaching the semiconductor substrate; removing at least a portion of the semiconductor substrate; supplying an impurity forming a p-type semiconductor to a portion of the semiconductor layer covering the first end portion of the columnar body; and Impurities that form an n-type semiconductor are supplied to another portion of the semiconductor layer.

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