Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body and a contact. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers includes a first gate electrode layer and a second gate electrode layer. The first gate electrode layer is connected with the contact in a second direction. The second gate electrode layer is separated from the contact in the second direction. The first gate electrode layer includes a first conductive portion and a first insulating film. The second gate electrode layer includes a second conductive portion and a second insulating film. The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is equal to or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] A NAND flash memory in which memory cells are three-dimensionally arranged is known (for example, see Japanese Patent Application Laid-Open No. 2022-41054). Summary of the Invention

[0003] A semiconductor memory device according to one embodiment includes a stack and a contact. The stack includes multiple gate electrode layers and multiple insulating layers. The multiple gate electrode layers and the multiple insulating layers are alternately stacked one on top of the other in a first direction. The contact extends within the stack along the first direction. The contact is conductive. The multiple gate electrode layers include a first gate electrode layer and a second gate electrode layer. The contact penetrates the first gate electrode layer in the first direction. The first gate electrode layer is connected to the contact in a second direction intersecting the first direction. The second gate electrode layer is positioned adjacent to the first gate electrode layer in the first direction among the multiple gate electrode layers. The contact penetrates the second gate electrode layer in the first direction. The second gate electrode layer is separated from the contact in the second direction. The multiple insulating layers include a first insulating layer positioned between the first gate electrode layer and the second gate electrode layer in the first direction. The first gate electrode layer includes a first conductive portion and a first insulating film provided between the first conductive portion and the first insulating layer and including a portion extending in the second direction. The second gate electrode layer includes a second conductive portion and a second insulating film disposed between the second conductive portion and the first insulating layer and including a portion extending along the second direction. The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is equal to or less than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 This is a block diagram showing a portion of a semiconductor memory device according to an embodiment.

[0005] Figure 2 This is a diagram showing an equivalent circuit of a portion of a memory cell array according to an embodiment.

[0006] Figure 3 This is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment.

[0007] Figure 4 It will Figure 3: is a cross-sectional view showing an enlarged area surrounded by line F4 of the memory cell array shown in .

[0008] Figure 5 It is along Figure 4 A cross-sectional view of the memory cell array taken along line F5-F5 shown in FIG.

[0009] Figure 6 It will Figure 4 : is a cross-sectional view showing an enlarged area surrounded by line F6 of the memory cell array shown in FIG.

[0010] Figure 7 It is along Figure 3 sectional view of the memory cell array along the line F7-F7 shown in FIG.

[0011] Figure 8 This is a cross-sectional view of the memory cell array according to the embodiment as viewed from above.

[0012] Figure 9 It is along Figure 8 A cross-sectional view of the memory cell array taken along line F9-F9 shown in FIG.

[0013] Figure 10 It will Figure 9 FIG. 1 is a cross-sectional view showing an enlarged area of ​​the memory cell array surrounded by line F10 shown in FIG.

[0014] Figure 11 It is along Figure 10 A cross-sectional view of the memory cell array taken along line F11-F11 shown in FIG.

[0015] Figure 12 It is along Figure 10 sectional view of the memory cell array taken along line F12-F12 shown in FIG.

[0016] Figure 13A It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0017] Figure 13B It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0018] Figure 13C It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0019] Figure 13D It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0020] Figure 13E It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0021] Figure 13F It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0022] Figure 13G It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0023] Figure 13H It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0024] Figure 14A It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0025] Figure 14B It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0026] Figure 14C It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0027] Figure 14D It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0028] Figure 14E It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the embodiment.

[0029] Figure 15 is a cross-sectional view showing a portion of the semiconductor memory device according to the first embodiment.

[0030] Figure 16A 1 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0031] Figure 16B 1 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0032] Figure 16C 1 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0033] Figure 16D 1 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment.

[0034] Figure 17 is a cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.

[0035] Figure 18A It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0036] Figure 18B It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0037] Figure 18C It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0038] Figure 18D It is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, semiconductor memory devices and methods for manufacturing semiconductor memory devices according to embodiments will be described with reference to the accompanying drawings. In the following description, components having identical or similar functions are denoted by the same reference numerals. Furthermore, duplicate descriptions of these components may be omitted. In the following description, reference numerals with a suffix of a distinguishing number or letter may have the suffix of the suffix omitted if they are indistinguishable.

[0040] In this application, the terms are defined as follows. "Parallel", "orthogonal" or "same" may include "approximately parallel", "approximately orthogonal" or "approximately the same" respectively. "Connected" is not limited to mechanical connection, but may include electrical connection. That is, "connected" is not limited to the situation where multiple elements are directly connected, but may include the situation where multiple elements are connected via other elements in the middle. "Overlap" is not limited to the situation where multiple elements are connected to each other, but may include the situation where multiple elements are separated (the situation where the projected images of multiple elements overlap each other when viewed from a certain direction).

[0041] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the word line WL described later extends (see Figure 3 ). The -X direction is the opposite direction of the +X direction. In the case where the +X direction and the -X direction are not distinguished, it is simply referred to as the X direction. The +Y direction is a direction that intersects (for example, is perpendicular to) the X direction. The +Y direction is the direction in which the bit line BL extends (refer to Figure 7 ). The -Y direction is the opposite direction of the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (for example, is perpendicular to) the X direction and the Y direction. The +Z direction is a direction from the bit line BL described later toward the stacked body 40 (see Figure 3). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, it is simply referred to as the Z direction. In this application, the +Z direction side is sometimes referred to as "upper" and the -Z direction side is referred to as "lower". In addition, in this application, the position in the Z direction is sometimes referred to as "height". However, these expressions are for convenience of explanation and do not specify the direction of gravity. The Z direction is an example of a "first direction". The X direction is equivalent to an example of a "second direction". In addition, in the drawings described below, illustrations of structures that are not related to the description are sometimes omitted.

[0042] (Implementation Method)

[0043] <1. Configuration of Semiconductor Memory Device>

[0044] Figure 1 This is a block diagram showing a portion of a semiconductor memory device 1 according to an embodiment. Semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device. Semiconductor memory device 1 is a NAND flash memory. Semiconductor memory device 1 can be connected to an external host device. Semiconductor memory device 1 is used as storage space for the host device. Semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0045] The memory cell array 11 includes multiple blocks BLK0 to BLK(k-1) (k is an integer greater than or equal to 1). Each block BLK is a collection of memory cell transistors. A block BLK serves as a unit for erasing data. The memory cell array 11 includes multiple bit lines and multiple word lines. Each memory cell transistor is associated with one bit line and one word line.

[0046] The command register 12 holds a command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds address information ADD received by the semiconductor memory device 1 from the host device. Address information ADD is used to select blocks BLK, word lines, and bit lines. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes data write, read, or erase operations based on the command CMD stored in the command register 12.

[0047] The driver module 15 includes a voltage generation circuit that generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage on each bit line and transmits the determination result as read data DAT to the host device.

[0048] <2. Electrical Structure of Memory Cell Array>

[0049] Figure 2 1 is a diagram showing an equivalent circuit of a portion of the memory cell array 11 . Figure 2 1 block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (eg, five strings STR0 to STR4).

[0050] Each string STR includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer greater than or equal to 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0051] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is stored in the charge storage unit according to the voltage applied to the control gate via the word line WL. This allows each memory cell transistor MT to store data in a nonvolatile manner.

[0052] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.

[0053] The drain of source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of source-side select transistor STS is connected to source line SL. The control gate of source-side select transistor STS is connected to source-side select gate line SGS. When a predetermined voltage is applied to source-side select gate line SGS, source-side select transistor STS connects NAND string NS to source line SL.

[0054] In the same block BLK, the control gates of memory cell transistors MT0-MTn ​​are commonly connected to corresponding word lines WL0-WLn, respectively. In the same string STR, the control gates of drain-side select transistors STD are commonly connected to corresponding drain-side select gate lines SGD. The control gates of source-side select transistors STS are commonly connected to source-side select gate lines SGS. In the memory cell array 11, bit lines BL are shared by NAND strings NS assigned the same column address within multiple strings STR.

[0055] <3. Structure of Semiconductor Memory Device>

[0056] Next, the structure of semiconductor memory device 1 will be described.

[0057] Figure 3 1 is a cross-sectional view showing a portion of a semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0058] <3.1 First Chip>

[0059] The first chip 2 is a circuit chip including a peripheral circuit and includes, for example, a semiconductor substrate 21 , a peripheral circuit 22 , an insulating portion 23 , and a plurality of pads 24 .

[0060] The semiconductor substrate 21 is, for example, a substrate serving as a base for the first chip 2. At least a portion of the semiconductor substrate 21 has a plate shape extending along the X and Y directions. The semiconductor substrate 21 is formed of, for example, a semiconductor material such as silicon.

[0061] Peripheral circuit 22 is a circuit for enabling the memory cell array 11 to function. Peripheral circuit 22 includes multiple transistors 22a and multiple wirings 22b. Peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. An insulating portion 23 covers peripheral circuit 22. Multiple bonding pads 24 are provided on the surface of insulating portion 23. Each bonding pad 24 is electrically connected to peripheral circuit 22.

[0062] <3.2 Second Chip>

[0063] The second chip 3 is an array chip including the memory cell array 11. The second chip 3 includes, for example, the memory cell array 11, an insulating portion 31, and a plurality of pads 32. Here, the insulating portion 31 and the plurality of pads 32 are described, and the memory cell array 11 will be described later.

[0064] The insulating portion 31 covers the memory cell array 11 from the -Z direction. A plurality of solder pads 32 are provided on the surface of the insulating portion 31. Each solder pad 32 is electrically connected to a wiring (e.g., wiring 71 or wiring 72) included in a wiring portion 70 of the memory cell array 11, which will be described later. In this embodiment, the plurality of solder pads 24 of the first chip 2 and the plurality of solder pads 32 of the second chip 3 are bonded together so as to face each other. Thus, the first chip 2 and the second chip 3 are integrated.

[0065] <4. Memory Cell Array>

[0066] Next, the memory cell array 11 will be described.

[0067] like Figure 3 As shown, the memory cell array 11 includes an array region AR and a junction region FR. Multiple memory pillars MH, described later, are provided in the array region AR. The array region AR is a region capable of storing data. Multiple contacts CC, described later, are provided in the junction region FR. The array region AR is where multiple gate electrode layers 41, described later, connect to the wiring portion 70. The junction regions FR are provided, for example, on both sides of the array region AR in the X direction.

[0068] like Figure 3 As shown, the memory cell array 11 includes, for example, a stacked body 40, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the conductive layer, a wiring portion 70, a support body HR, and a plurality of partition portions 80 (see FIG. Figure 7 ).

[0069] <4.1 Laminated Body>

[0070] First, the laminated body 40 will be described.

[0071] Figure 4 It will Figure 3 FIG4 is an enlarged cross-sectional view of the memory cell array 11 shown in FIG4 . The stacked body 40 includes, for example, a plurality of gate electrode layers 41, a plurality of insulating layers 42, an insulating layer 43, and an insulating portion 44. The plurality of gate electrode layers 41 and the plurality of insulating layers 42 are alternately stacked one on top of the other in the Z direction.

[0072] The gate electrode layers 41 extend along the X direction and the Y direction. Each gate electrode layer 41 includes a conductive material (eg, tungsten, molybdenum, or silicon doped with impurities).

[0073] One or more (e.g., multiple) of the multiple gate electrode layers 41 located at the bottom function as drain-side select gate lines SGD. Drain-side select gate lines SGD are provided in common with multiple memory pillars MH arranged in the X or Y direction. The intersection of drain-side select gate lines SGD and the channel layer 52 (described later) of each memory pillar MH functions as the drain-side select transistor STD described above.

[0074] One or more (e.g., multiple) of the multiple gate electrode layers 41 located at the top function as source-side select gate lines SGS. Source-side select gate lines SGS are provided in common with multiple memory pillars MH arranged in the X or Y direction. The intersection of source-side select gate lines SGS and the channel layer 52 of each memory pillar MH functions as the source-side select transistor STS.

[0075] The gate electrode layer 41 provided between the gate electrode layer 41 functioning as the drain side selection gate line SGD and the gate electrode layer 41 functioning as the source side selection gate line SGS among the plurality of gate electrode layers 41 is the remaining gate electrode layer 41. The remaining gate electrode layer 41 may also be referred to as a clamping gate electrode layer. At least a portion of such a remaining gate electrode layer 41 functions as a word line WL. The word line WL is provided in common with respect to the plurality of storage columns MH arranged in the X direction and the Y direction. In this embodiment, the intersection portion of the word line WL and the channel layer 52 of each storage column MH functions as a memory cell transistor MT. Details regarding the memory cell transistor MT will be described later.

[0076] The insulating layer 42 is provided between two gate electrode layers 41 adjacent to each other in the Z direction. The insulating layer 42 is an interlayer insulating film that insulates the two gate electrode layers 41. The insulating layer 42 extends along the X and Y directions. The insulating layer 42 is formed, for example, of a film containing silicon and oxygen (e.g., a silicon oxide film).

[0077] The insulating layer 43 is provided above the topmost gate electrode layer 41. In other words, the insulating layer 43 can also be referred to as an insulating layer provided above the topmost gate electrode layer. The insulating layer 43 is provided between the topmost gate electrode layer 41 and the source line SL. The insulating layer 43 extends along the X and Y directions. For example, the insulating layer 43 is formed of a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is greater than the thickness of the insulating layer 42 in the Z direction.

[0078] The insulating portion 44 is provided in the bonding region FR, which will be described later. The insulating portion 44 covers the ends of the multiple gate electrode layers 41 and the multiple insulating layers 42, which are provided in a stepped manner, from the -Z direction side. The insulating portion 44 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4).

[0079] <4.2 Source Line>

[0080] The source line SL is provided on the insulating layer 43. The source line SL is formed of, for example, a conductive layer or a semiconductor layer extending in the X and Y directions. The source line SL is formed of a conductive material such as tungsten or molybdenum, or a semiconductor material containing silicon.

[0081] <4.3 Storage Column>

[0082] A plurality of memory pillars MH are arranged in the X direction and the Y direction (see Figure 3 Each memory pillar MH extends in the Z direction within the stacked body 40. The plurality of memory pillars MH penetrate the stacked body 40. The memory pillars MH are an example of a "columnar body."

[0083] Figure 5 It is along Figure 4 The memory pillar MH includes, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating portion 53, a cavity (air gap) 54, and a cap 55 (see FIG. Figure 4 ).

[0084] The memory film 51 is provided on the outer peripheral side of the channel layer 52. The memory film 51 is located between the plurality of gate electrode layers 41 and the channel layer 52. The memory film 51 includes, for example, a blocking insulating film 61, a charge trapping film 62, and a tunnel insulating film 63.

[0085] The blocking insulating film 61 is arranged between the multiple gate electrode layers 41 and the charge capture film 62. The blocking insulating film 61 is an insulating film that suppresses the reverse tunnel effect. The reverse tunnel effect is a phenomenon in which charges return from the word line WL to the charge capture film 62. The blocking insulating film 61 is formed in a ring shape. The blocking insulating film 61 extends in the Z direction. The blocking insulating film 61 is, for example, set to extend over the entire length of the storage column MH in the Z direction except for the end MHe1 on the +Z direction side of the storage column MH described later. The blocking insulating film 61 is, for example, a stacked structural film formed by stacking multiple insulating films such as a film containing silicon and oxygen or a film containing metal and oxygen. An example of a film containing metal and oxygen is an aluminum oxide film. The blocking insulating film 61 may also contain a high dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0086] The charge capture film 62 is located between the blocking insulating film 61 and the tunnel insulating film 63. The charge capture film 62 is formed in a ring shape. The charge capture film 62 extends in the Z direction. The charge capture film 62 is provided, for example, in a manner that extends over the entire length of the storage column MH in the Z direction except for the end MHe1 on the +Z direction side of the storage column MH. The charge capture film 62 is a functional film having a plurality of crystal defects (capture energy levels) and capable of capturing charges in the crystal defects. The charge capture film 62 is formed, for example, of a film containing silicon and nitrogen. The portion of the charge capture film 62 adjacent to each word line WL is an example of a "charge storage portion" that can store information by accumulating charges.

[0087] The tunnel insulating film 63 is provided between the channel layer 52 and the charge capture film 62. The tunnel insulating film 63 has, for example, an annular shape provided along the outer peripheral surface of the channel layer 52. The tunnel insulating film 63 extends in the Z direction along the channel layer 52. The tunnel insulating film 63 is provided, for example, to extend over the entire length of the storage column MH in the Z direction except for the end MHe1 on the +Z direction side of the storage column MH. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge capture film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen or a film containing silicon, oxygen, and nitrogen.

[0088] The channel layer 52 is provided inside the memory film 51. The channel layer 52 is formed in a ring shape. The channel layer 52 extends in the Z direction. For example, the channel layer 52 is provided so as to extend over the entire length of the memory pillar MH in the Z direction. The channel layer 52 is formed of a semiconductor material such as polycrystalline silicon. The channel layer 52 may also be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 forms a channel, electrically connecting the bit line BL and the source line SL.

[0089] Thus, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the edge of the word line WL adjacent to the memory pillar MH, the blocking insulating film 61, the charge trapping film 62, the tunnel insulating film 63, and the channel layer 52. Furthermore, the memory film 51 may include a floating gate type charge storage portion (floating gate electrode) as the charge storage portion instead of the charge trapping film 62. The floating gate type charge storage portion is formed, for example, of polysilicon containing impurities.

[0090] The insulating portion 53 is provided inside the channel layer 52. The insulating portion 53 fills at least a portion of the interior of the channel layer 52. The insulating portion 53 is formed of a film containing silicon and oxygen. In this embodiment, the insulating portion 53 is formed in a ring shape along the inner peripheral surface of the channel layer 52 in such a manner that a cavity (air gap) 54 is formed inside. In addition, the cavity 54 may not exist. The insulating portion 53 extends in the Z direction. For example, the insulating portion 53 is provided to extend over the entire length of the storage column MH in the Z direction except for the end portion on the -Z direction side of the storage column MH (refer to Figure 4 ).

[0091] Figure 6 It will Figure 4 : is an enlarged cross-sectional view of a region surrounded by line F6 of the memory cell array 11 shown in FIG. In this embodiment, each gate electrode layer 41 includes, for example, a conductive portion 45 , a barrier metal film 46 , and an insulating film 47 .

[0092] The conductive portion 45 forms the main portion of the gate electrode layer 41. The conductive portion 45 extends in a layered manner in the X and Y directions. The conductive portion 45 includes the above-mentioned conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0093] The barrier metal film 46 is a film used to suppress the diffusion of the conductive material included in the conductive portion 45. The barrier metal film 46 may be made of, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The barrier metal film 46 is provided along the surface of the conductive portion 45. The barrier metal film 46 is provided between the conductive portion 45 and the insulating film 47. The barrier metal film 46 includes a first film portion 46a, a second film portion 46b, and a third film portion 46c.

[0094] The first film portion 46a is provided between the surface of the conductive portion 45 on the -Z direction side and the insulating layer 42 located on the -Z direction side of the conductive portion 45. The first film portion 46a extends along the surface of the conductive portion 45 on the -Z direction side in the X and Y directions.

[0095] The second film portion 46b is provided between the surface of the conductive portion 45 on the +Z direction side and the insulating layer 42 located on the +Z direction side of the conductive portion 45. The second film portion 46b extends in the X and Y directions along the surface of the conductive portion 45 on the +Z direction side.

[0096] The third film portion 46c is provided along an edge of the conductive portion 45 facing the memory pillar MH. The third film portion 46c is located between the conductive portion 45 and the memory pillar MH. The third film portion 46c extends along the Z direction.

[0097] The insulating film 47 improves the voltage resistance of the gate electrode layer 41. The insulating film 47 is formed, for example, of a film containing aluminum and oxygen (e.g., an aluminum oxide film). The insulating film 47 is provided along the surface of the barrier metal film 46. The insulating film 47 is provided along the surface of the gate electrode layer 41. The insulating film 47 includes a first film portion 47a, a second film portion 47b, and a third film portion 47c.

[0098] The first film portion 47a is provided between the first film portion 46a of the barrier metal film 46 and the insulating layer 42 located on the -Z direction side of the conductive portion 45. In other words, the first film portion 47a is provided between the surface on the -Z direction side of the conductive portion 45 and the insulating layer 42 located on the -Z direction side of the conductive portion 45. The first film portion 47a extends in the X and Y directions along the surface of the first film portion 46a of the barrier metal film 46.

[0099] The second film portion 47b is provided between the second film portion 46b of the barrier metal film 46 and the insulating layer 42 located on the +Z direction side of the conductive portion 45. In other words, the second film portion 47b is provided between the surface on the +Z direction side of the conductive portion 45 and the insulating layer 42 located on the +Z direction side of the conductive portion 45. The second film portion 47b extends in the X and Y directions along the surface of the second film portion 46b of the barrier metal film 46.

[0100] The third film portion 47c is provided between the third film portion 46c of the barrier metal film 46 and the charge trapping film 62 of the memory pillar MH. That is, the third film portion 47c is provided between the edge of the conductive portion 45 facing the memory pillar MH and the charge trapping film 62 of the memory pillar MH. The third film portion 47c extends in the Z direction along the surface of the third film portion 46c of the barrier metal film 46.

[0101] In this embodiment, the blocking insulating film 61 includes a first portion 61a and a second portion 61b. The first portion 61a is formed in a ring shape along the outer periphery of the charge trapping film 62. The first portion 61a extends in the Z direction. For example, the first portion 61a is provided to extend over the entire length of the memory pillar MH in the Z direction, excluding the end portion MHe1 on the +Z direction side of the memory pillar MH.

[0102] On the other hand, the second portion 61b is formed by the third film portion 47c of the insulating film 47 of the plurality of gate electrode layers 41. The second portion 61b is formed in a ring shape along the outer periphery of the first portion 61a of the blocking insulating film 61. The second portion 61b exists at a height corresponding to the arrangement of the gate electrode layer 41. In this embodiment, the blocking insulating film 61 is formed by the first portion 61a and the second portion 61b.

[0103] Then, return Figure 4, the cover portion 55 will be described. The cover portion 55 is provided below the insulating portion 53. The cover portion 55 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 55 may also be doped with impurities. The cover portion 55 is arranged on the inner peripheral side of the end portion on the -Z direction side of the memory film 51. The cover portion 55 is formed integrally with the channel layer 52. The cover portion 55, together with the lower end portion of the channel layer 52, forms the end portion on the -Z direction side of the storage column MH. The contact CH is connected to the cover portion 55 from the -Z direction side.

[0104] Next, the end MHe1 on the +Z direction side of the memory column MH is described. In this embodiment, the end MHe1 of the memory column MH protrudes from the stack 40 toward the +Z direction side. The end MHe1 of the memory column MH is connected to the source line SL. At the end MHe1 of the memory column MH, the memory film 51 does not exist, and the channel layer 52 is exposed outside the memory column MH. As a result, the channel layer 52 is connected to the source line SL.

[0105] <4.4 Bit Line>

[0106] Then, return Figure 3 Next, the bit lines BL are described. The bit lines BL are used to select one memory column MH from among the plurality of memory columns MH. The plurality of bit lines BL are arranged on the lower side (-Z direction side) relative to the stack 40. The plurality of bit lines BL are arranged in the X direction with intervals in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass under the corresponding plurality of memory columns MH.

[0107] Each bit line BL is connected to the channel layer 52 of the memory pillar MH via the contact VY and the contact CH. Thus, the combination of the word line WL and the bit line BL allows arbitrary selection of a memory cell transistor MT from a plurality of memory cell transistors MT arranged three-dimensionally.

[0108] <4.5 Contact for Gate Electrode Layer>

[0109] like Figure 3 As shown, the contact CC is an electrical connection portion that electrically connects the gate electrode layer 41 to the wiring 72 (described later) included in the wiring portion 70. A plurality of contacts CC are provided, for example, in the junction region FR of the memory cell array 11. The plurality of contacts CC extend along the Z direction within the stack 40. The plurality of contacts CC are connected to different gate electrode layers 41. The contact CC includes a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities). The contact CC is conductive. The structure of the junction region FR will be described in detail later.

[0110] <4.6 Wiring Section>

[0111] Next, the wiring portion 70 will be described. The wiring portion 70 is disposed, for example, between the laminate 40 and the semiconductor substrate 21. The wiring portion 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, and a plurality of wirings 72.

[0112] Wiring 71 is an electrical connection portion that electrically connects bit lines BL to pads 32. Multiple wirings 71 are arranged, for example, below the multiple bit lines BL. Each wiring 71 extends, for example, in the X direction or the Y direction. A via V1 is provided between wiring 71 and bit lines BL to electrically connect wiring 71 and bit lines BL.

[0113] Wiring 72 is an electrical connection portion that electrically connects the conductive layer contact CC to the pad 32. Wiring 72 is electrically connected to the gate electrode layer 41 via the conductive layer contact CC. A voltage is applied to wiring 72 to select the gate electrode layer 41 (word line WL, drain-side select gate line SGD, or source-side select gate line SGS).

[0114] <4.7 Support Body>

[0115] Next, the support body HR will be described. The support body HR is provided in the bonding region FR. The support body HR extends through the stacked body 40 in the Z direction in the bonding region FR. The support body HR is formed of, for example, an insulating material. The support body HR supports the plurality of insulating layers 42 during the replacement step described below.

[0116] <5. Partition>

[0117] Next, the partition portion 80 will be described.

[0118] Figure 7 It is along Figure 3 FIG2 is a cross-sectional view of the semiconductor memory device 1 taken along line F7-F7. In this embodiment, multiple partitions 80 are provided in the stacked body 40. The multiple partitions 80 are spaced apart in the Y direction. The multiple partitions 80 extend in the Z direction within the stacked body 40, dividing one or more gate electrode layers 41, including the bottommost layer, in the Y direction. The multiple partitions 80 include, for example, multiple partitions ST and multiple partitions SHE.

[0119] <5.1 Partition ST>

[0120] The partition portions ST are walls that divide the stack 40 in the Y direction. Multiple partition portions ST are spaced apart in the Y direction. The partition portions ST extend in the Z direction, penetrating the stack 40 and also extending in the X direction. In other words, the partition portions ST are walls arranged along both the Z and X directions. The partition portions ST divide all gate electrode layers 41 included in the stack 40 in the Y direction.

[0121] <5.2 Partition SHE>

[0122] The partition portion SHE is a partition portion having a shorter length in the Z direction than the partition portion ST. The partition portion SHE is a wall portion that partitions the lower end portion of the stack 40 in the Y direction. A plurality of partition portions SHE are arranged separately in the Y direction. In this embodiment, a plurality (e.g., four) of partition portions SHE are present between two adjacent partition portions ST in the Y direction. The partition portion SHE is provided at the lower end portion of the stack 40. The partition portion SHE extends to the middle of the stack 40 in the Z direction and also extends in the X direction. In other words, the partition portion SHE is a wall portion provided along the Z and X directions.

[0123] The partition portion SHE penetrates a portion of the gate electrode layers 41, including the bottommost layer, among the multiple gate electrode layers 41. The partition portion SHE divides this portion of the gate electrode layers 41 in the Y direction. For example, the partition portion SHE penetrates all gate electrode layers 41 that function as drain-side select gate lines SGD. On the other hand, the partition portion SHE does not reach the gate electrode layers 41 that function as word lines WL. The partition portion SHE divides only the gate electrode layers 41 that function as drain-side select gate lines SGD in the Y direction. The partition portion SHE is formed, for example, of a film containing silicon and oxygen.

[0124] <6. Joint Area>

[0125] Next, the junction region FR will be described. In the following drawings, for convenience of explanation, the structure related to six gate electrode layers 41 is extracted and illustrated.

[0126] <6.1 Structure of the Joint Area>

[0127] Figure 8 1 shows a cross-sectional view of the memory cell array 11 as viewed from above. The junction region FR is an area where no memory pillars MH are provided. The junction region FR includes a plurality of contacts CC and a plurality of support bodies HR. The contacts CC are electrical connectors that electrically connect the gate electrode layer 41 to the wiring 72 included in the wiring portion 70. The support bodies HR support the plurality of insulating layers 42 during the replacement process described later.

[0128] Figure 9 It is along Figure 8 is a cross-sectional view of the memory cell array 11 along the line F9-F9 shown in FIG. In the junction region FR, the lengths of the plurality of gate electrode layers 41 in the X direction differ from one another. For example, the lengths of the plurality of gate electrode layers 41 in the X direction are shorter on the -Z side. In other words, the lengths of the plurality of gate electrode layers 41 arranged in the Z direction gradually increase toward the -Z side.

[0129] In this embodiment, each gate electrode layer 41 has a terrace portion 101 and a non-terrace portion 102. The terrace portion 101 is a portion that does not overlap with another gate electrode layer 41 located on the -Z direction side when viewed from the Z direction. The non-terrace portion 102 is a portion that overlaps with another gate electrode layer 41 located on the -Z direction side when viewed from the Z direction.

[0130] In this embodiment, the terrace portion 101 of each gate electrode layer 41 has a protrusion 105 protruding toward the −Z direction. The thickness of the terrace portion 101 in the portion where the protrusion 105 exists is greater than the thickness of the non-terrace portion 102 in the Z direction.

[0131] In this embodiment, the plurality of contacts CC have the same length in the Z direction. Each contact CC penetrates the laminate 40 in the Z direction. When viewed in the Z direction, each contact CC extends in the Z direction through one or more (e.g., a plurality of) gate electrode layers 41 overlapping with the contact CC.

[0132] For example, when viewed in the Z direction, each contact CC is arranged at a position overlapping with the protruding portion 105 of the gate electrode layer 41 to which the contact CC is connected. Each contact CC penetrates the protruding portion 105 of the gate electrode layer 41 to which the contact CC is connected in the Z direction. Each contact CC penetrates the non-terrace portion 102 of the gate electrode layer 41 that is not the connection target of the contact CC (the non-connection target gate electrode layer 41) in the Z direction.

[0133] Each contact CC is separated from the non-connected gate electrode layer 41. An insulating portion 111 is provided between each contact CC and the non-connected gate electrode layer 41. The insulating portion 111 is arranged at the same height as the non-connected gate electrode layer 41. The insulating portion 111 is formed in a ring shape along the outer periphery of the contact CC. Each contact CC is electrically insulated from the non-connected gate electrode layer 41 by the insulating portion 111.

[0134] Figure 10 It will Figure 9 1 is a cross-sectional view showing an enlarged area of ​​the memory cell array 11 surrounded by line F10. Figure 10 and Figure 9The diagram is shown in an upside-down orientation. The multiple gate electrode layers 41 include, for example, a first gate electrode layer 41A, a second gate electrode layer 41B, and a third gate electrode layer 41C. The second gate electrode layer 41B is located adjacent to the first gate electrode layer 41A on the +Z direction side of the multiple gate electrode layers 41. The length of the second gate electrode layer 41B in the X direction is greater than the length of the first gate electrode layer 41A in the X direction. The third gate electrode layer 41C is located adjacent to the second gate electrode layer 41B on the +Z direction side of the multiple gate electrode layers 41. The length of the third gate electrode layer 41C in the X direction is greater than the length of the second gate electrode layer 41B in the X direction.

[0135] The plurality of insulating layers 42 include a first insulating layer 42A and a second insulating layer 42B. The first insulating layer 42A is disposed between the first gate electrode layer 41A and the second gate electrode layer 41B in the Z direction. The second insulating layer 42B is disposed between the second gate electrode layer 41B and the third gate electrode layer 41C in the Z direction.

[0136] The multiple contacts CC include a first contact CCA and a second contact CCB. The first contact CCA is electrically connected to the first gate electrode layer 41A. The first contact CCA is positioned so as to overlap with the protrusion 105 of the first gate electrode layer 41A when viewed from the Z direction. The first contact CCA penetrates the protrusion 105 of the first gate electrode layer 41A in the Z direction. The first contact CCA penetrates the non-terrace portion 102 of the second gate electrode layer 41B and the non-terrace portion 102 of the third gate electrode layer 41C in the Z direction.

[0137] The second contact CCB is located farther from the array area AR than the first contact CCA. The second contact CCB is a contact CC electrically connected to the second gate electrode layer 41B. The second contact CCB is located so as to overlap with the protrusion 105 of the second gate electrode layer 41B when viewed in the Z direction. The second contact CCB penetrates the protrusion 105 of the second gate electrode layer 41B in the Z direction. The second contact CCB penetrates the non-terrace portion 102 of the third gate electrode layer 41C in the Z direction.

[0138] Each contact CC has, for example, a columnar portion 121 and a bulge 122. The columnar portion 121 is formed in, for example, a cylindrical shape. The columnar portion 121 extends in the Z direction over the entire length of the contact CC in the Z direction. The bulge 122 is a portion that protrudes from the circumference of the columnar portion 121 toward the radially outer side of the contact CC. The bulge 122 is provided in a portion of the contact CC in the Z direction. The bulge 122 of each contact CC is provided at the same height as the gate electrode layer 41, which is the connection destination of the contact CC. The bulge 122 of each contact CC protrudes from the columnar portion 121 toward the gate electrode layer 41, which is the connection destination of the contact CC. For example, the bulge 122 of the first contact CCA is provided at the same height as the first gate electrode layer 41A, and protrudes from the columnar portion 121 toward the first gate electrode layer 41A. The bulge 122 of the second contact CCB is provided at the same height as the second gate electrode layer 41B, protruding from the columnar portion 121 toward the second gate electrode layer 41B. The columnar portion 121 is an example of a "third conductive portion." The columnar portion 121 can also be referred to as a "first portion." The bulge 122 is an example of a "fourth conductive portion." The bulge 122 can also be referred to as a "second portion."

[0139] In addition, each contact CC includes a conductive portion 125 and a barrier metal film 126 .

[0140] The conductive portion 125 is a portion that forms a main portion of the contact CC. The conductive portion 125 extends in the Z direction. The conductive portion 125 includes a conductive material (eg, tungsten, molybdenum, or silicon doped with impurities).

[0141] The barrier metal film 126 is a film used to suppress the diffusion of the conductive material contained in the conductive portion 125. The barrier metal film 126 may be made of, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The barrier metal film 126 is provided along the surface of the conductive portion 125. For example, the barrier metal film 126 includes a first film portion 126a and a second film portion 126b. The first film portion 126a is provided on the surface of the columnar portion 121 of the contact CC. The second film portion 126b is provided on the surface of the bulged portion 122 of the contact CC.

[0142] exist Figure 10 , a virtual center line CL1 passing through the center of the first contact CCA in the X direction is shown. Hereinafter, for convenience of explanation, the center of the first contact CCA in the X direction may be referred to as "center CL1." Center CL1 refers to a point located on center line CL1.

[0143] <6.2 First Gate Electrode Layer>

[0144] Next, the first gate electrode layer 41A will be described. The first contact CCA penetrates the first gate electrode layer 41A in the Z direction. The first gate electrode layer 41A is adjacent to the bulged portion 122 of the first contact CCA in the X and Y directions, and is in contact with the bulged portion 122 of the first contact CCA in the X and Y directions. The first gate electrode layer 41A is connected to the bulged portion 122 of the first contact CCA in the X and Y directions.

[0145] As described above, the first gate electrode layer 41A includes the conductive portion 45, the barrier metal film 46, and the insulating film 47. The conductive portion 45 of the first gate electrode layer 41A is an example of a "first conductive portion." The barrier metal film 46 of the first gate electrode layer 41A is an example of a "first barrier metal film." The insulating film 47 of the first gate electrode layer 41A is an example of a "first insulating film."

[0146] The insulating film 47 of the first gate electrode layer 41A includes the aforementioned first film portion 47a and second film portion 47b. The first film portion 47a of the first gate electrode layer 41A is provided along the surface of the first gate electrode layer 41A on the -Z direction side. A portion of the first film portion 47a of the first gate electrode layer 41A extends in the X direction along the surface of the protrusion 105 of the first gate electrode layer 41A. The second film portion 47b of the first gate electrode layer 41A is provided along the surface of the first gate electrode layer 41A on the +Z direction side. The second film portion 47b of the first gate electrode layer 41A is provided between the conductive portion 45 of the first gate electrode layer 41A and the first insulating layer 42A. The second film portion 47b extends in the X direction.

[0147] The shortest distance in the X direction between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is a distance L1. The distance L1 is defined by, for example, the following shortest distance L1A or shortest distance L1B.

[0148] The shortest distance L1A is the shortest distance in the X direction between the first film portion 47a of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction. The shortest distance L1B is the shortest distance in the X direction between the second film portion 47b of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction.

[0149] The barrier metal film 46 of the first gate electrode layer 41A includes, in addition to the first to third film portions 46a, 46c, described above, a fourth film portion 46d. The fourth film portion 46d is disposed between the conductive portion 45 of the first gate electrode layer 41A and the bulged portion 122 of the first contact CCA. The fourth film portion 46d extends in the Z direction. The fourth film portion 46d is in contact with the second film portion 126b of the barrier metal film 126 of the first contact CCA in the X direction. The first film portion 46a or the second film portion 46b is an example of the "first portion of the first barrier metal film." The fourth film portion 46d is an example of the "second portion of the first barrier metal film."

[0150] In this embodiment, a boundary B is formed between the first contact CCA and the first gate electrode layer 41A. The boundary B is formed by at least one of the fourth film portion 46d of the barrier metal film 46 of the first gate electrode layer 41A and the second film portion 126b of the barrier metal film 126 of the first contact CCA.

[0151] <6.2 Second Gate Electrode Layer>

[0152] Next, the second gate electrode layer 41B is described. The contact CCA and the contact CCB penetrate the second gate electrode layer 41B in the Z direction. The second gate electrode layer 41B is adjacent to the bulged portion 122 of the second contact CCB in the X and Y directions, and is in contact with the bulged portion 122 of the second contact CCB in the X and Y directions. The second gate electrode layer 41B is connected to the bulged portion 122 of the second contact CCB in the X and Y directions. On the other hand, the second gate electrode layer 41B is separated from the first contact CCA in the X and Y directions. An insulating portion 111 is provided between the second gate electrode layer 41B and the first contact CCA.

[0153] As described above, the second gate electrode layer 41B includes the conductive portion 45, the barrier metal film 46, and the insulating film 47. The conductive portion 45 of the second gate electrode layer 41B is an example of a "second conductive portion." The insulating film 47 of the second gate electrode layer 41B is an example of a "second insulating film." The insulating film 47 of the second gate electrode layer 41B includes, in addition to the first to third film portions 47a to 47c described above, a fourth film portion 47d.

[0154] The first film portion 47a of the second gate electrode layer 41B is provided along the surface of the second gate electrode layer 41B on the -Z direction side. The first film portion 47a of the second gate electrode layer 41B is provided between the conductive portion 45 of the second gate electrode layer 41B and the first insulating layer 42A. The first film portion 47a extends in the X direction.

[0155] The second film portion 47b of the second gate electrode layer 41B is provided along the surface of the second gate electrode layer 41B on the +Z direction side. The second film portion 47b of the second gate electrode layer 41B is provided between the conductive portion 45 of the second gate electrode layer 41B and the second insulating layer 42B. The second film portion 47b extends in the X direction.

[0156] The fourth film portion 47d of the second gate electrode layer 41B extends in the Z direction, extending over the edge of the first film portion 47a of the second gate electrode layer 41B and the edge of the second film portion 47b of the second gate electrode layer 41B. The fourth film portion 47d of the second gate electrode layer 41B is positioned adjacent to the insulating portion 111 in the X direction. The fourth film portion 47d is in contact with the insulating portion 111 in the X direction. The fourth film portion 47d of the second gate electrode layer 41B extends in the Z direction along the insulating portion 111.

[0157] The shortest distance between the insulating film 47 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction is a distance L2. The distance L2 is defined by, for example, the following shortest distance L2A, the shortest distance L2B, or the shortest distance L2C.

[0158] The shortest distance L2A is the shortest distance in the X direction between the first film portion 47a of the second gate electrode layer 41B and the X-direction center CL1 of the first contact CCA. The shortest distance L2B is the shortest distance in the X direction between the second film portion 47b of the second gate electrode layer 41B and the X-direction center CL1 of the first contact CCA. The shortest distance L2C is the shortest distance in the X direction between the fourth film portion 47d of the second gate electrode layer 41B and the X-direction center CL1 of the first contact CCA.

[0159] <6.3 Third Gate Electrode Layer>

[0160] Next, the third gate electrode layer 41C will be described. The first contact CCA and the second contact CCB penetrate the third gate electrode layer 41C in the Z direction. For example, the third gate electrode layer 41C is separated from the first contact CCA in the X and Y directions. An insulating portion 111 is provided between the third gate electrode layer 41C and the first contact CCA.

[0161] As described above, the third gate electrode layer 41C includes the conductive portion 45, the barrier metal film 46, and the insulating film 47. The insulating film 47 of the third gate electrode layer 41C includes the fourth film portion 47d in addition to the first film portion 47a and the second film portion 47b.

[0162] The first film portion 47a of the third gate electrode layer 41C is provided along the surface of the third gate electrode layer 41C on the -Z direction side. The first film portion 47a of the third gate electrode layer 41C is provided between the conductive portion 45 of the third gate electrode layer 41C and the second insulating layer 42B. The first film portion 47a extends in the X direction.

[0163] The second film portion 47b of the third gate electrode layer 41C is provided along the surface of the third gate electrode layer 41C on the +Z direction side. The second film portion 47b of the third gate electrode layer 41C is provided between the conductive portion 45 of the third gate electrode layer 41C and the other insulating layer 42 (the insulating layer 42 located on the +Z direction side of the third gate electrode layer 41C). The second film portion 47b extends in the X direction.

[0164] The fourth film portion 47d of the third gate electrode layer 41C extends in the Z direction, extending over the edge of the first film portion 47a of the third gate electrode layer 41C and the edge of the second film portion 47b of the third gate electrode layer 41C. The fourth film portion 47d of the third gate electrode layer 41C is positioned adjacent to the insulating portion 111 in the X direction. The fourth film portion 47d is in contact with the insulating portion 111 in the X direction. The fourth film portion 47d of the third gate electrode layer 41C extends in the Z direction along the insulating portion 111.

[0165] The shortest distance between the insulating film 47 of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction is distance L3. Distance L3 is, for example, the same as distance L2 described above. Distance L3 is defined, for example, by the following shortest distance L3A, shortest distance L3B, or shortest distance L3C.

[0166] The shortest distance L3A is the shortest distance between the first film portion 47a of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction. The shortest distance L3B is the shortest distance between the second film portion 47b of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction. The shortest distance L3C is the shortest distance between the fourth film portion 47d of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction.

[0167] <6.4 Positional Relationship of Insulating Films>

[0168] In this embodiment, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is smaller than the shortest distance in the X direction (distance L2) between the insulating film 47 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction. In this embodiment, in at least a portion of the area overlapping with the protrusion 105 of the first gate electrode layer 41A when viewed from the Z direction, the distance L1 is smaller than the distance L2. For example, the distance L1 is more than 20 nm smaller than the distance L2. However, the embodiment is not limited to the above-mentioned examples of numerical values. In addition, several examples of dimensional relationships are shown below. However, the embodiment is not limited to the example of a structure having the dimensional relationship described below. The embodiment may also have a structure having a dimensional relationship different from the dimensional relationship described below.

[0169] From another perspective, the shortest distance in the X direction (distance L11) between the insulating film 47 of the first gate electrode layer 41A and the columnar portion 121 of the first contact CCA is smaller than the shortest distance in the X direction (distance L12) between the insulating film 47 of the second gate electrode layer 41B and the columnar portion 121 of the first contact CCA. For example, the distance L11 is less than or equal to half the distance L12.

[0170] For example, the distance L11 is smaller than the thickness (eg, maximum thickness) T1 of the terrace portion 101 of the first gate electrode layer 41A in the Z direction. Meanwhile, the distance L12 is larger than the thickness (eg, maximum thickness) T1 of the terrace portion 101 of the first gate electrode layer 41A in the Z direction.

[0171] For example, the distance L11 is smaller than the thickness (eg, maximum thickness) T2 of the non-terrace portion 102 of the second gate electrode layer 41B in the Z direction. On the other hand, the distance L12 is larger than the thickness (eg, maximum thickness) T2 of the non-terrace portion 102 of the second gate electrode layer 41B in the Z direction.

[0172] For example, the distance L11 is smaller than the thickness (eg, maximum thickness) T3 of the first insulating layer 42A in the Z direction. On the other hand, the distance L12 is larger than the thickness (eg, maximum thickness) T3 of the first insulating layer 42A in the Z direction.

[0173] According to another point of view, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact member CCA in the X direction is smaller than the shortest distance in the X direction (distance L4) between the conductive portion 45 of the second gate electrode layer 41B and the center CL1 of the first contact member CCA in the X direction.

[0174] From another perspective, the shortest distance in the X direction (distance L5) between the fourth film portion 46d of the barrier metal film 46 of the first gate electrode layer 41A and the X-direction center CL1 of the first contact CCA is smaller than the shortest distance in the X direction (distance L2) between the insulating film 47 of the second gate electrode layer 41B and the X-direction center CL1 of the first contact CCA. In this embodiment, the shortest distance in the X direction between the boundary B (the boundary between the first contact CCA and the first gate electrode layer 41A) and the X-direction center CL1 of the first contact CCA corresponds to the distance L5.

[0175] According to another point of view, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact member CCA in the X direction is smaller than the shortest distance in the X direction (distance L3) between the insulating film 47 of the third gate electrode layer 41C and the center CL1 of the first contact member CCA in the X direction.

[0176] Furthermore, the embodiments are not limited to the above examples. For example, the distance L1 may be the same as the distance L2 or the distance L3. The distance L11 may be the same as the distance L12. The distance L1 may be the same as the distance L4. The distance L5 may be the same as the distance L2.

[0177] Figure 11 It is along Figure 10 11-11 line cross-sectional view of the memory cell array shown in FIG. In this embodiment, the first film portion 47a and the second film portion 47b (at the bottom of the first gate electrode layer 41A) are Figure 12 Only the edge of the second film portion 47b is shown in the figure. The fourth film portion 46d of the second gate electrode layer 41B and the fourth film portion 46d of the third gate electrode layer 41C are formed in a ring shape with the center line CL1 as the center.

[0178] Figure 12 It is along Figure 10 sectional view of the memory cell array along the line F12-F12 shown in FIG. In this embodiment, the cross section along the Y direction ( Figure 11 The cross section shown in ) also has the same cross section as that along the X direction ( Figure 10 Therefore, the description of the cross section along the Y direction can be replaced by "Y direction" in the above description of the cross section along the X direction.

[0179] <7. Method for Manufacturing a Semiconductor Memory Device>

[0180] Next, a method for manufacturing semiconductor memory device 1 will be described.

[0181] 13A to 13H and Figures 14A to 14E 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor memory device 1. 13A to 13H The configuration diagram shown on the left side of FIG. 1 shows a cross section of both the contact CC and the support body HR, taken along a cutting line through the joint region FR.

[0182] First, refer to 13A to 13H , explaining the overall process.

[0183] like Figure 13A As shown, insulating layer 43 is formed on semiconductor substrate 201. Next, insulating layer 202 and insulating layer 42 are alternately stacked on insulating layer 43. Insulating layer 202 is, for example, a sacrificial layer that is replaced with gate electrode layer 41 in the replacement step described later. Insulating layer 202 is, for example, formed of a film containing nitrogen and silicon (e.g., a silicon nitride film). Thus, stacked body 40A is formed. Insulating layer 202 is an example of a "first insulating layer." Insulating layer 42 is an example of a "second insulating layer."

[0184] Next, a resist (not shown) is applied to the laminate 40A, and resist thinning and vertical processing by anisotropic etching are alternately repeated to remove unnecessary portions of the insulating layer 202 and the insulating layer 42. This creates a stepped region SR in the laminate 40A. In the stepped region SR, the lengths of the plurality of insulating layers 202 in the X direction differ from one another.

[0185] Then, if Figure 13B As shown, in the stepped region SR, an insulating layer 203 is provided on each end portion 202a of the plurality of insulating layers 202. The insulating layer 203 is formed of, for example, the same insulating material as the insulating layer 202. The insulating layer 203 is formed of, for example, a film containing nitrogen and silicon (eg, a silicon nitride film).

[0186] Then, if Figure 13C As shown, unnecessary portions of the insulating layer 203 are removed by etching. Thus, multiple insulating layers 203a are formed from the insulating layer 203. The insulating layer 203a is formed on the end portion 202a of the insulating layer 202. The insulating layer 203a is a sacrificial layer that will be replaced with the protrusion 105 of the gate electrode layer 41 in the replacement step described later. The insulating layer 203a is an example of a "third insulating layer." Next, the insulating portion 44 is formed using TEOS so as to fill the end portion 202a of the insulating layer 202 and the insulating layer 203a in the step region SR. Thus, the stacked body 40B is formed.

[0187] Then, if Figure 13DAs shown, multiple holes h1 for forming contacts CC are formed in the laminate 40B. The holes h1 penetrate the laminate 40B in the Z direction. Then, semiconductor material (e.g., amorphous silicon) is supplied into the holes h1. As a result, a semiconductor portion 211 is formed inside the holes h1. The semiconductor portion 211 is a sacrificial portion that is replaced with the contacts CC in the process described later. Similarly, multiple holes h2 are formed in the laminate 40B for forming the support body HR. The holes h2 penetrate the laminate 40B in the Z direction. Then, insulating material is supplied into the holes h2. As a result, the support body HR is formed inside the holes h2.

[0188] Next, if Figure 13E As shown, the semiconductor portion 211 is removed from the inside of the hole h1 by etching. Then, by etching using the hole h1, the edge of the insulating layer 202 and the edge of the insulating layer 203a adjacent to the hole h1 are removed. As a result, a first space S1 and a second space S2 connected to the hole h1 are provided inside the laminate 40B. In the first space S1, the edge of the insulating layer 203a and the edge of the insulating layer 202 in contact with the insulating layer 203a are removed. As a result, the first space S1 is formed in the area where the edge of the insulating layer 203a and the edge of the insulating layer 202 in contact with the insulating layer 203a existed. This area is an example of the first area. On the other hand, the edge of the insulating layer 202 not in contact with the insulating layer 203a is removed from the second space S2. As a result, the second space S2 is formed in the area where the edge of the insulating layer 202 existed. This area is an example of the second area. The width of the first space S1 in the Z direction is larger than the width of the second space S2 in the Z direction.

[0189] Then, if Figure 13F As shown, an insulating material is supplied to the interior of hole h1. This forms an insulating portion 221 that fills the second space S2 and extends along the inner surface of hole h1. Insulating portion 221 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). At this point, the Z-direction width of first space S1 is greater than the Z-direction width of second space S2. Therefore, the interior of first space S1 is not completely filled with insulating portion 221.

[0190] Then, if Figure 13G As shown, etching through hole h1 removes unnecessary portions of insulating portion 221. Consequently, insulating portion 111 is formed from insulating portion 221 in the portion corresponding to second space S2. Insulating portion 111 fills second space S2. Insulating portion 111 is an example of a "first insulating portion." Meanwhile, insulating portion 221 present in first space S1 is removed, re-forming first space S1.

[0191] Then, if Figure 13HAs shown, a replacement step is performed to replace the insulating layer 202 and the insulating layer 203a with the gate electrode layer 41. For example, a groove (not shown) is etched through the stacked body 40B in the Z direction (e.g., a groove forming the partition portion ST), thereby removing the insulating layer 202 and the insulating layer 203a. This forms a third space S3 in the stacked body 40B corresponding to the insulating layer 202 and the insulating layer 203a.

[0192] Then, first, an insulating material for forming an insulating film 47 is supplied to the third space S3 to form the insulating film 47. Next, a metal material for forming a barrier metal film 46 is supplied to the third space S3 to form the barrier metal film 46 (at Figure 13H (not shown). Next, a conductive material for forming the conductive portion 45 is supplied to the third space S3 to form the conductive portion 45. As a result, the insulating layer 202 and the insulating layer 203a are replaced with the gate electrode layer 41. Next, a conductive material is supplied into the hole h1 to form the contact CC.

[0193] Next, the semiconductor substrate 201 is removed to form the second chip 3 (see Figure 3 ). Then, the separately prepared first chip 2 and second chip 3 are bonded together to form the semiconductor memory device 1.

[0194] Next, refer to Figures 14A to 14E , the detailed process of the manufacturing method is explained. 14A to 14E It will Figure 13G : This is a cross-sectional view showing an enlarged view of the region surrounded by line F14 of the structure shown in FIG.

[0195] Figure 14A is with Figure 13G . Specifically, etching through hole h1 removes unnecessary portions of insulating portion 221. This forms insulating portion 111, which fills second space S2. Insulating portion 111 is an example of a "first insulating portion." Meanwhile, insulating portion 221 present in first space S1 is removed, re-forming first space S1.

[0196] Then, if Figure 14BAs shown, an insulating material is supplied to the first space S1 to form an insulating portion 301 continuous with the insulating layer 202 or the insulating layer 203a. Thus, at least a portion of the first space S1 is backfilled with the insulating portion 301. The insulating portion 301 is formed, for example, of the same material as the insulating layer 202 or the insulating layer 203a. The insulating portion 301 is formed, for example, of a film containing nitrogen and silicon (for example, a silicon nitride film). The insulating portion 301 can also be formed, for example, by selective growth with the insulating layer 202 and the insulating layer 203a as a substrate. Alternatively, the insulating portion 301 can also be formed, for example, by depositing an insulating material in the first space S1 and then etching to remove unnecessary portions. In addition, the insulating portion 301 can also be formed by a method different from the above example. The insulating portion 301 is an example of a "second insulating portion".

[0197] Then, if Figure 14C As shown, the replacement process is performed while the hole h1 is filled with the semiconductor portion 212. For example, the plurality of insulating layers 202, the plurality of insulating layers 203a, and the insulating portion 301 are removed to form a third space S3 within the stacked body 40B. The gate electrode layer 41 is then formed within the third space S3. As a result, the first gate electrode layer 41A extends beyond the insulating layers 202 and 203a to the region where the insulating portion 301 is provided.

[0198] Next, if Figure 14D As shown, the semiconductor portion 212 is removed by etching through the hole h1. Then, the edge portion 47e of the insulating film 47 exposed in the first space S1 in the first gate electrode layer 41A is removed by etching through the hole h1 (see FIG. 1 ). Figure 14C ). As a result, the barrier metal film 46 or the conductive portion 45 is exposed in the first space S1.

[0199] Next, if Figure 14E As shown, a metal material forming a barrier metal film 126 of the contact CC is supplied to the hole h1 to form the barrier metal film 126. Next, a conductive material forming a conductive portion 125 of the contact CC is supplied to the hole h1 to form the conductive portion 125. Thus, the contact CC is formed inside the hole h1.

[0200] <8. Advantages>

[0201] As a comparative example, consider a semiconductor memory device manufactured by a process without providing the insulating portion 301. In the configuration of this comparative example, Figure 14DIn the process of removing a portion of the insulating film 47 of the first gate electrode layer 41A, there may be only a region of the insulating film 47 of the first gate electrode layer 41A that is farther from the contact CC than the insulating film 47 of the second gate electrode layer 41B. In this case, a portion of the conductive portion 45 of the first gate electrode layer 41A or a portion of the barrier metal film 46 is not covered by the insulating film 47 in the +Z direction or the -Z direction. As a result, the withstand voltage between the first gate electrode layer 41A and the second gate electrode layer 41B may be reduced, thereby degrading the electrical characteristics of the semiconductor memory device.

[0202] On the other hand, in this embodiment, the semiconductor memory device 1 includes a stacked structure 40 and a contact CCA. The stacked structure 40 includes multiple gate electrode layers 41 and multiple insulating layers 42. The multiple gate electrode layers 41 include a first gate electrode layer 41A and a second gate electrode layer 41B. The contact CCA penetrates the first gate electrode layer 41A in the Z direction. The first gate electrode layer 41A is connected to the contact CCA in the X direction. The second gate electrode layer 41B is arranged adjacent to the first gate electrode layer 41A in the Z direction among the multiple gate electrode layers 41. The contact CCA penetrates the second gate electrode layer 41B in the Z direction. The second gate electrode layer 41B is spaced apart from the contact CCA in the X direction. The first gate electrode layer 41A includes a conductive portion 45 and an insulating film 47 provided between the conductive portion 45 and the first insulating layer 42A and including a portion extending in the X direction. The second gate electrode layer 41B includes a conductive portion 45 and an insulating film 47 provided between the conductive portion 45 and the first insulating layer 42A and including a portion extending in the X direction. The shortest distance in the X direction (distance L1) between the center CL1 in the X direction of the contact CCA and the insulating film 47 of the first gate electrode layer 41A is the same as or smaller than the shortest distance in the X direction (distance L2) between the center CL1 in the X direction of the contact CCA and the insulating film 47 of the second gate electrode layer 41B.

[0203] With this configuration, the first gate electrode layer 41A extends toward the inside of the contact CC, extending as much as or beyond the second gate electrode layer 41B. This increases the amount of conductive portion 45 covered by the insulating film 47 of the first gate electrode layer 41A. This improves the withstand voltage between the first gate electrode layer 41A and the second gate electrode layer 41B, thereby enhancing the electrical characteristics of the semiconductor memory device 1.

[0204] <9. Examples>

[0205] <9.1 First Embodiment>

[0206] Next, a first example related to the above-described embodiment will be described.

[0207] Figure 15 This is a cross-sectional view showing a portion of the semiconductor memory device 1 according to the first embodiment. In the first embodiment, the conductive portion 45 of the first gate electrode layer 41A has a first edge 401 that faces the first contact CCA in the X and Y directions. The first edge 401 has a first end 401e1 on the -Z direction side and a second end 401e2 on the +Z direction side. The first end 401e1 has an arcuate curved portion 411 that is inclined toward the -Z direction and protrudes outward from the conductive portion 45. Meanwhile, the second end 401e2 has an arcuate curved portion 412 that is inclined toward the +Z direction and protrudes outward from the conductive portion 45.

[0208] 16A to 16D 1 is a cross-sectional view for explaining the method of manufacturing the semiconductor memory device 1 according to the first embodiment. 16A to 16D The process and Figures 14B to 14E The process described in the above is corresponding. Figure 16A As shown, in this embodiment, the insulating portion 301 is formed, for example, by selective growth based on the insulating layer 202 and the insulating layer 203 a .

[0209] In this case, the insulating portion 301 has a first edge 501 that faces the first space S1 in the X and Y directions. The first edge 501 has a first end 501e1 on the -Z direction side and a second end 501e2 on the +Z direction side. The first end 501e1 has an arcuate curved portion 511 that is inclined toward the -Z direction and protrudes outward from the insulating portion 301. Meanwhile, the second end 501e2 has an arcuate curved portion 512 that is inclined toward the +Z direction and protrudes outward from the insulating portion 301.

[0210] In this embodiment, the insulating portion 301 having the bent portions 511 and 512 is replaced by a portion of the first gate electrode layer 41A through a replacement process. Therefore, the first gate electrode layer 41A has rounded corners in the areas corresponding to the bent portions 511 and 512 of the insulating portion 301.

[0211] <9.2 Second embodiment>

[0212] Next, a second example related to the above-mentioned embodiment will be described.

[0213] Figure 17 This is a cross-sectional view showing a portion of a semiconductor memory device 1 according to a second embodiment. In the second embodiment, the conductive portion 45 of the first gate electrode layer 41A has a first edge 401 that faces the first contact CCA in the X and Y directions. The first edge 401 has a recessed portion 431 at its center in the Z direction that is recessed away from the first contact CCA.

[0214] 18A to 18D It is a cross-sectional view for explaining the method of manufacturing the semiconductor memory device 1 according to the second embodiment. 18A to 18D The process and Figures 14B to 14E The process described in the above is corresponding. Figure 18A As shown, in this embodiment, the insulating portion 301 is formed by depositing an insulating material in the first space S1 and then etching to remove unnecessary portions.

[0215] In this case, the insulating portion 301 has a first edge 501 facing the first space S1 in the X and Y directions. The first edge 501 has a recess 531 in the center portion in the Z direction that is recessed in a direction away from the first space S1.

[0216] In this embodiment, the insulating portion 301 having the recess 531 is replaced by a portion of the first gate electrode layer 41A in a replacement process. Therefore, the first gate electrode layer 41A has the recess 431 in a region corresponding to the recess 531 of the insulating portion 301 .

[0217] As mentioned above, although one embodiment and a plurality of examples were described, the embodiment and examples are not limited to the above examples.

[0218] According to at least one embodiment described above, a semiconductor memory device includes a stack and a contact. The stack includes multiple gate electrode layers and multiple insulating layers. The multiple gate electrode layers include a first gate electrode layer and a second gate electrode layer. The first gate electrode layer is connected to the contact in a second direction. The second gate electrode layer is separated from the contact in the second direction. The multiple insulating layers include a first insulating layer arranged between the first gate electrode layer and the second gate electrode layer in the first direction. The first gate electrode layer includes a first conductive portion and a first insulating film provided between the first conductive portion and the first insulating layer and including a portion extending in the second direction. The second gate electrode layer includes a second conductive portion and a second insulating film provided between the second conductive portion and the first insulating layer and including a portion extending in the second direction. The shortest distance between the first insulating film and the contact in the second direction is the same as or smaller than the shortest distance between the second insulating film and the contact in the second direction. With this configuration, the electrical characteristics of the semiconductor memory device can be improved.

[0219] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0220] Description of Reference Numerals

[0221] 1…Semiconductor storage device

[0222] 40…Laminated body

[0223] 41…Gate electrode layer

[0224] 41A…first gate electrode layer

[0225] 41B…second gate electrode layer

[0226] 42…Insulation layer

[0227] 42A…first insulation layer

[0228] 45…conductive part

[0229] 46…Barrier metal film

[0230] 47…Insulation film

[0231] 105…protrusion

[0232] 121…columnar part

[0233] 122…bulge

[0234] 202…Insulation layer

[0235] 203…Insulation layer

[0236] 203a…Insulation layer

[0237] 411, 412…bend

[0238] 431…concave

[0239] FR…Joint area

[0240] CC…Contact

Claims

1. A semiconductor memory device comprising: A stacked body comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately stacked one on top of the other in a first direction; and a contact extending in the first direction within the laminate and having conductivity, The plurality of gate electrode layers include: a first gate electrode layer, the contact member penetrating the first gate electrode layer in the first direction, and the first gate electrode layer being connected to the contact member in a second direction intersecting the first direction; and a second gate electrode layer, arranged beside the first gate electrode layer in the first direction among the plurality of gate electrode layers, the contact member penetrating the second gate electrode layer in the first direction, and the second gate electrode layer being separated from the contact member in the second direction, The plurality of insulating layers include a first insulating layer arranged between the first gate electrode layer and the second gate electrode layer in the first direction, The first gate electrode layer includes a first conductive portion and a first insulating film provided between the first conductive portion and the first insulating layer and including a portion extending along the second direction. The second gate electrode layer includes a second conductive portion and a second insulating film provided between the second conductive portion and the first insulating layer and including a portion extending along the second direction. The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is equal to or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film.

2. The semiconductor memory device according to claim 1, The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is equal to or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second conductive portion.

3. The semiconductor memory device according to claim 1 or 2, The stacked body includes junction regions of the plurality of gate electrode layers having different lengths in the second direction. In the bonding region, the length of the first gate electrode layer in the second direction is smaller than the length of the second gate electrode layer in the second direction. The first gate electrode layer has a protrusion in the bonding region that protrudes toward a side opposite to the second gate electrode layer. The contact member passes through the protrusion in the first direction, In at least a portion of the area overlapping with the protrusion when viewed from the first direction, the shortest distance in the second direction between the center of the contact member in the second direction and the first insulating film is equal to or less than the shortest distance in the second direction between the center of the contact member in the second direction and the second insulating film.

4. The semiconductor memory device according to claim 1 or 2, The contact has a columnar portion extending in the first direction and a bulging portion bulging from the columnar portion toward the first gate electrode layer. The shortest distance between the columnar portion of the contact and the first insulating film in the second direction is equal to or shorter than the shortest distance between the columnar portion of the contact and the second insulating film in the second direction.

5. The semiconductor memory device according to claim 4, The shortest distance between the columnar portion of the contact and the first insulating film in the second direction is less than or equal to half of the shortest distance between the columnar portion of the contact and the second insulating film in the second direction.

6. The semiconductor memory device according to claim 1 or 2, The first conductive portion has a first edge facing the contact element in the second direction, An end portion of the first edge in the first direction has a bent portion that is inclined toward the first direction and protrudes toward the outside of the first conductive portion.

7. The semiconductor memory device according to claim 1 or 2, The first conductive portion has a first edge opposite to the contact member in the second direction, A central portion of the first edge in the first direction has a recessed portion that is recessed in a direction away from the contact.

8. A method for manufacturing a semiconductor memory device, The first insulating layer and the second insulating layer are alternately stacked in a first direction to form a stacked body including a plurality of first insulating layers and a plurality of second insulating layers. forming, in the laminate, stepped regions in which the lengths of the plurality of first insulating layers are different in a second direction intersecting the first direction, forming a third insulating layer on each end portion of the plurality of first insulating layers in the stepped region, forming a hole penetrating the third insulating layer, the plurality of first insulating layers, and the plurality of second insulating layers in the first direction; Etching is performed through the hole to remove an edge portion of the third insulating layer adjacent to the hole and edges of the plurality of first insulating layers adjacent to the hole, thereby forming a first space in a first region where the edge portion of the third insulating layer and the edge portion of the first insulating layer in contact with the third insulating layer existed, and forming a second space in a second region of the plurality of first insulating layers where the edge portion of the first insulating layer not in contact with the third insulating layer existed. forming a first insulating portion filling the second space, A second insulating portion continuous with the third insulating layer and the first insulating layer is formed in at least a portion of the first space. The second insulating portion, the third insulating layer, and the plurality of first insulating layers are removed to form a third space, and a plurality of gate electrode layers each including an insulating film and a conductive portion are formed in the third space.

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