Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

The present invention addresses the problem of suppressing contact between a contact point and other components. The embodiment of the invention relates to a semiconductor memory device and a semiconductor memory device manufacturing method. A semiconductor memory device according to an embodiment includes: a first stacked body formed by stacking a plurality of first conductive layers spaced apart from each other and having a first stepped portion formed by processing the plurality of first conductive layers into a stepped shape; a second stacked body disposed above the first stacked body, in which a plurality of second conductive layers are stacked apart from each other, the second stacked body having a second stepped portion formed by processing the plurality of second conductive layers into a stepped shape and continuously extending from the first stepped portion; a first insulating layer covering the first and second stepped portions; a first layer, which contains a material different from that of the first insulating layer, is interposed in the first insulating layer on the first stepped portion, and is disposed at a height position between the first and second laminated bodies; and a first contact extending downward from the first stepped portion through the first insulating layer and the first layer, and connected to any one of the plurality of first conductive layers processed in a stepped shape.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] In semiconductor memory devices, such as three-dimensional nonvolatile memories, memory cells are three-dimensionally arranged in a laminated structure composed of multiple conductive layers stacked one on top of the other. These conductive layers are processed into a stepped pattern in a portion of the laminate, with each layer connected to a contact. During contact formation, these contacts may come into contact with other components, potentially degrading the electrical characteristics of the semiconductor memory device.

[0003] [Background Art Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-034651

[0006] [Patent Document 2] Japanese Patent Application Laid-Open No. 2022-047595

[0007] [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-060838 Summary of the Invention

[0008] [Problems to be solved by the invention]

[0009] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device, which can suppress contact between a contact and other components.

[0010] [Technical means to solve the problem]

[0011] The semiconductor storage device of the embodiment comprises: a first stacked body, which is formed by stacking a plurality of first conductive layers apart from each other, and has a first step portion in which the plurality of first conductive layers are processed into a step shape; a second stacked body, which is arranged above the first stacked body, and is formed by stacking a plurality of second conductive layers apart from each other, and has a second step portion in which the plurality of second conductive layers are processed into a step shape and continuously extends from the first step portion; a first insulating layer, which covers the first and second step portions; a first layer, which includes a material different from that of the first insulating layer and is interposed in the first insulating layer above the first step portion, and is arranged at a height position between the first and second stacked bodies; and a first contact, which extends downward from above the first step portion, penetrates the first insulating layer and the first layer, and is connected to any one of the plurality of first conductive layers processed into a step shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1Aand Figure 1B A diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment.

[0013] Figures 2A to 2D It is a cross-sectional view showing an example of the structure of a semiconductor memory device according to an embodiment.

[0014] Figures 3A to 3E The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figures 4A to 4D The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Figures 5A to 5C The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Figures 6A to 6C The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Figures 7A to 7C The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Figures 8A to 8D The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0020] Figures 9A to 9C The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0021] Figures 10A to 10C The diagram is a cross-sectional view sequentially illustrating a portion of steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0022] Figures 11A to 11D It is a cross-sectional view showing an example of a method for forming a contact hole according to the embodiment and the comparative example.

[0023] Figure 12A and Figure 12B A diagram showing an example of the configuration of a semiconductor memory device according to a modification of the embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments described below. Furthermore, the components of the embodiments described below include components that can be easily conceived by those skilled in the art or components that are substantially the same.

[0025] (Configuration Example of Semiconductor Memory Device)

[0026] Figure 1A and Figure 1B 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. Figure 1A is a cross-sectional view of the semiconductor memory device 1 along the X direction, Figure 1B 1 is a schematic plan view showing the layout of semiconductor memory device 1 .

[0027] However, in Figure 1A In consideration of the ease of viewing the accompanying drawings, shadows are omitted. Figure 1A , components that do not necessarily exist on the same cross section are shown, and some upper layer wirings are omitted.

[0028] In this specification, both the X and Y directions are directions along the plane of the word line WL, and the X and Y directions are orthogonal to each other. The electrical extraction direction of the word line WL is sometimes referred to as the first direction, which is along the X direction. A direction intersecting the first direction is sometimes referred to as the second direction, which is along the Y direction. However, semiconductor memory device 1 may include manufacturing variations, so the first and second directions are not necessarily orthogonal.

[0029] like Figure 1A As shown, the semiconductor memory device 1 includes, in order from the bottom of the paper, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB provided with a peripheral circuit CBA.

[0030] A source line SL is arranged on the electrode film EL, with an insulating layer 60 interposed therebetween. Multiple plugs PG are arranged in the insulating layer 60, maintaining electrical continuity between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for externally supplying power and signals to the semiconductor memory device 1 are provided on the same layer as the electrode film EL. A select gate line SGS, multiple word lines WL, and a select gate line SGD are sequentially stacked on the source line SL to form a stacked body LM.

[0031] like Figure 1A and Figure 1B As shown, a memory region MR is arranged in the center of the multiple word lines WL in the X direction, and a step region SR is arranged at each end of the multiple word lines WL in the X direction. These memory region MR and step region SR are divided into multiple regions by multiple plate-shaped contacts LI that penetrate the multiple word lines WL and extend in the X direction.

[0032] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the step region SR is referred to as a block region BLK. As described below, the memory region MR includes a plurality of memory cells that store data nonvolatilely, and the block region BLK serves as an erase unit for these data.

[0033] Furthermore, between adjacent plate contacts LI in the Y direction, multiple isolation layers SHE are arranged, penetrating select gate line SGD and extending in the X direction. The multiple isolation layers SHE extend in the X direction across the entire memory region MR and reach a portion of the step region SR at both ends in the X direction.

[0034] In the memory region MR, multiple pillars PL are arranged, penetrating the word lines WL and select gate lines SGD and SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. Multiple memory cells are formed at the intersections of the pillars PL and the word lines WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional nonvolatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0035] In the step region SR, multiple word lines WL and select gate lines SGD and SGS are processed into a stepped shape and terminated. At this point, as the multiple word lines WL and select gate lines SGD and SGS forming the stepped portion move from the upper layer to the lower layer as they move away from the memory region MR in the X direction, the height position of the stepped portion decreases toward the source line SL.

[0036] Furthermore, the separation layer SHE extends from the memory region MR to the select gate line SGD in the step region SR, forming a stair-shaped portion. This separates the select gate line SGD into multiple regions within a single block region BLK. In other words, by extending the separation layer SHE through the portion above the multiple word lines WL, the upper portion is divided into a pattern of multiple select gate lines SGD.

[0037] Contacts CC are located on each of the terraces, which include multiple word lines WL and select gate lines SGD and SGS. Each layer of word lines WL and select gate lines SGD and SGS is connected to a contact CC. Each layer of select gate line SGD, separated by a separation layer SHE, is connected to a contact CC.

[0038] Here, in one block region BLK, a plurality of contacts CC are arranged on one side of the step region SR on both sides in the X direction. When viewed from one side in the X direction, for example, a plurality of contacts CC are arranged for every two block regions BLK.

[0039] That is to say, in Figure 1BIn the example shown in FIG. 1 , in the block area BLK at the top of the paper, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, for example, in the stepped region SR on the left side of the paper. Furthermore, in the block area BLK below this block area BLK and the block area BLK below that, multiple contacts CC are arranged in the stepped regions SR on the right side of the paper, in the stepped regions SR at both ends in the X direction. Furthermore, in the block area BLK at the bottom of the paper, multiple contacts CC are arranged in the stepped region SR on the left side of the paper.

[0040] therefore, Figure 1A The contacts CC of the step regions SR at both ends in the X direction shown belong to different block regions BLK and are not actually located in the same cross section.

[0041] The word lines WL and other components stacked in multiple layers are led out through these contacts CC. More specifically, write voltages and read voltages are applied from these contacts CC to the memory cells contained in the memory region MR in the center of the word lines WL via the word lines WL at the same height as the memory cells.

[0042] The plurality of word lines WL, the select gate lines SGD and SGS, the pillars PL, and the contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components.

[0043] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA, including transistors TR and wiring, is arranged on the surface of the semiconductor substrate SB. The various voltages applied to the memory cells via the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. Thus, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0044] The peripheral circuit CBA is covered by an insulating layer 40, which is joined to an insulating layer 50 covering a plurality of word lines WL, etc., thereby forming a semiconductor storage device 1, which includes a plurality of word lines WL and selection gate lines SGD, SGS, pillars PL, and contacts CC, etc., and the peripheral circuit CBA.

[0045] Next, use Figures 2A to 2D Next, a detailed configuration example of the semiconductor memory device 1 will be described. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0046] In more detail, Figure 2A 1 is a cross-sectional view of the memory region MR of the semiconductor memory device 1 along the Y direction. Figure 2A In FIG, the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0047] Figure 2B4 is an enlarged cross-sectional view of the pillar PL at a height position of the selection gate lines SGD and SGS. Figure 2C 4 is an enlarged cross-sectional view of the pillar PL at a height position of the word line WL.

[0048] Figure 2D FIG is a cross-sectional view of the step region SR of the semiconductor memory device 1 along the X direction. Figure 2D In FIG, the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0049] In this specification, the direction in which the terraces of the word lines WL of each stage in the step region SR face is defined as an upward direction in the semiconductor memory device 1 .

[0050] like Figure 2A As shown, the source line SL has a multilayer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are sequentially stacked on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stacked body LM.

[0051] The lower source line DSLa, the middle source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the middle source line BSL can be a conductive polysilicon layer, etc., in which impurities are diffused.

[0052] Furthermore, the source line SL connects the insulating layer 50 outside the laminate LM to the peripheral circuit CBA via the electrode film EL using a through contact (not shown) extending from the electrode film EL to the peripheral circuit CBA.

[0053] A laminated body LM is arranged on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated.

[0054] Laminated body LMa is arranged above source line SL. Below word line WL in the lowest layer of laminated body LMa, multiple select gate lines SGS0 and SGS1 are arranged sequentially from the upper layer side of laminated body LMa, with insulation layer OL interposed therebetween. Laminated body LMb is arranged above laminated body LMa. Above word line WL in the highest layer of laminated body LMb, multiple select gate lines SGD0 and SGD1 are arranged sequentially from the upper layer side of laminated body LMb, with insulation layer OL interposed therebetween.

[0055] However, the number of word lines WL and select gate lines SGD, SGS in the laminate LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0056] The upper surface of the laminated body LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with the insulating layer 51 described below, respectively constitute Figure 1A A portion of the insulating layer 50.

[0057] As described above, the laminate LM is divided by the plurality of plate-shaped contacts LI in the Y direction. That is, the plate-shaped contacts LI are arranged in the Y direction and extend in the lamination direction of the laminate LM and along the X direction.

[0058] Thus, the plate contact LI extends continuously from one end to the other end of the laminate LM in the X direction. In addition, the plate contact LI penetrates the laminate LM and the upper source line DSLb and reaches the middle source line BSL in the memory region MR.

[0059] The plate-shaped contact LI has a tapered shape with its width in the Y direction decreasing from the upper end toward the lower end, or a curved shape with its width in the Y direction being the largest at a predetermined position between the upper and lower ends.

[0060] The plate-shaped contact LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, and the conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer.

[0061] The insulating layer 54 covers the sidewalls of the plate-shaped contact LI adjacent in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the middle source line BSL. In addition, the upper end of the conductive layer 24 is adjacent to the Figure 2A The plate-shaped contact LI is connected to an upper layer wiring at a position where the cross section of the plate-shaped contact LI is different via a plug, etc. Thus, the plate-shaped contact LI functions as a source line contact.

[0062] However, instead of the plate contacts LI, a plate member filled with an insulating layer may penetrate the laminate LM and extend in the direction along the X direction, thereby dividing the laminate LM in the Y direction. In this case, the plate contacts do not function as source line contacts.

[0063] Between adjacent plate contacts LI in the Y direction, multiple isolation layers SHE are arranged, penetrating the upper layer portion of the laminate LMb and extending in the X direction. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, that penetrate select gate lines SGD0 and SGD1 and reach the insulating layer OL directly below select gate line SGD1.

[0064] In other words, these separation layers SHE penetrating the upper portion of the laminate LMb extend along the X direction between the plate contacts LI in the memory region MR and a portion of the step region SR, thereby dividing the upper portion of the laminate LMb into the selection gate lines SGD0 and SGD1.

[0065] In the memory region MR, a plurality of pillars PL are dispersedly arranged, penetrating the laminated body LM, the upper source line DSLb, and the intermediate source line BSL and reaching the lower source line DSLa.

[0066] When viewed from the stacking direction of the laminate LM, the plurality of pillars PL are arranged in a staggered manner, for example. Each pillar PL has a circular, elliptical, or oblong shape as a cross-sectional shape along the stacking direction of the laminate LM, that is, along the XY plane.

[0067] Furthermore, the column PL has a tapered shape in which the diameter and cross-sectional area gradually decrease from the upper layer side toward the lower layer side in the portion penetrating the laminated body LMa and the portion penetrating the laminated body LMb. Alternatively, the column PL has a curved shape in which the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side in the portion penetrating the laminated body LMa and the portion penetrating the laminated body LMb, for example.

[0068] The multiple pillars PL respectively have a memory layer ME extending in the stacking direction within the stacking body LM, a channel layer CN penetrating the stacking body LM and connected to the intermediate source line BSL, a top cover layer CP covering the upper surface of the channel layer CN, and a core layer CR serving as the core material of the pillar PL.

[0069] like Figure 2B and Figure 2C As shown, the memory layer ME has a multilayer structure in which a blocking insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surfaces of the pillar PL except at the depth of the middle source line BSL. Furthermore, the memory layer ME is also arranged on the bottom surface of the pillar PL, reaching the depth of the lower source line DSLa.

[0070] The channel layer CN is located inside the memory layer ME, penetrating the laminate body LM, the upper source line DSLb, and the middle source line BSL, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillars PL via the memory layer ME. However, a portion of the channel layer CN contacts the middle source line BSL at its side, thereby electrically connecting it to the source lines SL, including the middle source line BSL. Further inside the channel layer CN is the core layer CR.

[0071] Each of the plurality of pillars PL includes a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillars PL to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. Furthermore, the cap layer CP is connected to the bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the laminate LM in the Y direction, intersecting the direction in which the word line WL is drawn.

[0072] In addition, Figure 2A Among the six pillars PL, only three pillars PL are connected to the plugs CH. The three pillars PL respectively pass through three separate selection gate lines SGD and are connected to the plugs CH. Figure 2A The other columns PL are electrically connected to the bit lines BL shown. Figure 2A At different locations of the cross section shown, Figure 2A The plug CH not shown in the figure is connected to Figure 2A The illustrated bit lines BL are parallel to other bit lines BL extending in a direction along the Y direction.

[0073] The blocking insulating layer BK, tunnel insulating layer TN, and core layer CR of the memory layer ME are, for example, silicon oxide layers. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0074] like Figure 2C As shown in FIG1 , with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the word lines WL. Data is written into and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0075] In addition, if Figure 2B As shown, select gates STD are formed on the side surfaces of pillars PL facing select gate lines SGD0 and SGD1 above word lines WL. Select gates STS are also formed on the side surfaces of pillars PL facing select gate lines SGS0 and SGS1 below word lines WL.

[0076] By applying predetermined voltages from the select gate lines SGD and SGS, respectively, the select gates STD and STS can be turned on or off, thereby placing the memory cells MC of the pillars PL to which the select gates STD and STS belong in the selected or unselected state.

[0077] like Figure 2D As shown, the step region SR has a step portion SP formed by processing a plurality of word lines WL and select gate lines SGD and SGS into a step shape. Figure 2DThe step portion SP shown is a portion where the contact CC is arranged in the step region SR divided into a plurality of block regions BLK and has a function of leading out the word line WL and the like.

[0078] The step portion SP is covered by an insulating layer 51. The insulating layer 51 reaches the height of the uppermost layer of the laminate LM, for example, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 is also constituted separately. Figure 1A A portion of the insulating layer 50 is provided.

[0079] A stopper layer STP is disposed above the portion of the stacked body LMa where the word lines WL and select gate lines SGS are processed into a stepped shape. Stopper layer STP is composed of a material different from that of insulating layer 51 and is interposed within insulating layer 51 at a height between stacked bodies LMa and LMb. While insulating layer 51 is made of, for example, a silicon oxide layer, stopper layer STP is made of, for example, a silicon nitride layer.

[0080] In the step region SR, the source line SL includes an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0081] Therefore, in the step region SR, the plate contact LI penetrates the insulating layer 51, the laminate body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0082] Each contact CC (CCs, CCt) penetrates the insulating layer 51 and other layers and is connected to a word line WL or select gate line SGD or SGS located directly below the insulating layer OL at each stage of the terrace SP. Among the multiple contacts CCs and CCt, contact CCs is a contact CC connected to any one of the multiple word lines WL and select gate line SGD included in the laminate LMb. On the other hand, contact CCt is a contact CC connected to any one of the multiple word lines WL and select gate line SGS included in the laminate LMa.

[0083] Each contact CCs has, for example, a tapered shape with a diameter and cross-sectional area decreasing from the upper end toward the lower end. Alternatively, the contact CC has, for example, a curved shape with the diameter and cross-sectional area reaching their maximum at a predetermined position between the upper and lower ends. In either case, the cross-sectional area of ​​the contacts CCs changes continuously from the upper end toward the lower end.

[0084] Each contact CCt penetrates the insulating layer 51 and the stopper layer STP interposed therein, reaching the word line WL or the select gate line SGS immediately below the insulating layer OL of each stage constituting the step portion SP. Each of these contacts CCt includes a contact portion CCb, which is an upper portion of the stopper layer STP, and a contact portion CCa, which is a lower portion of the stopper layer STP.

[0085] Each contact portion CCb has, for example, a tapered shape whose diameter and cross-sectional area decrease from the upper end toward the lower end in contact with the termination layer STP. Alternatively, the contact portion CCb has, for example, a curved shape whose diameter and cross-sectional area are maximized at a predetermined position between the upper and lower ends. In either case, the cross-sectional area of ​​the contact portion CCb changes continuously from the upper end toward the lower end.

[0086] Each contact portion CCa has, for example, a tapered shape with a diameter and a cross-sectional area decreasing from an upper end portion contacting the stop layer STP toward a lower end portion contacting a word line WL or the like to be connected. The cross-sectional area of ​​the contact portion CCa changes continuously from the upper end portion toward the lower end portion.

[0087] Within a single contact CCt, the cross-sectional area of ​​contact portion CCb along the XY plane is generally larger than the cross-sectional area of ​​contact portion CCa along the XY plane. More specifically, the cross-sectional area of ​​contact CCt varies discontinuously between the upper and lower sides of termination layer STP, with the cross-sectional area of ​​the lower end of contact portion CCb being larger than the cross-sectional area of ​​the upper end of contact portion CCa.

[0088] Furthermore, when viewed in the stacking direction of the laminated bodies LMa and LMb, the center axis of the contact portion CCb may be offset from the center axis of the contact portion CCa. The cause of this offset will be described below.

[0089] In the following description, when there is no need to particularly distinguish between these contacts CCs and CCt, they will be simply referred to as contacts CC.

[0090] The contact CC includes an insulating layer 55 covering the periphery of the contact CC and a conductive layer 25 such as a tungsten layer or a copper layer filled inside the insulating layer 55. The conductive layer 25 is connected to the upper wiring MX arranged in the insulating layer 53 via a plug V0 arranged in the insulating layer 52. The upper wiring MX is connected to the peripheral circuit CBA (see Figure 1A ) electrical connection.

[0091] This configuration allows word lines WL in each layer, as well as select gate lines SGD and SGS above and below word lines WL, to be electrically extended from one or both ends of the laminate LM in the X direction. In other words, this configuration allows a predetermined voltage to be applied from peripheral circuit CBA via upper-layer wiring MX, contacts CC, and word lines WL to memory cells MC, thereby operating the memory cells MC as storage elements.

[0092] In the stepped region SR, a plurality of columnar portions HR are dispersed throughout the entire region. As described below, these columnar portions HR serve to support the laminated body LM formed by laminating sacrificial layers and insulating layers, but do not contribute to the function of the semiconductor memory device 1.

[0093] In principle, the multiple columnar portions HR are arranged to avoid interference with the plate-shaped contacts LI and CC, and are arranged, for example, in a grid or staggered pattern when viewed in the stacking direction of the laminate LM. Each columnar portion HR has, for example, a circular, elliptical, or oblong cross-sectional shape along the XY plane.

[0094] Furthermore, the columnar portion HR has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side toward the lower layer side in the portion penetrating the stacked body LMa and the portion penetrating the stacked body LMb, respectively. Alternatively, the columnar portion HR has a curved shape in which the diameter and cross-sectional area are maximized at a predetermined position between the upper layer side and the lower layer side in the portion penetrating the stacked body LMa and the portion penetrating the stacked body LMb, respectively.

[0095] The entire columnar portion HR is a single body of the insulating layer 57, such as a silicon oxide layer. In other words, the columnar portion HR includes the insulating layer 57, which is substantially made of a single material. Here, "substantially a single material" means that the columnar portion HR may contain different element ratios of constituent components within a single columnar portion HR or between multiple columnar portions HR, and that the columnar portions HR may contain different types and amounts of impurities. Furthermore, the columnar portion HR made of a single material may contain voids.

[0096] Since the columnar portion HR is a separate body from the insulating layer 57 , it does not electrically affect other components and can tolerate interference with adjacent plate-shaped contacts LI and the like within a predetermined range.

[0097] (Method for Manufacturing Semiconductor Memory Device)

[0098] Next, use Figures 3A to 10C , a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figures 3A to 10C These are diagrams sequentially illustrating a portion of the steps of a method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0099] first, Figures 3A to 3E 5 shows the laminated body LMsa, which is the lower layer portion of the laminated body LM before the word line WL is formed, and the state where various structures are formed in the laminated body LMsa.

[0100] Figures 3A to 3E It is a cross-sectional view taken along the X direction of a region which will later become the memory region MR and the step region SR.

[0101] like Figure 3A As shown, a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are sequentially formed on the supporting substrate SS.

[0102] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 (see FIG. 1 ) can also be formed on the upper surface side of the support substrate SS. Figure 2A wait).

[0103] The middle sacrificial layer SCN is formed in a region of the supporting substrate SS that will later become the memory region MR, and the middle insulating layer SCO is formed in a region of the supporting substrate SS that will later become the step region SR. The middle sacrificial layer SCN is, for example, a silicon nitride layer, and is later replaced by a polysilicon layer or the like to become the middle source line BSL. As described above, the middle insulating layer SCO is, for example, a silicon oxide layer or the like.

[0104] Furthermore, a laminate LMsa is formed on the upper source line DSLb by alternately stacking multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that is later replaced with a conductive material to become a word line WL or a select gate line SGS.

[0105] like Figure 3B As shown, the insulating layer NL and the insulating layer OL are processed into a step-like shape in a part of the laminate LMsa. Such processing can be performed by repeatedly thinning the mask pattern of the photoresist layer and etching the insulating layer NL and the insulating layer OL of the laminate LMsa.

[0106] Specifically, a mask pattern is formed on the upper surface of the laminated body LMsa, and the exposed portions of the insulating layers NL and OL are etched away layer by layer. Furthermore, by treatment with oxygen plasma or the like, the ends of the mask pattern are retracted, exposing the upper surface of the laminated body LMsa again, and the insulating layers NL and OL are further etched away layer by layer. This step-like shape is formed by repeating this process multiple times.

[0107] like Figure 3CAs shown in FIG. 1 , an insulating layer 51 is formed to a height that covers the stepped portion and reaches the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the laminated body LMsa.

[0108] like Figure 3D As shown, for example, multiple memory holes MHa and multiple holes HLa extending in the stacking direction are formed in the stacked body LMsa. The memory holes MHa will later become the lower structure of the pillars PL. The holes HLa will later become the lower structure of the columnar portion HR.

[0109] Multiple memory holes MHa are arranged in a region that will later become the memory region MR, and penetrate the laminated body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. Multiple holes HLa are arranged in a region that will later become the step region SR, and penetrate the insulating layer 51, the laminated body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0110] like Figure 3E As shown, the memory holes MHa and the holes HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer.

[0111] Thus, in the region that will later become the memory region MR, pillars PLc are formed with the plurality of memory holes MHa filled with the sacrificial layer 26. Furthermore, in the region that will later become the step region SR, columnar portions HRc are formed with the plurality of holes HLa filled with the sacrificial layer 26.

[0112] Next, Figures 4A to 5C The upper portion of the laminated body LM, that is, the laminated body LMsb before the word line WL is formed is formed with a stopper layer STP partially interposed therebetween, and various structures are further formed in the laminated body LMsb.

[0113] Figures 4A to 5C With the Figures 3A to 3E Similarly, it is a cross-sectional view taken along the X direction of a region which will later become the memory region MR and the step region SR.

[0114] like Figure 4A As shown in FIG. 1 , a termination layer STPb is formed covering the laminated body LMsa and the insulating layer 51 of the step portion. The termination layer STPb is formed as described above. Figure 2D Before the pattern is formed, a layer covering the entire surface of the laminate body LMsa and the insulating layer 51 is formed.

[0115] like Figure 4BAs shown, the termination layer STPb is processed into the pattern of the termination layer STP. Specifically, the portion of the termination layer STPb covering the laminated body LMsa and the portion covering the insulation layer 51 is removed, while the portion of the termination layer STPb remaining on the insulation layer 51 where the multiple contacts CCt are to be formed remains. Furthermore, multiple openings CLa are formed in the portion remaining on the insulation layer 51. These openings CLa are the portions through which the contacts CCt will later pass. Furthermore, a mask pattern, etc., is used to align the openings CLa with the columnar portion HRc.

[0116] More specifically, a mark (not shown) is provided in a certain area on the supporting substrate SS for aligning the mask pattern when forming the columnar portion HRc. Using this mark as a reference, a mask pattern having a pattern for the columnar portion HRc is formed on the laminated body LMsa. This mask pattern can be used to form the columnar portion HRc at the desired position on the laminated body LMsa. Using this same mark as a reference, a mask pattern having a pattern for the opening CLa formed in the stopper layer STP is formed. This aligns the position of the opening CLa with respect to the columnar portion HRc.

[0117] By aligning the opening CLa with respect to the columnar portion HRc in this manner, the opening CLa can be formed while avoiding interference with the columnar portion HRc.

[0118] As described above, the stopper layer STP is formed on the insulating layer 51 covering the portion of the laminated body LMa processed into the step shape.

[0119] like Figure 4C As shown, a laminated body LMsb is formed by alternating multiple insulating layers NL and multiple insulating layers OL, covering the laminated body LMsa and the stopper layer STP at the stepped portion. At this point, the opening CLa provided in the stopper layer STP is filled with, for example, the insulating layer OL. Furthermore, the sacrificial layer NL of the laminated body LMsb is later replaced with a conductive layer to become a word line WL or a select gate line SGD.

[0120] like Figure 4D As shown, in a part of the laminate LMsb, the insulating layer NL and the insulating layer OL are processed into a step-like shape. Figure 3B The process is the same as that shown, and can be performed by repeatedly performing thinning of the mask pattern of the photoresist layer or the like and etching of the insulating layer NL and the insulating layer OL of the laminated body LMsb a plurality of times.

[0121] At this time, the uppermost step of the stepped portion formed in laminate LMsa is brought closer to the lowermost step of the stepped portion formed in laminate LMsb, so that they are continuously connected from the lower side of laminate LMsa to the upper side of laminate LMsb. Furthermore, since laminate LMsb on the stepped portion of laminate LMsa is removed, the termination layer STP formed above the stepped portion of laminate LMsa is exposed again.

[0122] like Figure 5A As shown, an insulating layer 51 is formed, covering the newly exposed upper surface of stop layer STP and the newly formed step portion of laminated body LMsb, reaching the height of the upper surface of laminated body LMsb. Insulating layer 51 is also formed in the outer regions of laminated bodies LMsa and LMsb. Thus, insulating layer 51 is formed, partially interposed with stop layer STP.

[0123] like Figure 5B As shown, for example, multiple memory holes MHb and multiple holes HLb are formed simultaneously, extending in the stacking direction along the height of the stacked body LMsb. The memory holes MHb will later become the upper structure of the pillars PL. The holes HLb will later become the upper structure of the columnar portion HR.

[0124] The plurality of memory holes MHb are arranged in a region that will later become the memory region MR, penetrate the laminated body LMsb, and reach the upper end portions of the pillars PLc formed in the laminated body LMsa.

[0125] A portion of the multiple holes HLb is arranged at a position overlapping with the stepped portion of the laminated bodies LMsa and LMsb in the lamination direction, and penetrates the insulating layer 51, and the laminated body LMsb or the termination layer STP, respectively reaching the upper end portion of the columnar portion HRc formed in the laminated body LMsa.

[0126] like Figure 5C As shown, the sacrificial layer 26 is removed from the pillar PLc and the columnar portion HRc at the bottom of the memory hole MHb and the hole HLb.

[0127] Thus, memory holes MHa are formed at the bottoms of the plurality of memory holes MHb, thereby forming a plurality of memory holes MH that penetrate the laminated bodies LMsb and LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reach the lower source line DSLa. Furthermore, holes HLa are formed at the bottoms of the plurality of holes HLb, thereby forming a plurality of holes HL that penetrate the insulating layer 51, the laminated body LMsb or the stopper layer STP, the laminated body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO, and reach the lower source line DSLa.

[0128] In addition, when the sacrificial layer 26 filled in the pillar PLc and the columnar portion HRc is a CVD-carbon layer or the like, the sacrificial layer 26 is removed by ashing using oxygen plasma or the like. Figure 5B When the mask pattern used in the process is changed, the sacrificial layer 26 may be removed from these pillars PLc and the columnar portion HRc.

[0129] Then, the insulating layer 57 is embedded in the hole HR formed in a region that will later become the step region SR, thereby forming a plurality of columnar portions HR.

[0130] Next, use Figures 6A to 7C , which shows a case where a multilayer structure is formed in the memory hole MH to form a pillar PL. Figures 6A to 7C It is a cross-sectional view taken along the Y direction of a region which will later become the memory region MR.

[0131] like Figure 6A As shown in FIG. 1 , a plurality of memory holes MH are formed in a region which will later become a memory region MR.

[0132] like Figure 6B As shown, a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are sequentially formed within the memory hole MH. Thus, the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surfaces of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0133] The multilayer insulating layer MEb is an insulating layer of a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0134] The multi-layer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also sequentially formed on the upper surface of the laminated body LMsb.

[0135] like Figure 6C As shown, in the area that will later become the memory area MR, the insulating layer CRb, the semiconductor layer CNb and the multi-layer insulating layer MEb are etched back in sequence to remove them from the upper surface of the laminate LMsb, and a recessed portion DN is formed at the upper end of the memory hole MH after the insulating layer CRb and the semiconductor layer CNb are removed.

[0136] Thus, in the memory hole MH, the memory layer ME, the channel layer CN, and the core layer CR are formed in this order from the outer peripheral side.

[0137] like Figure 7AAs shown, in the region that will later become the memory region MR, a semiconductor layer CPb is formed in the recessed portion DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the laminated body LMsb.

[0138] like Figure 7B As shown, in the region that will later become the memory region MR, the semiconductor layer CPb on the upper surface of the laminate body LMsb is removed by CMP or the like, and a cap layer CP is formed at the upper end of the memory hole MH. Furthermore, the insulating layer OL of the uppermost layer of the laminate body LMsb, which has been thinned by CMP or the like, is thickened.

[0139] Thus, the pillars PL are formed with the cap layer CP embedded in the uppermost insulating layer OL. However, at this point, the memory layer ME does not cover the entire sidewalls of the pillars PL, and part of the side surface of the channel layer CN is exposed from the memory layer ME.

[0140] Next, use Figures 8A to 9C , showing the situation where the source line SL and the word line WL are formed. Figures 8A to 9C With the Figure 6A 7 , it is a cross-sectional view taken along the Y direction of a region which will later become the memory region MR.

[0141] like Figure 8A As shown in FIG. 1 , a slit ST is formed that penetrates the stacked layers LMsb, LMsa, and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. In addition, an insulating layer 54s is formed on the adjacent side walls of the slit ST in the Y direction.

[0142] The slit ST has a tapered or curved Y-direction longitudinal section and extends in the laminated bodies LMsa, LMsb along the X-direction. Therefore, in the step region SR (not shown), the lower end of the slit ST reaches the intermediate insulating layer SCO.

[0143] like Figure 8B As shown, a remover of the intermediate sacrificial layer SCN, such as hot phosphoric acid, flows through the slit ST whose sidewalls are protected by the insulating layer 54s, thereby removing the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0144] Thus, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME at the periphery of the pillar PL is exposed in the gap layer GPs.

[0145] At this time, the sidewalls of the slit ST are protected by the insulating layer 54s, thereby preventing the insulating layer NL within the stacked layers LMsa and LMsb from being removed. Furthermore, in the step region SR (not shown), no intermediate sacrificial layer SCN exists between the lower source line DSLa and the upper source line DSLb, and no gap layer GPs is formed.

[0146] like Figure 8C As shown, the chemical solution is appropriately flowed into the gap layer GPs through the slit ST, and the blocking insulating layer BK, the charge storage layer CT, and the tunnel insulating layer TN of the memory layer ME exposed in the gap layer GPs are removed in sequence (see Figure 2B and Figure 2C ). Thus, the memory layer ME is removed from a portion of the sidewall of the pillar PL, and a portion of the inner channel layer CN is exposed in the gap layer GPs.

[0147] like Figure 8D As shown, a raw material gas such as amorphous silicon is injected through the slit ST, the sidewalls of which are protected by the insulating layer 54s, to fill the gap layer GPs with amorphous silicon. Furthermore, the supporting substrate SS is heated to polycrystallize the amorphous silicon filling the gap layer GPs, thereby forming an intermediate source line BSL composed of polycrystalline silicon.

[0148] Thus, a portion of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0149] At this time, in the step region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb, and no intermediate source line BSL is formed.

[0150] like Figure 9A As shown, the insulating layer 54s on the sidewalls of the slit ST is temporarily removed.

[0151] like Figure 9B As shown, a solution for removing the insulating layer NL, such as hot phosphoric acid, is flowed through the slits ST into the laminated bodies LMsa and LMsb to remove the insulating layer NL. This forms laminated bodies LMga and LMgb having a plurality of gap layers GP after removing the insulating layer NL between the insulating layers OL.

[0152] The stacked bodies LMga and LMgb, including multiple gap layers GP, have a fragile structure. In the area that will later become the memory region MR, the multiple pillars PL support these fragile stacked bodies LMga and LMgb. Meanwhile, in the area that will later become the step region SR, the multiple columnar portions HR support these stacked bodies LMga and LMgb.

[0153] Such a support structure of the pillars PL and the columnar portions HR prevents the remaining insulating layer OL from being bent or the laminated bodies LMga and LMgb from being deformed and collapsed.

[0154] like Figure 9C As shown, a source gas containing a conductive material such as tungsten or molybdenum is injected into the laminated bodies LMga and LMgb through the slit ST. The gap layers GP of the laminated bodies LMga and LMgb are filled with the conductive material to form a plurality of word lines WL and the like. This forms the laminated body LM, which includes the laminated bodies LMa and LMb formed by alternately stacking the plurality of word lines WL and the like with the plurality of insulating layers OL.

[0155] Furthermore, the uppermost layer and the second conductive layer from the uppermost layer of the laminated body LMb are divided into a pattern of a plurality of select gate lines SGD by later forming a separation layer SHE penetrating therethrough.

[0156] As described above, the process of forming the middle source line BSL from the middle sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also referred to as replacement processes.

[0157] As described above, the stopper layer STP is formed only in the region where the contact CCt is to be arranged. Therefore, even the stopper layer STP, such as a silicon nitride layer of the same type as the insulating layer NL, is prevented from being replaced by a conductive layer by the replacement process.

[0158] Then, insulating layer 54 is formed on the sidewall of slit ST, and conductive layer 24 is filled in insulating layer 54 to form plate-shaped contact LI. However, conductive layer 24 may not be formed in slit ST, but insulating layer 54 may be filled to form a plate-shaped member.

[0159] Furthermore, by forming a groove penetrating one or more conductive layers including the uppermost conductive layer of the laminated body LMb and filling the groove with the insulating layer 56 , a separation layer SHE is formed that divides these conductive layers into a pattern of the select gate line SGD.

[0160] Next, use Figures 10A to 10C , which shows a case where a plurality of contacts CC are formed in the step region SR. Figures 10A to 10C It is a cross-sectional view of the step region SR along the X direction.

[0161] like Figure 10A As shown, in the step region SR, a plurality of columnar portions HR are formed in which the insulating layer 57 is embedded in the hole HL.

[0162] Furthermore, a plurality of contact holes CL (CLs, CLt) are formed so as to penetrate the insulating layer 51 and reach the plurality of word lines WL and the selection gate lines SGD, SGS of the laminated bodies LMa, LMb, respectively.

[0163] The plurality of contact holes CLs are formed so as to penetrate the insulating layer 51 covering the stepped portions of the plurality of word lines WL and the select gate lines SGD of the laminated body LMb and reach the word lines WL and the select gate lines SGD.

[0164] The plurality of contact holes CLt are formed so as to penetrate the insulating layer 51 covering the stepped portions of the plurality of word lines WL and the select gate lines SGS of the laminate body LMa and reach the word lines WL and the select gate lines SGS.

[0165] At this time, the openings of these contact holes CLt correspond to the formation positions of the openings CLa provided in the stopper layer STP, for example, and are formed larger than the openings CLa. In addition, the etching conditions for forming the contact holes CL (CLs, CTt) are adjusted to achieve selectivity for the stopper layer STP.

[0166] As a result, the insulating layer 51, such as a silicon oxide layer, is selectively etched compared to the stopper layer STP, such as a silicon nitride layer, etc. Then, in the portion of the etched bottom surface of the contact hole CLt having an opening larger than the opening CLa of the stopper layer STP that reaches the stopper layer STP, the etching rate is extremely slow, or etching stops.

[0167] In addition, in the portion of the etching bottom surface of the contact hole CLt that reaches the opening CLa of the stopper layer STP, etching can proceed through the opening CLa to below the stopper layer STP, thereby reaching the word line WL and the like as a connection target.

[0168] Furthermore, as a result, in the contact hole CLt, the cross-sectional area of ​​the lower side of the stopper layer STP along the XY plane is generally smaller than the cross-sectional area of ​​the upper side of the stopper layer STP along the XY plane. More specifically, the cross-sectional area of ​​the contact hole CLt changes discontinuously between the upper and lower sides of the stopper layer STP, and the cross-sectional area of ​​the upper end portion of the lower portion of the stopper layer STP is smaller than the cross-sectional area of ​​the lower end portion of the upper portion of the stopper layer STP.

[0169] Furthermore, each contact hole CLt is opened at a position corresponding to each opening CLa of the stopper layer STP. However, the formation position of the contact hole CLt may be slightly offset. In this case, the central axis of the contact hole CLt, as viewed in the stacking direction of the stacked bodies LMa and LMb, may be offset above or below the stopper layer STP.

[0170] like Figure 10B As shown, an insulating layer 55 is formed on the sidewalls of the contact hole CL.

[0171] like Figure 10C As shown, the gap within the contact hole CL is filled with a conductive layer 25 .

[0172] Through the above, a plurality of contacts CC (CCs, CCt) are formed.

[0173] Next, an insulating layer 52 is formed on the upper surface of the laminate LM and the upper surface of the insulating layer 51 covering the stepped region SR. A plug V0 connected to the contact CC is formed through the insulating layer 52. Furthermore, a plug CH connected to the pillar PL is formed through the insulating layer 52. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and upper-layer wiring MX and bit lines BL connected to the plugs V0 and CH are formed. Furthermore, electrode pads and the like are formed on the upper surface of the insulating layer 53 to establish electrical continuity with the peripheral circuit CBA.

[0174] Alternatively, the plugs V0 and CH, the upper layer wiring MX, the bit lines BL, and the like may be formed collectively by using, for example, a dual damascene method.

[0175] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB that is separate from the supporting substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, through-holes, wiring, and the like are formed in the insulating layer 40 to lead the peripheral circuit CBA to the surface of the insulating layer 40, and are connected to electrode pads and the like formed on the upper surface of the insulating layer 40.

[0176] Next, the supporting substrate SS and the semiconductor substrate SB are bonded together using the insulating layers 50 and 40 respectively provided thereon, and the electrode pads in the insulating layers 50 and 40 are connected. Then, the supporting substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 having the plug PG formed thereon.

[0177] As described above, the semiconductor memory device 1 according to the embodiment is manufactured.

[0178] (Summary)

[0179] Semiconductor memory devices such as three-dimensional nonvolatile memories are configured such that a plurality of word lines are stacked, a portion of which is formed in a stepped shape, and contacts are connected to the stepped portions, thereby enabling voltage to be applied to the plurality of word lines.

[0180] Furthermore, a laminated structure formed by stacking multiple word lines, etc., is formed, for example, by stacking multiple sacrificial layers and replacing them with conductive materials. In order to support the fragile structure of the laminated structure when the sacrificial layers are replaced with word lines, etc., a columnar portion penetrating the laminated structure is sometimes formed at the stepped portion of the laminated structure.

[0181] However, the columnar portion may be formed tilted due to stress generated between various components such as the laminate, or due to the oblique incidence of ions during etching. The contacts may also be tilted due to the oblique incidence of ions during etching. In addition, when forming the columnar portion and the contacts, the mask pattern used to process them may also be misaligned. If at least one of the columnar portion and the contact is tilted or misaligned, the columnar portion and the contact may come into contact.

[0182] By using the method for manufacturing the semiconductor memory device 1 according to the embodiment, it is possible to suppress contact between the columnar portion HR and the contact CC. Figures 11A to 11D Provide explanation.

[0183] Figures 11A to 11D 1 is a cross-sectional view showing an example of a method for forming the contact holes CLt and CLx according to the embodiment and the comparative example. Figures 11A to 11D As shown, the contact holes CLt and CLx are formed using a mask pattern 70 .

[0184] exist Figure 11A In the comparative example shown, the columnar portion HRx is tilted. In addition, a void VD is generated when the insulating layer is embedded in the columnar portion HRx. In addition, the mask pattern 70 is positionally misaligned in a direction approaching the formed columnar portion HRx.

[0185] like Figure 11B As shown, when the contact hole CLx of the comparative example is formed, for example, contact is made with the inclined columnar portion HRx, and further, the contact hole CLx is connected to the void VD in the columnar portion HRx, resulting in etching proceeding through the void VD toward the bottom of the columnar portion HRx.

[0186] When the conductive layer is filled in the contact hole CLx in such a state, the conductive layer may also be filled in the gap VD extending below, causing electrical leakage between the adjacent lower word line WLx and the word line WLx connected to the contact.

[0187] Furthermore, the contact between the contact hole CLx and the columnar portion HRx described above is more likely to occur on the lower layer side of the laminate. In other words, contact is more likely to occur near the lower end of the columnar portion HRx disposed near the contact hole CLx connected to the word line WLx in the lower layer of the laminate.

[0188] exist Figure 11C In the illustrated embodiment, the pillars HR also tilt, and a void VD is created when the insulating layer is embedded within the pillars HR. Furthermore, the mask pattern 70 is positionally offset in a direction approaching the already formed pillars HR. As a result, the openings of the mask pattern 70, which should vertically overlap, do not overlap at all with the opening CLa provided in the stop layer STP.

[0189] like Figure 11D As shown, when forming the contact hole CLt according to the embodiment, the portion of the etched bottom surface of the contact hole CLt that vertically overlaps with the inclined columnar portion HR is located at a position offset from the opening CLa of the stopper layer STP. Therefore, the contact hole CLt reaches the stopper layer STP, where etching stops. This prevents contact between the contact hole CLt and the columnar portion HR.

[0190] On the other hand, the portion of the etching bottom surface of contact hole CLt that vertically overlaps opening CLa passes directly through opening CLa and reaches the word line WL to be connected. This allows the contact CCt formed from contact hole CLt to be more reliably connected to the word line WL to be connected.

[0191] Furthermore, if the tilt of the columnar portion HR is caused by stress generated by the laminated bodies LMga and LMgb after the columnar portion HR is formed, the stopper layer STP will also be subject to the same stress. Therefore, the relative positional relationship between the opening CLa provided in the stopper layer STP and the columnar portion HR remains substantially unchanged.

[0192] As described above, the opening CLa is formed to be aligned with the lower structure of the columnar portion HR to avoid interference with the lower structure of the columnar portion HR. Therefore, even if the columnar portion HR tilts due to stress, the contact hole CLt can be formed through the opening CLa while maintaining its relative positional relationship with the columnar portion HR, further suppressing contact between the contact hole CLt and the columnar portion HR.

[0193] The semiconductor memory device 1 according to the first embodiment includes a contact CCt extending downward from above a stepped portion SP provided in the stacked body LMa, penetrating the insulating layer 51 and the stopper layer STP, and connected to any one of the plurality of word lines WL and select gate lines SGS processed into a stepped shape. This prevents contact CCt from contacting other components.

[0194] In the above embodiment, the stop layer STP is, for example, a silicon nitride layer. However, the stop layer STP may also be, for example, a polysilicon layer, an amorphous silicon layer, or a metal oxide layer, as long as it is made of a material different from that of the insulating layer 51 and has etching selectivity with respect to the insulating layer 51. The metal oxide layer may be, for example, an aluminum oxide (Al2O3) layer.

[0195] In the above embodiment, the opening CLa of the stopper layer STP is, for example, smaller than the opening area of ​​the contact hole CLt. However, the opening CLa may be substantially equal to the opening area of ​​the contact hole CLt. In this case, the diameters of the contact portions CCa and CCb of the contact CCt can be substantially equal without positional offset relative to the opening CLa.

[0196] However, the area of ​​the opening CLa can be determined based on, for example, the distance between the columnar portion HR and the contact CCt, more preferably, the distance between their lower ends, and the size of the gap VD that may be generated by the columnar portion HR.

[0197] (Variation Example)

[0198] Next, use Figure 12A and Figure 12B A semiconductor memory device 2 according to a modified example of the embodiment will be described. The semiconductor memory device 2 according to the modified example includes a stopper layer STPp made of a material different from that of the stopper layer STP.

[0199] Figure 12A and Figure 12B This is a diagram showing an example of the configuration of a semiconductor memory device 2 according to a modification of the embodiment.

[0200] In more detail, Figure 12A It is a cross-sectional view taken along the X direction in the step region SR of the semiconductor memory device 2 . Figure 12B 2 is a cross-sectional view along the XY plane at a height position of the selection gate line SGD in the step region SR of the semiconductor memory device 2. Figure 12A In FIG, the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0201] In addition, Figure 12A and Figure 12B In the embodiment, the same components as those in the embodiment described above are sometimes denoted by the same reference numerals and their descriptions are omitted.

[0202] like Figure 12A and Figure 12B As shown, the semiconductor memory device 2 of the modified example includes a stopper layer STPp instead of the stopper layer STP. The stopper layer STPp is, for example, a conductive layer such as a metal layer. As the metal layer, for example, a tungsten layer or a molybdenum layer can be used.

[0203] Since the stopper layer STPp is a conductive layer, in the semiconductor memory device 2 of the modified example, the stopper layer STPp is provided separately for each contact CCt. Although the contact CCt has an insulating layer 55 on its sidewall, by preliminarily separating the stopper layer STPp for each contact CCt, it is possible to more reliably suppress the occurrence of conduction between the contacts CCt.

[0204] like Figure 12B As shown, each separate termination layer STPp is formed to occupy an area at least larger than the cross-section of the upper structure of the contact CCt, that is, the contact portion CCb. Figure 12B 2 shows a stopper layer STPp having a circular shape as an example. However, the stopper layer STPp may have other shapes such as a quadrilateral or other polygons.

[0205] Such a termination layer STPp is formed, for example, by Figure 4B The opening CLa shown is obtained by performing a process of separating each of the plurality of contacts CCt simultaneously.

[0206] According to the semiconductor memory device 2 of the modification, the stopper layers STPp are dispersedly arranged at positions corresponding to the plurality of contacts CCt. Thus, even when the stopper layer STPp is conductive, conduction between the contacts CCt can be suppressed.

[0207] According to the semiconductor memory device 2 of the modification, the stopper layer STPp contains at least one of tungsten and molybdenum as a main component. Thus, by using a metal material as the stopper layer STPp, the etching selectivity with respect to the insulating layer 51 such as a silicon oxide layer can be further improved.

[0208] According to the semiconductor memory device 2 of the modification, the same effects as those of the semiconductor memory device 1 of the embodiment are achieved except for the above-described details.

[0209] (Other Variations)

[0210] Furthermore, in the above-described embodiment and variations, the columnar portions HR are formed after the stepped structure is formed. However, the columnar portions HR may also be formed before the stepped structure is formed. In this case, when the stepped structure is formed, the columnar portions HR on the upper layer will partially disappear along with the stacked bodies LMsa and LMsb processed into the stepped shape. Even in this case, the columnar portions HR on the lower layer will remain. Therefore, by employing this configuration, the risk of contact with the contacts CCt can be reduced.

[0211] Furthermore, in the embodiment and variations described above, in the method of extending multiple word lines WL and the like on one side, contacts are alternately arranged in the Y direction for every two block areas BLK in the step region SR on one side in the X direction. However, in the method of extending word lines WL and the like on one side, the contacts can be arranged on one side in the X direction within the same block area BLK, and the arrangement order is not limited to the above.

[0212] In the above-described embodiment and modification, a double-layered laminate LM is provided, wherein two laminates LMa and LMb are stacked one above the other. However, the laminate is not limited to a double-layered laminate and may be three or more layers.

[0213] In the above-described embodiment and variations, the pillars PL are connected to the source lines SL at the side surfaces of the channel layer CN, but the present invention is not limited thereto. For example, the pillars may be formed by removing the memory layer at the bottom surfaces of the pillars and connecting the pillars to the source lines at the bottom ends of the channel layer.

[0214] In the above-described embodiment and modification, the peripheral circuit CBA is arranged above the laminate LM. However, the peripheral circuit may be arranged below the laminate or on the same layer as the laminate.

[0215] When the peripheral circuit is disposed below the laminate, for example, the source line and the laminate can be formed on the insulating layer of the semiconductor substrate having the peripheral circuit covered by the insulating layer. When the peripheral circuit is disposed on the same layer as the laminate, the laminate can be formed at a position different from that of the peripheral circuit on the semiconductor substrate having the peripheral circuit formed thereon.

[0216] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0217] [Explanation of Symbols]

[0218] 1,2:Semiconductor storage devices

[0219] CC, CCs, CCt: Contact

[0220] CCa, CCb: contact part

[0221] CLa: opening

[0222] HR: columnar part

[0223] LI: Plate contact

[0224] LM, LMa, LMb, LMga, LMgb, LMsa, LMsb: laminated body

[0225] MC: Storage Unit

[0226] MR: Memory Region

[0227] NL,OL: insulation layer

[0228] 51: Insulation layer

[0229] PL: Column

[0230] SGD, SGS: select gate line

[0231] SP: Step

[0232] SR: Stepped Area

[0233] ST: Slit

[0234] STP, STPp: Termination Layer

[0235] WL: word line.

Claims

1. A semiconductor memory device comprising: The first laminate is formed by laminating a plurality of first conductive layers spaced apart from each other, and has a first step portion formed by processing the plurality of first conductive layers into a step-like shape; a second laminate, disposed above the first laminate, formed by laminating a plurality of second conductive layers spaced apart from each other, and having a second stepped portion formed by processing the plurality of second conductive layers into a stepped shape and continuously extending from the first stepped portion; a first insulating layer covering the first and second stepped portions; a first layer comprising a material different from that of the first insulating layer, interposed in the first insulating layer above the first stepped portion, and disposed at a height position between the first and second laminated bodies; and The first contact extends downward from above the first stepped portion, penetrating the first insulating layer and the first layer, and is connected to any one of the plurality of first conductive layers processed into a stepped shape.

2. The semiconductor memory device according to claim 1, wherein The cross-sectional area of ​​the first contact viewed in the stacking direction of the first and second stacked bodies changes discontinuously between the upper side and the lower side of the first layer.

3. The semiconductor memory device according to claim 2, wherein A cross-sectional area of ​​the first contact at a height position of the upper surface of the first layer as viewed from the stacking direction is larger than a cross-sectional area of ​​the first contact at a height position of the lower surface of the first layer as viewed from the stacking direction.

4. The semiconductor memory device according to claim 1, wherein The center axis of the first contact, viewed in the stacking direction of the first and second stacked bodies, is offset between the upper side and the lower side of the first layer.

5. The semiconductor memory device according to claim 2, wherein The device further comprises a second contact extending downward from above the second stepped portion through the first insulating layer and connected to any one of the plurality of second conductive layers processed into a stepped shape. A cross-sectional area of ​​the second contact viewed in the stacking direction changes continuously from an upper end portion to a lower end portion. The semiconductor memory device according to claim 1 , wherein The device further comprises a plurality of third contacts, the plurality of third contacts extending downward from above the first stepped portion through the first insulating layer and the first layer, and respectively connected to the plurality of first conductive layers processed into a stepped shape. The plurality of third contacts include the first contact.

7. The semiconductor memory device according to claim 6, wherein The first layer extends continuously over the entire region where the plurality of third contacts are arranged.

8. The semiconductor memory device according to claim 6, wherein The first layer is dispersedly arranged at positions corresponding to the plurality of third contacts.

9. A method for manufacturing a semiconductor memory device, comprising the following steps: forming a first laminated body formed by laminating a plurality of first sacrificial layers spaced apart from each other, the first laminated body having a first step portion formed by processing the plurality of first sacrificial layers into a step-like shape; covering the first stepped portion with a first insulating layer; forming a first layer including a material different from that of the first insulating layer on the first insulating layer; A second laminate is formed above the first laminate, wherein a plurality of second sacrificial layers are laminated in a manner spaced apart from each other, and the second laminate has a second stepped portion formed by processing the plurality of second sacrificial layers into a stepped shape and continuously extending from the first stepped portion; additionally forming the first insulating layer to cover the second stepped portion and the first layer; Replacing the first and second sacrificial layers with conductive materials to form the first conductive layers included in the first laminate and the second conductive layers included in the second laminate; as well as forming a first contact extending downward from above the first stepped portion through the first insulating layer and the first layer to connect to any one of the plurality of first conductive layers processed into a stepped shape; The first layer is formed to have an opening at a portion where the first contact is to pass through. The first contact is formed through the first insulating layer so as to extend in the vertical direction of the first layer via the opening.

10. The method for manufacturing a semiconductor memory device according to claim 9, wherein A columnar portion extending to a height position of the first laminate is further formed on the first step portion, and the opening is formed by being aligned with the columnar portion.

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