Storage device
By allocating common addresses to short-circuit wiring in a storage device and reducing the use of redundant lines, the problems of line complexity and resource waste caused by redundant lines are solved, and the simplification and efficient operation of the storage device are achieved.
Patent Information
- Application Number
- CN202510295526.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-18
- Filing Date
- 2025-03-13
- Publication Date
- 2025-09-19
AI Technical Summary
In existing storage devices, the existence of redundant lines increases circuit complexity and wastes resources, and it is difficult to efficiently handle short circuit defects.
By introducing an address allocation circuit into the memory device, a common address is allocated to mutually short-circuited wirings, and a redundancy control circuit is used to reduce the use of redundant lines, so that only one of the memory cells is selected for effective operation.
The number of redundant lines is effectively reduced, the line structure is simplified, the reliability and efficiency of the storage device are improved, and resource waste is reduced.
Smart Images
Figure CN120676640A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a storage device. Background Art
[0002] A memory device has been proposed in which a plurality of variable resistance memory elements (resistance change memory elements) such as magnetoresistive elements are integrated on a semiconductor substrate. Summary of the Invention
[0003] Provided is a memory device capable of reducing the number of redundant lines used.
[0004] A storage device in an embodiment comprises: a plurality of first wirings, each extending in a first direction; a plurality of second wirings, each extending in a second direction intersecting the first direction; a plurality of storage cells, arranged between the plurality of first wirings and the plurality of second wirings, each including a variable resistance storage element and a switching element connected in series; and an address allocation circuit, which allocates addresses to the plurality of first wirings, and when the plurality of first wirings include a first short-circuit wiring and a second short-circuit wiring that are short-circuited to each other, the address allocation circuit allocates a common address to the first short-circuit wiring and the second short-circuit wiring. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 This is a block diagram showing the configuration of a storage device according to an embodiment.
[0006] Figure 2 It is a perspective view schematically showing the structure of a memory cell array portion included in the memory device according to the embodiment.
[0007] Figure 3 This is a cross-sectional view schematically showing a basic structure of a magnetoresistive element included in a memory cell array portion of a memory device according to an embodiment.
[0008] Figure 4 This is a cross-sectional view schematically showing a basic structure of a selector included in a memory cell array portion of a memory device according to an embodiment.
[0009] Figure 5 A diagram schematically illustrates the configuration of a memory cell array unit, a driver circuit, and an address allocation circuit included in a memory device according to an embodiment.
[0010] Figure 6 This is a diagram schematically showing a configuration example of a connection relationship setting circuit and the like included in an address allocation circuit of a memory device according to an embodiment.
[0011] Figure 7This is a diagram schematically showing a configuration example of a connection relationship setting circuit and the like included in an address allocation circuit of a memory device according to an embodiment.
[0012] Figure 8 This is a diagram schematically showing a configuration example of a connection relationship setting circuit and the like included in an address allocation circuit of a memory device according to an embodiment.
[0013] Figure 9 This is a diagram schematically showing a configuration example of a connection relationship setting circuit and the like included in an address allocation circuit of a memory device according to an embodiment.
[0014] Figure 10 This is a flowchart showing the operation of the storage device according to the embodiment.
[0015] Figure 11 It is a diagram showing a process for detecting a short-circuit failure in the storage device according to the embodiment.
[0016] Figure 12 This is a block diagram showing the configuration of a modified example of the storage device according to the embodiment.
[0017] Description of labels
[0018] 100 ...memory cell array portion
[0019] 101a, 102a ...areas where normal wiring is provided
[0020] Area outside 101b, 102b...
[0021] 110L…lower wiring 110U…upper wiring
[0022] 111... First wiring 111a... Normal wiring 111b... Redundant wiring
[0023] 112...Second wiring 112a...Normal wiring 112b...Redundant wiring
[0024] 120…storage unit
[0025] 120a ...normal storage unit 120b ...redundant storage unit
[0026] 121…Magnetoresistive element (variable resistance memory element)
[0027] 122…Selector (switching element)
[0028] 200, 201, 202... driving circuit
[0029] 300, 301, 302…address allocation circuit
[0030] 301a…Connection relationship setting circuit
[0031] 400 ...Detection processing circuit 500 ...Redundancy control circuit
[0032] 1000…IC chip 2000…external controller
[0033] Ta, Ta1 to Ta8…input terminals Tb, Tb1 to Tb10…output terminals
[0034] Cn…Connecting member ST, ST1, ST2…Short-circuit part DETAILED DESCRIPTION
[0035] Hereinafter, embodiments will be described with reference to the drawings.
[0036] Figure 1 This is a block diagram showing the configuration of a storage device according to an embodiment.
[0037] Figure 1 The illustrated memory device includes a memory cell array unit 100 , a driver circuit 200 , an address allocation circuit 300 , a detection processing circuit 400 , and a redundancy control circuit 500 .
[0038] Figure 2 It is a perspective view schematically showing the structure of the memory cell array unit 100 .
[0039] like Figure 2 As shown, the memory cell array section 100 includes a plurality of lower wirings 110L each extending in the X direction, a plurality of upper wirings 110U each extending in the Y direction, and a plurality of memory cells 120 disposed between the plurality of lower wirings 110L and the plurality of upper wirings 110U. One of the lower wirings 110L and the upper wirings 110U corresponds to a word line, and the other of the lower wirings 110L and the upper wirings 110U corresponds to a bit line.
[0040] Each of the plurality of memory cells 120 includes a magnetoresistive effect element (variable resistance memory element (resistance change memory element)) 121 and a selector (switching element) 122 connected in series. The magnetoresistive effect element 121 and the selector 122 are stacked in the Z direction. Figure 2 In the example shown, the magnetoresistive effect element 121 is provided on the upper layer side of the selector 122 , but the magnetoresistive effect element 121 may be provided on the lower layer side of the selector 122 .
[0041] Furthermore, the X direction, the Y direction, and the Z direction are directions that intersect with each other. Specifically, the X direction, the Y direction, and the Z direction are orthogonal to each other.
[0042] Figure 3 1 is a cross-sectional view schematically showing the basic structure of the magnetoresistive effect element 121 .
[0043] like Figure 3 As shown, the magnetoresistive effect element 121 includes a storage layer (first magnetic layer) 121a, a reference layer (second magnetic layer) 121b and a tunnel barrier layer (non-magnetic layer) 121c, and has a structure in which the storage layer 121a, the reference layer 121b and the tunnel barrier layer 121c are stacked in the Z direction.
[0044] The storage layer 121a is a ferromagnetic layer with a variable magnetization direction. The reference layer 121b is a ferromagnetic layer with a fixed magnetization direction. The tunnel barrier layer 121c is an insulating layer provided between the storage layer 121a and the reference layer 121b. A variable magnetization direction means that the magnetization direction changes with respect to a predetermined write current. A fixed magnetization direction means that the magnetization direction remains unchanged with respect to a predetermined write current.
[0045] When the magnetization direction of the storage layer 121a is parallel to the magnetization direction of the reference layer 121b, the magnetoresistive element 121 is in a low-resistance state with a relatively low resistance. When the magnetization direction of the storage layer 121a is antiparallel to the magnetization direction of the reference layer 121b, the magnetoresistive element 121 is in a high-resistance state with a relatively high resistance. Therefore, the magnetoresistive element 121 can store binary data depending on its resistance state.
[0046] also, Figure 3 The magnetoresistance effect element 121 shown is a bottom free type magnetoresistance effect element in which the storage layer 121a is located on the lower layer side of the reference layer 121b, but a top free type magnetoresistance effect element in which the storage layer 121a is located on the upper layer side of the reference layer 121b can also be used.
[0047] Figure 4 It is a cross-sectional view schematically showing the basic structure of the selector 122.
[0048] The selector 122 is a two-terminal switching element including a lower electrode 122a, an upper electrode 122b and a selector material layer 122c, and has the characteristic of changing from an off state (OFF) to an on state (ON) when the voltage applied between the two terminals (between the lower electrode 122a and the upper electrode 122b) becomes greater than a threshold voltage.
[0049] When a voltage is applied between the selected lower wiring 110L and the selected upper wiring 110U and a voltage greater than the threshold voltage is applied to the selected selector 122 included in the selected storage cell 120, current flows through the selected magnetoresistive effect element 121 connected in series with the selected selector 122, and the selected magnetoresistive effect element 121 can be read or written.
[0050] Figure 5 Schematically illustrates the configuration of the memory cell array unit 100 , the driver circuit 200 , and the address allocation circuit 300 .
[0051] like Figure 5 As shown, the memory cell array portion 100 includes a plurality of first wirings 111, a plurality of second wirings 112, and a plurality of memory cells 120 connected between the plurality of first wirings 111 and the plurality of second wirings 112. Figure 2 The second wiring 112 corresponds to one of the lower wiring 110L and the upper wiring 110U shown. Figure 2 The memory cell 120 corresponds to the other of the lower wiring 110L and the upper wiring 110U shown. Figure 2 The storage unit 120 shown corresponds to .
[0052] The plurality of first wirings 111 include a plurality of normal wirings 111a and at least one redundant line 111b. Similarly, the plurality of second wirings 112 include a plurality of normal wirings 112a and at least one redundant line 112b. The plurality of memory cells 120 include a plurality of normal memory cells 120a and a plurality of redundant memory cells 120b.
[0053] The plurality of normal wirings 111a are regular first wirings 111. The at least one redundant line 111b is a first wiring 111 other than the plurality of normal wirings 111a. Like the normal redundant lines, it is a backup first wiring 111 used when the plurality of normal wirings 111a include defective wiring. In this embodiment, the at least one redundant line 111b is used when the plurality of normal wirings 111a include short-circuited wirings.
[0054] The plurality of normal wirings 112a and the at least one redundant line 112b are similar to the plurality of normal wirings 111a and the at least one redundant line 111b described above.
[0055] At least one redundant line 111b is entirely provided in a region 101b outside the region 101a where the plurality of normal wirings 111a are provided, and at least one redundant line 112b is entirely provided in a region 102b outside the region 102a where the plurality of normal wirings 112a are provided.
[0056] The driver circuit 200 includes a driver circuit 201 and a driver circuit 202 . The driver circuit 201 generates a driver signal to be supplied to the memory cells 120 via the first wirings 111 , and the driver circuit 202 generates a driver signal to be supplied to the memory cells 120 via the second wirings 112 .
[0057] By supplying a selection signal from the driving circuit 201 to the selected first wiring 111 and supplying a selection signal from the driving circuit 202 to the selected second wiring 112, the selected storage unit 120 connected between the selected first wiring 111 and the selected second wiring 112 becomes conductive, and the selected storage unit 120 can be written or read.
[0058] The address allocation circuit 300 includes an address allocation circuit 301 and an address allocation circuit 302. The address allocation circuit 301 is provided between the driver circuit 201 and the plurality of first wirings 111, and allocates addresses to the plurality of first wirings 111. The address allocation circuit 302 is provided between the driver circuit 202 and the plurality of second wirings 112, and allocates addresses to the plurality of second wirings 112.
[0059] In this embodiment, when multiple short-circuited wirings are included among the multiple first wirings 111, the address allocation circuit 301 assigns a common address to the multiple short-circuited wirings. Specifically, when multiple short-circuited wirings are included among the multiple normal wirings 111a, the address allocation circuit 301 assigns a common address to the multiple short-circuited wirings. A short circuit failure is an inter-line failure (bridging failure) that occurs between adjacent first wirings 111. Therefore, the multiple short-circuited wirings are first wirings 111 arranged continuously.
[0060] Similarly, when the plurality of second wirings 112 include a plurality of short-circuited wirings that are short-circuited to one another, the address allocation circuit 302 allocates a common address to the plurality of short-circuited wirings. Specifically, when the plurality of normal wirings 112a include a plurality of short-circuited wirings that are short-circuited to one another, the address allocation circuit 302 allocates a common address to the plurality of short-circuited wirings. Regarding the second wirings 112, the plurality of short-circuited wirings are also continuously arranged second wirings 112.
[0061] The following describes an example configuration and functions of the address allocation circuit 300. For simplicity, the following describes the address allocation circuit 301, but the address allocation circuit 302 also has the same configuration and functions as the address allocation circuit 301.
[0062] Figure 6 as well as Figure 7 Each of them schematically shows a configuration example of the connection relationship setting circuit 301 a and the like included in the address allocation circuit 301 . Figure 6 The case where the plurality of first wirings 111 (specifically, the plurality of normal wirings 111 a ) do not include short-circuited wirings that short-circuit each other is shown. Figure 7 The case where the plurality of first wirings 111 (specifically, the plurality of normal wirings 111 a ) include short-circuited wirings that are short-circuited to each other is shown.
[0063] like Figure 6 as well as Figure 7 As shown, the connection relationship setting circuit 301a includes a plurality of input terminals Ta (Ta1 to Ta8), a plurality of output terminals Tb (Tb1 to Tb10), and a plurality of connection members Cn, and sets the connection relationship between the plurality of input terminals Ta and the plurality of output terminals Tb.
[0064] The driving signals supplied to the plurality of memory cells 120 via the plurality of first wirings 111 are input to the plurality of input terminals Ta. Figure 5 The driving circuit 201 shown supplies driving signals to the plurality of input terminals Ta. The plurality of output terminals Tb outputs the driving signals input to the plurality of input terminals Ta to the plurality of first wirings 111. The connection relationship between the plurality of input terminals Ta and the plurality of output terminals Tb is appropriately set by the plurality of connection members Cn.
[0065] The connection relationship setting circuit 301 a includes, for example, a plurality of fuses, and can set the connection relationship between the plurality of input terminals Ta and the plurality of output terminals Tb by adjusting the connection relationship using the plurality of fuses.
[0066] like Figure 6 As shown, when the plurality of normal wirings 111a do not include short-circuiting wiring that shorts each other, the plurality of input terminals Ta1 to Ta8 are connected to the plurality of output terminals Tb1 to Tb8 via the plurality of connection members Cn, respectively, and the output terminals Tb9 and Tb10 are not used. In other words, only the normal wirings 111a are used, and the redundant wires 111b are not used.
[0067] like Figure 7 As shown in FIG. 1 , in the case where a plurality of normal wirings 111a include short-circuited wirings that short-circuit each other, the plurality of short-circuited wirings ( Figure 7 That is, a common address is assigned to two adjacent short-circuit wirings (two adjacent normal wirings 111a) short-circuited by the short-circuit portion ST, and a common drive signal is supplied to the two adjacent short-circuit wirings.
[0068] Specifically, in Figure 7In the example shown, one of the two short-circuit wirings is used as the first short-circuit wiring, and the other of the two short-circuit wirings is used as the second short-circuit wiring. The output terminal Tb5 provided for the first short-circuit wiring among the multiple output terminals Tb1 to Tb8 is connected to one input terminal Ta4 among the multiple input terminals Ta1 to Ta8, and the output terminal Tb4 provided for the second short-circuit wiring among the multiple output terminals Tb1 to Tb8 is not connected to the above-mentioned one input terminal Ta4.
[0069] The two short-circuit wirings (the first short-circuit wiring and the second short-circuit wiring) are electrically connected to each other via the short-circuit portion ST. Therefore, a common address is assigned to the two short-circuit wirings via the input terminal Ta4, and a common drive signal is supplied to the two short-circuit wirings.
[0070] In addition, Figure 7 In the example shown, the input terminal Ta8 is connected to the output terminal Tb9 provided for the redundant line 111b. Thus, the driving signal input to the input terminal Ta8 is supplied to the redundant line 111b connected to the output terminal Tb9.
[0071] As can be seen from the above, in this embodiment, instead of using two redundant lines 111b to replace two short-circuit wirings, a common address is assigned to the two short-circuit wirings, thereby reducing the number of redundant lines 111b used for redundancy processing.
[0072] Here, the memory cell provided between the first short-circuit wiring and one second wiring is referred to as the first memory cell, and the memory cell provided between the second short-circuit wiring and the above-mentioned one second wiring is referred to as the second memory cell. As described above, in the present embodiment, a common address is assigned to the first short-circuit wiring and the second short-circuit wiring. Therefore, when a common drive signal (selection signal) is supplied to the first short-circuit wiring and the second short-circuit wiring, either the first memory cell or the second memory cell becomes selectable. The first memory cell and the second memory cell are controlled by a common address, and therefore, both the first memory cell and the second memory cell cannot be selected, and only one of the first memory cell and the second memory cell needs to be selected. In the present embodiment, only one of the first memory cell and the second memory cell can be selected for the following reasons.
[0073] The selection voltage (threshold voltage) of a memory cell varies from memory cell to memory cell. Therefore, only the memory cell with the lower threshold voltage of the first or second memory cell is selected as the usable memory cell. Specifically, during the forming process performed during initialization, only one of the first or second memory cell is selected for the forming process. During writing or reading, only the memory cell that has undergone the forming process functions as the usable memory cell.
[0074] Figure 8 Schematically shows another configuration example of the connection relationship setting circuit 301 a and the like included in the address allocation circuit 301 .
[0075] exist Figure 8 In the example shown, the output terminal Tb5 provided for the first short-circuit wiring among the plurality of output terminals Tb1 to Tb8 is connected to one input terminal Ta4 among the plurality of input terminals Ta1 to Ta8, and the output terminal Tb4 provided for the second short-circuit wiring among the plurality of output terminals Tb1 to Tb8 is also connected to the above-mentioned one input terminal Ta4. Figure 7 The structure shown is the same.
[0076] In this case, Figure 7 Similarly to the example of , a common address is assigned to two adjacent short-circuit wirings (a first short-circuit wiring and a second short-circuit wiring) via the input terminal Ta4, and a common drive signal is supplied to the two adjacent short-circuit wirings.
[0077] In this example, both the output terminal Tb5 provided for the first short-circuit wiring and the output terminal Tb4 provided for the second short-circuit wiring are connected to one input terminal Ta4. Therefore, a common drive signal can be more reliably supplied to the two short-circuit wirings (the first short-circuit wiring and the second short-circuit wiring).
[0078] Figure 9 Schematically shows still another configuration example of the connection relationship setting circuit 301 a and the like included in the address allocation circuit 301 .
[0079] exist Figure 9 In the example shown, three consecutively arranged first wiring lines 111 are short-circuited with one another. Specifically, the plurality of first wiring lines 111 also includes a third short-circuited wiring line that short-circuits the first and second short-circuited wiring lines. Specifically, the adjacent first and second short-circuited wiring lines are short-circuited by a short-circuit portion ST1, and the adjacent first and third short-circuited wiring lines are short-circuited by a short-circuit portion ST2.
[0080] In this example, a common address is assigned to three consecutively arranged short-circuit wirings (first, second, and third short-circuit wirings) via the input terminal Ta4, and a common drive signal is supplied to the three consecutively arranged short-circuit wirings.
[0081] In this example, input terminal Ta7 is connected to output terminal Tb9, and input terminal Ta8 is connected to output terminal Tb10. Thus, a drive signal input to input terminal Ta7 is supplied to redundant line 111b connected to output terminal Tb9, and a drive signal input to input terminal Ta8 is supplied to redundant line 111b connected to output terminal Tb10.
[0082] In addition, Figure 9 In the example shown, the output terminal Tb5 provided for the first short-circuit wiring is connected to the input terminal Ta4, and the output terminal Tb4 provided for the second short-circuit wiring and the output terminal Tb6 provided for the third short-circuit wiring are not connected to the input terminal Ta4, but it is also possible to connect two or more of the output terminals Tb4, Tb5 and Tb6 to the input terminal Ta4.
[0083] return Figure 1 Description, Figure 1 In the illustrated memory device, the detection processing circuit 400 and the redundancy control circuit 500 are built into the same integrated circuit chip 1000 that includes the memory cell array unit 100 , the driver circuit 200 , and the address allocation circuit 300 .
[0084] The detection processing circuit 400 performs short circuit detection processing on the plurality of first wirings 111 (specifically, the plurality of normal wirings 111 a ) and short circuit detection processing on the plurality of second wirings 112 (specifically, the plurality of normal wirings 112 a ).
[0085] Specifically, the detection processing circuit 400 detects whether the plurality of first wirings 111 include short-circuited wirings that short-circuit one another. If so, it detects which of the plurality of first wirings 111 is short-circuited (detects the location of the short-circuited wiring). The same is true for the plurality of second wirings 112.
[0086] The above-described detection processing operation performed by the detection processing circuit 400 can be performed after the integrated circuit chip 1000 is packaged.
[0087] The redundancy control circuit 500 performs redundancy control. Specifically, based on the detection results of the detection processing circuit 400, the redundancy control circuit 500 controls the connection relationship setting operation performed by the connection relationship setting circuit 301a included in the address allocation circuit 301. In other words, the redundancy control circuit 500 controls the connection relationship setting operation between the multiple input terminals Ta and the multiple output terminals Tb within the connection relationship setting circuit 301a. The address allocation circuit 302 is similarly controlled by the redundancy control circuit 500.
[0088] The above-mentioned redundancy control operation performed by the redundancy control circuit 500 can be performed after the integrated circuit chip 1000 is packaged.
[0089] Next, refer to Figure 10 The flowchart shown in FIG. 1 illustrates the operation of this embodiment. Specifically, the initialization operation of the aforementioned storage device is described. For simplicity, the following description uses the operation on the first wiring 111 as an example. The same operation is also performed on the second wiring 112.
[0090] First, after the integrated circuit chip 1000 is packaged, a short circuit detection process is performed by the detection processing circuit 400 ( S11 ), that is, a self-test for short circuit failure is performed within the integrated circuit chip 1000 .
[0091] Figure 11 This figure shows the detection process for a short circuit failure. Specifically, it shows the potential (a1, a2) of the selected first wiring 111 and the potential (b) of the selected second wiring 112 when current flows between the selected first wiring 111 and the selected second wiring 112.
[0092] When there is no short circuit, a normal current flows between the selected first wiring 111 and the selected second wiring 112 via the selected memory cell. Therefore, the potential of the selected first wiring 111 is ensured to rise, resulting in characteristics (a1). In contrast, when there is a short circuit, current flows between adjacent short-circuited wirings (between the selected first wiring 111 and the unselected first wiring 111 adjacent to the selected first wiring 111). Therefore, the potential of the selected first wiring 111 does not rise, resulting in characteristics (a2). Therefore, by detecting the potential of the selected first wiring 111, short circuit detection is possible.
[0093] Next, it is determined whether a short circuit failure is detected ( S12 ).
[0094] When no short circuit failure is detected, the connection relationship setting circuit 301a is Figure 6 In the state shown, no redundant processing is performed and the initial setting operation is completed.
[0095] If a short circuit is detected, it is determined whether the number of redundant lines 111b is excessive (overflow) (S13). In other words, if the number of short-circuited wiring lines is large, the number of redundant lines 111b may be insufficient. In this case, it is determined to be excessive, and the redundant processing is not performed, and the initial setting operation is terminated.
[0096] If the number of redundant lines 111b is not excessive, the redundant processing (S14) already described is performed, and the process returns to step S11 to perform the short-circuit detection process again.
[0097] As described above, in this embodiment, instead of replacing all short-circuited wirings with redundant lines as in the conventional method, a common address is assigned to a plurality of short-circuited wirings that short-circuit each other and used. This can reduce the number of redundant lines used for redundant processing.
[0098] Figure 12 This is a block diagram showing the configuration of a modified example of the storage device according to the present embodiment.
[0099] In the above-mentioned embodiment, the detection processing circuit 400 and the redundant control circuit 500 are built into the integrated circuit chip 1000 including the memory cell array unit 100, the driving circuit 200 and the address allocation circuit 300, but in this variant example, the detection processing circuit 400 and the redundant control circuit 500 are not built into the integrated circuit chip 1000, but are arranged in the external controller 2000.
[0100] In this variation, the basic configuration of the memory cell array unit 100, the driver circuit 200, and the address allocation circuit 300 is the same as that of the aforementioned embodiment. Furthermore, the operations performed by the detection processing circuit 400 and the redundancy control circuit 500 are also the same as those of the aforementioned embodiment. Therefore, this variation also achieves the same effects as those of the aforementioned embodiment.
[0101] Furthermore, in the above-described embodiment and modified examples, the short-circuit detection process and redundancy process are performed after the integrated circuit chip 1000 is packaged. However, these processes may also be performed before packaging. Specifically, the above-described processes may be performed before the plurality of integrated circuit chips 1000 are separated from the semiconductor wafer, and then the plurality of integrated circuit chips 1000 may be separated from the semiconductor wafer and packaged.
[0102] In the above embodiment, as the address allocation circuit 301, a circuit including Figures 6 to 9 Although the connection relationship setting circuit 301a is shown in FIG. 1 , any other structure may be used as long as a common address is assigned to the short-circuited wirings when the first wirings 111 include short-circuited wirings. The same applies to the address assignment circuit 302.
[0103] Furthermore, in the above-described embodiment, a magnetoresistive element is used as the variable resistance memory element, but other variable resistance memory elements may be used.
[0104] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the gist of the invention. These embodiments and / or their variations are included within the scope and gist of the invention, and are included within the invention set forth in the claims and their equivalents.
Claims
1. A storage device comprising: a plurality of first wirings, each extending in a first direction; a plurality of second wirings, each extending in a second direction intersecting the first direction; a plurality of memory cells provided between the plurality of first wirings and the plurality of second wirings, each including a variable resistance memory element and a switch element connected in series; as well as The address allocation circuit allocates addresses to the plurality of first wirings. It is characterized by: When the plurality of first wirings include a first short-circuit wiring and a second short-circuit wiring that are short-circuited to each other, the address allocation circuit allocates a common address to the first short-circuit wiring and the second short-circuit wiring.
2. The storage device according to claim 1, wherein Also features: a plurality of input terminals to which drive signals supplied to the plurality of memory cells via the plurality of first wirings are input; and a plurality of output terminals for outputting the drive signals input to the plurality of input terminals to the plurality of first wirings; The address allocation circuit includes a connection relationship setting circuit that sets a connection relationship between the plurality of input terminals and the plurality of output terminals.
3. The storage device according to claim 2, wherein: The connection relationship setting circuit connects a first output terminal provided for the first short-circuit wiring among the plurality of output terminals to one input terminal among the plurality of input terminals, and does not connect a second output terminal provided for the second short-circuit wiring among the plurality of output terminals to the one input terminal.
4. The storage device according to claim 2, wherein: The connection relationship setting circuit connects a first output terminal provided for the first short-circuit wiring among the plurality of output terminals to one input terminal among the plurality of input terminals, and connects a second output terminal provided for the second short-circuit wiring among the plurality of output terminals to the one input terminal.
5. The storage device according to claim 1, wherein When the plurality of first wirings further include a third short-circuit wiring that short-circuits the first short-circuit wiring and the second short-circuit wiring, the address allocation circuit allocates a common address to the first short-circuit wiring, the second short-circuit wiring, and the third short-circuit wiring. The storage device according to claim 1 , wherein: A memory cell among the plurality of memory cells that is disposed between the first short-circuit wiring and one of the plurality of second wirings is referred to as a first memory cell, and a memory cell among the plurality of memory cells that is disposed between the second short-circuit wiring and one of the plurality of second wirings is referred to as a second memory cell, and one of the first memory cell and the second memory cell functions as a usable unit.
7. The storage device according to claim 1, wherein: The plurality of first wirings include a plurality of normal wirings and at least one redundant line used when the plurality of normal wirings include short-circuited wirings that short-circuit each other.
8. The storage device according to claim 7, wherein: The at least one redundant line is provided in a region outside a region where the plurality of normal wirings are provided.
9. The storage device according to claim 1, wherein: A detection processing circuit is further provided. The detection processing circuit is built into a chip including the plurality of first wirings, the plurality of second wirings, the plurality of memory cells, and the address allocation circuit, and performs a detection process for a short-circuit failure in the plurality of first wirings.
10. The storage device according to claim 9, wherein: The detection processing performed by the detection processing circuit can be performed after the chip is packaged.
11. The storage device according to claim 1, wherein: A redundancy control circuit is further provided. The redundancy control circuit is built into a chip including the plurality of first wirings, the plurality of second wirings, the plurality of memory cells, and the address allocation circuit, and performs redundancy control.
12. The storage device according to claim 11, wherein: The redundancy control performed by the redundancy control circuit can be performed after the chip is packaged.
13. The storage device according to claim 1, wherein: The variable resistance memory element and the switching element are stacked in a third direction intersecting the first direction and the second direction.
14. The storage device according to claim 1, wherein: The variable resistance memory element is a magnetoresistive effect element.
15. The storage device according to claim 1, wherein: The switching element is a two-terminal switching element having a characteristic of switching from an off state to an on state when a voltage applied between the two terminals becomes equal to or higher than a threshold voltage.