Semiconductor structure and forming method thereof
By using a second sacrificial layer of non-homogeneous material in a 3D memory and adjusting the wet etching rate to control the remaining size of the conductive plate structure, the problem of leakage between the conductive plate structures is solved, and the working performance and integration of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202510807436.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-16
- Publication Date
- 2025-09-19
AI Technical Summary
It is difficult to guarantee the working performance between the conductive plate structures in the 3D memory with the existing technology, especially when the wet etching process easily causes leakage between the longitudinally adjacent conductive plate structures.
A non-homogeneous material is used as the second sacrificial layer, and its wet etching rate is adjusted to be different from the part close to the through-hole sidewall to the part far from the through-hole sidewall. By adjusting the etching rate change, the remaining size of the second sacrificial layer is controlled, the probability of peeling at the contact position between the dielectric layer and the second sacrificial layer is reduced, and the working performance of the semiconductor structure is guaranteed.
The leakage probability between longitudinally adjacent conductive plate structures is effectively reduced, and the working performance and integration of the semiconductor structure are improved.
Smart Images
Figure CN120676646A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] The structure of 3D memory is composed of multiple conductive plates (plates) and dielectric layers stacked crosswise, interspersed with a large number of conductive pillars (pillars) that are wide at the top and narrow at the bottom. The surface where the conductive plates and pillars meet is arranged as an upper electrode – capacitor material – lower electrode. The upper electrode connects to the upper conductor within the conductive plate, while the lower electrode connects to the lower conductor within the conductive pillar. 3D memory uses a plate-last process, where the conductive pillars are first completed, and then wet etching is used to contact the sacrificial material layers corresponding to each layer of the conductive plates through the grooves near the conductive pillar matrix. The sacrificial material layers are then removed, and the conductive plate material is then filled to form the conductive plate. Summary of the Invention
[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to ensuring the working performance of the semiconductor structure.
[0004] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top in a longitudinal direction; forming a plurality of through holes penetrating the stacked structure; forming a second sacrificial layer covering the sidewalls of the through holes, wherein the material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material varies from a portion close to the sidewall of the through hole to a portion away from the sidewall of the through hole; forming a conductive pillar structure filling the through hole, the conductive pillar structure covering the second sacrificial layer; removing all first sacrificial layers in the stacked structure to form a plurality of first trenches spaced apart in the longitudinal direction, the first trenches being surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each first trench to form a second trench exposing the sidewall of the conductive pillar structure, the second trench being connected to the first trench to form a third trench; forming a dielectric layer covering each side surface and bottom surface of the third trench; and forming a conductive plate structure filling the third trench, the conductive plate structure covering the dielectric layer.
[0005] Accordingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; a conductive stack located on the substrate, the conductive stack comprising dielectric layers and conductive plate structures stacked alternately in a longitudinal direction from bottom to top; a plurality of conductive column structures running through the conductive stack; a dielectric layer covering each surface of the conductive plate structure and located between the conductive plate structure and the conductive column structure; a second sacrificial layer located between the dielectric layer and the conductive column structure, the material of the second sacrificial layer being a non-homogeneous material, and the wet etching rate of the material from a portion far from the conductive column structure to a portion close to the conductive column structure is different.
[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0007] In the formation method provided in an embodiment of the present invention, a second sacrificial layer covering the sidewall of the through-hole is formed. The material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material from the portion close to the through-hole sidewall to the portion far from the through-hole sidewall is different. In the embodiment of the present invention, the material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material from the portion close to the through-hole sidewall to the portion far from the through-hole sidewall is different. That is, in the step of removing the exposed portion of the second sacrificial layer along each first trench, the etching rate of the second sacrificial layer from the portion close to the through-hole sidewall to the portion far from the through-hole sidewall is different. This is conducive to adjusting the morphology of the second sacrificial layer remaining after removing the exposed portion of the second sacrificial layer along each first trench by adjusting the change in the lateral etching rate of the second sacrificial layer. That is, the size of the second sacrificial layer remaining between longitudinally adjacent conductive plate structures can be flexibly adjusted, which is conducive to ensuring that the second sacrificial layer remaining between longitudinally adjacent conductive plate structures meets actual performance requirements, thereby facilitating the working performance of the semiconductor structure.
[0008] In an optional scheme, in the step of forming a second sacrificial layer covering the side wall of the through-hole, the density of the second sacrificial layer gradually decreases from the portion close to the side wall of the through-hole to the portion far from the side wall of the through-hole, so as to achieve a gradually increasing wet etching rate, or the element doping concentration of the second sacrificial layer changes gradiently from the portion close to the side wall of the through-hole to the portion far from the side wall of the through-hole, so as to achieve a gradually increasing wet etching rate; in an embodiment of the present invention, the etching rate of the portion close to the side wall of the through-hole with a larger density is slower, and the etching rate of the portion far from the side wall of the through-hole with a smaller density is faster, or the element doping concentration is adjusted, the etching rate of the portion close to the side wall of the through-hole is slower, and the etching rate of the portion far from the side wall of the through-hole is faster, and at the same time, the removal step starts from the process of the position of the second sacrificial layer close to the side wall of the through-hole and ends at the position far from the side wall of the through-hole, then the process time for the position of the second sacrificial layer close to the side wall of the through-hole is longer, and the process time for the position far from the side wall of the through-hole is shorter. The time is short, so that although the position of the second sacrificial layer close to the side wall of the through hole has a longer process damage time in the longitudinal direction, the process damage rate is slow. Although the position of the second sacrificial layer away from the side wall of the through hole has a faster process damage rate in the longitudinal direction, the process damage time is short, which is beneficial to making the damage consistency of the remaining second sacrificial layer at various positions in the transverse direction better, so that the end surface flatness of the remaining second sacrificial layer in the transverse direction is higher, and it is beneficial to making the damage of the remaining second sacrificial layer at various positions in the transverse direction smaller, so that the overall damage of the remaining second sacrificial layer in the longitudinal direction is smaller, which is beneficial to increasing the size of the remaining second sacrificial layer between the conductive plate structures adjacent in the longitudinal direction, and correspondingly beneficial to reducing the probability of peeling at the contact position between the dielectric layer and the second sacrificial layer when removing the exposed second sacrificial layer along the first groove, thereby reducing the probability of leakage between the conductive plate structures adjacent in the longitudinal direction, and ensuring the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figures 1 to 8 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0010] Figures 9 to 17 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;
[0011] Figure 18 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION
[0012] As can be seen from the background art, it is currently difficult to guarantee the working performance of semiconductor structures. The reasons why the working performance of semiconductor structures still needs to be guaranteed are now analyzed in conjunction with a semiconductor structure.
[0013] Figures 1 to 8 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0014] refer to Figure 1 A substrate 10 is provided, on which a stacked structure 20 is formed. The stacked structure 20 includes dielectric layers 21 and first sacrificial layers 22 alternately stacked longitudinally from bottom to top. A conductive block structure 11 is formed in the substrate 10, and the conductive block structure 11 is exposed on the top surface of the substrate 10; a plurality of through holes 23 are formed through the stacked structure 20, and the through holes 23 expose the conductive block structure 11.
[0015] refer to Figure 2 , forming a sacrificial material layer 31 covering the sidewall and bottom of the through hole 23 and the top of the stacked structure 20; and forming a protective material layer 32 covering the sacrificial material layer 31.
[0016] refer to Figure 3 , remove the sacrificial material layer 31 and the protective material layer 32 at the bottom of the through hole 23 and the top of the stacked structure 20, retain the sacrificial material layer 31 covering the side wall of the through hole 23 as the second sacrificial layer 33, and retain the protective material layer 32 covering the side wall of the through hole 23 as the protective layer 34.
[0017] refer to Figure 4 , remove the protective layer 34.
[0018] refer to Figure 5 , forming a conductive pillar structure 40 that fills the through hole 23 and covers the second sacrificial layer 33 .
[0019] After removing the protective layer 34 , the corner morphology of the second sacrificial layer 33 will be left at the bottom of the through hole 23 , and the size of the contact position between the bottom of the conductive column structure 40 and the conductive block structure 11 will be reduced, resulting in a larger contact resistance between the conductive column structure 40 and the conductive block structure 11 .
[0020] refer to Figure 6 , the first sacrificial layer 22 is removed, forming a first trench 51 surrounded by the longitudinally adjacent dielectric layers 21. It should be understood that the first sacrificial layer 22 is removed by a wet etching process, and before the wet etching process, at least one opening is formed through the stacked structure 20, allowing the etching solution to etch and remove the first sacrificial layer 22 through this opening.
[0021] refer to Figure 7 , Figure 7 (b) After removal Figure 7 (a) A partial enlarged schematic diagram of the position of the dotted box, showing that the exposed portion of the second sacrificial layer 33 is removed along the first trench 51 to form a second trench 52 that exposes a portion of the sidewall of the conductive pillar structure 40. The second trench 52 and the first trench 51 are connected to form a third trench 53.
[0022] Typically, a wet etching process is used to remove the exposed portion of the second sacrificial layer 33 along the first trench 51, such as Figure 7As shown in (b), due to the isotropy of the wet etching process, the loss (Loss) of the remaining second sacrificial layer 33 in the longitudinal direction is almost equal to twice the thickness of the second sacrificial layer 33, which easily leads to a smaller remaining size of the second sacrificial layer 33 in the longitudinal direction. After the conductive plate structure is subsequently formed in the third groove 53, it is easy to cause leakage between the conductive plate structures adjacent to each other in the longitudinal direction, thereby affecting the working performance of the semiconductor structure.
[0023] refer to Figure 8 , forming a dielectric layer 60 covering the side surfaces and bottom surface of the third trench 53 ; and forming a conductive plate structure 50 filling the third trench 53 and covering the dielectric layer 60 .
[0024] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top in a longitudinal direction; forming a plurality of through holes penetrating the stacked structure; forming a second sacrificial layer covering the sidewalls of the through holes, wherein the material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material varies from a portion close to the sidewall of the through hole to a portion far from the sidewall of the through hole; forming a conductive pillar structure filling the through hole, the conductive pillar structure covering the second sacrificial layer; removing all first sacrificial layers in the stacked structure to form a plurality of first trenches spaced apart in the longitudinal direction, the first trenches being surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each first trench to form a second trench exposing a portion of the sidewall of the conductive pillar structure, the second trench being connected to the first trench to form a third trench; forming a dielectric layer covering each side surface and bottom surface of the third trench; and forming a conductive plate structure filling the third trench, the conductive plate structure covering the dielectric layer.
[0025] In an embodiment of the present invention, the material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material from the portion close to the side wall of the through-hole to the portion away from the side wall of the through-hole is different. That is, in the step of removing the exposed portion of the second sacrificial layer along each first groove, the etching rate of the second sacrificial layer from the portion close to the side wall of the through-hole to the portion away from the side wall of the through-hole is different. This is beneficial for adjusting the morphology of the remaining second sacrificial layer after removing the exposed portion of the second sacrificial layer along each first groove by adjusting the change in the rate of lateral etching of the second sacrificial layer. That is, the size of the remaining second sacrificial layer between longitudinally adjacent conductive plate structures can be flexibly adjusted, which is beneficial for making the remaining second sacrificial layer between longitudinally adjacent conductive plate structures meet actual performance requirements, and thus is beneficial for ensuring the working performance of the semiconductor structure.
[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0027] Figures 9 to 171 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0028] refer to Figure 9 , providing a substrate 100, on which a laminated structure 200 is formed, the laminated structure 200 including a longitudinal direction (such as Figure 9 The dielectric layers 210 and the first sacrificial layers 220 are alternately stacked from bottom to top (as shown in the Z direction).
[0029] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure of the present invention.
[0030] In this embodiment, the substrate 100 is a semiconductor substrate. For example, the substrate 100 may include other semiconductor structures. The material of the film layer in contact with the substrate 100 and the stacked structure 200 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the film layer in contact with the substrate 100 and the stacked structure 200 is silicon oxide.
[0031] The stacked structure 200 is used to subsequently form a conductive pillar structure and a conductive plate structure.
[0032] It should be noted that, in this embodiment, the bottom layer and the top layer of the stacked structure 200 are both dielectric layers 210 .
[0033] Specifically, the first sacrificial layer 220 is used to occupy a space for the subsequent formation of a conductive plate structure.
[0034] In this embodiment, the material of the first sacrificial layer 220 includes silicon nitride.
[0035] In this embodiment, the thickness of the first sacrificial layer 220 is 10 nm to 200 nm, which provides sufficient space for the subsequent formation of the conductive plate structure, while ensuring that the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.
[0036] The dielectric layer 210 is used to subsequently isolate longitudinally adjacent conductive plate structures.
[0037] In this embodiment, the material of the dielectric layer 210 includes silicon oxide.
[0038] Using silicon nitride to form the first sacrificial layer 220 and using silicon oxide to form the dielectric layer 210 is advantageous in that during the subsequent wet etching process to remove the first sacrificial layer 220 , the etching solution causes minimal or almost no damage to the dielectric layer 210 .
[0039] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.
[0040] In this embodiment, in the step of providing the substrate 100 , a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .
[0041] The conductive block structure 110 is used for subsequent electrical connection with the conductive pillar structure.
[0042] refer to Figure 10 , forming a plurality of through holes 230 penetrating the stacked structure 200 .
[0043] The through hole 230 is used to provide a space for the subsequent formation of a conductive pillar structure.
[0044] Accordingly, in this embodiment, in the step of forming a through hole 230 penetrating the stacked structure 200 using a dry etching process, the through hole 230 exposes the conductive block structure 110, so that the conductive column structure subsequently formed in the through hole 230 contacts the conductive block structure 110 for electrical connection.
[0045] In this embodiment, through-hole 230 is used to form a conductive pillar structure. The opening size of through-hole 230 is between 10 nm and 80 nm. The smaller the size of through-hole 230, the more difficult it is to form. However, the smaller the size of through-hole 230, the more conducive it is to achieving a higher integration density in the semiconductor structure. It should be understood that due to the limitations of existing photolithography equipment, the size of through-hole 230 cannot be further reduced. If a smaller conductive pillar structure is required, other methods must be used to further reduce the size of through-hole 230.
[0046] Combined with reference Figure 11 and Figure 12 , forming a second sacrificial layer 330 covering the sidewall of the through hole 230. The material of the second sacrificial layer 330 is a non-homogeneous material, and the wet etching rate of the material from the part close to the sidewall of the through hole 230 to the part far from the sidewall of the through hole 230 is different.
[0047] After the conductive column structure is subsequently formed in the through hole 230, when the first sacrificial layer 220 is removed, the second sacrificial layer 330 is used to protect the side wall of the conductive column structure. Moreover, in order to completely remove the first sacrificial layer 220, it is usually necessary to increase the excessive etching time, so that the second sacrificial layer 330 can better protect the conductive column structure during this etching process.
[0048] In this embodiment, the material of the second sacrificial layer 330 is a non-homogeneous material, and the wet etching rate of the material from the portion close to the sidewall of the through hole 230 to the portion away from the sidewall of the through hole 230 is different. That is, in the subsequent step of removing the exposed portion of the second sacrificial layer 220 along each first trench, the etching rate of the second sacrificial layer 220 from the portion close to the sidewall of the through hole 230 to the portion away from the sidewall of the through hole 230 is different, which is beneficial to adjust the lateral (such as Figure 12 The morphology of the remaining second sacrificial layer 330 after removing the exposed portion of the second sacrificial layer 330 along each first trench can be adjusted by changing the etching rate (as shown in the X direction). That is, the size of the remaining second sacrificial layer 330 between the subsequently formed longitudinally adjacent conductive plate structures can be flexibly adjusted, which is beneficial for ensuring that the remaining second sacrificial layer 330 between the longitudinally adjacent conductive plate structures meets actual performance requirements, thereby helping to ensure the working performance of the semiconductor structure.
[0049] In this embodiment, in the step of forming the second sacrificial layer 330 covering the sidewall of the through hole 230 , the material of the second sacrificial layer 330 is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.
[0050] Silicon oxide, amorphous silicon, silicon nitride and titanium nitride are easy to adjust the wet etching rate and can subsequently provide good protection for the conductive column structure.
[0051] The material of the second sacrificial layer 330 is described below in two embodiments.
[0052] The following is a first embodiment.
[0053] In this embodiment, the material of the second sacrificial layer 330 is a non-homogeneous material with different densities. The different densities of the material from the portion close to the sidewall of the through hole 230 to the portion far from the sidewall of the through hole 230 achieve different wet etching rates.
[0054] By using different densities, different wet etching rates can be achieved in the same wet etching process with the same concentration. Specifically, the smaller the density, the greater the wet etching rate that can be achieved.
[0055] In this embodiment, in the step of forming the second sacrificial layer 330 covering the sidewall of the through hole 230, the density of the second sacrificial layer 330 gradually decreases from the part close to the sidewall of the through hole 230 to the part away from the sidewall of the through hole 230, so as to achieve a gradually increasing wet etching rate.
[0056] For wet etching solution of the same concentration, the wet etching rate decreases as the film density increases. Therefore, the density of the second sacrificial layer 330 gradually decreases from the part close to the side wall of the through hole 230 to the part away from the side wall of the through hole 230, so as to achieve a gradually increasing wet etching rate.
[0057] Specifically, refer to Figure 11 The step of forming a second sacrificial layer 330 covering the sidewalls of the through hole 230 includes: forming a sacrificial material layer 310 covering the sidewalls and bottom of the through hole 230 and the top of the stacked structure 200, and the density of the sacrificial material layer 310 gradually decreases from the part close to the sidewall of the through hole 230 to the part away from the sidewall of the through hole 230, so as to achieve a gradually increasing wet etching rate.
[0058] The sacrificial material layer 310 is used to form a second sacrificial layer 330 .
[0059] In this embodiment, in the step of forming a sacrificial material layer 310 covering the side walls and bottom of the through hole 230 and the top of the stacked structure 200, the material of the sacrificial material layer 310 is silicon oxide, and the sacrificial material layer 310 is formed by a chemical vapor deposition process or a furnace tube process. The process temperature for forming the sacrificial material layer 310 is adjusted to increase with the increase of the process time, so that the density of the sacrificial material layer 310 gradually decreases from the part close to the side wall of the through hole 230 to the part away from the side wall of the through hole 230.
[0060] The sacrificial material layer 310 is grown through a chemical vapor deposition process or a furnace tube process, and the process temperature can be controlled. As the process temperature increases, the density of the sacrificial material layer 310 can be reduced, and the growth rate of the sacrificial material layer 310 can also increase. When the sacrificial material layer 310 grows, the growth rate of the sacrificial material layer 310 can be calculated to achieve that the density of the sacrificial material layer 310 becomes lower as the growth thickness increases.
[0061] In this embodiment, in the step of adjusting the process temperature of forming the sacrificial material layer 310 to increase with the increase of process time, the process temperature ranges from 300° C. to 600° C., so that the process is easy to control.
[0062] The following is a second embodiment.
[0063] In this embodiment, the material of the second sacrificial layer 330 is a non-homogeneous material with different doping element concentrations. The different doping element concentrations from the part close to the sidewall of the through hole 230 to the part far from the sidewall of the through hole 230 achieve different wet etching rates.
[0064] By adopting different concentrations of doping elements, different wet etching rates of the material can be achieved when wet etching is performed using the same etching solution under the same process parameter conditions. Specifically, for some specific wet etching solutions, the lower the doping element concentration, the higher the wet etching rate can be achieved. For other specific wet etching solutions, the higher the doping element concentration, the higher the wet etching rate can be achieved.
[0065] In this embodiment, the element doping concentration of the second sacrificial layer 330 changes gradually from the portion close to the sidewall of the through hole 230 to the portion far from the sidewall of the through hole 230 , so as to achieve a gradually increasing wet etching rate.
[0066] For wet etching chemical solution of the same concentration, the wet etching rate increases with the gradient of element doping concentration. Therefore, the element doping concentration of the second sacrificial layer 330 changes gradually from the part close to the side wall of the through hole 230 to the part away from the side wall of the through hole 230, so as to achieve a gradually increasing wet etching rate.
[0067] Specifically, refer to Figure 11 The step of forming a second sacrificial layer 330 covering the sidewalls of the through hole 230 includes: forming a sacrificial material layer 310 covering the sidewalls and bottom of the through hole 230 and the top of the stacked structure 200, and the element doping concentration of the sacrificial material layer 310 changes gradually from the part close to the sidewall of the through hole 230 to the part away from the sidewall of the through hole 230, so as to achieve a gradual increase in the wet etching rate.
[0068] The sacrificial material layer 310 is used to form a second sacrificial layer 330 .
[0069] In this embodiment, in the step of forming a sacrificial material layer 310 covering the sidewalls and bottom of the through hole 230 and the top of the stacked structure 200, the material of the sacrificial material layer 310 is silicon oxide doped with boron or phosphorus, and the sacrificial material layer 310 is formed by a chemical vapor deposition process or a furnace tube process. The element doping concentration of the sacrificial material layer 310 is adjusted to increase with the increase of process time, so that the element doping concentration of the sacrificial material layer 310 gradually decreases from the part close to the sidewall of the through hole 230 to the part away from the sidewall of the through hole 230, so that the wet etching rate gradually increases.
[0070] The sacrificial material layer 310 is grown and doped with elements through a chemical vapor deposition process or a furnace tube process. As the element doping concentration increases, the element doping concentration of the sacrificial material layer 310 can gradually increase from close to the side wall of the through hole 230 to far away from the side wall of the through hole 230, the porosity of the film becomes worse, and the growth rate also increases accordingly. When the sacrificial material layer 310 grows, the film growth rate can be calculated to realize that the porosity of the film becomes worse as the growth thickness increases, so that the wet etching rate gradually increases.
[0071] As can be seen from the foregoing, in this embodiment, the etching rate of the portion close to the side wall of the through hole 230 with a larger density is slower, and the etching rate of the portion away from the side wall of the through hole 230 with a smaller density is faster. Alternatively, the element doping concentration is adjusted so that the etching rate of the portion close to the side wall of the through hole 230 is slower, and the etching rate of the portion away from the side wall of the through hole 230 is faster. At the same time, the removal step starts from the process of the position of the second sacrificial layer 330 close to the side wall of the through hole 230 and ends at the position away from the side wall of the through hole 230. Then, the process time for the position of the second sacrificial layer 230 close to the side wall of the through hole is longer, and the process time for the position away from the side wall of the through hole 230 is shorter, so that although the process damage time of the second sacrificial layer 330 close to the side wall of the through hole 230 is longer in the longitudinal direction, the process damage rate is slower, and the second sacrificial layer 330 away from the through hole has a longer longitudinal process damage time. Although the process damage rate of the position of the side wall 230 along the longitudinal direction is faster, the process damage time is shorter, which is beneficial to making the damage consistency of the remaining second sacrificial layer 330 at various positions along the lateral direction better, so that the end surface flatness of the remaining second sacrificial layer 330 along the lateral direction is higher, and it is beneficial to making the damage of the remaining second sacrificial layer 330 at various positions along the lateral direction smaller, so that the overall damage of the remaining second sacrificial layer 330 along the longitudinal direction is smaller, which is beneficial to increase the size of the remaining second sacrificial layer 330 between the conductive plate structures adjacent in the longitudinal direction, and correspondingly, when the exposed second sacrificial layer 330 is subsequently removed along the first groove, the probability of peeling at the contact position between the dielectric layer and the second sacrificial layer 330 is reduced, and thus it is beneficial to reduce the probability of leakage between the conductive plate structures adjacent in the longitudinal direction, thereby ensuring the working performance of the semiconductor structure.
[0072] refer to Figure 12 , the sacrificial material layer 310 at the bottom of the through hole 230 and the top of the stacked structure 200 is removed, and the sacrificial material layer 310 covering the sidewall of the through hole 230 is retained as the second sacrificial layer 330 .
[0073] The sacrificial material layer 310 at the bottom of the through hole 230 and the top of the stacked structure 200 is removed to expose the conductive block structure 110 in preparation for the subsequent formation of the conductive column structure.
[0074] In this embodiment, before removing the sacrificial material layer 310 at the bottom of the through hole 230 and the top of the stacked structure 200 , the process further includes forming a protective layer 340 covering the sacrificial material layer 310 on the sidewalls of the through hole 230 .
[0075] The protective layer 340 is used to protect the sacrificial material layer 310 on the side wall of the through hole 230 during the process of removing the sacrificial material layer 310 at the bottom of the through hole 230 and the top of the stacked structure 200, so as to reduce damage to the second sacrificial layer 330 on the side wall of the sub-through hole 230 and avoid the formation of pinhole defects (pin holes) in the side wall sacrificial layer 330. The protective layer 340 is also used to protect the conductive column structure together with the second sacrificial layer 330 when the first sacrificial layer 220 is subsequently removed.
[0076] In this embodiment, the material of the protection layer 340 includes silicon nitride.
[0077] Continue to refer Figure 11 The step of forming the protection layer 340 covering the sacrificial material layer 310 on the sidewall of the through hole 230 includes: forming a protection material layer 320 covering the sacrificial material layer 310 .
[0078] The protective material layer 320 is used to form a protective layer 340 .
[0079] Continue to refer Figure 12 , the protective material layer 320 at the bottom of the through hole 230 and the top of the stacked structure 200 is removed, and the protective material layer 320 of the sacrificial material layer 310 covering the sidewall of the through hole 230 is retained as the protective layer 340 .
[0080] refer to Figure 13 Before forming the conductive pillar structure filling the through hole 230 , the process further includes: removing the protective layer 340 .
[0081] In other embodiments, the protection layer 340 may not be removed.
[0082] refer to Figure 14 , forming a conductive pillar structure 400 filling the through hole 230 , and the conductive pillar structure 400 covers the second sacrificial layer 330 .
[0083] The conductive pillar structure 400 is used as a conductive pillar in a 3D memory.
[0084] Accordingly, in this embodiment, in the step of forming the conductive pillar structure 400 filling the through hole 230 and covering the second sacrificial layer 330 , the conductive pillar structure 400 is in contact with the conductive block structure 110 to be electrically connected.
[0085] Specifically, in this embodiment, the conductive column structure 400 includes a lower electrode covering the sidewalls and bottom of the through hole 230, and a lower conductive line filling the through hole 230 and covering the lower electrode. The lower electrode and the lower conductive line subsequently form a capacitor structure with the upper electrode and the upper conductive line.
[0086] It should be noted that, in this embodiment, the outer diameter of the conductive column structure 400 is regulated by controlling the thickness of the second sacrificial layer 330 / and the protective layer 340, so that when the size of the through hole 230 reaches the device limit, the second sacrificial layer 330 / and the protective layer 340 can be formed to occupy part of the space to achieve shrinkage, and a smaller conductive column structure 400 can be formed.
[0087] Correspondingly, in other embodiments, in the step of forming the conductive pillar structure filling the through hole and covering the second sacrificial layer, the conductive pillar structure covers the protection layer 340 .
[0088] refer to Figure 15 , all the first sacrificial layers 220 in the stacked structure 200 are removed to form a plurality of first trenches 510 arranged at intervals in the longitudinal direction, and the first trenches 510 are surrounded by the dielectric layers 210 adjacent to each other in the longitudinal direction.
[0089] The first trench 510 is used to provide a space for the subsequent formation of a conductive plate structure.
[0090] In this embodiment, a wet etching process is used to remove all of the first sacrificial layer 220 in the stacked structure 200. It should be understood that the wet etching process is used to remove the first sacrificial layer 220, and before the wet etching process, at least one opening is formed through the stacked structure 200, allowing the etching solution to etch and remove the first sacrificial layer 220 through this opening.
[0091] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing all the first sacrificial layers 220 . The wet etching process can easily achieve a large etching selectivity, thereby reducing damage to other film layers when removing the first sacrificial layer 220 .
[0092] refer to Figure 16 , Figure 16 (b) to Figure 16 (e) Figure 16 (a) shows various enlarged schematic diagrams of the parts at the dotted box position, where the exposed portion of the second sacrificial layer 330 is removed along each first trench 510 to form a second trench 520 exposing a portion of the sidewall of the conductive pillar structure 400. The second trench 520 is connected to the first trench 510 to form a third trench 530.
[0093] The second trench 520 is connected to the first trench 510 to form a third trench 530 , which is used to provide a spatial location for the subsequent formation of a conductive plate structure.
[0094] It should be noted that Figure 16 (b) to Figure 16 The morphology of the second sacrificial layer 330 in (e) is not limited to Figure 16 At the dotted box in (a), Figure 16The longitudinal morphology of each second sacrificial layer 330 in (a) can be Figure 16 (b) to Figure 16 (e).
[0095] Specifically, in this embodiment, Figure 16 As shown in (b), the second sacrificial layer 330 has a horizontal morphology along the longitudinal end surface; or Figure 16 As shown in (c), the end surface of the second sacrificial layer 330 in the longitudinal direction presents a morphology that tilts inward from away from the conductive pillar structure 400 to close to the conductive pillar structure 400, and the angle α1 of the end surface tilt is 0° to 30°; or Figure 16 As shown in (d), the end surface of the second sacrificial layer 330 in the longitudinal direction presents a morphology that tilts inward from close to the conductive pillar structure 400 to away from the conductive pillar structure 400, and the angle α1 of the end surface tilt is 0° to 45°; or Figure 16 As shown in (e), the longitudinal end surface of the second sacrificial layer 330 presents an arc shape that is concave inward from close to the conductive column structure 400 to away from the conductive column structure 400, and the angle α3 between the tangent line of the arc end and the longitudinal direction is 0° to 60°.
[0096] In this embodiment, a wet etching process is used to remove the exposed portion of the second sacrificial layer 330 along each first trench 510 to form a second trench 520 that exposes a portion of the sidewall of the conductive pillar structure 400 .
[0097] The wet etching process can easily achieve a large etching selectivity ratio, thereby reducing damage to other film layers when removing a portion of the second sacrificial layer 330 .
[0098] As an example, in this embodiment, when the material of the second sacrificial layer 330 is silicon oxide, the etching solution of the wet etching process is hydrofluoric acid.
[0099] Accordingly, in other embodiments, the step of removing the exposed portion of the second sacrificial layer along the first trench to form the second trench exposing a portion of the sidewall of the conductive pillar structure further includes: removing the exposed portion of the protective layer along each first trench.
[0100] The exposed portion of the protection layer is removed along the first trench to expose the sidewall of the conductive pillar structure.
[0101] refer to Figure 17 , forming a dielectric layer 600 covering the side surfaces and bottom surface of the third trench 530 ; forming a conductive plate structure 500 filling the third trench 530 , and the conductive plate structure 500 covering the dielectric layer 600 .
[0102] The conductive plate structure 500 is used as a conductive plate in a 3D memory, and the dielectric layer 600 is used as a storage capacitor material in the memory.
[0103] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 and an upper conductive line filling the third trench 530 and covering the upper electrode. The upper electrode and the upper conductive line together with the dielectric layer, the lower electrode and the lower conductive line form a capacitor structure.
[0104] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 400 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 400.
[0105] Figure 18 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention.
[0106] refer to Figure 18 , Figure 18 (b) to Figure 18 (e) Figure 18 (a) Various partial enlarged schematic diagrams at the dotted box position, where, for the sake of clarity, Figure 18 (b) to Figure 18 (e) The dielectric layer 600 and the conductive plate structure 500 are not shown. The semiconductor structure includes: a substrate 100; a conductive stack 201 located on the substrate 100, and the conductive stack 201 includes a longitudinal direction (such as Figure 18 The dielectric layer 210 and the conductive plate structure 500 are alternately stacked from bottom to top (as shown in the Z direction); a plurality of conductive pillar structures 400, wherein the conductive pillar structure 400 penetrates the conductive stack 201; a dielectric layer 600, covering the side surfaces and bottom surface of the conductive plate structure 500 and being located between the conductive plate structure 500 and the conductive pillar structure 400; a second sacrificial layer 330, covering part of the sidewall of the conductive pillar structure 400 and being located between the dielectric layer 210 and the conductive pillar structure 400. The material of the second sacrificial layer 330 is a non-homogeneous material, and the wet etching rate of the material from the part away from the conductive pillar structure 400 to the part close to the conductive pillar structure 400 is different.
[0107] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure of the present invention.
[0108] In this embodiment, the substrate 100 is a semiconductor substrate. For example, the substrate 100 may include other semiconductor structures. The film layer in contact with the substrate 100 and the stacked structure 200 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the film layer in contact with the substrate 100 and the stacked structure 200 is silicon oxide.
[0109] The conductive stack 201 is used to form a plurality of conductive plate structures 500 spaced apart in the longitudinal direction.
[0110] The conductive plate structure 500 is used as a conductive plate in a 3D memory.
[0111] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 , and an upper conductive line filled between longitudinally adjacent dielectric layers 210 and covering the upper electrode.
[0112] The dielectric layer 210 is used to isolate longitudinally adjacent conductive plate structures 500 .
[0113] In this embodiment, the material of the dielectric layer 210 includes silicon oxide.
[0114] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.
[0115] It should be noted that, in this embodiment, the bottommost layer and the topmost layer of the conductive stack 201 are both the dielectric layer 210 .
[0116] In this embodiment, a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .
[0117] The conductive block structure 110 is used to be electrically connected to the conductive pillar structure 400 .
[0118] The conductive pillar structure 400 is used as a conductive pillar in a 3D memory.
[0119] In this embodiment, the conductive pillar structure 400 includes a lower conductive line penetrating the conductive stack 201 and a lower electrode covering the sidewall and bottom of the lower conductive line. The lower electrode and the lower conductive line form a capacitor structure together with the dielectric layer, the upper electrode and the upper conductive line.
[0120] It should be noted that, in this embodiment, the outer diameter of the conductive column structure 400 is regulated by controlling the thickness of the second sacrificial layer 330 / and the protective layer 340, so that when the size of the through hole used to form the conductive column structure 400 reaches the limit of the equipment, the second sacrificial layer 330 / and the protective layer 340 formed can occupy part of the space to achieve shrinkage, and a smaller conductive column structure 400 can be formed.
[0121] Accordingly, in this embodiment, the conductive pillar structure 400 penetrates the conductive stack 201 and contacts the conductive block structure 110 to be electrically connected.
[0122] The dielectric layer 600 is used as a storage capacitor material in the memory.
[0123] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 400 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 400.
[0124] In the semiconductor manufacturing process, a stacked structure in which a dielectric layer 210 and a first sacrificial layer are alternately stacked is first formed, and then a conductive pillar structure 400 is formed that penetrates the stacked structure. At this time, the second sacrificial layer covers the sidewalls of the conductive pillar structure 400. The first sacrificial layer is then removed to expose the second sacrificial layer 330. Subsequently, a portion of the second sacrificial layer 330 is removed, leaving the second sacrificial layer 330 between the dielectric layer 210 and the conductive pillar structure 400. Finally, a conductive plate structure 500 is formed at the original location of the first sacrificial layer. To this end, when the first sacrificial layer is removed, the second sacrificial layer 330 is used to protect the sidewalls of the conductive pillar structure 400. Moreover, in order to completely remove the first sacrificial layer, it is usually necessary to increase the etching time excessively, so that the second sacrificial layer 330 can better protect the conductive pillar structure 400 during this etching process.
[0125] In this embodiment, the material of the second sacrificial layer 330 is a non-homogeneous material, and the wet etching rate of the material from the portion away from the conductive pillar structure 400 to the portion close to the conductive pillar structure 400 is different. That is, in the step of removing the exposed portion of the second sacrificial layer 220 in the semiconductor process, the etching rate of the second sacrificial layer 220 from the portion away from the conductive pillar structure 400 to the portion close to the conductive pillar structure 400 is different, which is conducive to adjusting the lateral (such as) etching rate of the second sacrificial layer 330. Figure 18 The morphology of the remaining second sacrificial layer 330 after removing the exposed portion of the second sacrificial layer 330 can be adjusted by changing the etching rate (as shown in the X direction). That is, the size of the second sacrificial layer 330 remaining between the subsequently formed longitudinally adjacent conductive plate structures 500 can be flexibly adjusted, which is beneficial for ensuring that the second sacrificial layer 330 remaining between the longitudinally adjacent conductive plate structures 500 meets actual performance requirements, thereby ensuring the working performance of the semiconductor structure.
[0126] In this embodiment, in the step of forming the second sacrificial layer 330 covering the sidewall of the through hole 230 , the material of the second sacrificial layer 330 is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.
[0127] Silicon oxide, amorphous silicon, silicon nitride and titanium nitride are easy to adjust the wet etching rate and can subsequently provide good protection for the conductive column structure.
[0128] In this embodiment, the thickness of the second sacrificial layer 330 is 1 nm to 25 nm.
[0129] The thickness of the second sacrificial layer 330 is 1 nm to 25 nm, which simplifies the process of forming the second sacrificial layer 330 while ensuring the protection of the second sacrificial layer 330 on the conductive pillar structure 400 .
[0130] The material of the second sacrificial layer 330 is described below in two embodiments.
[0131] The following is a first embodiment.
[0132] In this embodiment, the material of the second sacrificial layer 330 is a non-homogeneous material with different densities. The different densities of the material from the portion far from the conductive pillar structure 400 to the portion close to the conductive pillar structure 400 result in different wet etching rates.
[0133] By using different densities, different wet etching rates can be achieved in the same wet etching process with the same concentration. Specifically, the smaller the density, the greater the wet etching rate that can be achieved.
[0134] In this embodiment, the density of the second sacrificial layer 330 gradually decreases from the portion away from the conductive pillar structure 400 to the portion close to the conductive pillar structure 400, so as to achieve a gradually increasing wet etching rate.
[0135] For wet etching chemicals of the same concentration, the wet etching rate decreases as the film density increases. Therefore, the density of the second sacrificial layer 330 gradually decreases from the part away from the conductive column structure 400 to the part close to the conductive column structure 400, so as to achieve a gradually increasing wet etching rate.
[0136] The following is a second embodiment.
[0137] In this embodiment, the second sacrificial layer 330 is made of a heterogeneous material with different doping element concentrations. The different doping element concentrations from the portion away from the conductive pillar structure 400 to the portion close to the conductive pillar structure 400 achieve different wet etching rates.
[0138] By adopting different concentrations of doping elements, different wet etching rates can be achieved in the same wet etching process with the same concentration. Specifically, for some specific wet etching solutions, the lower the concentration of the doping element, the higher the wet etching rate can be achieved. For other specific wet etching solutions, the higher the concentration of the doping element, the higher the wet etching rate can be achieved.
[0139] In this embodiment, the element doping concentration of the second sacrificial layer 330 changes in a gradient from a portion away from the conductive pillar structure 400 to a portion close to the conductive pillar structure 400 , so as to achieve a gradually increasing wet etching rate.
[0140] For wet etching solution of the same concentration, the wet etching rate increases with the gradient of the element doping concentration. Therefore, the element doping concentration of the second sacrificial layer 330 changes gradually from the part away from the conductive column structure 400 to the part close to the conductive column structure 400, so as to achieve a gradually increasing wet etching rate.
[0141] As can be seen from the foregoing, in this embodiment, in the semiconductor process, the etching rate of the portion with a larger density away from the side wall of the conductive column structure 400 is slower, and the etching rate of the portion with a smaller density close to the side wall of the conductive column structure 400 is faster, or, by adjusting the element doping concentration, the etching rate of the portion away from the side wall of the conductive column structure 400 is slower, and the etching rate of the portion close to the side wall of the conductive column structure 400 is faster. At the same time, the removal step starts from the position of the second sacrificial layer 330 away from the side wall of the conductive column structure 400 and ends at the position close to the side wall of the conductive column structure 400. Then, the process time for the position of the second sacrificial layer 230 away from the side wall of the conductive column structure 400 is longer, and the process time for the position close to the side wall of the conductive column structure 400 is shorter, so that although the process damage time along the longitudinal direction of the position of the second sacrificial layer 330 away from the side wall of the conductive column structure 400 is longer, the process damage is reduced. The damage rate is slow. Although the position of the second sacrificial layer 330 close to the side wall of the conductive pillar structure 400 has a faster process damage rate in the longitudinal direction, the process damage time is short, which is beneficial to making the damage consistency of the remaining second sacrificial layer 330 in various positions in the transverse direction better, so that the end surface flatness of the remaining second sacrificial layer 330 in the transverse direction is higher, and it is beneficial to making the damage of the remaining second sacrificial layer 330 in various positions in the transverse direction smaller, so that the overall damage of the remaining second sacrificial layer 330 in the longitudinal direction is smaller, which is beneficial to increasing the size of the remaining second sacrificial layer 330 between the conductive plate structures 500 adjacent in the longitudinal direction, and correspondingly, when removing the exposed second sacrificial layer 330, it is beneficial to reduce the probability of peeling at the contact position between the dielectric layer 210 and the second sacrificial layer 330, thereby reducing the probability of leakage between the conductive plate structures 500 adjacent in the longitudinal direction, and ensuring the working performance of the semiconductor structure.
[0142] Specifically, in this embodiment, Figure 18 As shown in (b), the second sacrificial layer 330 has a horizontal morphology along the longitudinal end surface; or Figure 18 As shown in (c), the end surface of the second sacrificial layer 330 in the longitudinal direction presents a morphology that tilts inward from away from the conductive pillar structure 400 to close to the conductive pillar structure 400, and the angle α1 of the end surface tilt is 0° to 30°; or Figure 18 As shown in (d), the end surface of the second sacrificial layer 330 in the longitudinal direction presents a morphology that tilts inward from close to the conductive pillar structure 400 to away from the conductive pillar structure 400, and the angle α1 of the end surface tilt is 0° to 45°; or Figure 18As shown in (e), the longitudinal end surface of the second sacrificial layer 330 presents an arc shape that is concave inward from close to the conductive column structure 400 to away from the conductive column structure 400, and the angle α3 between the tangent line of the arc end and the longitudinal direction is 0° to 60°.
[0143] It should be noted that Figure 18 (b) to Figure 18 The morphology of the second sacrificial layer 330 in (e) is not limited to Figure 18 At the dotted box in (a), Figure 18 The longitudinal morphology of each second sacrificial layer 330 in (a) can be Figure 18 (b) to Figure 18 (e).
[0144] In other embodiments, a protection layer is further formed between the second sacrificial layer and the conductive pillar structure.
[0145] The protective layer is used to protect the second sacrificial layer on the side wall of the conductive column structure during the process of patterning the second sacrificial layer. The protective layer is also used to protect the conductive column structure together with the second sacrificial layer when removing the first sacrificial layer.
[0146] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top along a longitudinal direction; forming a plurality of through holes penetrating the laminate structure; forming a second sacrificial layer covering the sidewall of the through hole, wherein the material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material from a portion close to the sidewall of the through hole to a portion far from the sidewall of the through hole is different; forming a conductive pillar structure filling the through hole, wherein the conductive pillar structure covers the second sacrificial layer; removing all the first sacrificial layers in the stacked structure to form a plurality of first trenches spaced apart in a longitudinal direction, wherein the first trenches are surrounded by longitudinally adjacent dielectric layers; removing the exposed portion of the second sacrificial layer along each of the first trenches to form a second trench exposing a portion of the sidewall of the conductive pillar structure, wherein the second trench is connected to the first trench to form a third trench; forming a dielectric layer covering the side surfaces and bottom surface of the third trench; A conductive plate structure filling the third trench is formed, wherein the conductive plate structure covers the dielectric layer.
2. The forming method according to claim 1, wherein: The material of the second sacrificial layer is a heterogeneous material with different densities, and the density of the material varies from the portion close to the sidewall of the through hole to the portion far from the sidewall of the through hole, thereby achieving different wet etching rates; or, The material of the second sacrificial layer is a heterogeneous material with different doping element concentrations. The different doping element concentrations from the portion close to the through-hole sidewall to the portion far from the through-hole sidewall achieve different wet etching rates.
3. The forming method according to claim 2, wherein: In the step of forming a second sacrificial layer covering the sidewall of the through hole, the density of the second sacrificial layer gradually decreases from a portion close to the sidewall of the through hole to a portion far from the sidewall of the through hole, so as to achieve a gradually increasing wet etching rate; or, The element doping concentration of the second sacrificial layer changes in a gradient from a portion close to the sidewall of the through hole to a portion far away from the sidewall of the through hole, so as to achieve a gradually increasing wet etching rate.
4. The forming method according to claim 3, wherein: The step of forming a second sacrificial layer covering the sidewalls of the through-hole includes: forming a sacrificial material layer covering the sidewalls and bottom of the through-hole and the top of the stacked structure, wherein the density of the sacrificial material layer gradually decreases from a portion close to the sidewalls of the through-hole to a portion far from the sidewalls of the through-hole, so as to achieve a gradually increasing wet etching rate, or the element doping concentration of the sacrificial material layer changes in a gradient from a portion close to the sidewalls of the through-hole to a portion far from the sidewalls of the through-hole, so as to achieve a gradually increasing wet etching rate; The sacrificial material layer at the bottom of the through hole and the top of the stacked structure is removed, and the sacrificial material layer covering the sidewall of the through hole is retained as the second sacrificial layer.
5. The forming method according to claim 4, wherein: In the step of forming a second sacrificial layer covering the sidewall of the through hole, a material of the second sacrificial layer is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.
6. The forming method according to claim 5, wherein: In the step of forming a sacrificial material layer covering the sidewalls and bottom of the through hole and the top of the stacked structure, the material of the sacrificial material layer is silicon oxide, and the sacrificial material layer is formed by a chemical vapor deposition process or a furnace tube process. The process temperature for forming the sacrificial material layer is adjusted to increase with the increase of process time, so that the density of the sacrificial material layer gradually decreases from the part close to the sidewall of the through hole to the part away from the sidewall of the through hole.
7. The forming method according to claim 6, wherein: In the step of adjusting the process temperature of forming the sacrificial material layer to increase with the increase of process time, the process temperature ranges from 300° C. to 600° C.
8. The forming method according to claim 5, wherein: In the step of forming a sacrificial material layer covering the sidewalls and bottom of the through hole and the top of the stacked structure, the material of the sacrificial material layer is silicon oxide doped with boron or phosphorus, and the sacrificial material layer is formed by a chemical vapor deposition process or a furnace tube process. The element doping concentration of the sacrificial material layer is adjusted to increase with the increase of process time, so that the element doping concentration of the sacrificial material layer gradually decreases from the part close to the sidewall of the through hole to the part away from the sidewall of the through hole, so that the wet etching rate gradually increases.
9. The forming method according to claim 4, wherein: Before removing the sacrificial material layer at the bottom of the through hole and the top of the stacked structure, the method further includes: forming a protective layer of the sacrificial material layer covering the sidewalls of the through hole; Before forming the conductive pillar structure filling the through hole, the method further includes: removing the protective layer; or, In the step of forming a conductive pillar structure filling the through hole, the conductive pillar structure covers the protective layer; The step of removing the exposed portion of the second sacrificial layer along each of the first trenches to form a second trench exposing a portion of the sidewall of the conductive pillar structure further includes: removing the exposed portion of the protective layer along each of the first trenches.
10. The forming method according to claim 9, wherein: The step of forming a protective layer of the sacrificial material layer covering the sidewall of the through hole includes: forming a protective material layer covering the sacrificial material layer; The protective material layer at the bottom of the through hole and the top of the stacked structure is removed, and the protective material layer of the sacrificial material layer covering the sidewall of the through hole is retained as the protective layer.
11. The forming method according to claim 10, wherein: A wet etching process is used to remove the exposed portion of the second sacrificial layer along the first trench to form a second trench exposing a portion of the sidewall of the conductive pillar structure.
12. A semiconductor structure, characterized in that include: substrate; A conductive stack is located on the substrate, the conductive stack comprising dielectric layers and conductive plate structures alternately stacked in a longitudinal direction from bottom to top; A plurality of conductive pillar structures extending through the conductive stack; a dielectric layer covering each side surface and bottom surface of the conductive plate structure and located between the conductive plate structure and the conductive column structure; The second sacrificial layer covers a portion of the sidewall of the conductive column structure and is located between the dielectric layer and the conductive column structure. The material of the second sacrificial layer is a non-homogeneous material, and the wet etching rate of the material from the part far away from the conductive column structure to the part close to the conductive column structure is different.
13. The semiconductor structure according to claim 12, wherein: The material of the second sacrificial layer is a non-homogeneous material with different densities, and the density of the second sacrificial layer gradually decreases from the portion far away from the conductive column structure to the portion close to the conductive column structure, so as to achieve a gradually increasing wet etching rate, or the material of the second sacrificial layer is a non-homogeneous material with different doping element concentrations, and the element doping concentration of the second sacrificial layer changes gradiently from the portion far away from the conductive column structure to the portion close to the conductive column structure, so as to achieve a gradually increasing wet etching rate.
14. The semiconductor structure according to claim 13, wherein: The material of the second sacrificial layer is selected from any one of silicon oxide, amorphous silicon, silicon nitride and titanium nitride.
15. The semiconductor structure according to claim 13, wherein: The end surface of the second sacrificial layer along the longitudinal direction presents a horizontal morphology; Alternatively, the end surface of the second sacrificial layer in the longitudinal direction presents a morphology that tilts inward from away from the conductive pillar structure to close to the conductive pillar structure, and the tilt angle of the end surface is 0° to 30°; Alternatively, the end surface of the second sacrificial layer in the longitudinal direction presents a morphology that tilts inward from close to the conductive pillar structure to away from the conductive pillar structure, and the tilt angle of the end surface is 0° to 45°; Alternatively, the longitudinal end surface of the second sacrificial layer presents an arc shape that is concave inward from close to the conductive column structure to away from the conductive column structure, and the angle between the tangent line of the arc end and the longitudinal direction is 0° to 60°.
16. The semiconductor structure according to claim 12, wherein: A protective layer is further formed between the second sacrificial layer and the conductive pillar structure.