Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, forming a laminated structure on the substrate, and enabling the laminated structure to comprise dielectric layers and first sacrificial layers which are alternately stacked from bottom to top in the longitudinal direction; forming a plurality of through holes penetrating through the laminated structure; the end face, exposed out of the side wall of the through hole, of the first sacrificial layer transversely grows towards the interior of the through hole to form a second sacrificial layer, meanwhile, a conductive column containing hole is formed, and the size of the conductive column containing hole in the layer where the dielectric layer is located is larger than that of the conductive column containing hole in the layer where the first sacrificial layer is located; forming a conductive column structure for filling the conductive column accommodating hole; all the first sacrificial layers and the second sacrificial layers are removed, and a plurality of grooves which are formed by surrounding of longitudinally adjacent dielectric layers and are arranged at intervals in the longitudinal direction are formed; forming a dielectric layer covering each side surface and the bottom surface of the groove; a conductive plate structure filling the trench and covering the dielectric layer is formed. The electrical property and the application range of the semiconductor structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The structure of 3D memory is composed of multiple conductive plates (plates) and dielectric layers stacked crosswise, interspersed with a large number of conductive pillars (pillars) that are wide at the top and narrow at the bottom. The surface where the conductive plates and pillars meet is arranged as an upper electrode – capacitor material – lower electrode. The upper electrode connects to the upper conductor within the conductive plate, while the lower electrode connects to the lower conductor within the conductive pillar. 3D memory uses a plate-last process, where the conductive pillars are first completed, and then wet etching is used to contact the sacrificial material layers corresponding to each layer of the conductive plates through the grooves near the conductive pillar matrix. The sacrificial material layers are then removed, and the conductive plate layer material is then filled to form the conductive plates. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the electrical properties and wide application of the semiconductor structure.

[0004] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top in the longitudinal direction; forming a plurality of through holes penetrating the stacked structure; growing the end face of the first sacrificial layer exposed from the side wall of the through hole laterally toward the inside of the through hole to form a second sacrificial layer, and simultaneously forming a conductive column accommodating hole, wherein the size of the conductive column accommodating hole in the layer where the dielectric layer is located is larger than the size of the conductive column accommodating hole in the layer where the first sacrificial layer is located; forming a conductive column structure filling the conductive column accommodating hole; removing all the first sacrificial layers and the second sacrificial layers to form a plurality of grooves arranged at intervals in the longitudinal direction and surrounded by longitudinally adjacent dielectric layers; forming a dielectric layer covering the side surfaces and bottom surface of the grooves; and forming a conductive plate structure filling the grooves and covering the dielectric layer.

[0005] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate; a conductive stack located on the substrate, the conductive stack including dielectric layers and conductive plate structures stacked alternately in a longitudinal direction from bottom to top, a conductive column accommodating hole penetrating therein is formed, and at the side wall position of the conductive column accommodating hole, the conductive plate structure protrudes laterally toward the outside of the dielectric layer compared to the dielectric layer; a plurality of conductive column structures, the conductive column structures being filled in the conductive column accommodating holes; a plurality of dielectric layers spaced apart in the longitudinal direction, the dielectric layers covering each surface of the corresponding conductive structure plate, and being located between the conductive column structure and the conductive plate structure.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the formation method provided by the embodiment of the present invention, a plurality of through holes are formed that penetrate the stacked structure, and the end surface of the first sacrificial layer exposed by the side wall of the through hole grows laterally toward the inside of the through hole to form a second sacrificial layer, and at the same time, a conductive column accommodating hole is formed, and the size of the conductive column accommodating hole in the layer where the dielectric layer is located is larger than its size in the layer where the first sacrificial layer is located, forming a conductive column structure that fills the conductive column accommodating hole, and removing all the first sacrificial layers and the second sacrificial layers to form a plurality of grooves arranged in the longitudinal direction and spaced apart, forming a dielectric layer covering each side and bottom surface of the groove, and forming a conductive plate structure that fills the groove and covers the dielectric layer; In the embodiment of the present invention, the end surface of the first sacrificial layer exposed by the side wall of the through hole grows laterally toward the inside of the through hole to form a second sacrificial layer, and then the first sacrificial layer and The second sacrificial layer forms a conductive plate structure, that is, the first sacrificial layer and the second sacrificial layer are used together to occupy a spatial position for the conductive plate structure. By additionally forming a second sacrificial layer to occupy a position for the conductive plate structure, the size of the conductive column accommodating hole in the layer where the dielectric layer is located is larger than its size in the layer where the first sacrificial layer is located, thereby increasing the lateral size of the conductive plate structure, which is beneficial to improving the electrical properties of the conductive plate structure, thereby improving the electrical properties of the semiconductor structure. Moreover, the end face of the first sacrificial layer exposed by the side wall of the through hole grows laterally toward the inside of the through hole to form the second sacrificial layer, which can flexibly control the lateral size of the formed second sacrificial layer, which is correspondingly beneficial to flexible adjustment of the lateral size of the formed conductive plate structure, thereby improving the size adjustment freedom of the semiconductor structure, and thereby improving the application range of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 8 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0009] Figures 9 to 15 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0010] Figure 16 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] As can be seen from the background art, it is currently difficult to improve the electrical properties of semiconductor structures. The reasons why the electrical properties of semiconductor structures still need to be improved are now analyzed using a semiconductor structure.

[0012] Figures 1 to 8 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1A substrate 10 is provided, on which a stacked structure 20 is formed. The stacked structure 20 includes dielectric layers 21 and first sacrificial layers 22 alternately stacked longitudinally from bottom to top. A conductive block structure 11 is formed in the substrate 10, and the conductive block structure 11 is exposed on the top surface of the substrate 10; a plurality of through holes 23 are formed through the stacked structure 20, and the through holes 23 expose the conductive block structure 11.

[0014] refer to Figure 2 , forming a sacrificial material layer 31 covering the sidewall and bottom of the through hole 23 and the top of the stacked structure 20; and forming a protective material layer 32 covering the sacrificial material layer 31.

[0015] refer to Figure 3 , remove the sacrificial material layer 31 and the protective material layer 32 at the bottom of the through hole 23 and the top of the stacked structure 20, retain the sacrificial material layer 31 covering the side wall of the through hole 23 as the second sacrificial layer 33, and retain the protective material layer 32 covering the side wall of the through hole 23 as the protective layer 34.

[0016] refer to Figure 4 , remove the protective layer 34.

[0017] refer to Figure 5 , forming a conductive pillar structure 40 that fills the through hole 23 and covers the second sacrificial layer 33 .

[0018] After removing the protective layer 34 , the corner morphology of the second sacrificial layer 33 will remain at the bottom of the through hole 23 , which will reduce the size of the contact position between the bottom of the conductive column structure 40 and the conductive block structure 11 , resulting in a larger contact resistance between the conductive column structure 40 and the conductive block structure 11 .

[0019] refer to Figure 6 , the first sacrificial layer 22 is removed to form a first trench 51 surrounded by the longitudinally adjacent dielectric layers 21 .

[0020] refer to Figure 7 , Figure 7 (b) is the process of removal Figure 7 (a) A partial enlarged schematic diagram of the position of the dotted box, showing that the exposed portion of the second sacrificial layer 33 is removed along the first trench 51 to form a second trench 52 that exposes a portion of the sidewall of the conductive pillar structure 40. The second trench 52 and the first trench 51 are connected to form a third trench 53.

[0021] Typically, a wet etching process is used to remove the exposed portion of the second sacrificial layer 33 along the first trench 51, such as Figure 7As shown in (b), due to the isotropy of the wet etching process, the loss (Loss) of the remaining second sacrificial layer 33 in the longitudinal direction is almost equal to twice the thickness of the second sacrificial layer 33, which easily leads to a smaller remaining size of the second sacrificial layer 33 in the longitudinal direction. After the conductive plate structure is subsequently formed in the third groove 53, it is easy to cause leakage between the conductive plate structures adjacent to each other in the longitudinal direction, thereby affecting the working performance of the semiconductor structure.

[0022] refer to Figure 8 , forming a dielectric layer 60 covering the side surfaces and bottom surface of the third trench 53 ; and forming a conductive plate structure 50 filling the third trench 53 and covering the dielectric layer 60 .

[0023] The conductive plate structure 50 occupies a spatial position through the first sacrificial layer 22. The lateral size of the first sacrificial layer 22 is related to the aperture size of the through hole 23. The smaller the aperture size of the through hole 23, the larger the lateral size of the first sacrificial layer 22. However, due to the lithography limit of the lithography equipment, the aperture size of the through hole 23 cannot be infinitely reduced. The lateral size of the first sacrificial layer 22 is still not large enough, and the corresponding lateral size of the conductive plate structure 50 is also not large enough, making it difficult to improve the electrical properties of the semiconductor structure through the conductive plate structure 50.

[0024] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a stacked structure is formed, the stacked structure including dielectric layers and first sacrificial layers alternately stacked from bottom to top in the longitudinal direction; forming a plurality of through holes penetrating the stacked structure; the end face of the first sacrificial layer exposed from the side wall of the through hole grows laterally toward the inside of the through hole to form a second sacrificial layer, and at the same time forms a conductive column accommodating hole, the size of the conductive column accommodating hole in the layer where the dielectric layer is located being larger than the size of the conductive column accommodating hole in the layer where the first sacrificial layer is located; forming a conductive column structure filling the conductive column accommodating hole; removing all the first sacrificial layers and the second sacrificial layers to form a plurality of grooves arranged at intervals in the longitudinal direction surrounded by longitudinally adjacent dielectric layers; forming a dielectric layer covering the side surfaces and bottom surface of the grooves; and forming a conductive plate structure filling the grooves and covering the dielectric layer.

[0025] In an embodiment of the present invention, the end face of the first sacrificial layer exposed by the side wall of the through hole grows laterally toward the inside of the through hole to form a second sacrificial layer, and then the first sacrificial layer and the second sacrificial layer are removed to form a conductive plate structure, that is, the first sacrificial layer and the second sacrificial layer are used together to occupy a spatial position for the conductive plate structure, and the second sacrificial layer is additionally formed to occupy a position for the conductive plate structure. The size of the conductive column accommodating hole in the layer where the dielectric layer is located is larger than its size in the layer where the first sacrificial layer is located, thereby increasing the lateral size of the conductive plate structure, which is beneficial to improving the electrical properties of the conductive plate structure, thereby improving the electrical properties of the semiconductor structure. Moreover, the end face of the first sacrificial layer exposed by the side wall of the through hole grows laterally toward the inside of the through hole to form the second sacrificial layer, and the lateral size of the formed second sacrificial layer can be flexibly controlled, which is correspondingly beneficial to flexible adjustment of the lateral size of the formed conductive plate structure, thereby improving the size adjustment freedom of the semiconductor structure, and thereby improving the application range of the semiconductor structure.

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 9 to 15 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0028] refer to Figure 9 , providing a substrate 100, on which a laminated structure 200 is formed, the laminated structure 200 including a longitudinal direction (such as Figure 9 The dielectric layers 210 and the first sacrificial layers 220 are alternately stacked from bottom to top (as shown in the Z direction).

[0029] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0030] In this embodiment, the base 100 includes a semiconductor substrate, or a semiconductor substrate having a semiconductor structure formed thereon. The uppermost layer of the base 100 is a dielectric material layer. Specifically, the dielectric material layer includes silicon oxide or silicon nitride. As an example, in this embodiment, the dielectric material layer is made of silicon oxide.

[0031] The stacked structure 200 is used to subsequently form a conductive pillar structure and a conductive plate structure.

[0032] It should be noted that, in this embodiment, the bottom layer and the top layer of the stacked structure 200 are both dielectric layers 210 .

[0033] Specifically, the first sacrificial layer 220 is used to occupy a space for the subsequent formation of a conductive plate structure.

[0034] In this embodiment, the material of the first sacrificial layer 220 is selected from any one of silicon, germanium, silicon germanium and Group III-V semiconductor materials.

[0035] The material of the first sacrificial layer 220 is selected from any one of silicon, germanium, silicon germanium and Group III-V semiconductor materials, so that it is easy to subsequently grow a second sacrificial layer based on the first sacrificial layer 220 .

[0036] In this embodiment, the thickness of the first sacrificial layer 220 is 10 nm to 200 nm, which provides sufficient space for the subsequent formation of the conductive plate structure, while ensuring that the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0037] The dielectric layer 210 is used to subsequently isolate longitudinally adjacent conductive plate structures.

[0038] In this embodiment, the material of the dielectric layer 210 is silicon oxide or silicon nitride.

[0039] Using silicon oxide or silicon nitride to form the dielectric layer 210 is beneficial for ensuring that, during the subsequent removal of the first sacrificial layer 220, the first sacrificial layer 220 has a larger etching selectivity with respect to the dielectric layer 210, thereby reducing damage to the dielectric layer 210. Furthermore, when silicon oxide or silicon nitride is used to form the dielectric layer 210, when the second sacrificial layer is subsequently grown, the second sacrificial layer cannot grow on the dielectric layer 210, but only selectively grows on the first sacrificial layer 220.

[0040] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0041] In this embodiment, in the step of providing the substrate 100 , a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .

[0042] The conductive block structure 110 is used for subsequent electrical connection with the conductive pillar structure.

[0043] refer to Figure 10 , forming a plurality of through holes 240 penetrating the stacked structure 200 .

[0044] The through hole 240 is used to provide a space for the subsequent formation of a conductive pillar structure.

[0045] It should be noted that, in this embodiment, in the step of forming a plurality of through holes 240 passing through the stacked structure 200, the side walls of the through holes 240 have an inclination angle. As an example, in this embodiment, at the opening position of the through holes 240, the angle between the side walls of the through holes 240 and the horizontal direction is 70° to 90°.

[0046] Accordingly, in this embodiment, in the step of forming the through hole 240 penetrating the stacked structure 200 , the through hole 230 exposes the conductive block structure 110 , so that the conductive pillar structure subsequently formed in the through hole 240 contacts the conductive block structure 110 for electrical connection.

[0047] In this embodiment, the opening size of the through hole 240 is 10 nm to 80 nm, which reduces the difficulty of the process for forming the through hole 240 and is conducive to achieving a higher integration level of the semiconductor structure.

[0048] refer to Figure 11 , Figure 11 (b) to Figure 11 (e) Figure 11 (a) shows various partial enlarged schematic diagrams at the dotted line frame position, where the end surface of the first sacrificial layer 220 exposed by the side wall of the through hole 240 is along the horizontal direction (such as Figure 11 The second sacrificial layer 230 is grown into the through hole 240 (as shown in the X direction in (a)), and the conductive column accommodating hole 250 is formed at the same time. The size of the conductive column accommodating hole 250 in the layer where the dielectric layer 210 is located is larger than that in the layer where the first sacrificial layer 220 is located.

[0049] The second sacrificial layer 230 is used together with the first sacrificial layer 220 to occupy a space for the subsequent formation of a conductive plate structure.

[0050] In this embodiment, the end surface of the first sacrificial layer 220 exposed by the sidewall of the through hole 240 grows laterally into the through hole 240 to form the second sacrificial layer 230. The first sacrificial layer 220 and the second sacrificial layer 230 are then removed to form a conductive plate structure. That is, the first sacrificial layer 220 and the second sacrificial layer 230 together occupy the space for the conductive plate structure. By additionally forming the second sacrificial layer 230 to occupy the space for the conductive plate structure, the size of the conductive pillar receiving hole 250 in the layer where the dielectric layer 210 is located is larger than that in the layer where the first sacrificial layer 220 is located. This increases the lateral size of the subsequently formed conductive plate structure, which is beneficial for improving the electrical properties of the conductive plate structure and thus the electrical properties of the semiconductor structure. Furthermore, the end surface of the first sacrificial layer 220 exposed by the sidewall of the through hole 240 grows laterally into the through hole 240 to form the second sacrificial layer 230. This allows for flexible control of the lateral size of the formed second sacrificial layer 230, which in turn facilitates flexible adjustment of the lateral size of the formed conductive plate structure, thereby improving the dimensional adjustment freedom of the semiconductor structure and thereby increasing the wide range of applications of the semiconductor structure.

[0051] In this embodiment, an epitaxial growth process is used to grow the end surface of the first sacrificial layer 220 exposed from the sidewall of the through hole 240 toward the inside of the through hole 240 in a transverse direction to form the second sacrificial layer 230 .

[0052] The epitaxial growth process can selectively grow the second sacrificial layer 230 only on the cross-section of the first sacrificial layer 220, and will not grow the second sacrificial layer 230 on the dielectric layer 210. Therefore, when the second sacrificial layer 220 is subsequently removed, the isotropic properties of wet etching can be avoided, which will cause the film layer on which the dielectric layer 210 is located to be lost. Moreover, the epitaxial growth process can better control the process parameters, and the process controllability is high. It is easy to obtain a more accurate thickness dimension of the second sacrificial layer 230. The epitaxial growth process can also easily form a film layer with fewer impurities, so that the quality of the second sacrificial layer 230 is higher.

[0053] In this embodiment, in the step of growing the end face of the first sacrificial layer 220 exposed by the side wall of the through hole 240 laterally toward the inside of the through hole 240 to form the second sacrificial layer 230, the material of the first sacrificial layer 220 and the second sacrificial layer 230 is the same, and is selected from any one of silicon, germanium, silicon germanium and III-V semiconductor materials.

[0054] The first sacrificial layer 220 and the second sacrificial layer 230 are made of the same material, which is selected from any one of silicon, germanium, silicon germanium and Group III-V semiconductor materials, so that the second sacrificial layer 230 can be easily epitaxially grown on the first sacrificial layer 220, and when the first sacrificial layer 220 and the second sacrificial layer 230 are subsequently removed, the first sacrificial layer 220 and the second sacrificial layer 230 can be easily removed together.

[0055] In other embodiments, the second sacrificial layer may be made of a material different from that of the first sacrificial layer, and may be made of a material that can be epitaxially grown on the first sacrificial layer.

[0056] Specifically, in this embodiment, in the step of forming the second sacrificial layer 230 by growing the end surface of the first sacrificial layer 220 exposed from the side wall of the through hole 240 in the transverse direction toward the inside of the through hole 240, as shown in FIG. Figure 11 As shown in (b), the second sacrificial layer 230 has a rectangular cross-section along the longitudinal direction; or Figure 11 As shown in (c), the cross section of the second sacrificial layer 230 along the longitudinal direction presents a rectangular morphology, and the two adjacent corners of the rectangle away from the first sacrificial layer 220 are rounded, and the angle α1 between the tangent line of the rounded end and the longitudinal direction is 0° to 60°; or Figure 11 As shown in (d), the second sacrificial layer 230 has a trapezoidal cross-section along the longitudinal direction, with the side close to the first sacrificial layer 220 as the lower base and the side away from the first sacrificial layer 220 as the upper base, and the angle α2 between the lower base and the waist is 30° to 90°; or Figure 11 As shown in (e), the second sacrificial layer 230 has a trapezoidal cross-section along the longitudinal direction, with the side away from the first sacrificial layer 220 as the lower base and the side close to the first sacrificial layer 220 as the upper base. The angle α3 between the lower base and the waist is 30° to 90°.

[0057] It should be noted that Figure 11 (b) to Figure 11 The morphology of the second sacrificial layer 230 in (e) is not limited to Figure 11 At the dotted box in (a), Figure 11 The longitudinal morphology of each second sacrificial layer 230 in (a) can be Figure 11 (b) to Figure 11 (e).

[0058] refer to Figure 12 Before the subsequent step of forming a conductive column structure that fills the conductive column receiving hole 250 , the method further includes: forming a third sacrificial layer 260 that covers the sidewalls and bottom surface of the conductive column receiving hole 250 .

[0059] After the conductive column structure is subsequently formed in the conductive column accommodating hole 250, when the first sacrificial layer 220 and the second sacrificial layer 230 are removed, the third sacrificial layer 260 is used to protect the side wall of the conductive column structure. Moreover, in order to completely remove the first sacrificial layer 220 and the second sacrificial layer 230, it is usually necessary to increase the excessive etching time, so that the third sacrificial layer 260 can better protect the conductive column structure during this etching process.

[0060] In this embodiment, the third sacrificial layer 260 is formed by an atomic layer deposition process.

[0061] The third sacrificial layer 260 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the third sacrificial layer 260 can conformally cover the bottom and sidewalls of the conductive pillar receiving hole 250 .

[0062] In this embodiment, the third sacrificial layer 260 is made of a conductive material selected from tantalum nitride or niobium oxide.

[0063] The material of the third sacrificial layer 260 is a conductive material, so that even if the third sacrificial layer 260 is not removed subsequently, the capacitor structure formed between the conductive column structure and the conductive plate structure will not be affected, and the conductive column structure formed subsequently can be electrically connected to the conductive block structure 110. Moreover, the material of the third sacrificial layer 260 is selected from tantalum nitride or niobium oxide, which is conducive to the third sacrificial layer 260 and the conductive column structure forming better electrical properties together, and also makes the contact resistance between the conductive column structure formed subsequently and the conductive block structure 110 smaller.

[0064] In this embodiment, the thickness of the third sacrificial layer 260 is less than 30% of the opening size of the conductive column accommodating hole 250, so that the third sacrificial layer 260 can play a better protective role. At the same time, the space occupied by the third sacrificial layer 260 in the conductive column accommodating hole 250 is smaller, thereby providing sufficient space for the formation of the conductive column structure.

[0065] refer to Figure 13 , forming a conductive pillar structure 300 filling the conductive pillar receiving hole 250 .

[0066] The conductive pillar structure 300 is used as a conductive pillar in a 3D memory.

[0067] Specifically, in this embodiment, the conductive column structure 300 includes a lower electrode covering the side walls and bottom of the conductive column accommodating hole 250, and a lower conductive wire filling the conductive column accommodating hole 250 and covering the lower electrode. The lower electrode and the lower conductive wire subsequently form a capacitor structure with the dielectric layer, the upper electrode and the upper conductive wire.

[0068] Accordingly, in this embodiment, in the step of forming the conductive pillar structure 300 filling the conductive pillar receiving hole 250 , the conductive pillar structure 300 is in contact with the conductive block structure 110 to be electrically connected.

[0069] Accordingly, in this embodiment, in the step of forming the conductive pillar structure 300 filling the conductive pillar receiving hole 250 , the conductive pillar structure 300 covers the third sacrificial layer 260 .

[0070] The conductive pillar structure 300 covers the third sacrificial layer 260 and is electrically connected to the conductive block structure 110 through the third sacrificial layer 260 at the bottom of the conductive pillar receiving hole 250 .

[0071] It should be noted that, in this embodiment, the third sacrificial layer 260 is retained at the bottom of the conductive column accommodating hole 250, so that the contact area between the conductive column structure 300 at the bottom of the conductive column accommodating hole 250 and the conductive block structure 110 remains large, which is beneficial to reducing the contact resistance between the conductive column structure 300 and the conductive block structure 110.

[0072] refer to Figure 14 , all the first sacrificial layers 220 and the second sacrificial layers 230 are removed to form a plurality of trenches 400 arranged at intervals in the longitudinal direction and surrounded by the longitudinally adjacent dielectric layers 210 .

[0073] The groove 400 is used to provide a space for the subsequent formation of a conductive plate structure.

[0074] In this embodiment, a wet etching process is used to remove all of the first sacrificial layer 220 and the second sacrificial layer 230 .

[0075] The wet etching process has the characteristic of isotropic etching, which is conducive to completely removing all the first sacrificial layer 220 and the second sacrificial layer 230, and the wet etching process can easily achieve a larger etching selectivity, thereby reducing damage to other film layers when removing the first sacrificial layer 220 and the second sacrificial layer 230.

[0076] In other embodiments, after removing all of the first sacrificial layer 220 and the second sacrificial layer 230 , the exposed third sacrificial layer 260 may be further removed to form a plurality of longitudinally spaced trenches surrounded by longitudinally adjacent dielectric layers 210 , wherein the trenches expose part of the sidewall of the conductive pillar structure.

[0077] refer to Figure 15 , forming a dielectric layer 600 covering the side surfaces and bottom surface of the trench 400 ; and forming a conductive plate structure 500 filling the trench 400 and covering the dielectric layer 600 .

[0078] The conductive plate structure 500 is used as a conductive plate in a 3D memory, and the dielectric layer 600 is used as a storage capacitor material in a capacitor.

[0079] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 and an upper conductive line filling the trench 400 and covering the upper electrode. The upper electrode and the upper conductive line together with the dielectric layer, the lower electrode and the lower conductive line form a capacitor structure.

[0080] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 300 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 300.

[0081] Figure 16 It is a structural schematic diagram corresponding to an embodiment of the semiconductor structure of the present invention.

[0082] refer to Figure 16 , Figure 16 (b) to Figure 16 (e) Figure 16 (a) Various partial enlarged schematic diagrams at the dotted box position, where, for the sake of clarity, Figure 16 (b) to Figure 16 (e) shows only the dielectric layer 210, the conductive plate structure 500 and the dielectric layer 600. The semiconductor structure includes: a substrate 100; a conductive stack 207 located on the substrate 100, and the conductive stack 207 includes a longitudinal direction (such as Figure 16 The dielectric layer 210 and the conductive plate structure 500 are alternately stacked from bottom to top (as shown in the Z direction), and a conductive column receiving hole 250 is formed in the conductive stack 207. At the side wall position of the conductive column receiving hole 250, the conductive plate structure 500 is relatively larger than the dielectric layer 210 in the horizontal direction (as shown in the Z direction). Figure 16The conductive plate structure 500 is provided with a plurality of conductive pillar structures 300, the conductive pillar structures 300 are filled in the conductive pillar receiving holes 250, and the dielectric layers 600 are arranged at intervals in the longitudinal direction. The dielectric layers 600 cover the respective surfaces of the corresponding conductive plate structures 500 and are located between the conductive plate structures 500 and the conductive pillar structures 300.

[0083] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0084] In this embodiment, the base 100 includes a semiconductor substrate, or a semiconductor substrate having a semiconductor structure formed thereon. The uppermost layer of the base 100 is a dielectric material layer. Specifically, the dielectric material layer includes silicon oxide or silicon nitride. As an example, in this embodiment, the dielectric material layer is made of silicon oxide.

[0085] The conductive stack 270 is used to form a plurality of conductive plate structures 500 spaced apart in the longitudinal direction.

[0086] The conductive plate structure 500 is used as a conductive plate in a 3D memory.

[0087] In this embodiment, the conductive plate structure 500 includes an upper electrode covering the dielectric layer 600 , and an upper conductive line filled between longitudinally adjacent dielectric layers 210 and covering the upper electrode.

[0088] In this embodiment, the material of the dielectric layer 210 is silicon oxide or silicon nitride.

[0089] In a semiconductor manufacturing process, a stacked structure of alternating dielectric layers 210 and first sacrificial layers is first formed, a through hole is then formed penetrating the stacked structure, a second sacrificial layer is epitaxially grown along the first sacrificial layer to form a conductive pillar receiving hole 250, a conductive pillar structure 300 is formed in the conductive pillar receiving hole 250, the first and second sacrificial layers are then removed, and finally a conductive plate structure 500 is formed at the original location of the first and second sacrificial layers. Using silicon oxide or silicon nitride to form the dielectric layer 210 facilitates a greater etching selectivity between the first and second sacrificial layers and the dielectric layer 210 during the removal process, thereby reducing damage to the dielectric layer 210. Furthermore, using silicon oxide or silicon nitride to form the dielectric layer 210 prevents the second sacrificial layer from growing on the dielectric layer 210 during growth, and selectively grows only on the first sacrificial layer.

[0090] In this embodiment, the dielectric layer 210 has a thickness of 10 nm to 100 nm, so that the dielectric layer 210 has a better isolation effect and the space occupied by the semiconductor structure is not too large, thereby improving the integration of the semiconductor structure.

[0091] It should be noted that, in this embodiment, the bottommost layer and the topmost layer of the conductive stack 270 are both the dielectric layer 210 .

[0092] In this embodiment, a conductive block structure 110 is formed in the substrate 100 , and the conductive block structure 110 is exposed on the top surface of the substrate 100 .

[0093] The conductive block structure 110 is used to be electrically connected to the conductive pillar structure 300 .

[0094] The conductive pillar structure 300 is used as a conductive pillar in a 3D memory.

[0095] In this embodiment, the conductive pillar structure 300 includes a lower conductive line penetrating the conductive stack 207 and a lower electrode covering the sidewall and bottom of the lower conductive line. The lower electrode and the lower conductive line form a capacitor structure together with the dielectric layer, the upper electrode and the upper conductive line.

[0096] Accordingly, in this embodiment, the conductive pillar structure 300 penetrates the conductive stack 270 and contacts the conductive block structure 110 to be electrically connected.

[0097] It should be noted that, in this embodiment, the conductive column structure 300 at the bottom of the conductive column accommodating hole 250 is retained and extended laterally to the side of the conductive plate structure 500, so that the contact area between the conductive column structure 300 at the bottom of the conductive column accommodating hole 250 and the conductive block structure 110 remains large, which is beneficial to reducing the contact resistance between the conductive column structure 300 and the conductive block structure 110.

[0098] The dielectric layer 600 is used as a storage capacitor material in the memory.

[0099] Specifically, the surface distribution of the conductive plate structure 500 and the conductive column structure 300 is upper electrode-storage capacitor material-lower electrode, that is, the capacitor layer. The upper electrode is connected to the upper wire in the conductive plate structure 500, and the lower electrode is connected to the lower wire in the conductive column structure 300.

[0100] In this embodiment, at the side wall position of the conductive column accommodating hole 250, the conductive plate structure 500 protrudes laterally toward the outside of the dielectric layer 210 compared to the dielectric layer 210, thereby increasing the lateral size of the conductive plate structure 500, which is beneficial to improving the electrical properties of the conductive plate structure 500, thereby improving the electrical properties of the semiconductor structure.

[0101] It should be noted that in this embodiment, the conductive plate structure 500 protrudes laterally toward the outside of the dielectric layer 210 compared to the dielectric layer 210 , which means that the conductive plate structure 500 protrudes laterally toward the conductive pillar receiving hole 250 compared to the dielectric layer 210 .

[0102] In this embodiment, the semiconductor structure further includes a third sacrificial layer 260 covering the sidewalls and bottom of the conductive pillar receiving hole 250 and located between the conductive pillar structure 300 , the dielectric layer 210 , and the conductive plate structure 500 .

[0103] In the semiconductor manufacturing process, after the conductive column structure 300 is formed in the conductive column receiving hole 250, when the first sacrificial layer and the second sacrificial layer are removed, the third sacrificial layer 260 is used to protect the side wall of the conductive column structure 300. Moreover, in order to completely remove the first sacrificial layer and the second sacrificial layer, it is usually necessary to increase the excessive etching time, so that the third sacrificial layer 260 can better protect the conductive column structure 300 during this etching process.

[0104] In this embodiment, the third sacrificial layer 260 is made of a conductive material selected from tantalum nitride or niobium oxide.

[0105] The material of the third sacrificial layer 260 is a conductive material, so that the third sacrificial layer 260 is located between the conductive column structure 300 and the conductive plate structure 500, which will not affect the capacitor structure formed between the conductive column structure 300 and the conductive plate structure 500, and also enables the conductive column structure 300 and the conductive block structure 110 to be electrically connected. Moreover, the material of the third sacrificial layer 260 is selected from tantalum nitride or niobium oxide, which is conducive to the third sacrificial layer 260 and the conductive column structure 300 forming better electrical properties together, and also makes the contact resistance between the conductive column structure 300 and the conductive block structure 110 smaller.

[0106] In this embodiment, the thickness of the third sacrificial layer 260 is less than 30% of the opening size of the conductive column accommodating hole 250, so that the third sacrificial layer 260 can play a better protective role. At the same time, the space occupied by the third sacrificial layer 260 in the conductive column accommodating hole 250 is smaller, thereby providing sufficient space for the formation of the conductive column structure 300.

[0107] Accordingly, in this embodiment, the conductive pillar structure 300 covers the third sacrificial layer 260 and is electrically connected to the conductive block structure 110 through the third sacrificial layer 260 at the bottom of the conductive pillar receiving hole 250 .

[0108] Specifically, in this embodiment, based on the morphology of the second sacrificial layer in the semiconductor process, the morphology of the filling structure composed of the conductive plate structure 500 and the dielectric layer 600 can be as follows: Figure 16 As shown in (b), the filling structure has a rectangular cross-section along the longitudinal direction; or, as shown in Figure 16 As shown in (c), the cross section of the filling structure along the longitudinal direction presents a rectangular morphology, and the two adjacent corners of the rectangle close to the conductive pillar structure 300 are rounded, and the angle α1 between the tangent line of the rounded end and the longitudinal direction is 0° to 60°; or Figure 11As shown in (d), the filling structure has a trapezoidal cross-section along the longitudinal direction, with the side away from the conductive column structure 300 as the lower base and the side close to the conductive column structure 300 as the upper base, and the angle α2 between the lower base and the waist is 30° to 90°; or Figure 11 As shown in (e), the longitudinal cross-section of the filling structure presents a trapezoidal morphology, with the side close to the conductive column structure 300 as the lower base and the side away from the conductive column structure 300 as the upper base. The angle α3 between the lower base and the waist is 30° to 90°.

[0109] It should be noted that Figure 16 (b) to Figure 16 (e) The morphology of the dielectric layer 210, the conductive plate structure 500 and the dielectric layer 600 is not limited to Figure 16 At the dotted box in (a), Figure 16 The longitudinal morphologies of each dielectric layer 210, conductive plate structure 500 and dielectric layer 600 in (a) can be Figure 16 (b) to Figure 16 (e).

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure comprising dielectric layers and first sacrificial layers alternately stacked from bottom to top along a longitudinal direction; forming a plurality of through holes penetrating the laminate structure; The end surface of the first sacrificial layer exposed from the side wall of the through hole grows laterally toward the inside of the through hole to form a second sacrificial layer, and at the same time forms a conductive column accommodating hole, wherein the size of the conductive column accommodating hole in the layer where the dielectric layer is located is larger than the size of the conductive column accommodating hole in the layer where the first sacrificial layer is located; forming a conductive column structure filling the conductive column receiving hole; removing all of the first sacrificial layer and the second sacrificial layer to form a plurality of grooves spaced apart in the longitudinal direction and surrounded by longitudinally adjacent dielectric layers; forming a dielectric layer covering the side surfaces and bottom surface of the trench; A conductive plate structure is formed to fill the trench and cover the dielectric layer.

2. The forming method according to claim 1, wherein: The second sacrificial layer is formed by growing the end surface of the first sacrificial layer exposed from the side wall of the through hole toward the inside of the through hole in a transverse direction using an epitaxial growth process.

3. The forming method according to claim 1, wherein: In the step of growing the end face of the first sacrificial layer exposed by the side wall of the through hole laterally toward the inside of the through hole to form a second sacrificial layer, the first sacrificial layer and the second sacrificial layer are made of the same material, which is selected from any one of silicon, germanium, silicon germanium and Group III-V semiconductor materials.

4. The forming method according to claim 3, wherein: The material of the dielectric layer is silicon oxide or silicon nitride.

5. The forming method according to claim 1, wherein: In the step of growing the end surface of the first sacrificial layer exposed from the side wall of the through hole toward the inside of the through hole in a transverse direction to form a second sacrificial layer, the cross section of the second sacrificial layer in a longitudinal direction presents a rectangular morphology; Alternatively, the second sacrificial layer has a rectangular cross-section along the longitudinal direction, and two adjacent corners of the rectangle on a side away from the first sacrificial layer are rounded, and the angle between the tangent line of the rounded end and the longitudinal direction is 0° to 60°; Alternatively, the second sacrificial layer has a trapezoidal cross-section along the longitudinal direction, with the side close to the first sacrificial layer being the lower base and the side away from the first sacrificial layer being the upper base, and the angle between the lower base and the waist being 30° to 90°; Alternatively, the second sacrificial layer has a trapezoidal cross-section along the longitudinal direction, with the side away from the first sacrificial layer being the lower base and the side close to the first sacrificial layer being the upper base, and the angle between the lower base and the waist being 30° to 90°.

6. The forming method according to claim 1, wherein: Before the step of forming the conductive pillar structure filling the conductive pillar receiving hole, the method further includes: forming a third sacrificial layer covering the sidewalls and bottom surface of the conductive pillar receiving hole; In the step of forming a conductive pillar structure filling the conductive pillar accommodating hole, the conductive pillar structure covers the third sacrificial layer; In the step of removing all of the first sacrificial layer and the second sacrificial layer to form a trench surrounded by longitudinally adjacent dielectric layers, the trench exposes the third sacrificial layer.

7. The forming method according to claim 6, wherein: The material of the third sacrificial layer is a conductive material selected from tantalum nitride or niobium oxide.

8. The forming method according to claim 6, wherein: The third sacrificial layer is formed by an atomic layer deposition process.

9. The forming method according to claim 1, wherein: In the step of providing the substrate, a conductive block structure is formed in the substrate, and the conductive block structure is exposed on the top surface of the substrate; In the step of forming a through hole penetrating the stacked structure, the through hole exposes the conductive block structure.

10. A semiconductor structure, characterized in that include: substrate; a conductive stack located on the substrate, the conductive stack comprising dielectric layers and conductive plate structures stacked alternately in a longitudinal direction from bottom to top, a conductive column receiving hole formed through the conductive stack, and the conductive plate structure protruding laterally outward from the dielectric layer at a sidewall of the conductive column receiving hole; A plurality of conductive column structures, wherein the conductive column structures are filled in the conductive column receiving holes; Multiple dielectric layers are arranged at intervals in the longitudinal direction, the dielectric layers cover corresponding surfaces of the conductive plate structure and are located between the conductive column structure and the conductive plate structure.

11. The semiconductor structure according to claim 10, wherein: The semiconductor structure further includes a third sacrificial layer covering the sidewalls and the bottom of the conductive column receiving hole and located between the conductive column structure, the dielectric layer, and the conductive plate structure.

12. The semiconductor structure according to claim 11, wherein The material of the third sacrificial layer is a conductive material selected from tantalum nitride or niobium oxide.

13. The semiconductor structure according to claim 10, wherein: A conductive block structure is further formed in the substrate, and the conductive block structure is exposed on the top surface of the substrate; The conductive pillar structure penetrates the conductive stack and contacts the conductive block structure.

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