Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. A method includes forming a shallow trench isolation region alongside a protruding fin; and forming a composite hard mask over the shallow trench isolation region. The composite hard mask is formed by a plurality of deposition processes and a plurality of etch processes. The method further includes forming a dummy gate stack over the protruding fin; removing the sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; and removing the disposable interposer using an etching chemical. When the disposable interposer is removed, the composite hard mask is exposed to an etch chemical, and a bottom of the composite hard mask remains after the disposable interposer is removed. A gate stack is then formed to fill the space.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a shallow trench isolation region next to a protruding fin; forming a composite hard mask above the shallow trench isolation region, wherein forming the composite hard mask comprises multiple deposition processes and multiple etching processes; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between a first semiconductor nanostructure and a second semiconductor nanostructure in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the composite hard mask is exposed to the etching chemical, and a bottom portion of the composite hard mask remains after removing the disposable interposer; and forming a gate stack, wherein a portion of the gate stack fills the space.

[0005] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor strip; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region, the shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack, the gate stack comprising a first portion located below the first semiconductor nanostructure and overlying the semiconductor strip; and a hard mask, the hard mask overlying the shallow trench isolation region and located below a second portion of the gate stack, wherein the hard mask comprises: a first hard mask layer comprising a first sidewall; a second hard mask layer comprising: a second sidewall, the second sidewall contacting the first sidewall to form an interface; and a third sidewall opposite to the second sidewall, wherein the third sidewall contacts the semiconductor strip.

[0006] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and contacts the shallow trench isolation region to serve as a semiconductor strip; a dielectric hard mask above the shallow trench isolation region, wherein the dielectric hard mask comprises: a first portion; and a second portion and a third portion, wherein the second portion and the third portion contact opposite sidewalls of the first portion, wherein a first bottom surface of the first portion is higher than or lower than a second bottom surface of the second portion; and a gate stack, wherein the gate stack is located above and contacts the dielectric hard mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following specific implementations when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 3A 、 Figure 3B 、 Figures 4 to 8 as well as Figures 21 to 29A 、 Figure 29B 、 Figure 29C and Figure 29D A diagram illustrates an intermediate stage in the formation of a transistor, in accordance with some embodiments.

[0009] Figures 9 to 20 A diagram illustrates an intermediate stage in forming a hard mask over an STI region, in accordance with some embodiments.

[0010] Figure 30 The difference in incubation time for silicon nitride according to some embodiments is shown.

[0011] Figure 31 A process flow for forming a transistor according to some embodiments is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms (e.g., "below," "beneath," "lower," "overlying," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0014] A gate-all-around (GAA) transistor and a method for forming the same are provided. According to some embodiments of the present disclosure, a hard mask is formed over a shallow trench isolation (STI) region to protect the STI region during subsequent removal of a disposable interposer. The hard mask may have a composite structure comprising multiple parts.

[0015] The purpose of the embodiments discussed herein is to provide examples to enable making or using the subject matter of the present disclosure, and those skilled in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, like reference numerals are used to represent like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figures 1 to 8 as well as Figures 21 to 29A , 29B, 29C and 29D show views of intermediate stages in forming a GAA transistor according to some embodiments of the present disclosure. Figure 31 The process flow 200 shown schematically also reflects the corresponding process.

[0017] refer to Figure 1 , a perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., although other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0018] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. Figure 31 The illustrated process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material that is different from the first semiconductor material.

[0019] According to some embodiments, the first layer 22A is formed of or includes a first semiconductor material (e.g., SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc.). According to some embodiments, the first layer 22A (e.g., SiGe) is deposited by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc.

[0020] The second layer 22B is formed of or includes a second semiconductor material (e.g., Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, etc.), wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A includes silicon germanium, the second layer 22B can be formed of silicon, or vice versa. It should be understood that any suitable material combination can be used to form the first layer 22A and the second layer 22B.

[0021] According to some embodiments, second layer 22B is epitaxially grown on first layer 22A using a deposition technique similar to the deposition technique used to form first layer 22A. The deposition process for forming alternating first and second layers 22A, 22B is repeated to form the remaining layers in multilayer stack 22 until the desired topmost layer of multilayer stack 22 has been formed.

[0022] According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A will be removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A in the specification.

[0023] According to some embodiments, there may be some pad oxide layer(s) and hard mask layer(s) (not shown) formed over the multilayer stack 22. These layers are patterned and used to subsequently pattern the multilayer stack 22.

[0024] refer to Figure 2 , the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in (one or more) etching processes so that the trench 23 is formed. Figure 31 This is shown as process 204 in the illustrated process flow 200. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', portions of substrate 20 are left, and these portions are hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layer 22A and semiconductor layer 22B. Hereinafter, semiconductor layer 22A is alternatively referred to as a sacrificial layer, and semiconductor layer 22B is alternatively referred to as a nanostructure. Multilayer stack 22' and the portions of substrate strip 20' below are collectively referred to as semiconductor strip 24.

[0025] In the above-described embodiments, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the created pattern to have a spacing smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the GAA structure.

[0026] Figure 3A The formation of the isolation region 26 is shown, and the isolation region 26 is also referred to as the shallow trench isolation (STI) region in the specification. Figure 31This is shown as process 206 in the illustrated process flow 200. The STI regions 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20, or may be deposited. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like.

[0027] STI regions 26 may further include a dielectric material over the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to level the top surface of the dielectric material, with the remaining portion of the dielectric material being STI regions 26.

[0028] STI regions 26 are then recessed so that the tops of semiconductor strips 24 protrude above the top surface 26T of the remaining portions of STI regions 26 to form protruding fins 28. Protruding fins 28 include the tops of multilayer stack 22' and substrate strips 20'. Recessing STI regions 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, recessing STI regions 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0029] Figure 3B Shown Figure 3A The cross section A1-A1 in the figure. Figure 3B As shown, STI region 26 may include dielectric liner 26A and dielectric region 26B on dielectric liner 26A. Dielectric liner 26A and dielectric region 26B may be formed of different dielectric materials or the same dielectric material. For example, dielectric liner 26A may be formed of silicon nitride or silicon oxide, while dielectric region 26B may be formed of silicon oxide or silicon nitride.

[0030] Dielectric liner 26A and dielectric region 26B may also be formed of the same dielectric material (e.g., silicon oxide) but have different properties. For example, dielectric region 26B may have a lower density and a higher etch rate than dielectric liner 26A. According to an alternative embodiment, the entirety of STI region 26 is formed of a uniform material such as silicon oxide. In subsequent figures, dielectric liner 26A and dielectric region 26B are not shown separately.

[0031] Figures 3B to 8 The formation of a hard mask according to some embodiments is shown. Figure 3B, forming a dielectric layer 120. The corresponding process is Figure 31 The process flow 200 is shown as process 208. According to some embodiments, the dielectric layer 120 includes silicon oxide. The thickness of the dielectric layer 120 can be about peace treaty The forming may include a deposition process, which may be a conformal deposition process, such as ALD, CVD, etc.

[0032] Figure 4 The deposition of the hard mask layer 122 (also referred to as the protective layer 122) is shown. Figure 31 The process flow 200 is shown as process 210. The formation of the hard mask layer 122 may include plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), etc. According to some embodiments, the hard mask layer 122 is formed as a non-conformal layer having a sidewall portion (having a thickness T1), a top portion (having a thickness T2), and a bottom portion (having a thickness T3). Thicknesses T2 and T3 are greater than thickness T1. For example, the ratios T2 / T1 and T3 / T1 may be in a range between approximately 3 and approximately 20. The formation of the non-conformal hard mask layer 122 may be achieved, for example, by applying a bias power during the deposition of the hard mask layer 122.

[0033] The hard mask layer 122 is formed of a dielectric material that is different from the dielectric material of the underlying STI region 26 (and has a high etch selectivity with respect to the STI region 26). The material of the hard mask layer 122 may also be different from that of the disposable interposer 29 ( Figure 24A and 24B ) (and having a high etch selectivity relative to the disposable interposer 29). For example, the etch selectivity can be higher than about 10 and can be in a range between about 10 and 100.

[0034] According to some embodiments, hard mask layer 122 may be formed of or include a dielectric material containing silicon and nitrogen and / or a dielectric material containing silicon and carbon (e.g., SiN, SiCN, SiCON, SiC, SiOC, etc.). Hard mask layer 122 may also include a high-k dielectric material, such as Al2O3 (ALD), HfO2, HfSiO, ZrO2, La2O3, Y2O3, etc., or a combination thereof.

[0035] Figure 4The formation of a sacrificial layer 124 used as an etch mask is also shown. According to some embodiments, the sacrificial layer 124 includes a material that can be used as a bottom anti-reflective coating (BARC) and can include a cross-linked photoresist, SiOC, etc. The formation of the sacrificial layer 124 can include: a deposition (or dispensing) process, followed by a planarization process, and then an etch-back process. The top portion of the hard mask layer 122 is thereby exposed. The thickness T4 of the sacrificial layer 124 can be about peace treaty within the range between.

[0036] An etching process is then performed to remove some of the top portion and sidewall portions of the hard mask layer 122. Figure 31 This is shown as process 212 in the illustrated process flow 200. The etching chemistry is selected to have a low etch rate for the dielectric layer 120, and the dielectric layer 120 is used as an etch stop layer. The etching can be performed by a dry etching process, a wet etching process, or the like.

[0037] According to some embodiments, the etching gas may include a fluorine-containing gas, such as CF4, NF3, SF6, CHF3, ClF3, or the like, or a combination thereof. Other gases may also be added, such as O2, N2, H2, Ar, NO, or the like. According to alternative embodiments, a wet etching process may be employed, for example, using H3PO4. After the etching process, the top portion of the hard mask layer 122 may be completely removed to expose the dielectric layer 120, or a thin portion may remain.

[0038] The sacrificial layer 124 is then removed, followed by an etching process to remove the top portion (when remaining) and sidewall portions of the hard mask layer 122 . Figure 5 The resulting structure is shown in FIG. The remaining portion of hard mask layer 122 is referred to as hard mask 122′ (or alternatively, hard mask layer 122′). The top surface of hard mask 122′ can be flush with or lower than the top surface of substrate strip 20′ so that hard mask 122′ does not adversely affect the removal of sacrificial layer 22A in subsequent processes.

[0039] According to alternative embodiments, the top surface of hard mask layer 122' can be higher than the top surface of substrate strip 20', but lower than the top surface of the bottom sacrificial layer 22A in sacrificial layers 22A. The etching process can be isotropic and can be performed using a dry etching process or a wet etching process, for example, using the aforementioned chemistry for removing the top portion of hard mask layer 122. Dielectric layer 120 is used as an etch stop layer. During the etching of hard mask layer 122, the etching process is controlled so that the top portion and sidewall portions of hard mask layer 122 are completely removed, while at least some portion of the bottom portion remains.

[0040] Next, the dielectric layer 120 is etched to expose the protruding fins 28. Figure 31 This is shown in the illustrated process flow 200 as process 214 . Figure 6 The resulting structure is shown in .

[0041] Due to the removal of dielectric layer 120, a recess 126 is formed, which is located between protruding fin 28 and hard mask 122'. The bottom of recess 126 can be located at any level below the top surface of hard mask 122'. For example, Figure 6 In the figure, dashed line 128 shows a possible location of the bottom of recess 126, which may be located between the top and bottom surfaces of hard mask layer 122', flush with the bottom surface of hard mask layer 122', flush with the top surface of STI region 26, or lower than the top surface of STI region 26 (when some edge portions of STI region 26 are etched). According to another alternative embodiment, the portion of dielectric layer 120 located in region 127 may be laterally recessed to form an undercut.

[0042] refer to Figure 7 , depositing the second hard mask layer 130, which is called a hard mask re-deposition process because it is deposited to fill the recess 126 not filled by the hard mask 122 ′. Figure 31 This is shown in the illustrated process flow 200 as process 216 .

[0043] The material of hard mask layer 130 may be selected from the same candidate material group as the candidate material group of hard mask 122′, and may be the same as or different from the material of hard mask 122′. When hard mask layer 130 is formed of the same material as hard mask 122′, hard mask layer 130 may have the same density as hard mask 122′, or a higher or lower density than hard mask 122′. According to some embodiments, hard mask 122′ includes silicon nitride, and hard mask layer 130 may be formed of silicon nitride or other dielectric materials. According to some embodiments, hard mask layer 130 may be distinguishable from hard mask 122′, for example, by transmission electron microscopy (TEM). According to other embodiments, hard mask layer 130 may not be distinguishable from hard mask 122′.

[0044] According to some embodiments, hard mask layer 130 can be deposited by PEALD, PECVD, CVD, ALD, etc. Some of these methods (e.g., PEALD) have the advantageous feature of bottom-up growth and can therefore better fill recess 126 without forming voids. According to embodiments in which the portion of dielectric layer 120 located in region 127 is laterally recessed to form an undercut, the undercut can be completely filled by hard mask layer 130. According to alternative embodiments, the undercut in region 127 is partially filled by hard mask layer 130. Thus, hard mask layer 130 includes some lateral portions in region 127 that overlap with hard mask 122'.

[0045] A void (air spacer) is formed between the lateral portion of hard mask layer 130 and dielectric layer 120. According to yet another alternative embodiment, the undercut in region 127 is not filled by hard mask layer 130, and thus region 127 is a void (air gap).

[0046] refer to Figure 8 , an etching process is performed to etch the top portion and sidewall portion of the hard mask layer 130. The corresponding process is Figure 31 This is shown as process 218 in the illustrated process flow 200. The etching can be performed using an isotropic etching process using an etching chemical that is selective for the hard mask layer 130. For example, when the hard mask layer 130 comprises SiN, an H3PO4 solution can be used as an etchant. On the other hand, the nanostructures 22B and the sacrificial layer 22A are not etched.

[0047] In the resulting structure, the remaining portion of the hard mask layer 130 fills the recess 126 ( Figure 6 ). Hard masks (also referred to as hard mask layers) 122 ′ and 130 are collectively referred to as hard mask layer 134, which may or may not include the underlying dielectric layer 120, depending on their materials. The material of dielectric layer 120 may be the same as or different from the material of STI region 26. Dielectric layer 120 may be distinct from STI region 26 (e.g., having a different material and / or a different density). The material of hard mask layer 130 may be the same as or different from the material of hard mask 122 ′. Hard mask layer 130 may be distinct from hard mask 122 ′ (e.g., having a different material and / or a different density of the same material).

[0048] According to some embodiments, region 127 may include portions of hard mask 130. According to alternative embodiments, region 127 may include voids (air gaps). According to yet another alternative embodiment, region 127 may include portions of hard mask 130 directly below hard mask layer 122′ and voids between corresponding proximal portions of hard mask 130 and dielectric layer 120.

[0049] Figures 9 to 20 The formation of a hard mask 134 according to an alternative embodiment is shown. Figure 9 , a dielectric layer 136-1 is deposited. This deposition can be achieved by a conformal deposition process (e.g., ALD, CVD, etc.). Dielectric layer 136-1 may include an oxide, such as silicon oxide (SiO2), SiOC, etc. The thickness of dielectric layer 136-1 is small, for example, in a range between about 0.5 nm and about 2 nm.

[0050] refer to Figure 10 , depositing a hard mask layer 138-1. This formation process may include PEALD or another suitable process. Hard mask layer 138-1 includes portions on top of protruding fins 28, bottom portions at the bottom of trenches between adjacent protruding fins 28, and may or may not include some discrete islands on sidewall portions of dielectric layer 136-1 (as schematically shown). According to some embodiments, hard mask layer 138-1 may include a nitrogen-containing material, such as Si3N4, SiON, SiCN, etc.

[0051] According to some embodiments, during the PEALD process, a bias power is applied to increase the thickness of the top and bottom portions of the hard mask layer 138-1 and (relatively) reduce the sidewall portion of the hard mask layer 138-1. The bias power is selected to be neither too high nor too low. If the bias power is too high, there is a significant bombardment effect, and the top and bottom portions of the hard mask layer 138-1 cannot be deposited. If the bias power is too low, the difference between the incubation time of the top and bottom portions and the incubation time of the sidewall portion is not high enough, which is desirable for subsequent processes. According to some embodiments, the bias power is in a range between about 80 watts and about 220 watts.

[0052] It should be understood that some materials (e.g., silicon nitride) have high activation energy when grown on silicon oxide, and therefore have a long incubation time. Therefore, the incubation time of hard mask layer 138-1 is long. According to some embodiments, to reduce the incubation time of the top and bottom portions, a bias power is applied to overcome the activation energy barrier. However, the bias power does not affect the incubation time of the sidewall portions. Therefore, the top and bottom portions of hard mask layer 138-1 are incubated earlier than the sidewall portions of hard mask layer 138-1.

[0053] Figure 30The thickness of the grown SiN layer is shown as a function of the number of ALD cycles. Solid rectangles 142 represent data obtained at the top and bottom portions of dielectric layer 136-1, which are in a plasma-rich region due to the bias power. Hollow rectangles 144 represent data obtained at the sidewall portions of dielectric layer 136-1, which are in a plasma-poor region. The data represented by solid rectangles 142 and hollow rectangles 144 indicate that the top and bottom portions of hardmask layer 138-1 heat up much faster and earlier than the sidewall portions of hardmask layer 138-1. Therefore, the thickness of the top and bottom portions of hardmask layer 138-1 can increase linearly for a period of time while the sidewall portions of hardmask layer 138-1 are still attempting to heat up. In an example, when 100 ALD cycles are completed, the thickness of the top / bottom portions may be greater than 2 nm, while the sidewall portions of the hard mask layer 138 - 1 are still attempting to incubate.

[0054] Furthermore, other process conditions (eg, source power, pressure, etc.) during deposition of the hard mask layer 138 - 1 may be controlled to increase the difference between the incubation time of the top / bottom portions and the incubation time of the sidewall portions of the hard mask layer 138 - 1 .

[0055] According to some embodiments, deposition of hard mask layer 138-1 is stopped when the top and bottom portions of hard mask layer 138-1 grow into a continuous layer. The thickness of the top and bottom portions of hard mask layer 138-1 may range between about 1 nm and about 3 nm.

[0056] Deposition of the hard mask layer 138-1 is stopped before the sidewall portion of the hard mask layer 138-1 grows into a continuous layer covering the entire sidewall portion of the dielectric layer 136-1. In addition, the coverage of the sidewall portion of the hard mask layer 138-1 is less than about 50%, and can be less than about 30%, or less than about 10%.

[0057] In order to improve process efficiency, the deposition of the hard mask layer 138-1 is also as long as possible, with as many ALD (eg, PEALD) cycles as possible, so that Figure 12 、 13 The cycle shown in FIG14 does not need to be repeated too many times. Therefore, the deposition of the hard mask layer 138-1 may be stopped when the coverage of the sidewall portion of the hard mask layer 138-1 is greater than about 1% or greater than about 5%. According to an alternative embodiment, the deposition of the hard mask layer 138-1 may be stopped when the hard mask layer 138-1 has not yet grown on the sidewall portion of the dielectric layer 136-1.

[0058] Next, if Figure 11As shown, an etching process 140 (which may be an isotropic etching process) is performed to remove the sidewall portion of the dielectric layer 136-1. The isotropic etching process may be a dry etching process or a wet etching process. For example, in the case of dry etching, a mixture of NF3 and NH3 or a mixture of HF and NH3 may be used as the etching gas. In the case of wet etching, a diluted HF solution may also be used as the etching solution.

[0059] As a result of etching process 140, sidewall portions of dielectric layer 136-1 are removed. However, the top and bottom portions of dielectric layer 136-1 are protected by the top and bottom portions of hard mask layer 138-1 and are not removed. If hard mask layer 138-1 has any portions grown on sidewall portions of dielectric layer 136-1, the corresponding sidewall portions are discrete islands and will not hinder the removal of the sidewall portions of dielectric layer 136-1. Therefore, due to the removal of the sidewall portions of dielectric layer 136-1, the sidewall portions of hard mask layer 138-1 are removed.

[0060] like Figures 9-11 The illustrated process is collectively referred to as a first hard mask deposition and etching cycle. Due to the limitation of stopping the growth of dielectric hard mask layer 138-1 before complete incubation occurs on the sidewall portion of dielectric layer 136-1, the thickness of the bottom portion of dielectric hard mask layer 138-1 is limited. Therefore, more hard mask deposition and etching cycles can be performed to increase the thickness of hard mask layer 138 (which includes hard mask layer 138-1 and subsequent hard mask layers). Figures 12 to 14 A second hard mask deposition and etching cycle is shown in accordance with some embodiments. The processes, materials, and structures may be substantially the same as those of Figures 9 to 11 The process, materials and structure are the same.

[0061] refer to Figure 12 , a dielectric layer 136 - 2 is deposited. The material of the dielectric layer 136 - 2 may be the same as or different from the material of the dielectric layer 136 - 1 .

[0062] Next, if Figure 13 As shown, a hard mask layer 138-2 is deposited. The materials, formation processes, and process conditions used to form the hard mask layer 138-2 are substantially the same and are not repeated herein. The material of the hard mask layer 138-2 can be the same as or different from the material of the hard mask layer 138-1. On the sidewalls of the dielectric layer 136-2, the hard mask layer 138-2 is not incubated (not formed) or is partially incubated and can be formed as discrete islands.

[0063] Next, an etching process 140' is performed on the dielectric layer 136-2, removing the sidewall portions of the dielectric layer 136-2 and the portion of the hard mask layer 138-2 located on the sidewall portions of the dielectric layer 136-2, if any. Figure 14 The resulting structure is shown in .

[0064] Figure 15 and 16 A third hard mask deposition and etching cycle is shown, wherein dielectric layer 136-3 and hard mask layer 138-3 are formed. Figure 15 As shown, a blanket dielectric layer 136-3 is deposited using substantially the same materials and processes discussed for forming dielectric layer 136-1. Next, a hard mask layer 138-3 is deposited. The materials and processes can be selected from the same set of candidate materials and processes as used to form hard mask layer 138-1. Similarly, hard mask layer 138-3 may not be incubated or may be partially incubated on the sidewall portions of dielectric layer 136-3 and may or may not include deposited islands. Figure 16 Etching of sidewall portions of dielectric layer 136 - 3 and sidewall portions of hard mask layer 138 - 3 (if any) is shown.

[0065] Figure 17 and 18 A fourth hard mask deposition and etch cycle is shown, in which dielectric layer 136-4 and hard mask layer 138-4 are formed. The process details are substantially the same as those described for the layers below and are not repeated herein. According to some embodiments, more deposition and etch cycles can be performed to add more hard mask layers and dielectric layers. Dielectric layers 136-1, 136-2, 136-3, and 138-4, etc., are individually or collectively referred to as dielectric layer 136. Hard mask layers 138-1, 138-2, 138-3, and 138-4, etc., are individually or collectively referred to as hard mask layer 138. Throughout the description, dielectric layer 136 and the hard mask layer 138 immediately above it are collectively referred to as a dual-layer hard mask layer 136 / 138. Multiple dual-layer hard mask layers 136 / 138 together form a composite hard mask 134.

[0066] exist Figure 18 In the embodiment, the top surface of the top hard mask layer (e.g., top hard mask layer 138-4) can be flush with or lower than the top surface of substrate strip 20', so that composite hard mask 134 does not hinder the removal of sacrificial layer 22A in subsequent processes. According to alternative embodiments, the top surface of the top hard mask layer (e.g., top hard mask layer 138-4) can be higher than the top surface of substrate strip 20', but lower than the top surface of the bottom sacrificial layer 22A in sacrificial layers 22A.

[0067] Figure 19and Figure 20 The removal of the top portion of the composite hard mask 134 is shown. Figure 19 , forming a sacrificial layer 141, which is used as an etching mask. According to some embodiments, sacrificial layer 141 includes a material that can be used as a BARC, and may include a cross-linked photoresist, SiOC, etc. The formation of sacrificial layer 141 may include a deposition (or dispensing) process, followed by a planarization process and an etch-back process. This exposes the top portion of composite hard mask 134.

[0068] Figure 20 An etching process is shown to remove some of the top portion of the composite hard mask 134. The etching may include a plurality of first etching processes and a plurality of second etching processes that are performed alternately. The first etching process is used to etch the hard mask 138, while the second etching process is used to etch the dielectric layer 136. The etching may also be performed using an etching chemical that etches both the dielectric layer 136 and the hard mask 138. After the etching process, the sacrificial layer 141 is removed, leaving a Figure 20 The structure shown, wherein the composite hard mask 134 includes a plurality of hard mask layers 138 and a plurality of dielectric layers 136 .

[0069] refer to Figure 21 , Figure 21 , a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. Figure 31 The process flow 200 is shown as process 220. Figure 21 The composite hard mask 134 shown may have a Figure 8 The structure shown or Figure 20 The structure shown in FIG. Dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located above dummy gate dielectric 32. Dummy gate dielectric 32 may be formed by oxidizing a surface portion of protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, and may also be formed using other materials such as amorphous carbon.

[0070] Each dummy gate stack 30 may further include one (or more) hard masks 36 located above the dummy gate electrode 34. The hard mask 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. The dummy gate stack 30 may span a single protruding fin 28 or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fin 28. Forming the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard masks, and then patterning the formed layer by (one or more) patterning processes.

[0071] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of a dielectric material (e.g., silicon nitride (SiN), silicon monoxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.) and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include: depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the dielectric layer(s). The remaining portion of the dielectric layer(s) is the gate spacer 38.

[0072] Figure 22 The source / drain recess process is shown in FIG. Figure 31 This is shown in the illustrated process flow 200 as process 222 . Figure 22 Shown as Figure 21 The protruding fins 28 that are not directly below the dummy gate stack 30 and the gate spacers 38 are etched in the anisotropic etching process. This forms the source / drain recesses 42, as shown in FIG. Figure 22 shown.

[0073] Figure 23A 、 Figure 23B 、 Figure 24A and Figure 24B The sacrificial layer 22A is shown replaced with a disposable interposer 29. Figure 23A and Figure 23B , Figure 23A and Figure 23B Shown respectively Figure 21 In the cross sections BB and A2-A2, the sacrificial layer 22A is first removed to form openings 27 between the nanostructures 22B. Figure 31 The process flow 200 is shown as process 224. According to various embodiments, Figure 23BThe hard mask 134 shown in the subsequent figures may represent Figure 8 The hard mask 134 shown in FIG. Figure 20 The hard mask 134 is shown in FIG.

[0074] refer to Figure 24A and Figure 24B , forming a disposable intermediary layer 29 between the nanostructures 22B. The corresponding process is Figure 31 This is shown as process 226 in the illustrated process flow 200. According to some embodiments, disposable interposer 29 includes an oxide such as silicon oxide, and therefore may also be referred to as disposable oxide interposer (DOI) 29. According to other embodiments, other types of oxides may be employed.

[0075] The formation of disposable interposer 29 may include depositing a dielectric layer using a conformal deposition process such that the dielectric layer includes portions filling openings 27 and other portions outside of openings 27. A trimming process (which may include an isotropic etching process) is then performed to etch and remove the portions of the dielectric layer outside of openings 27. Thus, the remaining portion of the dielectric layer is disposable interposer 29.

[0076] The disposable insert 29 is then recessed laterally to form the internal spacer 44 ( Figure 24A ). The lateral recessing of the disposable insert 29 can be achieved by a wet etching process or a dry etching process. The wet etching process can be performed using a dipping process, a spraying process, a spin coating process, etc. The nanostructure 22B is not etched.

[0077] Then the inner spacer 44 is formed. The corresponding process is Figure 31 This is shown as process 228 in the illustrated process flow 200. According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess. Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the dielectric layer that is located outside the lateral recess, thereby leaving a portion of the dielectric layer within the lateral recess. The remaining portion of the dielectric layer is referred to as the internal spacer 44.

[0078] refer to Figure 25A and Figure 25B , Figure 25A and Figure 25B Shown respectively with Figure 21 The cross section A1-A1 in FIG. 1 is the same as the cross section BB, and the epitaxial source / drain region 48 is formed in the recess 42 by selective epitaxy. The corresponding process is Figure 31This is shown as process 230 in the illustrated process flow 200. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, p-type or n-type impurities may be in-situ doped as the epitaxy proceeds. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeb), silicon boron (SiB), etc. may be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc. may be grown.

[0079] Figure 26A and Figure 26B A cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 is shown. Figure 26A and Figure 26B Shown respectively Figure 21 1 and 1 . CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0080] CESL 50 and ILD 52 are planarized by a planarization process (eg, a CMP process or a mechanical grinding process). According to some embodiments, the planarization process may remove hard mask 36 to expose dummy gate electrode 34, such as Figure 26A and Figure 26B According to alternative embodiments, the planarization process may expose hard mask 36 and stop at hard mask 36. According to some embodiments, after the planarization process, the top surfaces of dummy gate electrode 34 (or hard mask 36), gate spacers 38, and ILD 52 are flush within process variations.

[0081] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if remaining) are removed in one or more etching processes, thereby forming the recess 58, as shown in FIG. Figure 27A and Figure 27B The corresponding process is shown in Figure 31This is shown as process 232 in the illustrated process flow 200. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process(es). For example, the etching process may be performed using a reactive gas(es) that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than etching the ILD 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22B that include future channel regions in a subsequently completed transistor.

[0082] The disposable interposer 29 is then removed to leave the recess 58 extending between the nanostructures 22B. Figure 31 This is shown as process 234 in the illustrated process flow 200. The corresponding process is also referred to as a sheet forming process. The disposable interposer 29 can be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective for the material of the disposable interposer 29, while the nanostructures 22B and the substrate 20 remain relatively unetched compared to the disposable interposer 29.

[0083] According to some embodiments in which the disposable interposer 29 includes, for example, silicon oxide, a mixture of NF 3 and NH 3 , a mixture of HF and NH 3 , or a diluted HF solution may be used to remove the disposable interposer 29 .

[0084] During the etching of disposable interposer 29 , STI regions 26 are protected from the etching chemicals by hard mask 134 due to the high etch selectivity (ie, the ratio of the etch rate of disposable interposer 29 to the etch rate of hard mask 134 ).

[0085] refer to Figure 28A and Figure 28B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is Figure 31 This is shown as process 236 in the illustrated process flow 200. According to some embodiments, each gate dielectric 62 includes an interfacial layer and a high-k dielectric layer on the interfacial layer. The interfacial layer may be formed of or include silicon oxide, which may be deposited by a conformal deposition process (e.g., ALD or CVD) or by an oxidation process.

[0086] According to some embodiments, the high-k dielectric layer includes one or more high-k dielectric layers. For example, the high-k dielectric layer(s) may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0087] Gate electrode 68 is also formed. During formation, a conductive layer is first formed over the high-k dielectric layer and fills the remaining portion of recess 58. Gate electrode 68 may comprise a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, gate electrode 68 may comprise any number of layers, any number of work function layers, and may include a filler material. Gate dielectric 62 and gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the bottom nanostructure 22B and the underlying substrate strip 20'.

[0088] After filling recess 58, a planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to remove excess portions of gate dielectric 62 and gate electrode 68 above the top surface of ILD 52. Gate electrode 68 and gate dielectric 62 are collectively referred to as a gate stack 70 of the resulting transistor.

[0089] exist Figure 29A and Figure 29B In the illustrated process, gate stack 70 is recessed so that recesses are formed directly above gate stack 70 and between portions of opposing gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each of these recesses, and a planarization process is then performed to remove excess portions of the dielectric material that extend over ILD 52.

[0090] like Figure 29A and Figure 29B Also shown, ILD 76 is deposited over ILD 52 and gate mask 74. An etch stop layer (not shown) may (or may not) be deposited prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, or the like. ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0091] ILD 76, ILD 52, CESL 50, and gate mask 74 are then etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surface of source / drain regions 48 and / or gate stack 70. Figure 29B The contact plugs 80A and 80B are shown in the same cross-section, but in various embodiments, the contact plugs 80A and 80B may be formed in different cross-sections, thereby reducing the risk of shorting to each other.

[0092] Silicide regions 78 are formed over source / drain regions 48. Contact plugs 80B are formed over silicide regions 78. In addition, contacts 80A (also referred to as gate contact plugs) are formed in the recesses, and contact 80A is located over and contacts gate electrode 68. Corresponding structures are also formed in FIG. Figure 29A As shown in , transistor 82 is thus formed.

[0093] Figure 29C Shown Figure 29A The structure shown in FIG. Figure 8 Detail of composite hard mask 134 of the structure shown. Composite hard mask 134 according to these embodiments includes hard masks 122′ and 130, and may include dielectric layer 120, which may or may not be distinct from underlying STI regions 26. It should be noted that the bottom of hard mask layer 130 may be at any level 128. Furthermore, dielectric layer 120 may or may not include sidewall portions between semiconductor strips 20′ and hard mask 122′.

[0094] Figure 29D Shown Figure 29A The structure shown in FIG. Figure 20 Detail of the composite hard mask 134 of the structure shown. The composite hard mask 134 according to these embodiments includes a plurality of hard mask layers 138 and a plurality of dielectric layers 136 positioned alternately. The number of hard mask layers 138 can be as large as Figure 20 The same as shown in , or less than due to the loss of hard mask layer 138 Figure 20 The amount shown in , wherein this loss may occur during the removal of the disposable interposer 29 .

[0095] The embodiments of the present disclosure have several advantageous features. By forming a hard mask to protect the STI region, the loss of the STI region during the sheet formation process (disposable interposer removal) can be eliminated. The hard mask can have various structures formed using different methods.

[0096] According to some embodiments of the present disclosure, a method includes: forming a shallow trench isolation region next to a protruding fin; forming a composite hard mask above the shallow trench isolation region, wherein forming the composite hard mask includes multiple deposition processes and multiple etching processes; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between a first semiconductor nanostructure and a second semiconductor nanostructure in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; removing the disposable interposer using an etching chemical, wherein when the disposable interposer is removed, the composite hard mask is exposed to the etching chemical, and a bottom portion of the composite hard mask remains after removing the disposable interposer; and forming a gate stack, wherein a portion of the gate stack is filled in the space.

[0097] In one embodiment, forming a composite hardmask includes: depositing an etch stop layer on the protruding fin; forming a first hardmask layer on the etch stop layer and at the bottom of the trench next to the protruding fin; etching the etch stop layer to leave a recess between the protruding fin and the first hardmask layer; and forming a second hardmask layer to fill the recess. In one embodiment, forming the second hardmask layer includes: depositing a blanket hardmask layer including a first portion on the protruding fin and a second portion filling the recess; and etching the first portion, wherein the second portion remains in the recess.

[0098] In one embodiment, forming a composite hard mask includes: forming a first dielectric layer at the bottom of the trench next to the protruding fin; forming a first hard mask layer above the first dielectric layer; forming a second dielectric layer above the first hard mask layer; and forming a second hard mask layer above the second dielectric layer. In one embodiment, the first dielectric layer and the first hard mask layer are formed by the following processes, which include: depositing a first dielectric layer, the first dielectric layer including a top portion on the top surface of the protruding fin and a first sidewall portion on the sidewall of the protruding fin; depositing a first hard mask layer, wherein the first hard mask layer includes a second sidewall portion, the second sidewall portion including the discrete island; and removing the first sidewall portion of the first dielectric layer.

[0099] In one embodiment, the composite hardmask includes a first sidewall that physically contacts a second sidewall of the protruding fin. In one embodiment, the composite hardmask includes a first dielectric material; and a second dielectric material that contacts an opposite sidewall of the first dielectric material, wherein the second dielectric material is different from the first dielectric material. In one embodiment, the composite hardmask includes a first dielectric material; and a second dielectric material that contacts an opposite sidewall of the first dielectric material, wherein the second dielectric material is the same as the first dielectric material.

[0100] In an embodiment, forming the disposable interposer includes: depositing a silicon oxide layer; and performing an etching process on the silicon oxide layer. In an embodiment, when etching the disposable interposer, the shallow trench isolation region is separated from the etching chemical by the bottom of the composite hard mask.

[0101] According to some embodiments of the present disclosure, a structure includes: a semiconductor strip; a first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack including a first portion located below the first semiconductor nanostructure and overlying the semiconductor strip; and a hard mask overlying the shallow trench isolation region and located below a second portion of the gate stack, wherein the hard mask includes a first hard mask layer including a first sidewall; and a second hard mask layer including a second sidewall contacting the first sidewall to form an interface; and a third sidewall opposite the second sidewall, wherein the third sidewall contacts the semiconductor strip.

[0102] In one embodiment, the first hardmask layer and the second hardmask layer comprise the same dielectric material. In one embodiment, the first hardmask layer and the second hardmask layer both comprise silicon nitride. In one embodiment, the structure further comprises a dielectric layer below the first hardmask layer and overlying the shallow trench isolation region. In one embodiment, a first bottom portion of the first hardmask layer is higher or lower than a second bottom portion of the second hardmask layer.

[0103] In an embodiment, the structure further includes a second semiconductor nanostructure that overlaps with and is spaced apart from the first semiconductor nanostructure, wherein the gate stack further includes a third portion located between the first semiconductor nanostructure and the second semiconductor nanostructure.

[0104] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and contacts the shallow trench isolation region to serve as a semiconductor strip; a dielectric hard mask above the shallow trench isolation region, wherein the dielectric hard mask includes a first portion; and a second portion and a third portion, the second portion and the third portion contacting opposite sidewalls of the first portion, wherein a first bottom surface of the first portion is higher or lower than a second bottom surface of the second portion; and a gate stack, which is located above the dielectric hard mask and contacts the dielectric hard mask.

[0105] In one embodiment, the first bottom surface of the first portion is higher than the second bottom surface of the second portion. In one embodiment, the first bottom surface of the first portion is lower than the second bottom surface of the second portion. In one embodiment, the structure further comprises a dielectric layer located below the first portion of the dielectric hard mask and physically contacting the first portion of the dielectric hard mask.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0107] Example 1 is a method for forming a semiconductor structure, comprising: forming a shallow trench isolation region next to a protruding fin; forming a composite hard mask above the shallow trench isolation region, wherein forming the composite hard mask includes multiple deposition processes and multiple etching processes; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between a first semiconductor nanostructure and a second semiconductor nanostructure in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; using an etching chemical to remove the disposable interposer, wherein when the disposable interposer is removed, the composite hard mask is exposed to the etching chemical, and a bottom portion of the composite hard mask remains after removing the disposable interposer; and forming a gate stack, wherein a portion of the gate stack fills the space.

[0108] Example 2 is the method described in Example 1, wherein forming the composite hard mask includes: depositing an etch stop layer on the protruding fin; forming a first hard mask layer on the etch stop layer and at the bottom of the trench next to the protruding fin; etching the etch stop layer to leave a recess between the protruding fin and the first hard mask layer; and forming a second hard mask layer to fill the recess.

[0109] Example 3 is the method described in Example 2, wherein forming the second hard mask layer includes: depositing a blanket hard mask layer, the blanket hard mask layer including a first portion on the protruding fin and a second portion filling the recess; and etching the first portion, wherein the second portion is left in the recess.

[0110] Example 4 is the method of Example 2, wherein a first bottom portion of the first hard mask layer is lower than a second bottom portion of the second hard mask layer.

[0111] Example 5 is the method of Example 2, wherein forming the first hard mask layer includes a non-conformal deposition process, and forming the second hard mask layer includes a conformal deposition process.

[0112] Example 6 is the method of Example 1, wherein the composite hard mask includes a first sidewall that physically contacts a second sidewall of the protruding fin.

[0113] Example 7 is the method of Example 1, wherein the composite hard mask includes: a first dielectric material; and a second dielectric material, the second dielectric material contacting opposite sidewalls of the first dielectric material, wherein the second dielectric material is different from the first dielectric material.

[0114] Example 8 is the method of Example 1, wherein the composite hard mask includes: a first dielectric material; and a second dielectric material, the second dielectric material contacting opposite sidewalls of the first dielectric material, wherein the second dielectric material is the same as the first dielectric material.

[0115] Example 9 is the method of Example 1, wherein forming the disposable interposer includes: depositing a silicon oxide layer; and performing an etching process on the silicon oxide layer.

[0116] Example 10 is the method of Example 1, wherein when etching the disposable interposer, the shallow trench isolation region is separated from the etch chemistry by the bottom portion of the composite hard mask.

[0117] Example 11 is a semiconductor structure comprising: a semiconductor strip; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region, the shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack, the gate stack comprising a first portion located below the first semiconductor nanostructure and overlying the semiconductor strip; and a hard mask, the hard mask overlying the shallow trench isolation region and located below a second portion of the gate stack, wherein the hard mask comprises: a first hard mask layer comprising a first sidewall; a second hard mask layer comprising: a second sidewall, the second sidewall contacting the first sidewall to form an interface; and a third sidewall opposite the second sidewall, wherein the third sidewall contacts the semiconductor strip.

[0118] Example 12 is the structure of Example 11, wherein the first hard mask layer and the second hard mask layer include the same dielectric material.

[0119] Example 13 is the structure of Example 12, wherein the first hard mask layer and the second hard mask layer both include silicon nitride.

[0120] Example 14 is the structure described in Example 13, further including: a dielectric layer, wherein the dielectric layer is located below the first hard mask layer and overlies the shallow trench isolation region.

[0121] Example 15 is the structure of Example 11, wherein a first bottom portion of the first hard mask layer is higher or lower than a second bottom portion of the second hard mask layer.

[0122] Example 16 is the structure described in Example 11, further including: a second semiconductor nanostructure, which overlaps and is spaced apart from the first semiconductor nanostructure, wherein the gate stack also includes a third portion located between the first semiconductor nanostructure and the second semiconductor nanostructure.

[0123] Example 17 is a semiconductor structure comprising: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and contacts the shallow trench isolation region to serve as a semiconductor strip; a dielectric hard mask above the shallow trench isolation region, wherein the dielectric hard mask comprises: a first portion; and a second portion and a third portion, the second portion and the third portion contacting opposite side walls of the first portion, wherein a first bottom surface of the first portion is higher or lower than a second bottom surface of the second portion; and a gate stack, the gate stack being located above and contacting the dielectric hard mask.

[0124] Example 18 is the structure of Example 17, wherein the first bottom surface of the first portion is higher than the second bottom surface of the second portion.

[0125] Example 19 is the structure of Example 17, wherein the first bottom surface of the first portion is lower than the second bottom surface of the second portion.

[0126] Example 20 is the structure of Example 17, further comprising: a dielectric layer located below the first portion of the dielectric hard mask and physically contacting the first portion of the dielectric hard mask.

Claims

1. A method for forming a semiconductor structure, comprising: forming a shallow trench isolation region next to the protruding fin; forming a composite hard mask on the shallow trench isolation region, wherein forming the composite hard mask comprises a plurality of deposition processes and a plurality of etching processes; forming a dummy gate stack on the protruding fin; removing the sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure in the protruding fin; forming a disposable intermediary layer in the space; removing the dummy gate stack; removing the disposable interposer using an etch chemistry, wherein the composite hard mask is exposed to the etch chemistry when the disposable interposer is removed, and a bottom portion of the composite hard mask remains after removing the disposable interposer; and A gate stack is formed, wherein a portion of the gate stack fills the space.

2. The method according to claim 1, wherein Forming the composite hard mask includes: depositing an etch stop layer on the protruding fin; forming a first hard mask layer on the etch stop layer and at the bottom of the trench beside the protruding fin; etching the etch stop layer to leave a recess between the protruding fin and the first hard mask layer; and A second hard mask layer is formed to fill the recess.

3. The method according to claim 2, wherein: Forming the second hard mask layer includes: depositing a blanket hard mask layer comprising a first portion on the protruding fin and a second portion filling the recess; and The first portion is etched, wherein the second portion remains in the recess.

4. The method according to claim 2, wherein: A first bottom portion of the first hard mask layer is lower than a second bottom portion of the second hard mask layer.

5. The method according to claim 2, wherein: Forming the first hard mask layer includes a non-conformal deposition process, and forming the second hard mask layer includes a conformal deposition process.

6. The method according to claim 1, wherein The composite hard mask includes a first sidewall physically contacting a second sidewall of the protruding fin.

7. The method according to claim 1, wherein The composite hard mask comprises: a first dielectric material; and A second dielectric material contacts opposite sidewalls of the first dielectric material, wherein the second dielectric material is different from the first dielectric material.

8. The method according to claim 1, wherein The composite hard mask comprises: a first dielectric material; and A second dielectric material contacts opposite sidewalls of the first dielectric material, wherein the second dielectric material is the same as the first dielectric material.

9. A semiconductor structure comprising: semiconductor strips; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region, wherein the shallow trench isolation region contacts an edge of the semiconductor strip; a gate stack comprising a first portion underlying the first semiconductor nanostructure and overlying the semiconductor strip; as well as a hard mask overlying the shallow trench isolation region and below the second portion of the gate stack, wherein the hard mask comprises: a first hard mask layer including a first sidewall; A second hard mask layer comprising: a second sidewall contacting the first sidewall to form an interface; and A third sidewall is opposite to the second sidewall, wherein the third sidewall contacts the semiconductor strip.

10. A semiconductor structure comprising: semiconductor substrates; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and contacts the shallow trench isolation region to serve as a semiconductor strip; A dielectric hard mask is provided on the shallow trench isolation region, wherein the dielectric hard mask comprises: Part I; and a second portion and a third portion contacting opposite side walls of the first portion, wherein a first bottom surface of the first portion is higher or lower than a second bottom surface of the second portion; and A gate stack is located above and contacts the dielectric hard mask.

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