Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and is designed for solving the problems that in a manufacturing method of a GAAFET provided by the related technology, the number of process steps for forming an insulating layer is large, and the process difficulty is large. The manufacturing method of the semiconductor device comprises the steps that a first substrate is provided, a laminated structure is formed on the top of the first substrate, and the laminated structure comprises sacrificial layers and channel layers which are sequentially and alternately stacked in the direction away from the first substrate; forming a first bonding layer on the top of the laminated structure; providing a second substrate, and forming a second bonding layer on the top of the second substrate; at least one of the first bonding layer and the second bonding layer is an insulating material; the first bonding layer is opposite to the second bonding layer; and bonding the first bonding layer and the second bonding layer. According to the invention, the process steps for forming the insulating layer are fewer, and the process difficulty is low.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology, the number of transistors accommodated per unit area of ​​a chip continues to increase. In order to meet the technical requirements of proportionally reducing the characteristic size of transistors, the structure of semiconductor devices has undergone a transformation from traditional planar transistors to three-dimensional transistors, and FinFET (Fin Field Effect Transistor) and GAAFET (Gate-All-Around Field Effect Transistor) have been developed successively. For GAAFET, since the gate structure completely surrounds the channel layer in a three-dimensional manner, compared with the planar transistor structure, this fully surrounded structure can significantly enhance the electrostatic control ability of the gate structure on the channel layer, thereby effectively suppressing the short channel effect and improving the performance of semiconductor devices.

[0003] In GAAFETs, an insulating layer is formed between the substrate and the channel layer to reduce the risk of leakage between adjacent source and drain doped layers, as well as the parasitic capacitance between the source and drain doped layers and the subsequently formed gate structure, and between the gate structure and the substrate. This insulating layer provides isolation to reduce the aforementioned leakage risk and parasitic capacitance. However, the GAAFET manufacturing methods provided in related art involve numerous process steps for forming the insulating layer, making the process more difficult. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device to solve the technical problem that the method for manufacturing a GAAFET provided by the related art has many process steps for forming an insulating layer and is difficult to manufacture.

[0005] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a first substrate, forming a stacked structure on top of the first substrate, the stacked structure comprising sacrificial layers and channel layers alternately stacked in a direction away from the first substrate; and forming a first bonding layer on top of the stacked structure;

[0007] Providing a second substrate, and forming a second bonding layer on top of the second substrate; at least one of the first bonding layer and the second bonding layer is an insulating material;

[0008] making the first bonding layer face the second bonding layer; and

[0009] The first bonding layer and the second bonding layer are bonded.

[0010] Furthermore, after the step of bonding the first bonding layer and the second bonding layer, the method further includes: removing the first substrate.

[0011] Furthermore, after the step of removing the first substrate, the method further includes: etching the stacked structure, the first bonding layer, the second bonding layer and a portion of the second substrate to form a fin structure.

[0012] Furthermore, the step of making the first bonding layer face the second bonding layer includes: turning over the device structure formed by the first substrate, the stacked structure and the first bonding layer so that the first bonding layer is located on top of the second bonding layer.

[0013] Furthermore, the first bonding layer and the second bonding layer each include one or more dielectric layers.

[0014] Furthermore, the first bonding layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride, and the material of the second bonding layer is the same as that of the first bonding layer.

[0015] Furthermore, in the step of bonding the first bonding layer and the second bonding layer, the process temperature is 200-500° C., and the process time is 0.5-8 hours.

[0016] Furthermore, the first bonding layer is formed on the top of the stacked structure by a deposition process, and the second bonding layer is formed on the top of the second substrate by a deposition process.

[0017] Furthermore, the step of removing the first substrate includes: removing a portion of the first substrate by a back grinding process, and removing the remaining first substrate by an etching process.

[0018] Furthermore, the material of the channel layer is silicon, and the material of the sacrificial layer is silicon germanium, wherein the concentration of germanium in the sacrificial layer is 10% to 90%.

[0019] The beneficial effects brought about by the method for manufacturing a semiconductor device of the present invention are:

[0020] In the manufacturing method of the semiconductor device, the semiconductor device is divided into two parts, which are manufactured separately and then recombined to form. Specifically, a first substrate, a stacked structure arranged on the top of the first substrate, and a first bonding layer arranged on the top of the stacked structure are first formed in one part of the structure, and a second substrate and a second bonding layer located on the top of the second substrate are formed in the other part of the structure; then, by flipping one of them, the first bonding layer and the second bonding layer can be made opposite to each other, so that the two parts used to form the semiconductor device are arranged longitudinally; thereafter, the first bonding layer and the second bonding layer are bonded together, and the two parts are combined to form an integrated semiconductor device. At this time, the first bonding layer and the second bonding layer are located between the second substrate and the channel layer of the stacked structure. Since at least one of the first bonding layer and the second bonding layer is made of insulating material, an insulating layer can be formed between the second substrate and the channel layer of the stacked structure.

[0021] It can be seen that in the manufacturing method of the semiconductor device, by bonding together two structures including a first bonding layer and a second bonding layer, the first bonding layer and the second bonding layer made of insulating material can be used to automatically form an insulating layer located between the second substrate and the channel layer. The process steps are small, and the tedious steps of first removing the placeholder material of the insulating layer, re-deposition and modification to obtain the required insulating layer in the related technology are eliminated, which simplifies the process flow, greatly reduces the process difficulty and complexity, and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] Figure 1 Schematic cross-sectional views of a semiconductor device formed by a GAAFET manufacturing method according to related art at various steps, wherein (a) illustrates the initial state of the device structure; (b) illustrates the formation of an opening between the channel protrusion and the substrate; (c) illustrates the deposition of insulating material; and (d) illustrates the removal of excess insulating material.

[0024] Figure 2 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0025] Figure 3Schematic cross-sectional views of a semiconductor device formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention at various steps, wherein (a) is a schematic diagram of forming a stacked structure and a first bonding layer on a first substrate; (b) is a schematic diagram of forming a second bonding layer on a second substrate; (c) is a schematic diagram of making the first bonding layer and the second bonding layer face each other; (d) is a schematic diagram of bonding the first bonding layer and the second bonding layer; (e) is a schematic diagram after removing the first substrate; and (f) is a schematic diagram after etching the stacked structure, the first bonding layer, the second bonding layer, and a portion of the second substrate.

[0026] Figure 4 A flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0027] Description of reference numerals:

[0028] 101 - substrate; 102 - raised portion; 103 - base; 104 - first sacrificial layer; 105 - protective layer; 106 - second sacrificial layer; 107 - channel layer; 108 - channel stack; 109 - channel raised portion; 110 - stacked structure; 120 - opening; 130 - insulating material; 131 - insulating layer;

[0029] 210 - first substrate; 220 - stacked structure; 230 - channel stack; 231 - sacrificial layer; 232 - channel layer; 240 - first bonding layer;

[0030] 310 - second substrate; 320 - second bonding layer;

[0031] 400-Fin structure. DETAILED DESCRIPTION

[0032] In GAAFET, in order to reduce the risk of leakage between adjacent source and drain doped layers, and to reduce the parasitic capacitance between the source and drain doped layers and the subsequently formed gate structure, as well as the parasitic capacitance between the gate structure and the substrate, an insulating layer is formed between the substrate and the channel layer.

[0033] The manufacturing method of GAAFET provided by the related art is as follows: when forming the insulating layer, Figure 1 As shown in (a), the device structure includes a base 103, a first sacrificial layer 104, a protective layer 105 and a channel protrusion 109 (a stacked structure 110) arranged in sequence from bottom to top, wherein the base 103 includes a substrate 101 and a protrusion 102; the channel protrusion 109 includes a plurality of channel stacks 108 stacked in sequence in the longitudinal direction, and the channel stack 108 includes a second sacrificial layer 106 and a channel layer 107 stacked in layers.

[0034] like Figure 1As shown in (b), when the insulating layer needs to be formed, the first sacrificial layer 104 and the protective layer 105 need to be removed first to form an opening 120 between the channel protrusion 109 and the substrate 103; then, as shown in FIG. Figure 1 As shown in (c) in FIG. 1 , an insulating material 130 is deposited so that the insulating material 130 is filled between the channel protrusion 109 and the substrate 103. At this time, the insulating material 130 covers the substrate 103 and the channel protrusion 109 from above and covers the channel protrusion 109 laterally. Finally, as shown in FIG. Figure 1 As shown in (d) , the insulating material 130 on the top and sidewalls of the trench protrusion 109 is removed, and the remaining insulating material 130 filling the opening 120 serves as an insulating layer 131 .

[0035] The above-mentioned method for forming the insulating layer 130 between the channel protrusion 109 and the substrate 103 requires first removing the first sacrificial layer 104 and the protective layer 105 used to form a placeholder in the opening 120, and then depositing the insulating material 130 on the device surface. The excess insulating material 130 needs to be removed before forming the required insulating layer 131. Not only does this method involve many process steps, but it is also more difficult to process.

[0036] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device to solve the technical problem in the above-mentioned method for manufacturing GAAFET, that the process steps for forming the insulating layer are numerous and the process is difficult.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] like Figure 2 As shown, this embodiment provides a method for manufacturing a semiconductor device, comprising:

[0039] Step S100: Figure 3 As shown in (a) of FIG. 1 , a first substrate 210 is provided, and a stacked structure 220 is formed on top of the first substrate 210. The stacked structure 220 includes sacrificial layers 231 and channel layers 232 alternately stacked in a direction away from the first substrate 210. A first bonding layer 240 is formed on top of the stacked structure 220. The first bonding layer 240 is made of an insulating material.

[0040] Through step S100, a portion of a device structure for forming a semiconductor device can be obtained. Specifically, the first substrate 210 may include a single crystal semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium antimonide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP), and may be doped with impurities (e.g., dopants having p-type or n-type conductivity). Specifically, in this embodiment, the material of the first substrate 210 is silicon.

[0041] Please continue to refer to Figure 3 In (a), the stacked structure 220 includes a plurality of channel stacks 230 stacked in a longitudinal direction, and each channel stack 230 includes a sacrificial layer 231 and a channel layer 232 stacked in sequence in a direction away from the first substrate 210 . The sacrificial layer 231 and the channel layer 232 are made of materials with different etching selectivities. The sacrificial layer 231 may be a combination of one or more of germanium (Ge), silicon carbide (SiC), germanium arsenide (GeAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP). Similarly, the channel layer 232 may also be a combination of one or more of germanium (Ge), silicon carbide (SiC), germanium arsenide (GeAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0042] Specifically, in this embodiment, the material of the channel layer 232 is silicon, the material of the sacrificial layer 231 is silicon germanium, and the concentration of germanium in the sacrificial layer 231 is 10% to 90%. This configuration can improve the etching selectivity between the channel layer 232 and the sacrificial layer 231, thereby effectively reducing the impact of the removal process of the sacrificial layer 231 on the channel layer 232, thereby improving the quality of the channel layer 232 and further improving the performance of the formed semiconductor device.

[0043] In this embodiment, the stacked structure 220 includes three groups of channel stacks 230. In other embodiments, the stacked structure 220 may also include only one group of channel stacks 230. The number of channel stacks 230 can be selected based on the ultimate function of the semiconductor device to be obtained, and this embodiment is not limited to this.

[0044] The first bonding layer 240 formed in the above step S100 may include one or more dielectric layers. When the first bonding layer 240 includes one dielectric layer, the structure of the first bonding layer 240 can be simplified, making the first bonding layer 240 easier to process and manufacture; when the first bonding layer 240 includes multiple dielectric layers, since different dielectric layers are formed of different materials, the parameters such as the dielectric constant and thermal expansion coefficient of the first bonding layer 240 can be optimized by combining different materials to improve the electrical isolation performance of the first bonding layer 240.

[0045] Specifically, the material of the first bonding layer 240 may include silicon carbonitride (SiCN), silicon carbonitride oxide (SiOCN), silicon oxide (SiO2), silicon nitride (Si3N4), hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3) and silicon oxynitride (SiON), their compounds, their composite materials, their combinations, etc.

[0046] In this embodiment, the first bonding layer 240 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. This configuration can improve the electrical insulation performance of the first bonding layer 240, thereby enhancing the electrical isolation effect between the channel layer 232 and the second substrate 310 in the final semiconductor device.

[0047] Step S200: Figure 3 As shown in (b), a second substrate 310 is provided, and a second bonding layer 320 is formed on the top of the second substrate 310; the second bonding layer 320 is also an insulating material.

[0048] Through step S200, another portion of the device structure for forming a semiconductor device can be obtained. Specifically, the second substrate 310 may include a single crystal semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium antimonide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP), and may be doped with impurities (e.g., dopants having p-type or n-type conductivity). Specifically, in this embodiment, the material of the second substrate 310 is silicon.

[0049] In this embodiment, the material of the second bonding layer 320 is the same as that of the first bonding layer 240 .

[0050] By selecting the same material as the first bonding layer 240 to form the second bonding layer 320, on the one hand, the second bonding layer 320 and the first bonding layer 240 have the same thermal expansion coefficient, so as to reduce the thermal stress generated when the temperature changes, thereby reducing the risk of cracking at the bonding interface. On the other hand, the selection of the same material also makes the two-part device structure used to form the semiconductor device have better process compatibility, thereby reducing process complexity.

[0051] Step S300: Figure 3 As shown in (c) in FIG. 5 , the first bonding layer 240 and the second bonding layer 320 are made to face each other.

[0052] Specifically, in step S300, the device structure formed by the first substrate 210, the stacked structure 220, and the first bonding layer 240 can be flipped so that the first bonding layer 240 is located on top of the second bonding layer 320. At this time, the second substrate 310 is located at the bottom and can provide support for the bonding process. Moreover, after the two-part structure in steps S100 and S200 is combined into a semiconductor device, the second substrate 310 can serve as the substrate structure of the semiconductor device to facilitate subsequent manufacturing processes.

[0053] It should be noted that flipping the device structure formed by the above-mentioned first substrate 210, stacked structure 220 and first bonding layer 240 can be achieved by wafer flipping equipment. Wafer flipping equipment is a mature technology in this field, so it will not be described in detail.

[0054] Step S400: Figure 3 As shown in (d) in FIG. 3 , the first bonding layer 240 and the second bonding layer 320 are bonded.

[0055] Through step S400, the device structure formed in the above step S100 can be combined with the device structure formed in the above step S200 to form an integrated semiconductor device. At this time, the first bonding layer 240 and the second bonding layer 320 are located between the second substrate 310 and the channel layer 232 of the stacked structure 220. Since the first bonding layer 240 and the second bonding layer 320 are made of insulating material, an insulating layer can be formed between the second substrate 310 and the channel layer 232 of the stacked structure 220.

[0056] It can be seen that in the manufacturing method of the semiconductor device, by bonding together two structures including a first bonding layer 240 and a second bonding layer 320, the first bonding layer 240 and the second bonding layer 320 made of insulating material can be used to automatically form an insulating layer located between the second substrate 310 and the channel layer 232. The process steps are small, and the tedious steps of first removing the placeholder material of the insulating layer, re-deposition and modification to obtain the required insulating layer in the related technology are eliminated, which simplifies the process flow, greatly reduces the process difficulty and complexity, and reduces the manufacturing cost.

[0057] In addition, since the first bonding layer 240 and the second bonding layer 320 used to form the insulating layer are both made of insulating materials, the isolation effect between the channel layer 232 and the second substrate 310 can be enhanced.

[0058] In the step of bonding the first bonding layer 240 and the second bonding layer 320 , the process temperature is 200 to 500° C., and the process time is 0.5 to 8 hours.

[0059] By limiting the temperature of the first bonding layer 240 and the second bonding layer 320 to within the aforementioned range, the atomic activity on the surfaces of the first bonding layer 240 and the second bonding layer 320 can be increased, thereby enhancing the atomic diffusion capability and thereby improving the bonding strength between the first bonding layer 240 and the second bonding layer 320. By limiting the process time to within the aforementioned range, the bonding process can be ensured to proceed adequately while also avoiding material performance degradation or excessive energy consumption due to an excessively long process time.

[0060] In this embodiment, the first bonding layer 240 is formed on the top of the stacked structure 220 by a deposition process, and the second bonding layer 320 is formed on the top of the second substrate 310 by a deposition process.

[0061] This form of using a deposition process to form the first bonding layer 240 on the top of the stacked structure 220 can, on the one hand, enhance the diffusion ability of the material of the first bonding layer 240 into the stacked structure 220, making the first bonding layer 240 and the stacked structure 220 more tightly bonded. On the other hand, it also makes the formed first bonding layer 240 more uniform to ensure its comprehensive bonding with the second bonding layer 320, thereby improving the subsequent bonding quality.

[0062] Similarly, the second bonding layer 320 is formed on top of the second substrate 310 by using a deposition process. On the one hand, the diffusion ability of the material of the second bonding layer 320 to the second substrate 310 can be enhanced, so that the second bonding layer 320 and the second substrate 310 are more tightly bonded. On the other hand, the formed second bonding layer 320 is more uniform to ensure the comprehensiveness of its bonding with the first bonding layer 240, thereby improving the subsequent bonding quality.

[0063] like Figure 4 As shown, this embodiment also provides another method for manufacturing a semiconductor device, which Figure 2 The method for manufacturing a semiconductor device further includes: step S500, removing the first substrate 210. That is, after the step of bonding the first bonding layer 240 and the second bonding layer 320, the first substrate 210 is removed. After this step, the structure of the semiconductor device obtained is as follows: Figure 3 As shown in (e) in .

[0064] By removing the first substrate 210 , the stacked structure 220 can be exposed on the top, so that an upper functional layer (such as a metal electrode, etc.) can be formed in a subsequent process to facilitate electrical connection of the semiconductor device.

[0065] The step of removing the first substrate 210 includes: removing a portion of the first substrate 210 by a back grinding process, and removing the remaining first substrate 210 by an etching process.

[0066] In other words, the removal of the first substrate 210 can be performed in stages. First, a portion of the first substrate 210 can be removed through a backside grinding process. In this case, the removed first substrate 210 can account for more than 1 / 2 of the total thickness of the first substrate 210. Then, the remaining first substrate 210 can be removed through an etching process. In this case, the removed first substrate 210 accounts for less than 1 / 2 of its total thickness. In other words, the majority of the first substrate 210 is first removed through a backside grinding process to ensure efficient removal of the first substrate 210. Then, the remaining small portion of the first substrate 210 is removed through an etching process to ensure accurate removal of the first substrate 210 and avoid damaging the stacked structure 220.

[0067] Please continue to refer to Figure 4 In this embodiment, after removing the first substrate 210, the step further includes etching the stacked structure 220, the first bonding layer 240, the second bonding layer 320 and a portion of the second substrate 310 to form a fin structure 400. At this time, the structure of the obtained semiconductor device is as follows: Figure 3 As shown in (f) in .

[0068] By forming the fin-like structure 400, the gate can be filled in the area between the fin-like structures 400 in the subsequent process. At the same time, after removing the sacrificial layer 231, the space occupied by the sacrificial layer 231 is also filled by the gate, so that the channel layer 232 is surrounded by the gate on all sides to improve the gate control capability of the current in the channel layer 232. At the same time, since the fin-like structure 400 has a high aspect ratio, the effective carrier mobility of the channel layer 232 can also be increased to improve the switching speed and performance of the semiconductor device.

[0069] Specifically, the fin structure 400 can be manufactured by suitable methods including double patterning or multiple patterning processes, which generally combine photolithography and self-aligned etching techniques to form patterns with finer pitches on semiconductor devices than can be achieved using a single, direct photolithography process.

[0070] In this embodiment, the etching process for forming the fin structure 400 may include dry etching, wet etching, reactive ion etching (RIE) or other suitable processes.

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

[0072] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0073] In the above embodiments, the descriptions of directions such as “upper”, “lower”, and “side” are all based on the drawings.

[0074] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first substrate (210), forming a stacked structure (220) on top of the first substrate (210), the stacked structure (220) comprising sacrificial layers (231) and channel layers (232) stacked alternately in a direction away from the first substrate (210); forming a first bonding layer (240) on top of the stacked structure (220); Providing a second substrate (310), and forming a second bonding layer (320) on the top of the second substrate (310); at least one of the first bonding layer (240) and the second bonding layer (320) is an insulating material; making the first bonding layer (240) face the second bonding layer (320); as well as The first bonding layer (240) and the second bonding layer (320) are bonded.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After the step of bonding the first bonding layer (240) and the second bonding layer (320), the method further includes: The first substrate (210) is removed.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: After the step of removing the first substrate (210), the method further includes etching the stacked structure (220), the first bonding layer (240), the second bonding layer (320) and a portion of the second substrate (310) to form a fin structure (400).

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of making the first bonding layer (240) and the second bonding layer (320) face each other includes: The device structure formed by the first substrate (210), the stacked structure (220) and the first bonding layer (240) is flipped over so that the first bonding layer (240) is located on top of the second bonding layer (320).

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The first bonding layer (240) and the second bonding layer (320) each include one or more dielectric layers.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The first bonding layer (240) includes one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the second bonding layer (320) is the same as that of the first bonding layer (240).

7. The method for manufacturing a semiconductor device according to claim 1, wherein: In the step of bonding the first bonding layer (240) and the second bonding layer (320), the process temperature is 200 to 500° C., and the process time is 0.5 to 8 hours.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The first bonding layer (240) is formed on the top of the stacked structure (220) through a deposition process, and the second bonding layer (320) is formed on the top of the second substrate (310) through a deposition process.

9. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of removing the first substrate (210) includes: removing a portion of the first substrate (210) by a back grinding process, and removing the remaining first substrate (210) by an etching process.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the channel layer (232) is silicon, and the material of the sacrificial layer (231) is germanium silicon, wherein the concentration of germanium in the sacrificial layer (231) is 10% to 90%.

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