Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: arranging a protection ring which is divided into a plurality of ring segments at the periphery of an active region, arranging binding pads at the two ends of at least one ring segment, enabling the protection ring to comprise a substrate and a plurality of metal layers in the thickness direction, and enabling the adjacent metal layers to be interconnected through a first through hole structure, the bonding pads at least comprise top metal layers, cracks introduced by packaging scribing are prevented from extending into the active area, meanwhile, the back face of the semiconductor structure is heated, resistance between the bonding pads is tested, the heat conduction condition is judged, the real-time monitoring and temperature monitoring functions on the packaging quality of a device at an FT site are achieved, and the reliability of the device is improved. And the protection ring is prepared on the basis of a preparation process compatible with the active region while the active region is prepared, so that the method is compatible with the existing process, an additional photomask or process flow is not needed, and the method has good universality.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the preparation process of GaN RF devices, although the back segment process (back hole and back gold) can effectively reduce parasitic effects, it also brings new challenges, such as Figure 1 As shown, on the one hand, voids 11 are easily formed between the device backhole and the adhesive 10, which will lead to the degradation of heat conduction efficiency. On the other hand, under high temperature or conductive working conditions, due to the difference in thermal expansion coefficients between the void 11 and the adhesive 10, the device is prone to delamination during actual application or temperature cycling (TC) verification, which in turn leads to sample failure.

[0003] Current conventional detection methods, such as C-Sam (C-mode Scanning Acoustic Microscopy), can determine the condition of cavitation, but their timeliness is poor and verification usually requires final testing (FT) at the site, which undoubtedly increases production and time costs.

[0004] The traditional guard ring (Cell Ring) structure only prevents cracks introduced by package dicing from extending into the active area of ​​the device, and cannot meet the needs of real-time monitoring of device packaging quality. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor structure and a preparation method thereof, which are used to solve the problem that the existing detection method has poor timeliness when there are voids between the back hole and the adhesive, thereby leading to degradation of heat conduction efficiency and delamination failure due to differences in thermal expansion coefficients under high temperature or conduction working conditions.

[0006] To achieve the above objectives and other related objectives, the present invention provides a semiconductor structure, comprising:

[0007] an active area, wherein the active area includes a plurality of semiconductor devices;

[0008] A guard ring is arranged around the periphery of the active area and spaced apart from the active area, the guard ring is divided into two or more ring segments, and binding pads are provided at both ends of at least one of the ring segments; the guard ring includes a substrate and several metal layers located above the substrate in the thickness direction; wherein two adjacent metal layers are interconnected through a first via structure, and the binding pads include at least the top metal layer of all the metal layers.

[0009] Optionally, the guard ring is divided into two ring segments of equal size along the extension direction of the guard ring, and the binding pads are provided at both ends of one of the ring segments.

[0010] Optionally, the binding pad includes the substrate and all the metal layers located above the substrate, and two adjacent metal layers are interconnected through the first via structure.

[0011] Optionally,

[0012] The semiconductor device is a D-Mode GaN HEMT device, and the semiconductor device includes, from bottom to top:

[0013] the substrate;

[0014] A gallium nitride-based epitaxial layer, located on the substrate, comprising a channel layer and a barrier layer of a D-Mode GaN HEMT device;

[0015] The electrodes of the D-Mode GaN HEMT device, including a source, a drain and a gate, are located above the gallium nitride-based epitaxial layer, and the source, the drain and the gate are electrically isolated by a dielectric layer;

[0016] a back hole extending from the lower surface of the substrate through the substrate and the gallium nitride-based epitaxial layer to expose the source electrode;

[0017] a back metal layer covering the lower surface of the substrate and the sidewalls and bottom wall of the back hole;

[0018] The active area also includes several interconnect metal layers located above the electrodes of the D-Mode GaN HEMT device;

[0019] The guard ring includes, from bottom to top, the substrate, an epitaxial layer on the same layer as the gallium nitride-based epitaxial layer, and several metal layers; wherein all the metal layers are located above the epitaxial layer, and the number and thickness of all the metal layers correspond one-to-one to the electrodes and all the interconnecting metal layers of the D-Mode GaN HEMT device.

[0020] Furthermore, the semiconductor device further comprises an adhesive, wherein the adhesive covers the surface of the back metal layer on the lower surface of the substrate and fills a portion of the space inside the back hole.

[0021] Furthermore, the material of the channel layer includes GaN, and the material of the barrier layer includes AlGaN.

[0022] Furthermore,

[0023] The interconnect metal layer includes a lower interconnect metal layer and a top interconnect metal layer; the lower interconnect metal layer includes a lower source interconnect metal layer interconnected with the source, a lower gate interconnect metal layer interconnected with the gate, and a lower drain interconnect metal layer interconnected with the drain; the top interconnect metal layer includes a top source interconnect metal layer interconnected with the lower source interconnect metal layer, a top gate interconnect metal layer interconnected with the lower gate interconnect metal layer, and a top drain interconnect metal layer interconnected with the lower drain interconnect metal layer;

[0024] The source electrode and the lower source interconnection metal layer, the lower source interconnection metal layer and the top source interconnection metal layer, the gate electrode and the lower gate interconnection metal layer, the lower gate interconnection metal layer and the top gate interconnection metal layer, the drain electrode and the lower drain interconnection metal layer, and the lower drain interconnection metal layer and the top drain interconnection metal layer are all interconnected through a second via structure;

[0025] The metal layers in the guard ring include, from bottom to top, an electrode metal layer, a lower metal layer, and a top metal layer, wherein the electrode metal layer and the lower metal layer, as well as the lower metal layer and the top metal layer, are interconnected through the first via structure;

[0026] The electrode metal layer corresponds to the electrode of the D-Mode GaN HEMT device in the thickness direction, the lower metal layer corresponds to the lower interconnect metal layer in the thickness direction; the top metal layer corresponds to the top interconnect metal layer in the thickness direction.

[0027] The present invention also provides a method for preparing a semiconductor structure, the method comprising:

[0028] preparing an active area, wherein the active area includes a plurality of semiconductor devices;

[0029] While preparing the active area, based on a preparation process compatible with the active area, guard rings are prepared at intervals around the periphery of the active area, wherein the guard rings are composed of two or more electrically isolated ring segments, and binding pads are provided at both ends of at least one of the ring segments. The guard rings include a substrate and several metal layers above the substrate in the thickness direction, wherein two adjacent metal layers are interconnected through a first via structure, and the binding pads include at least the top metal layer of all the metal layers.

[0030] Optionally, the semiconductor device is a D-Mode GaN HEMT, and the method for preparing the semiconductor device includes:

[0031] providing the substrate;

[0032] forming a gallium nitride-based epitaxial layer on the substrate, wherein the gallium nitride-based epitaxial layer includes a channel layer and a barrier layer of a D-Mode GaN HEMT device;

[0033] forming electrodes of a D-Mode GaN HEMT device on the gallium nitride-based epitaxial layer, wherein the electrodes include a source, a drain, and a gate, and the source, the drain, and the gate are electrically isolated by a dielectric layer;

[0034] forming a back hole from the lower surface of the substrate, penetrating the substrate and the gallium nitride-based epitaxial layer, until the source electrode is exposed;

[0035] forming a back metal layer covering the lower surface of the substrate and the sidewalls and bottom walls of the back hole;

[0036] The active region preparation method includes the steps of forming several interconnect metal layers above the electrode of the D-Mode GaN HEMT device. All the metal layers of the guard ring are formed simultaneously with the electrode and all the interconnect metal layers of the D-Mode GaN HEMT device. The guard ring also includes an epitaxial layer formed simultaneously with the gallium nitride-based epitaxial layer.

[0037] Furthermore,

[0038] The interconnect metal layer includes a lower interconnect metal layer and a top interconnect metal layer; the lower interconnect metal layer includes a lower source interconnect metal layer interconnected with the source, a lower gate interconnect metal layer interconnected with the gate, and a lower drain interconnect metal layer interconnected with the drain; the top interconnect metal layer includes a top source interconnect metal layer interconnected with the lower source interconnect metal layer, a top gate interconnect metal layer interconnected with the lower gate interconnect metal layer, and a top drain interconnect metal layer interconnected with the lower drain interconnect metal layer;

[0039] The source electrode and the lower source interconnection metal layer, the lower source interconnection metal layer and the top source interconnection metal layer, the gate electrode and the lower gate interconnection metal layer, the lower gate interconnection metal layer and the top gate interconnection metal layer, the drain electrode and the lower drain interconnection metal layer, and the lower drain interconnection metal layer and the top drain interconnection metal layer are all interconnected through a second via structure;

[0040] The metal layers in the guard ring include, from bottom to top, an electrode metal layer, a lower metal layer, and a top metal layer, wherein the electrode metal layer and the lower metal layer, as well as the lower metal layer and the top metal layer, are interconnected through the first via structure;

[0041] The electrode metal layer is formed simultaneously with the electrode of the D-Mode GaN HEMT device, the lower metal layer is formed simultaneously with the lower interconnect metal layer, the top metal layer is formed simultaneously with the top interconnect metal layer, and the second via structure is formed simultaneously with the first via structure.

[0042] As described above, the semiconductor structure and its fabrication method of the present invention have the following advantageous effects: The semiconductor structure of the present invention comprises a guard ring divided into multiple segments disposed around the periphery of the active area, and bonding pads disposed at both ends of at least one of the segments. The guard ring comprises a substrate and multiple metal layers in the thickness direction, with adjacent metal layers interconnected by a first via structure, and the bonding pads comprise at least a top metal layer. While preventing cracks introduced by package scribing from extending into the active area, the backside of the semiconductor structure can be heated and the resistance between the bonding pads can be measured to determine thermal conductivity, thereby enabling real-time monitoring of device packaging quality and temperature monitoring at a FT site. This overcomes the shortcomings of existing detection methods, such as poor timeliness and inability to monitor device packaging quality in real time, in particular when addressing thermal conductivity degradation caused by voids between the backside vias and the adhesive, and delamination failure caused by differences in thermal expansion coefficients under high temperature or conductive operating conditions. The semiconductor structure of this embodiment is used to promptly detect thermal conductivity degradation caused by voids or delamination, thereby preemptively screening out defective products and reducing or even avoiding the risk of failure in subsequent applications. The method for preparing a semiconductor structure of the present invention prepares a protective ring divided into multiple electrically isolated ring segments at intervals around the periphery of the active area based on a preparation process compatible with the active area while preparing the active area, and provides binding pads at both ends of at least one ring segment. The method is compatible with existing processes, does not require additional masks or process flows, and has good universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure in the prior art.

[0044] Figure 2 Shown is a schematic top view of a semiconductor structure according to an example of the present invention.

[0045] Figure 3 A schematic top view of a semiconductor structure according to another example of the present invention is shown.

[0046] Figure 4 A schematic top view of a semiconductor structure according to another example of the present invention is shown.

[0047] Figure 5 It is a schematic cross-sectional structure diagram of a guard ring in the semiconductor structure of the present invention.

[0048] Figure 6 It is a schematic cross-sectional structural diagram of a semiconductor device in the semiconductor structure of the present invention.

[0049] Component number description

[0050] 10 Adhesive

[0051] 11 Hollow

[0052] 20 Active area

[0053] 21 protective ring

[0054] 211 First Ring Section

[0055] 212 Second Ring Section

[0056] 22 Bonding Pads

[0057] 23 substrate

[0058] 24 First epitaxial layer

[0059] 25 Second epitaxial layer

[0060] 26 Electrode metal layer

[0061] 27 First via structure

[0062] 28 Lower metal layer

[0063] 29 Top Metal Layer

[0064] 30 epitaxial layer

[0065] 31 metal layer

[0066] 32 electrodes

[0067] 33 channel layer

[0068] 34 Barrier layer

[0069] 35 GaN-based epitaxial layer

[0070] 36 Source

[0071] 37 Drain

[0072] 38 gate

[0073] 39 dielectric layer

[0074] 40 back hole

[0075] 41 back metal layer

[0076] 42 Lower interconnect metal layer

[0077] 43 Top interconnect metal layer

[0078] 44 Interconnect Metal Layer

[0079] 440 Lower source interconnect metal layer

[0080] 441 Top source interconnect metal layer

[0081] 442 Lower gate interconnect metal layer

[0082] 443 Top gate interconnect metal layer

[0083] 444 Lower drain interconnect metal layer

[0084] 445 top drain interconnect metal layer

[0085] 45 Second via structure DETAILED DESCRIPTION

[0086] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] See also Figures 2 to 6 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0088] This embodiment provides a semiconductor structure such as Figures 2 to 4 As shown, the semiconductor structure includes:

[0089] an active area 20, wherein the active area 20 includes a plurality of semiconductor devices;

[0090] A guard ring 21 surrounds the active area 20 and is spaced apart from the active area 20. The guard ring 21 is divided into two or more ring segments, and at least one of the ring segments has bonding pads 22 at both ends. Figure 5 As shown, the guard ring 21 includes a substrate 23 and several metal layers 31 located above the substrate 23 in the thickness direction, wherein two adjacent metal layers 31 are interconnected through a first via structure 27, and the binding pad 22 includes at least the top metal layer 29 of all the metal layers 31.

[0091] It should be noted here that the above-mentioned “more than two ring segments” include the case where the ring segment is divided into two ring segments, and examples thereof may be two, three or four.

[0092] The semiconductor structure of this embodiment comprises a guard ring divided into multiple segments disposed around the periphery of the active area, and bonding pads disposed at both ends of at least one of the segments. The guard ring comprises a substrate and several metal layers in the thickness direction, with adjacent metal layers interconnected by a first via structure. The bonding pads comprise at least a top metal layer. This prevents cracks introduced by package dicing from extending into the active area. Thermal conductivity can be assessed by heating the backside of the semiconductor structure and measuring the resistance between the bonding pads, enabling real-time monitoring of device package quality and temperature at the FT site. This overcomes the shortcomings of existing detection methods, such as poor timeliness and inability to monitor device package quality in real time, by addressing issues such as thermal conductivity degradation caused by voids between the backside vias and the adhesive, and delamination failure caused by differences in thermal expansion coefficients under high temperature or conductive operating conditions. The semiconductor structure of this embodiment is used to promptly detect thermal conductivity degradation caused by voids or delamination, thereby preemptively screening out defective products and reducing or even avoiding the risk of failure in subsequent applications.

[0093] As an example, the binding pad 22 can be connected to the package function PIN pin through a bonding wire. At the FT site, by heating the back of the semiconductor device and utilizing the temperature coefficient of the metal layer (several layers of the metal layer 31) in the guard ring 21 structure, the resistance between the binding pads 22 at both ends of the same ring segment is tested to determine the thermal conductivity of the semiconductor device, thereby screening out defective products from the package FT test site.

[0094] As a good example, Figure 2As shown, the guard ring 21 is divided into two ring segments of equal size along the extension direction of the guard ring 21, and the binding pads 22 are set at both ends of one of the ring segments. Specifically, the two ring segments are a first ring segment 211 and a second ring segment 212, and the binding pads 22 are set at both ends of the first ring segment 211. The division of the two ring segments allows the guard ring 21 to not only have basic protection functions, but also have temperature monitoring functions. The first ring segment 211 is used to monitor temperature changes, and the second ring segment 212 focuses on providing mechanical support and protection to prevent cracks from extending to the active area 20. Of course, the number and size of the ring segments, as well as on which ring segment the binding pads 22 are set, can be flexibly designed according to needs. For example, Figure 3 and Figure 4 As shown, the guard ring 21 is divided into two ring segments with unequal sizes along the extending direction of the guard ring 21. The size of the first ring segment 211 along the extending direction of the guard ring 21 is smaller than the size of the second ring segment 212 along the extending direction of the guard ring 21. The binding pads 22 are set at both ends of one of the ring segments. Figure 3 As shown, the binding pads 22 are provided at both ends of the first ring segment 211, as shown in FIG. Figure 4 As shown, the binding pads 22 are provided at both ends of the second ring segment 212 .

[0095] As an example, the binding pad 22 includes the substrate 23 and all the metal layers 31 located above the substrate 23, and two adjacent metal layers 31 are interconnected through the first via structure 27, that is, the binding pad 22 includes at least the top metal layer 29 in the thickness direction, and may also include other film layers that are the same as the guard ring 21 to increase design flexibility.

[0096] As an example, the type of semiconductor device in the active area 20 can be selected as needed, and exemplarily includes D-Mode GaN HEMT (depletion mode gallium nitride high electron mobility transistor) and E-Mode GaN HEMT (enhancement mode gallium nitride high electron mobility transistor), and is compatible with the existing enhancement mode high electron mobility transistor process using P-type gallium nitride.

[0097] This embodiment is described by taking the semiconductor device as a D-Mode GaN HEMT device as an example. Figure 6 As shown, the semiconductor device includes, from bottom to top:

[0098] The substrate 23;

[0099] A gallium nitride-based epitaxial layer 35 , located on the substrate 23 , including a channel layer 33 and a barrier layer 34 of a D-Mode GaN HEMT device;

[0100] The electrodes 32 of the D-Mode GaN HEMT device, including a source 36, a drain 37, and a gate 38, are located above the gallium nitride-based epitaxial layer 35, and the source 36, the drain 37, and the gate 38 are electrically isolated by a dielectric layer 39;

[0101] a back hole 40 extending from the bottom surface of the substrate 23 through the substrate 23 and the GaN-based epitaxial layer 35 to expose the source electrode 36;

[0102] A back metal layer 41 covers the lower surface of the substrate 23 and the sidewalls and bottom wall of the back hole 40;

[0103] The active area 20 further includes several interconnect metal layers 44 located above the electrodes 32 of the D-Mode GaN HEMT device;

[0104] As an example, Figure 5 As shown, the guard ring 21 includes, from bottom to top, the substrate 23, an epitaxial layer 30 that is the same layer as the gallium nitride-based epitaxial layer 35, and several metal layers 31; wherein all the metal layers 31 are located above the epitaxial layer 30, and the number and thickness of all the metal layers 31 correspond one-to-one to the electrodes 32 and all the interconnect metal layers 44 of the D-Mode GaN HEMT device.

[0105] Specifically, such as Figure 5 As shown, the epitaxial layer 30 includes a first epitaxial layer 24 corresponding to the channel layer 33 in the thickness direction, and a second epitaxial layer 25 corresponding to the barrier layer 34 in the thickness direction.

[0106] As an example, the semiconductor device also includes a bit adhesive (not shown), which covers the surface of the back metal layer 41 on the lower surface of the substrate 23, and also fills part of the space inside the back hole 40, that is, there is a void between the back hole 30 and the adhesive, which can easily lead to degradation of thermal conduction efficiency and delamination failure due to differences in thermal expansion coefficients under high temperature or conduction working conditions. The semiconductor structure of this embodiment can promptly detect the problem of degradation of thermal conduction efficiency caused by voids or delamination, thereby screening out defective products in advance.

[0107] Other layers (such as a transition layer) are illustratively formed between the substrate 23 and the channel layer 33. The specific design can be based on actual needs and is not overly limited herein. The channel layer 33 and the barrier layer 34 are made of different materials. A two-dimensional electron gas is formed at the interface between the channel layer 33 and the barrier layer 34. The two-dimensional electron gas serves as the channel of the HEMT device, providing a conductive channel between the source and drain of the device. As an example, the material of the channel layer 33 includes gallium nitride (GaN), and the material of the barrier layer 34 includes aluminum gallium nitride (AlGaN).

[0108] The interconnection metal layer 44 is used to form interconnections between the electrodes of the semiconductor device. The number of layers of the interconnection metal layer 44 can be set according to actual needs. This embodiment is described by taking two layers of the interconnection metal layer 44 as an example.

[0109] As an example, Figure 6 As shown, the interconnection metal layer 44 includes a lower interconnection metal layer 42 and a top interconnection metal layer 43; the lower interconnection metal layer 42 includes a lower source interconnection metal layer 440 interconnected with the source 36, a lower gate interconnection metal layer 442 interconnected with the gate 38, and a lower drain interconnection metal layer 444 interconnected with the drain 37; the top interconnection metal layer 43 includes a top source interconnection metal layer 441 interconnected with the lower source interconnection metal layer 440, a top gate interconnection metal layer 443 interconnected with the lower gate interconnection metal layer 442, and a top drain interconnection metal layer 445 interconnected with the lower drain interconnection metal layer 444.

[0110] The source 36 and the lower source interconnection metal layer 440, the lower source interconnection metal layer 440 and the top source interconnection metal layer 441, the gate 38 and the lower gate interconnection metal layer 442, the lower gate interconnection metal layer 442 and the top gate interconnection metal layer 443, the drain 37 and the lower drain interconnection metal layer 444, and the lower drain interconnection metal layer 444 and the top drain interconnection metal layer 445 are all interconnected through a second via structure 45.

[0111] like Figure 5 As shown, the several layers of metal layers 31 in the protective ring 21 include, from bottom to top, an electrode metal layer 26, a lower metal layer 28 and a top metal layer 29. The electrode metal layer 26 and the lower metal layer 28, as well as the lower metal layer 28 and the top metal layer 29 are interconnected through the first via structure 27.

[0112] The electrode metal layer 26 corresponds to the electrode 32 of the D-Mode GaN HEMT device in the thickness direction, the lower metal layer 28 corresponds to the lower interconnect metal layer 42 in the thickness direction; the top metal layer 29 corresponds to the top interconnect metal layer 43 in the thickness direction.

[0113] This embodiment also provides a method for preparing a semiconductor structure, which is used to prepare the above-mentioned semiconductor structure, but is not limited thereto. Other suitable preparation methods are also possible. The above content can be quoted in full here, and will not be repeated here for the purpose of brevity. Figures 2 to 6 As shown, the preparation method includes:

[0114] preparing an active area 20, wherein the active area 20 includes a plurality of semiconductor devices;

[0115] While preparing the active area 20, a guard ring 21 is prepared at intervals on the periphery of the active area 20 based on a preparation process compatible with the active area 20. The guard ring 21 is composed of two or more electrically isolated ring segments, and bonding pads 22 are provided at both ends of at least one of the ring segments. Figure 5 As shown, the guard ring 21 includes a substrate 23 and several metal layers 31 located above the substrate 23 in the thickness direction, wherein two adjacent metal layers 31 are interconnected through a first via structure 27, and the binding pad 22 includes the top metal layer 29 of all the metal layers 31.

[0116] The semiconductor structure fabrication method of this embodiment utilizes a fabrication process compatible with the active area to fabricate a guard ring, divided into multiple electrically isolated segments, spaced around the periphery of the active area. Bonding pads are provided at both ends of at least one of the segments. The guard ring comprises a substrate and several metal layers in the thickness direction, with adjacent metal layers interconnected by a first via structure. The bonding pads comprise a top metal layer, thereby preventing cracks introduced by package scribing from extending into the active area. Furthermore, thermal conductivity can be determined by heating the backside of the semiconductor structure and testing the resistance between the bonding pads, enabling real-time monitoring of device packaging quality and temperature at the FT site. This fabrication method overcomes the shortcomings of existing testing methods, such as poor timeliness and inability to monitor device packaging quality in real time. It can promptly detect delamination failures caused by voids between the backside vias and the adhesive, or by differences in thermal expansion coefficients under high temperature or conductive operating conditions, thereby preemptively screening out defective products, reducing or even preventing the risk of failure in subsequent applications. This improves device reliability and production efficiency. Furthermore, the method is compatible with existing processes, requiring no additional photomasks or process flows, and possesses excellent universal applicability.

[0117] As an example, the semiconductor device is a D-Mode GaN HEMT, and the method for preparing the semiconductor device includes:

[0118] Providing the substrate 23;

[0119] forming a gallium nitride-based epitaxial layer 35 on the substrate 23 , wherein the gallium nitride-based epitaxial layer 35 includes a channel layer 33 and a barrier layer 34 of a D-Mode GaNHEMT device;

[0120] Electrodes 32 of the D-Mode GaN HEMT device are formed on the gallium nitride-based epitaxial layer 35 . The electrodes 32 include a source 36 , a drain 37 , and a gate 38 . Adjacent sources 36 , drains 37 , and gates 38 are electrically isolated by a dielectric layer 39 .

[0121] A back hole 40 is formed from the lower surface of the substrate 23 , penetrating the substrate 23 and the GaN-based epitaxial layer 35 until the source electrode 36 is exposed;

[0122] forming a back metal layer 41 covering the lower surface of the substrate 23 and the sidewalls and bottom wall of the back hole 40;

[0123] The method for preparing the active region 20 includes the steps of forming several layers of interconnect metal layers 44 above the electrode 32 of the D-Mode GaN HEMT device. All the metal layers 31 of the guard ring 21 are formed simultaneously with the electrode 32 and all the interconnect metal layers 44 of the D-Mode GaN HEMT device. The guard ring 21 also includes an epitaxial layer 30 formed simultaneously with the gallium nitride-based epitaxial layer 35.

[0124] As an example, Figure 6 As shown, the interconnection metal layer 44 includes a lower interconnection metal layer 42 and a top interconnection metal layer 43; the lower interconnection metal layer 42 includes a lower source interconnection metal layer 440 interconnected with the source 36, a lower gate interconnection metal layer 442 interconnected with the gate 38, and a lower drain interconnection metal layer 444 interconnected with the drain 37; the top interconnection metal layer 43 includes a top source interconnection metal layer 441 interconnected with the lower source interconnection metal layer 440, a top gate interconnection metal layer 443 interconnected with the lower gate interconnection metal layer 442, and a top drain interconnection metal layer 445 interconnected with the lower drain interconnection metal layer 444.

[0125] The source 36 and the lower source interconnection metal layer 440, the lower source interconnection metal layer 440 and the top source interconnection metal layer 441, the gate 38 and the lower gate interconnection metal layer 442, the lower gate interconnection metal layer 442 and the top gate interconnection metal layer 443, the drain 37 and the lower drain interconnection metal layer 444, and the lower drain interconnection metal layer 444 and the top drain interconnection metal layer 445 are all interconnected through a second via structure 45.

[0126] like Figure 5 As shown, the several layers of metal layers 31 in the protective ring 21 include, from bottom to top, an electrode metal layer 26, a lower metal layer 28 and a top metal layer 29. The electrode metal layer 26 and the lower metal layer 28, as well as the lower metal layer 28 and the top metal layer 29 are interconnected through the first via structure 27.

[0127] Among them, the electrode metal layer 26 is formed simultaneously with the electrode 32 of the D-Mode GaN HEMT device, the lower metal layer 28 is formed simultaneously with the lower interconnect metal layer 42, the top metal layer 29 is formed simultaneously with the top interconnect metal layer 43, and the second via structure 45 is formed simultaneously with the first via structure 27 to be compatible with the existing preparation process.

[0128] In summary, the semiconductor structure of the present invention comprises a guard ring divided into multiple segments disposed around the periphery of the active area, and bonding pads disposed at both ends of at least one of the segments. The guard ring comprises a substrate and several metal layers in the thickness direction, with adjacent metal layers interconnected by a first via structure. The bonding pads comprise at least a top metal layer. While preventing cracks introduced by package dicing from extending into the active area, the backside of the semiconductor structure can be heated and the resistance between the bonding pads can be measured to determine thermal conductivity, thereby enabling real-time monitoring of device packaging quality and temperature monitoring at the FT site. This overcomes the shortcomings of existing detection methods, such as poor timeliness and inability to monitor device packaging quality in real time, in particular for thermal conductivity degradation caused by voids between the backside vias and the adhesive, as well as delamination failure caused by differences in thermal expansion coefficients under high temperature or conductive operating conditions. The semiconductor structure of this embodiment is used to promptly detect thermal conductivity degradation caused by voids or delamination, thereby preemptively screening out defective products and reducing or even avoiding the risk of failure in subsequent applications. The semiconductor structure fabrication method of the present invention utilizes a fabrication process compatible with the active area to simultaneously fabricate a guard ring divided into multiple electrically isolated segments at intervals around the periphery of the active area. Bonding pads are provided at both ends of at least one of the segments. This method is compatible with existing processes, requires no additional photomasks or process flows, and exhibits excellent universal applicability. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial applicability.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure comprises: an active area, wherein the active area includes a plurality of semiconductor devices; A guard ring is arranged around the periphery of the active area and spaced apart from the active area, the guard ring is divided into two or more ring segments, and binding pads are provided at both ends of at least one of the ring segments; the guard ring includes a substrate and several metal layers located above the substrate in the thickness direction; wherein two adjacent metal layers are interconnected through a first via structure, and the binding pads include at least the top metal layer of all the metal layers.

2. The semiconductor structure according to claim 1, wherein: The guard ring is divided into two ring segments with equal sizes along the extending direction of the guard ring, and the binding pads are provided at both ends of one of the ring segments.

3. The semiconductor structure according to claim 1, wherein: The binding pad includes the substrate and all the metal layers located above the substrate, and two adjacent metal layers are interconnected through the first via structure.

4. The semiconductor structure according to claim 1, wherein: The semiconductor device is a D-Mode GaN HEMT device, and the semiconductor device includes, from bottom to top: the substrate; a gallium nitride-based epitaxial layer, located on the substrate, comprising a channel layer and a barrier layer of the D-Mode GaN HEMT device; electrodes of the D-Mode GaN HEMT device, comprising a source, a drain, and a gate, located above the gallium nitride-based epitaxial layer, wherein the source, the drain, and the gate are electrically isolated by a dielectric layer; a back hole extending from the lower surface of the substrate through the substrate and the gallium nitride-based epitaxial layer to expose the source electrode; a back metal layer covering the lower surface of the substrate and the sidewalls and bottom wall of the back hole; The active area also includes several interconnect metal layers located above the electrodes of the D-Mode GaN HEMT device; The guard ring includes, from bottom to top, the substrate, an epitaxial layer on the same layer as the gallium nitride-based epitaxial layer, and several metal layers; wherein all the metal layers are located above the epitaxial layer, and the number and thickness of all the metal layers correspond one-to-one to the electrodes and all the interconnecting metal layers of the D-ModeGaN HEMT device.

5. The semiconductor structure according to claim 4, wherein: The semiconductor device further includes an adhesive, which covers the surface of the back metal layer on the lower surface of the substrate and fills a portion of the space inside the back hole.

6. The semiconductor structure according to claim 4, wherein: The material of the channel layer includes GaN, and the material of the barrier layer includes AlGaN.

7. The semiconductor structure according to claim 4, wherein: The interconnect metal layer includes a lower interconnect metal layer and a top interconnect metal layer; the lower interconnect metal layer includes a lower source interconnect metal layer interconnected with the source, a lower gate interconnect metal layer interconnected with the gate, and a lower drain interconnect metal layer interconnected with the drain; the top interconnect metal layer includes a top source interconnect metal layer interconnected with the lower source interconnect metal layer, a top gate interconnect metal layer interconnected with the lower gate interconnect metal layer, and a top drain interconnect metal layer interconnected with the lower drain interconnect metal layer; The source electrode and the lower source interconnection metal layer, the lower source interconnection metal layer and the top source interconnection metal layer, the gate electrode and the lower gate interconnection metal layer, the lower gate interconnection metal layer and the top gate interconnection metal layer, the drain electrode and the lower drain interconnection metal layer, and the lower drain interconnection metal layer and the top drain interconnection metal layer are all interconnected through a second via structure; The metal layers in the guard ring include, from bottom to top, an electrode metal layer, a lower metal layer, and a top metal layer, wherein the electrode metal layer and the lower metal layer, as well as the lower metal layer and the top metal layer, are interconnected through the first via structure; The electrode metal layer corresponds to the electrode of the D-Mode GaN HEMT device in the thickness direction, the lower metal layer corresponds to the lower interconnect metal layer in the thickness direction; the top metal layer corresponds to the top interconnect metal layer in the thickness direction.

8. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: preparing an active area, wherein the active area includes a plurality of semiconductor devices; While preparing the active area, based on a preparation process compatible with the active area, guard rings are prepared at intervals around the periphery of the active area, wherein the guard rings are composed of two or more electrically isolated ring segments, and binding pads are provided at both ends of at least one of the ring segments. The guard rings include a substrate and several metal layers above the substrate in the thickness direction, wherein two adjacent metal layers are interconnected through a first via structure, and the binding pads include at least the top metal layer of all the metal layers.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The semiconductor device is a D-Mode GaN HEMT, and the manufacturing method of the semiconductor device includes: providing the substrate; forming a gallium nitride-based epitaxial layer on the substrate, wherein the gallium nitride-based epitaxial layer includes a channel layer and a barrier layer of a D-Mode GaN HEMT device; forming electrodes of a D-Mode GaN HEMT device on the gallium nitride-based epitaxial layer, wherein the electrodes include a source, a drain, and a gate, and the source, the drain, and the gate are electrically isolated by a dielectric layer; forming a back hole from the lower surface of the substrate, penetrating the substrate and the gallium nitride-based epitaxial layer, until the source electrode is exposed; forming a back metal layer covering the lower surface of the substrate and the sidewalls and bottom walls of the back hole; The active region preparation method includes the steps of forming several interconnect metal layers above the electrode of the D-Mode GaN HEMT device. All the metal layers of the guard ring are formed simultaneously with the electrode and all the interconnect metal layers of the D-Mode GaN HEMT device. The guard ring also includes an epitaxial layer formed simultaneously with the gallium nitride-based epitaxial layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The interconnect metal layer includes a lower interconnect metal layer and a top interconnect metal layer; the lower interconnect metal layer includes a lower source interconnect metal layer interconnected with the source, a lower gate interconnect metal layer interconnected with the gate, and a lower drain interconnect metal layer interconnected with the drain; the top interconnect metal layer includes a top source interconnect metal layer interconnected with the lower source interconnect metal layer, a top gate interconnect metal layer interconnected with the lower gate interconnect metal layer, and a top drain interconnect metal layer interconnected with the lower drain interconnect metal layer; The source electrode and the lower source interconnection metal layer, the lower source interconnection metal layer and the top source interconnection metal layer, the gate electrode and the lower gate interconnection metal layer, the lower gate interconnection metal layer and the top gate interconnection metal layer, the drain electrode and the lower drain interconnection metal layer, and the lower drain interconnection metal layer and the top drain interconnection metal layer are all interconnected through a second via structure; The metal layers in the guard ring include, from bottom to top, an electrode metal layer, a lower metal layer, and a top metal layer, wherein the electrode metal layer and the lower metal layer, as well as the lower metal layer and the top metal layer, are interconnected through the first via structure; The electrode metal layer is formed simultaneously with the electrode of the D-Mode GaN HEMT device, the lower metal layer is formed simultaneously with the lower interconnect metal layer, the top metal layer is formed simultaneously with the top interconnect metal layer, and the second via structure is formed simultaneously with the first via structure.

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