Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate having a first conductivity type, an epitaxial layer formed on the substrate and having the first conductivity type, a plurality of doped portions having a second conductivity type, a trench structure, a well region having the second conductivity type, and a gate structure formed on the epitaxial layer and corresponding to the well region. The epitaxial layer includes a first epitaxial portion formed on the substrate and a second epitaxial portion formed on the first epitaxial portion. The doped parts are arranged in the first epitaxial part, the groove structure is arranged in the second epitaxial part, and the groove structure extends downwards from the top surface of the second epitaxial part and is in contact with one of the doped parts. The well region extends downward from the top surface of the second epitaxial portion into the second epitaxial portion. The first sidewall of the well region contacts the trench structure, and the bottom surface and the second sidewall of the well region contact the second epitaxial portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device and a method for forming the same that can reduce on-resistance and improve device reliability. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum device size, allowing more components to be integrated into a given area. For example, vertical-diffused metal oxide semiconductor (VDMOS) utilizes a vertical structure design to reduce the cell pitch and increase functional density. It uses the back of the chip as the drain, while the source and gate of multiple transistors are fabricated on the front of the chip. This shifts the driving current from a planar flow to a vertical flow, enabling semiconductor devices to withstand high voltages and is widely used in power switching devices.

[0003] As the requirements for the electrical performance of semiconductor devices continue to increase, the types and functions of the integrated devices also increase to meet the application requirements. However, as the requirements for the functional density of semiconductor devices continue to increase, the complexity of the components integrated into the semiconductor devices and their formation methods also increases, and there are some electronic characteristics with performance trade-offs that need to be considered. For example, the above-mentioned vertical semiconductor device uses a conductive trench set in the epitaxial layer as a field plate. However, the critical dimensions of the conductive trench, such as the trench opening width, the trench depth and the trench insulation layer thickness, need to increase with the increase of the device operating voltage to suit higher voltage device operation, thereby increasing the cell pitch between semiconductor units and reducing the setting density of the semiconductor device. Therefore, although existing semiconductor devices and formation methods are generally appropriate and sufficient to meet their intended purposes, they are not completely satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present application provide a semiconductor device comprising a substrate having a first conductivity type and an epitaxial layer formed on the aforementioned substrate and having the first conductivity type. The epitaxial layer comprises a first epitaxial portion formed on the aforementioned substrate and a second epitaxial portion formed on the first epitaxial portion. The semiconductor device further comprises a plurality of doped portions having a second conductivity type disposed in the first epitaxial portion, and a trench structure disposed in the second epitaxial portion, wherein the trench structure extends downward from the top surface of the second epitaxial portion. The trench structure comprises a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, and the insulating layer contacts one of the doped portions. The semiconductor device further comprises a well region having a second conductivity type, which extends downward from the top surface of the second epitaxial portion into the second epitaxial portion. The first sidewall of the well region contacts the trench structure, and the second sidewall of the bottom surface of the well region opposite to the first sidewall contacts the second epitaxial portion. The semiconductor device further comprises a gate structure formed on the top surface of the second epitaxial portion and corresponding to the well region.

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising providing a substrate having a first conductivity type; forming a first epitaxial portion having the first conductivity type on the substrate; forming a plurality of doped portions in the first epitaxial portion, wherein the doped portions have a second conductivity type and extend downward from the top surface of the first epitaxial portion into the first epitaxial portion; forming a second epitaxial portion having the first conductivity type on the first epitaxial portion, wherein the first epitaxial portion and the second epitaxial portion form an epitaxial layer; forming a trench structure extending downward from the top surface of the second epitaxial portion, and the trench structure contacts a corresponding one of the doped portions, wherein the trench structure includes a conductive portion and an insulating layer covering the sidewalls and bottom of the conductive portion, and the insulating layer directly contacts the corresponding doped portion; forming a well region having the second conductivity type extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region, whose bottom surface is opposite to the first sidewall, contacts the second epitaxial portion; and forming a gate structure on the top surface of the second epitaxial portion, and the gate structure corresponds to the well region below. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1G Schematic cross-sectional views of a semiconductor device at various intermediate manufacturing stages according to some embodiments of the present application.

[0007] Figure 2 It is a cross-sectional schematic diagram of a conventional semiconductor device.

[0008] Figure 3 Schematic top view of a doping portion and a trench structure of a semiconductor device according to some embodiments of the present application.

[0009] Figures 4A to 4CSchematic top view of a doped portion and a trench structure of a semiconductor device according to some embodiments of the present application.

[0010] Figure 5 Schematic top view of a doping portion and a trench structure of a semiconductor device according to some embodiments of the present application.

[0011]

Explanation of symbols

[0012] 10,20:Semiconductor devices

[0013] 100,200: substrate

[0014] 102,202: epitaxial layer

[0015] 1021: first extension

[0016] 1022: Second extension

[0017] 102t: Groove

[0018] 104,304,404A,404B,404C,504: Doping

[0019] 104h: Hole

[0020] 105,205: Groove structure

[0021] 1051,2051:Insulation layer

[0022] 1052,2052: conductive part

[0023] 100a, 1021a, 1022a, 104a, 106a: top surface

[0024] 106b, 1052b: bottom surface

[0025] 106,206: Well region

[0026] 106s1: first side wall

[0027] 106s2: second side wall

[0028] RD: Drift Zone

[0029] 108,208: first heavily doped portion

[0030] 110,210: Gate structure

[0031] 111: Gate dielectric layer

[0032] 112: Gate electrode

[0033] 114: interlayer dielectric layer

[0034] 115,215: Second heavily doped portion

[0035] 116,216: Contact plug

[0036] 1161: contact barrier layer

[0037] 1162: Contact conductive layer

[0038] T1: First thickness

[0039] T2: Second thickness

[0040] dp1: first depth

[0041] dp2: second depth

[0042] D1: First direction

[0043] D2: Second direction

[0044] D3: Third direction DETAILED DESCRIPTION

[0045] The following application provides many embodiments or examples for implementing different devices of the provided semiconductor device. Specific examples of each device and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first device formed on a second device, it may include an embodiment in which the first and second devices are in direct contact, and it may also include an embodiment in which an additional device is formed between the first and second devices so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to indicate the relationship between the different embodiments discussed.

[0046] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms may be used in the following description to simplify the description of the relationship between one device or component and other devices or components as shown in the figures. Such spatially relative terms encompass not only the orientation depicted in the figures but also different orientations of the semiconductor device during use or operation. The semiconductor device may be positioned in other orientations, and the spatially relative descriptions used herein should be interpreted accordingly.

[0047] The following describes some variations of the embodiments. Similar device symbols are used to designate similar devices in the various figures and illustrated embodiments. It is understood that additional steps may be provided before, during, or after the method, and that some of the described steps may be replaced or deleted for other embodiments of the method.

[0048] The embodiments of the present application provide semiconductor devices and methods for forming the same, which can produce semiconductor devices suitable for high-voltage operation by designing devices for low-voltage operation. Furthermore, the semiconductor devices of the embodiments can effectively reduce on-resistance and improve device reliability. The embodiments can be applied to metal-oxide-semiconductor (MOS) devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In some of the following embodiments, a metal-oxide-semiconductor field-effect transistor comprising a planar gate and a conductive trench structure is used as an example of a semiconductor device.

[0049] Figures 1A to 1G Schematic cross-sectional views of a semiconductor device at various intermediate manufacturing stages according to some embodiments of the present application.

[0050] Reference Figure 1A According to some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate 100 is a silicon wafer. In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, or the substrate 100 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 100 may include a compound semiconductor, such as silicon carbide or gallium nitride. In some embodiments, the substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, or other suitable substrates. In some embodiments, the substrate 100 may be composed of multiple layers of materials, such as silicon / silicon germanium, silicon / silicon carbide.

[0051] In this example, substrate 100 is, for example, a silicon wafer doped with a first conductivity type dopant. In an application of a metal oxide semiconductor field effect transistor (MOSFET) having a vertical conductive trench, substrate 100 having the first conductivity type can serve as a drain region of the semiconductor device. Furthermore, in this example, the first conductivity type is n-type, but the present application is not limited thereto. In some other examples, the first conductivity type can also be p-type.

[0052] In some embodiments, an epitaxial growth process is performed to form an epitaxial layer 102 on a substrate 100. During the epitaxial growth process, epitaxial layer 102 is grown, for example, in a first direction D1 (e.g., the Z direction). According to an embodiment of the present application, epitaxial layer 102 is grown in a two-stage process. After forming a first epitaxial portion 1021 below, a plurality of doped portions 104 spaced apart are formed in the first epitaxial portion 1021. Then, a second epitaxial portion 1022 is formed above the first epitaxial portion 1021. According to an embodiment of the present application, these doped portions 104 have a different conductivity type than the epitaxial layer 102.

[0053] Reference Figure 1A An epitaxial growth process is performed on the top surface 100a of the substrate 100 to form a first epitaxial portion 1021 having a first conductivity type. A plurality of doped portions 104 having a second conductivity type are formed in the first epitaxial portion 1021. These doped portions 104 extend downward from the top surface 1021a of the first epitaxial portion 1021 into the first epitaxial portion 1021. In some embodiments, these doped portions 104 are spaced apart in a second direction D2 (e.g., the X direction). Furthermore, in some embodiments, these doped portions 104 have substantially the same depth in the first epitaxial portion 1021.

[0054] Furthermore, the substrate 100 and the first epitaxial portion 1021 have the same conductivity type (e.g., the first conductivity type). In this example, the substrate 100 and the first epitaxial portion 1021 are n-type, while the doped portion 104 has an opposite conductivity type to the first epitaxial portion 1021, e.g., p-type. In some embodiments, the doping concentration of the first epitaxial portion 1021 is less than the doping concentration of the substrate 100. The doping concentration of the substrate 100 is, for example (but not limited to), approximately 1E18 atoms / cm 3 to approximately 1E21 atoms / cm 3 The doping concentration of the first epitaxial portion 1021 is, for example (but not limited to), about 1E14 atoms / cm 3 to approximately 1E16 atoms / cm 3 within the range.

[0055] In some embodiments, the doped portion 104 includes a dopant having a second conductivity type (e.g., p-type), and the doping concentration of the doped portion 104 is less than the doping concentration of the substrate 100. In some embodiments, the doping concentration of the doped portion 104 is substantially equal to the doping concentration of the first epitaxial portion 1021. The doping concentration of the doped portion 104 is, for example (but not limited to), approximately 1E14 atoms / cm3 to approximately 1E16 atoms / cm 3 within the range.

[0056] Furthermore, in some embodiments, the doped portion 104 and the first epitaxial portion 1021 comprise the same semiconductor material. For example, the doped portion 104 and the first epitaxial portion 1021 are both made of a silicon-containing material. In some embodiments, the doped portion 104 is epitaxial silicon having a second conductivity type (e.g., p-type).

[0057] The doped portion 104 of the above-described embodiment can be formed using various fabrication methods. For example, a corresponding doped bulk can be formed through an implantation process, or the doped portion 104 can be fabricated by etching a hole 104h in the first epitaxial portion 1021 and filling the hole 104h with a material having the second conductivity type. Two applicable methods for forming the doped portion 104 are briefly described below, but this application does not specifically limit these methods.

[0058] In some embodiments, the doped portion 104 may be formed by a deposition process, a photolithography patterning process, an etching process, and an implantation process. In one embodiment, a hard mask material layer (not shown) (e.g., an oxide hard mask material layer) may be deposited on the top surface 1021a of the first epitaxial portion 1021, and then a patterned photoresist (not shown) may be formed on the hard mask material layer. The hard mask material layer is etched according to the patterned photoresist to form a patterned hard mask (e.g., an oxide hard mask), and the plurality of openings of the patterned hard mask correspond to the positions of the doped portion 104 to be formed. Thereafter, the patterned photoresist is removed, leaving the patterned hard mask. An ion implantation process is performed on the first epitaxial portion 1021 according to the pattern of the patterned hard mask (e.g., the aforementioned openings) to form a plurality of doped regions in the first epitaxial portion 1021. These doped regions extend downward from the top surface 1021a of the first epitaxial portion 1021 into the first epitaxial portion 1021 and contain dopants of the second conductivity type. The patterned hard mask is then removed. A thermal drive-in process, such as a high-temperature annealing process, is then optionally performed to diffuse and shape these doped regions, forming the doped portion 104.

[0059] In some other embodiments, the position of the doped portion 104 can be defined by a suitable photolithography patterning process, and the doped portion 104 can be formed by a suitable deposition process and a planarization process. For example, a mask (not shown) is formed above the first epitaxial portion 1021, and the mask has a plurality of openings to expose the top surface 1021a of the first epitaxial portion 1021. In some embodiments, the mask is a patterned photoresist formed of a photoresist material. In some other embodiments, the material of the mask can be a hard mask (HM) composed of an oxide layer and a nitride layer. Thereafter, a portion of the first epitaxial portion 1021 can be removed through the openings of the mask, for example, by performing one or more etching processes to form a plurality of holes 104h in the first epitaxial portion 1021, and the positions of these holes 104h correspond to the following. Figure 1A The position of the doped portion 104 is shown. The depth of these holes 104h in the first epitaxial portion 1021 (for example, along the first direction D1) is equal to the depth of the subsequently formed doped portion 104 in the first epitaxial portion 1021. The above-mentioned etching process is, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the above-mentioned processes. After the holes are formed, the above-mentioned mask can be removed by an ashing process, a wet etching process (for example, acid etching) or other acceptable processes. Thereafter, a material having a second conductivity type (for example, p-type) is filled in these holes 104h to form the doped portion 104.

[0060] In some examples, a p-type material can be deposited over the first epitaxial portion 1021 through a deposition process, and the p-type material fills the hole 104h. An excess portion of the p-type material above the top surface 1021a of the first epitaxial portion 1021 is then removed through a planarization process to expose the top surface 1021a of the first epitaxial portion 1021. The p-type material in the hole 104h forms the doped portion 104. The deposition process can be, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the aforementioned processes. The planarization process can be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the aforementioned processes.

[0061] Furthermore, according to some embodiments, after forming the doped portion 104, the top surface 104a of the doped portion 104 and the top surface 1021a of the first epitaxial portion 1021 are substantially coplanar, as shown in FIG. Figure 1A shown.

[0062] Afterwards, refer to Figure 1BAccording to some embodiments, epitaxial growth continues on the top surface 1021a of the first epitaxial portion 1021 in the first direction D1 (e.g., the Z direction) to form a second epitaxial portion 1022. The second epitaxial portion 1022 covers the doped portion 104. The second epitaxial portion 1022 also has a first conductivity type, such as n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together constitute an epitaxial layer 102. After the second epitaxial portion 1022 is formed, the doped portion 104 is buried in the epitaxial layer 102. Figure 1B As shown, the doped portion 104 is buried in a lower portion of the epitaxial layer 102 .

[0063] The epitaxial growth process can be performed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods, or a combination of the aforementioned methods to form the first epitaxial portion 1021 and the second epitaxial portion 1022, respectively. In a semiconductor device such as a vertical trench gate metal oxide semiconductor field effect transistor (MOSFET), after the transistor is fabricated, the epitaxial layer 102 having the first conductivity type (e.g., n-type) can serve as a drift region of the semiconductor device.

[0064] Figure 1B The thicknesses of the deposited first epitaxial portion 1021 and second epitaxial portion 1022 are also shown, as well as the depth of the doped portion 104 within the second epitaxial portion 1022. As shown in the figure, the first epitaxial portion 1021 is deposited to a first thickness T1 along a first direction D1, the second epitaxial portion 1022 is deposited to a second thickness T2 along the first direction D1, and the doped portion 104 has a depth dp1 (hereinafter referred to as the first depth dp1) within the second epitaxial portion 1022 along the first direction D1. The first depth dp1 of the doped portion 104 is less than the first thickness T1 of the first epitaxial portion 1021. The first thickness T1 of the first epitaxial portion 1021 can be greater than, equal to, or less than the second thickness T2 of the second epitaxial portion 1022, depending on the electrical requirements of the semiconductor unit in the actual application.

[0065] Then, according to some embodiments, a trench structure 105 is formed in the second epitaxial portion 1022, such as Figure 1C and Figure 1D shown.

[0066] Reference Figure 1C , removing a portion of the second epitaxial portion 1022 to form a plurality of trenches 102t. These trenches 102t are, for example, spaced apart from each other by a distance in the second direction D2 and may extend along the third direction D3. Furthermore, in some embodiments, these trenches 102t correspond to the doped portions 104 below, respectively, and may expose at least a portion of the top surface 104a of the doped portion 104. Furthermore, in some embodiments, the depth of these trenches 102t in the second epitaxial portion 1022 (for example, along the first direction D1) is equal to the depth of the subsequently formed trench structure 105 in the second epitaxial portion 1022 (for example, along the first direction D1).

[0067] According to some embodiments, the trench 102t can be formed by a deposition process, a photolithography patterning process, and an etching process. For example, a hard mask material layer (not shown) is formed above the second epitaxial portion 1022, and a patterned photoresist layer (not shown) is formed on the hard mask material layer. The hard mask material layer can be a single layer or a multi-layer material layer. The patterned photoresist layer has an opening pattern corresponding to the position of the trench 102t. Then, the hard mask material layer and the second epitaxial portion 1022 are sequentially etched through the patterned photoresist layer to remove a portion of the second epitaxial portion 1022, thereby forming the trench 102t. The etching process can be, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the aforementioned processes. After the trench 102t is formed, the patterned photoresist layer is removed. The structure is then subjected to a cleaning process to remove residues. In addition, the hard mask material layer can be removed or left. To simplify the diagram, the hard mask material layer is removed in the figure.

[0068] Afterwards, refer to Figure 1D According to some embodiments, a plurality of trench structures 105 are formed in the trench 102t. Each trench structure 105 contacts a doped portion 104 below. Each trench structure 105 includes, for example, an insulating layer 1051 and a conductive portion 1052. The insulating layer 1051 covers the sidewalls and bottom of the conductive portion 1052.

[0069] Furthermore, if Figure 1DAs shown, each trench structure 105 in the second epitaxial portion 1022 can be spaced apart from each other by a distance in the second direction D2 and extend along the third direction D3. The insulating layer 1051 of each trench structure 105 is in direct contact (e.g., physically in contact with the doped portion 104). Therefore, according to an embodiment, the conductive portion 1052 of the trench structure 105 is electrically isolated from the corresponding doped portion 104 by the insulating layer 1051 of the trench structure 105.

[0070] In some embodiments, the insulating layer 1051 may be silicon oxide, or other suitable semiconductor oxide materials, or a combination of the foregoing materials. In some examples, an oxidation process may be used to conformably form an insulating material on the sidewalls and bottom surface of the trench 102t and on the top surface 1022a of the second epitaxial portion 1022. This insulating material may also be referred to as a shield insulating material. The oxidation process may be, for example, thermal oxidation, radical oxidation, or other suitable processes. Furthermore, in some embodiments, a thermal process may be selectively performed on the insulating material to increase the density of the insulating material. In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

[0071] In some other embodiments, an insulating material may be deposited on the sidewalls and bottom surface of the trench 102t and on the top surface 1022a of the second epitaxial portion 1022 by a deposition process. The deposition process is, for example, a conformal deposition process, and may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, other suitable deposition processes, or a combination of the foregoing processes.

[0072] Then, according to some embodiments, a conductive material (not shown) may be deposited on top of the insulating material through a deposition process, and the conductive material fills the space outside the insulating material in the trench 102t. Furthermore, a thermal process, such as an annealing process, may be optionally performed on the conductive material. In some embodiments, the conductive material may be a single layer or a multilayer structure, and the conductive material may include, for example, polysilicon, other suitable materials, or a combination of the foregoing materials. In some examples, the deposition process for the conductive material may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing processes.

[0073] Next, part of the insulating material and part of the conductive material are removed to form Figure 1D The trench structure 105 is shown. In some examples, the step of removing a portion of the insulating material and a portion of the conductive material may (but is not limited to) include: removing excess conductive material and excess insulating material above the top surface 1022a of the second epitaxial portion 1022 by a planarization process to expose the top surface 1022a of the second epitaxial portion 1022. The planarization process may be, for example, a chemical mechanical polishing (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes.

[0074] After the aforementioned removal step, the remaining portion of the insulating material becomes the insulating layer 1051, and the remaining portion of the conductive material becomes the conductive portion 1052. The conductive portion 1052 is separated from the second epitaxial portion 1022 by the insulating layer 1051. In some examples, after the planarization process, the conductive portion 1052 is located on the insulating layer 1051, and the top surface of the conductive portion 1052 and the top surface of the insulating layer 1051 are substantially coplanar with the top surface 1022a of the second epitaxial portion 1022.

[0075] Furthermore, in some embodiments, the trench structure 105 formed in the second epitaxial portion 1022 has a depth dp2 along the first direction D1 (hereinafter referred to as the second depth dp2 to distinguish it from the first depth dp1 of the doped portion 104). The second depth dp2 of the trench structure 105 is adjusted and determined accordingly with the first depth dp1 of the doped portion 104 below to meet the electrical requirements of the semiconductor unit being used.

[0076] Furthermore, according to some embodiments, the critical width (maximum width) of the bottom of the trench structure 105 is smaller than the critical width (maximum width) of the top surface 104a of the doped portion 104 below and in contact with the trench structure 105. Figure 1D As shown, the width of the bottom surface of the trench structure 105 in the second direction D2 may be smaller than the width of the top surface 104 a of the doped portion 104 in the second direction D2 , but the present application is not limited thereto.

[0077] In some embodiments, when the semiconductor device is operated at high voltage, carriers flowing to the lower first epitaxial portion 1021 can be depleted due to the superjunctions between the different conductivity type doped portion 104 and the first epitaxial portion 1021 as proposed in the embodiments. Therefore, a device design suitable for lower voltage operation, including a smaller cell pitch and a narrower trench structure 105, can be provided in the upper second epitaxial portion 1022. Therefore, according to some embodiments, the upper trench structure 105, in contact with and interaction with the lower doped portion 104, can achieve a semiconductor device design suitable for high voltage operation.

[0078] Afterwards, refer to Figure 1E According to some embodiments, a well region 106 is formed in the second epitaxial portion 1022, and the well region 106 has a conductivity type different from that of the second epitaxial portion 1022, for example, a second conductivity type. In this example, the well region 106 is p-type, also known as a p-body region. Furthermore, the depth of the trench structure 105 in the second epitaxial portion 1022 (for example, the depth dp2 along the first direction D1) is greater than the depth of the well region 106 in the second epitaxial portion 1022 (for example, along the first direction D1). More specifically, the bottom surface of the trench structure 105 is closer to the substrate 100 than the bottom surface of the well region 106. In some embodiments, the doping concentration of the well region 106 is approximately 1E16 atoms / cm 3 to approximately 1E18 atoms / cm 3 According to some embodiments, the surface of the well region 106 can serve as a channel region of a semiconductor device.

[0079] In some embodiments, a bottom surface 1052 b of the conductive portion 1052 of the trench structure 105 is lower than the bottom surface 106 b of the well region 106 , and the bottom surface 1052 b of the conductive portion 1052 is higher than the top surface 1021 a of the first epitaxial portion.

[0080] It is noted that although this example uses a symmetric configuration of components of each semiconductor unit (e.g., a transistor) as an example for illustration, for example, relevant components (including the well region 106, the first heavily doped portion 108, the gate structure 110, the contact plug 116, and other components) are symmetrically formed on opposite sides of a trench structure 105, this application is not limited to this. According to some other embodiments, the design proposed in the above embodiment, including the combination of providing a doped portion 104 in the lower first epitaxial portion 1021 to form a super junction and a trench structure 105 in the upper second epitaxial portion 1022, can also be applied to various semiconductor units having asymmetric components. The following describes the relevant components formed on one side of the trench structure 105 to simplify the description.

[0081] According to some embodiments, one side of the formed well region 106 contacts the trench structure 105, and the other side and the bottom of the well region 106 are covered by the second epitaxial portion 1022 of the epitaxial layer 102. For example, the first sidewall 106s1 of the well region 106 contacts one side of the trench structure 105. In other words, after the well region 106 is formed, one side of the trench structure 105 extends along the first sidewall 106s1 of the well region 106 in the second epitaxial portion 1022, as shown in FIG. Figure 1E shown.

[0082] According to some embodiments, a deposition process, a photolithography patterning process, an etching process, and an implantation process may be performed to form a doping agent in the second epitaxial portion 1022 by doping the top surface 1022a of the second epitaxial portion 1022. Figure 1D The well region 106 is shown. Note that although Figure 1D Although the cross-sectional view cannot be shown, each well region 106 is a doped region extending in the first direction D1 , the second direction D2 , and the third direction D3 .

[0083] Furthermore, according to some embodiments, the epitaxial portion outside and below the well region 106 is a drift region R D , this drift region R D has a first conductivity type (eg, n-type) and is in contact with the second sidewall 106s2 and the bottom surface 106b of the well region 106, such as Figure 1E In this example, the well region 106 and the drift region R D Directly contact the trench structure 105. The well region 106 and the drift region R D The second epitaxial portion 1022 is separated from the conductive portion 1052 by the insulating layer 1051 of the trench structure 105. In some embodiments, when viewed from above the second epitaxial portion 1022, the mask defining the well region 106 (extending in the second direction D2 and the third direction D3, not shown) and the mask defining the trench structure 105 (extending in the second direction D2 and the third direction D3, not shown) partially overlap in the second direction D2, so that the subsequently formed well region 106 contacts one side of the trench structure 105.

[0084] Next, according to some embodiments, doping is performed in the well region 106, for example, from the top surface 106a of the well region 106 (i.e., the top surface 1022a of the second epitaxial portion 1022), to form first heavily doped portions 108 in the well region 106. In some embodiments, one side of these first heavily doped portions 108 contacts the adjacent trench structure 105. For example, the first heavily doped portions 108 directly contact the insulating layer 1051 of the trench structure 105.

[0085] In some embodiments, the first heavily doped portion 108 has the same conductivity type as the epitaxial layer 102, such as the first conductivity type. In this example, the first heavily doped portion 108 is n-type. In some embodiments, the doping concentration of the first heavily doped portion 108 is greater than the doping concentration of the second epitaxial portion 1022. In some embodiments, the doping concentration of the first heavily doped portion 108 is approximately 1E18 atoms / cm 3 to approximately 1E21 atoms / cm 3 between the ranges.

[0086] According to some embodiments, doping can be performed from the top surface 1022a of the second epitaxial portion 1022 through a deposition process, a photolithography patterning process, an etching process, and an implantation process to form the first heavily doped portion 108 in the well region 106. In a non-limiting example, an oxide hard mask material layer (not shown) can be deposited above the top surface 1022a of the second epitaxial portion 1022. A patterned photoresist (not shown) is then formed on the oxide hard mask material layer corresponding to the location of the first heavily doped portion 108. The oxide hard mask material layer is then etched based on the patterned photoresist to form an oxide hard mask. The patterned photoresist is then removed, and the second epitaxial portion 1022 is doped based on the formed oxide hard mask to form the first heavily doped portion 108 in the well region 106. The oxide hard mask is then removed.

[0087] Afterwards, refer to Figure 1F According to some embodiments, a planar gate structure 110 is formed on the top surface 1022a of the second epitaxial portion 1022. Each gate structure 110 corresponds to the well region 106 below. Specifically, in some embodiments, each gate structure 110 is arranged across the corresponding well region 106, the first heavily doped portion 108 in the well region 106, and a portion of the drift region R. D Above.

[0088] In some embodiments, each gate structure 110 includes a gate dielectric layer 111 and a gate electrode 112 located above the gate dielectric layer 111. The gate dielectric layer 111 may be silicon oxide or other suitable dielectric materials. The gate electrode 112 may include polysilicon or other suitable conductive materials. A dielectric material layer (not shown) may be formed on the second epitaxial portion 1022 by a deposition process (such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process) or a thermal oxidation process. Thereafter, a conductive material (not shown) is deposited on the dielectric material layer, and the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or other suitable process. Next, the dielectric material layer and the conductive material may be patterned by a photolithography process and an etching process to form the gate dielectric layer 111 and the gate electrode 112 of the gate structure 110.

[0089] According to some embodiments, Figure 1FAs shown, after the gate structure 110 is formed, an interlayered dielectric (ILD) layer 114 is formed on the epitaxial layer 102. More specifically, the ILD layer 114 is formed on the top surface 1022a of the second epitaxial portion 1022 and covers the gate structure 110, the first heavily doped portion 108, and the trench structure 105.

[0090] In some embodiments, the interlayer dielectric layer 114 may be silicon oxide, other suitable low-k dielectric materials, or a combination thereof. In some embodiments, the material of the interlayer dielectric layer 114 is different from the material of the insulating layer 1051 of the trench structure 105. In other embodiments, the interlayer dielectric layer 114 and the insulating layer 1051 of the trench structure 105 comprise the same material. Furthermore, the interlayer dielectric layer 114 may be deposited on the epitaxial layer 102 by a deposition process. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination thereof.

[0091] Afterwards, refer to Figure 1G According to some embodiments, a contact plug 116 is formed in the interlayer dielectric layer 114 , and the contact plug 116 is electrically connected to the source region of the semiconductor device. A process for forming the contact plug 116 is proposed below.

[0092] In some embodiments, a portion of the interlayer dielectric layer 114, a portion of the first heavily doped portion 108, and a portion of the well region 106 are removed to form a contact hole (not shown) for subsequently forming a contact plug 116. The formed contact hole is located between the gate structure 110 and the trench structure 105, and the bottom of the contact hole, for example, exposes the well region 106.

[0093] According to some embodiments, the contact holes may be formed by a photolithography patterning process and an etching process. For example, after depositing an interlayer dielectric layer 114 above the second epitaxial portion 1022, one or more etching processes are used to remove a portion of the interlayer dielectric layer 114, a portion of the first heavily doped portion 108, and a portion of the well region 106 to form the contact holes. In some embodiments, the photolithography patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or a combination of the aforementioned processes. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the aforementioned processes.

[0094] According to the semiconductor device of some embodiments of the present application, after the contact hole is formed, the remaining portion of the first heavily doped portion 108 can serve as a source region of the semiconductor device of one embodiment.

[0095] According to some embodiments, after forming the contact holes, an ion implantation process may be performed through the bottom of the contact holes to form second heavily doped portions 115 in the well region 106. In some embodiments, these second heavily doped portions 115 have the same conductivity type as the well region 106, such as the second conductivity type. In this example, the second heavily doped portions 115 are p-type.

[0096] In some embodiments, the doping concentration of the second heavily doped portion 115 is greater than the doping concentration of the well region 106. Furthermore, in some embodiments, the doping concentration of the doped portion 104 disposed in the first epitaxial portion 1021 is less than the doping concentration of the second heavily doped portion 115. In some embodiments, the doping concentration of the second heavily doped portion 115 is approximately 1E18 atoms / cm 3 to approximately 1E21 atoms / cm 3 between the ranges.

[0097] Furthermore, in some embodiments, the second heavily doped portion 115 is located around the bottom of the contact hole, and the second heavily doped portion 115 is adjacent to the trench structure 105 and the first heavily doped portion 108. For example, the second heavily doped portion 115 is located below the first heavily doped portion 108. In this example, one side of these second heavily doped portions 115 physically contacts the adjacent trench structure 105, for example, the second heavily doped portion 115 directly contacts the insulating layer 1051 of the trench structure 105. According to some embodiments of the semiconductor device, the formation of the second heavily doped portion 115 can form a good ohmic contact between the subsequently formed contact plug 116 and the well region 106.

[0098] Then, contact plugs 116 are formed in the contact holes. According to some embodiments, along the second direction D2, each contact plug 116 is located between the gate structure 110 and the trench structure 105. According to some embodiments, the contact plugs 116 are electrically connected to the well region 106 and to the first heavily doped portion 108. In this example, the bottom of the contact plug 116 also contacts the second heavily doped portion 115, thereby further improving the electrical connection between the contact plug 116 and the well region 106 through the second heavily doped portion 115. In embodiments where the first heavily doped portion 108 serves as the source region of the semiconductor device 10, the contact plugs 116 may also be referred to as source contacts.

[0099] It is worth noting that Figure 1G The contact plug 116 shown in FIG. 1 directly contacts the adjacent trench structure 105 , that is, there is no drift region R between the contact plug 116 and the adjacent trench structure 105 (along the second direction D2 ). D However, the present application is not limited thereto. In some other embodiments, the contact plug 116 may also be separated from the adjacent trench structure 105 by a distance (not shown), that is, a portion of the first heavily doped portion 108 may be located between the contact plug 116 and the trench structure 105 (along the second direction D2).

[0100] In some embodiments, the contact plug 116 includes a contact barrier layer 1161 and a contact conductive layer 1162. The contact barrier layer 1161 is formed on the sidewalls and bottom of the contact hole and serves as a barrier liner, while the contact conductive layer 1162 fills the remaining space in the contact hole except for the contact barrier layer 1161. Figure 1G As shown, the top surface of the contact plug 116 (including the top surface of the contact barrier layer 1161 and the top surface of the contact conductive layer 1162 ) is substantially coplanar with the top surface of the interlayer dielectric layer 114 .

[0101] In some examples, a barrier material (not shown) can be formed on the interlayer dielectric layer 114 through a deposition process, and the barrier material is isotropically deposited in the contact hole. A conductive material (not shown) is then deposited over the barrier material layer, and the conductive material fills the remaining space in the contact hole. Excess portions of the conductive material and barrier material over the interlayer dielectric layer 114 are then removed, for example, by etching or other suitable methods, to form a contact barrier layer 1161 and a contact conductive layer 1162 in the contact hole.

[0102] In some embodiments, the material of the contact barrier layer 1161 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), ruthenium (Ru), aluminum oxide (Al2O3), magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta2O5), silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), magnesium fluoride (MgF2), calcium fluoride (CaF2), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer 1161 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or combinations thereof.

[0103] In some embodiments, the contact conductive layer 1162 may be a single-layer or multi-layer structure, and its conductive material may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other suitable metals, or combinations thereof. Furthermore, in some embodiments, the conductive material may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, other suitable processes, or combinations thereof.

[0104] After forming contact plug 116, subsequent processes for other components are performed. According to some embodiments, a metal layer (not shown) is formed over interlayer dielectric layer 114 and contact plug 116. The metal layer covers contact plug 116 and is in physical and electrical contact with contact plug 116. Thus, the metal layer is electrically connected to first heavily doped portion 108, second heavily doped portion 115, and well region 106 through contact plug 116.

[0105] In some embodiments, the metal layer may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or a combination of the foregoing materials. In some embodiments, the material of the metal layer is the same as the material of the contact plug 116. In some other embodiments, the material of the metal layer is different from the material of the contact plug 116. According to some embodiments, the metal layer may be formed on the contact plug 116 by a deposition process. In some embodiments, the deposition process may be a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination of the foregoing. According to some embodiments, this metal layer may serve as the top metal of a semiconductor device 10 to electrically connect to the first heavily doped portion 108 serving as the source region, and therefore may also be referred to as a source metal layer. After the metal layer is formed, the process of the semiconductor device 10 is completed.

[0106] According to embodiments, the doped portion 104 reaches a certain depth in the first epitaxial portion 1021. For example, in some embodiments, a ratio of a first depth dp1 of the doped portion 104 in the first epitaxial portion 1021 to a first thickness T1 of the first epitaxial portion 1021 is in a range of approximately 0.4 to approximately 0.9. In some embodiments, the ratio of the first depth dp1 to the first thickness T1 is in a range of approximately 0.5 to approximately 0.8, or in other suitable ranges.

[0107] Furthermore, according to embodiments, the depth of the doped portion 104 also reaches a ratio with respect to the depth of the overlying trench structure 105. For example, in some embodiments, the ratio of the first depth dp1 of the doped portion 104 in the first epitaxial portion 1021 to the second depth dp2 of the trench structure 105 in the second epitaxial portion 1022 is in a range of approximately 0.4 to 2.0, or in a range of approximately 0.5 to 1.5, or in a range of approximately 0.7 to 1.3, or in a range of approximately 0.8 to 1.2, or in other suitable ranges.

[0108] Furthermore, the first depth dp1 of the doped portion 104 of the embodiment can be greater than, equal to, or less than the second depth dp2 of the trench structure 105, depending on the electrical requirements of the semiconductor unit in the actual application. If the first depth dp1 is greater than the second depth dp2, the depth of the depletion region between the first epitaxial portion 1021 and the doped portion 104 increases. While this makes it more difficult to form the doped portion 104, it can reduce the relevant dimensions of the trench structure 105 in the second epitaxial portion 1022 (e.g., the width and depth of the trench structure 105 and the thickness of the insulating layer 1051) and shorten the cell pitch between adjacent semiconductor units. If the second depth dp2 is greater than the first depth dp1, the depth of the depletion region between the first epitaxial portion 1021 and the doped portion 104 decreases, which facilitates the formation of the doped portion 104.

[0109] The semiconductor device proposed according to some of the above embodiments has many advantages. In particular, through the embodiments, a device design suitable for lower voltage operation can be used, including a trench structure 105 with a smaller cell pitch and a narrower size, which cooperates with the doped portion 104 below the trench structure 105 to realize a semiconductor device suitable for high voltage operation. And the semiconductor device proposed in the embodiment can effectively reduce the on-resistance. Furthermore, according to some embodiments, the doped portion 104 located below the trench structure 105 is closer to the substrate 100 (drain region). When a high voltage is applied to the substrate 100, the doped portion 104 can reduce the electric field strength at the bottom of the insulating layer 1051 in the trench structure 105, thereby avoiding the formation of a leakage path between the bottom of the insulating layer 1051 and the substrate 100, thereby improving the reliability of the semiconductor device.

[0110] In addition, according to the semiconductor device of some embodiments of the present application, the conductive portion 1052 of the trench structure 105 can be electrically connected to the gate structure 110. For example, the conductive portion 1052 can be coupled to the gate electrode 112 through other internal connections (not shown) in the semiconductor device. Alternatively, a pin can be provided on the conductive portion 1052, and then the electrical connection with the gate structure 110 can be completed by wire bonding during the packaging stage. According to some embodiments, if the trench structure 105 is subsequently electrically connected to the gate, the conductive portion 1052 of the trench structure 105 can not only reduce the on-resistance, but the conductive portion 1052 of the first conductivity type can also further enhance the effect of reducing the surface electric field (RESURF).

[0111] Furthermore, in semiconductor devices according to some embodiments of the present application, the conductive portion 1052 of the trench structure 105 can also be electrically connected to a source terminal. For example, the conductive portion 1052 can be electrically connected to the first heavily doped portion 108 (source region) and the contact plug 116 (source contact) via other interconnects (not shown) in the semiconductor device. Alternatively, a lead can be provided on the conductive portion 1052, and then wire bonded during the packaging stage to achieve electrical connection with the first heavily doped portion 108 (source region) and the contact plug 116 (source contact).

[0112] Regardless of whether the trench structure 105 of the embodiment is electrically connected to the gate structure 110 or the source terminal, the on-resistance of the semiconductor device of the embodiment can be reduced.

[0113] Furthermore, the semiconductor device of the embodiments can be adapted for use in circuit systems requiring low or high frequency operation through appropriate circuit connections, depending on the application requirements. For example, in some embodiments, the conductive portion 1052 of the trench structure 105 is electrically connected to the gate structure 110. Although this results in a higher gate-drain capacitance (Cgd), the on-resistance is relatively low, making it generally suitable for applications in circuit systems requiring low frequency operation. In some embodiments, the conductive portion 1052 of the trench structure 105 is electrically connected to the source terminal. Although this results in a higher on-resistance, the gate-drain capacitance (Cgd) is lower, resulting in faster device switching speeds, making it generally suitable for applications in circuit systems requiring high frequency operation.

[0114] Furthermore, the semiconductor device proposed in the embodiment can be flexibly configured and designed according to application requirements. For example, a semiconductor structure may include multiple semiconductor cells as shown in the embodiment disposed on a substrate 100, wherein the conductive portions 1052 of the trench structures 105 of these cells can all be electrically connected to the source terminal or all be electrically connected to the gate structure 110, or a portion of the conductive portions 1052 of the trench structures 105 can be electrically connected to the source terminal, while the remaining portion of the conductive portions 1052 of the trench structures 105 can be electrically connected to the gate structure 110. Therefore, the semiconductor device proposed in the embodiment can be flexibly applied.

[0115] This application also presents electrical simulations of conventional semiconductor devices and some of the semiconductor devices of the embodiments. The simulation results demonstrate that the embodiments effectively improve various electronic characteristics of the semiconductor devices. The electrical simulations are described below.

[0116] Figure 2 It is a cross-sectional schematic diagram of a conventional semiconductor device. Figure 2 Zhongyu Figure 1G The same or similar components use the same or similar reference signs, and reference may be made to the contents of the above embodiments regarding these components, which will not be described in detail here.

[0117] like Figure 2 The semiconductor device 20 shown in FIG. 1 has a plurality of trench structures 205 formed in an epitaxial layer 202 grown on a substrate 200, wherein the trench structures 205 include an insulating layer 2051 and a conductive portion 2052. In a simulation test, the depth of the trench structures 205 in the epitaxial layer 202 is equal to that of the embodiment ( Figure 1G ) is the sum of the depth of the trench structure 105 and the depth of the doped portion 104. Figure 2The semiconductor device 20 shown also includes components such as a well region 206 having a second conductivity type (e.g., p-type), a first heavily doped portion 208 having a first conductivity type (e.g., n-type), a second heavily doped portion 215 having a second conductivity type (e.g., p-type), a gate structure 210, and a contact plug 216. Figure 2 For details on the configuration, materials and manufacturing methods of the components, please refer to the above Figures 1A to 1G The relevant description of the content will not be repeated here.

[0118] In this simulation experiment, Figure 1G The semiconductor device of the embodiment shown and Figure 2 The conventional semiconductor device shown is used as a comparative example, and a number of related electrical simulation tests are performed.

[0119] Table 1 lists the semiconductor devices of the present invention ( Figure 1G ) and conventional semiconductor devices ( Figure 2 ) when achieving the same breakdown voltage, for example, approximately 80V, the relevant size and electrical simulation results of the semiconductor device.

[0120] Table 1

[0121]

[0122] According to simulation results, when the breakdown voltage reaches the same value (e.g., about 80V), the conventional semiconductor device ( Figure 2 The critical dimension (e.g., along the second direction D2) of the epitaxial layer mesa of the embodiment semiconductor device is slightly higher than that of the epitaxial layer mesa of the embodiment semiconductor device. However, the trench opening critical dimension (0.6 micron) of the embodiment semiconductor device is only half that of a conventional semiconductor device, and the thickness of the insulating layer (e.g., shielding oxide layer) within the trench is approximately 53% of that of a conventional semiconductor device. According to Table 1, the cell pitch (2.68 microns) of the embodiment semiconductor device is approximately 34% lower than the cell pitch (4.06 microns) of the conventional semiconductor device. In other words, more semiconductor cells of the embodiment can be arranged within the same unit area.

[0123] If the data of the trench opening critical dimension (0.6 micron) and the trench insulation layer thickness (1900 angstroms) of the embodiment shown in Table 1 are used to make the following Figure 2If the trench structure 205 shown is used as a field plate in a semiconductor device without the doped portion 104 of the embodiment, the breakdown voltage of the semiconductor device is reduced and cannot reach 80 V, for example, it may only be 52 V. Therefore, according to the design of the trench structure and the doped portion of the embodiment of the present application, a device with a higher breakdown voltage can be realized by configuring the trench of a device with a lower breakdown voltage.

[0124] Furthermore, according to the electrical performance simulation results in Table 1, in the semiconductor device of the embodiment, whether the trench structure is electrically connected to the gate structure or the source terminal, the on-resistance of the semiconductor device of the embodiment can be reduced. Taking the trench structure electrically connected to the gate structure as an example, the characteristic on-resistance of the semiconductor device of the embodiment (14.83mΩ-mm 2 ) compared to the characteristic on-resistance of conventional semiconductor devices (24.68mΩ-mm 2 ) is greatly improved by about 40%. Taking the trench structure electrically connected to the source terminal as an example, the characteristic on-resistance of the semiconductor device of the embodiment (16.09mΩ-mm 2 ) compared to the characteristic on-resistance of conventional semiconductor devices (29.02mΩ-mm 2 ) has significantly improved by approximately 44.5%.

[0125] Furthermore, whether it is the semiconductor device of the embodiment or the conventional semiconductor device, the trench structure electrically connected to the gate structure can provide a field effect, so its on-resistance is lower than the on-resistance electrically connected to the source terminal. According to Table 1, the characteristic on-resistance (16.09 mΩ-mm) of the trench structure electrically connected to the source terminal of the semiconductor device of the embodiment is 2 ) is also higher than the characteristic on-resistance (24.68mΩ-mm) of the trench structure of the conventional semiconductor device electrically connected to the gate structure. 2 Therefore, the semiconductor device of the embodiment effectively improves the on-resistance.

[0126] In addition, the figure of merit (FOM) can be used to evaluate device performance, where the FOM is the product of the characteristic charge (Qg,sp, the charge required per unit area when charging and discharging a capacitor) and the characteristic on-resistance (Ron,sp). According to the electrical performance simulation results in Table 1, the FOM of the semiconductor device of the embodiment is lower than the FOM of the conventional semiconductor device, regardless of whether the trench structure is electrically connected to the gate structure or the source terminal. Taking the trench structure electrically connected to the gate structure as an example, the FOM of the semiconductor device of the embodiment (278.02mΩ-nC) is significantly improved by approximately 34.1% compared to the FOM of the conventional semiconductor device (421.93mΩ-nC). Taking the trench structure electrically connected to the source terminal as an example, the FOM of the semiconductor device of the embodiment (83.65mΩ-nC) is improved by approximately 10.4% compared to the FOM of the conventional semiconductor device (93.33mΩ-nC).

[0127] Furthermore, the size of the characteristic charge of the semiconductor device will affect the switching speed of the device. The larger the value of the characteristic charge, the more charge is required per unit area when the capacitor is charged and discharged, the slower the switching speed, and the semiconductor device is suitable for low-frequency operation. The smaller the value of the characteristic charge, the less charge is required per unit area when the capacitor is charged and discharged, the faster the switching speed, and the semiconductor device is suitable for high-frequency operation. According to Table 1, compared with the traditional semiconductor device, the characteristic charge value of the semiconductor device of the embodiment has only increased slightly, so the semiconductor device of the embodiment still has a good switching speed. Moreover, compared with the traditional semiconductor device, the semiconductor device of the embodiment can achieve the effect of significantly improving the characteristic on-resistance without sacrificing the characteristic charge.

[0128] Furthermore, when high-voltage operation is performed on a semiconductor device with vertical current flow (with the substrate as the drain terminal), excessively high electric field strength at the bottom of the trench insulation layer can easily damage the trench insulation layer, causing leakage or even a short circuit between the conductive portion within the trench and the substrate, thereby impacting the reliability of the semiconductor device. According to the electrical performance simulation results in Table 1, at the same breakdown voltage (approximately 80V), the electric field strength at the bottom of the trench insulation layer in the semiconductor device of the embodiment (2.18 MV / cm) is lower than that in conventional semiconductor devices (2.88 MV / cm), representing an improvement of approximately 24.3%. In the semiconductor device of the embodiment, the reduced electric field strength at the bottom of the trench insulation layer prevents damage to the trench insulation layer, resolving the leakage or short circuit issues that can occur in conventional semiconductor devices, thereby improving the reliability of the semiconductor device.

[0129] <Some Other Embodiments>

[0130] In addition, although the semiconductor device according to the above example, Figure 1G As shown, the extension direction of the doped portion 104 in the first epitaxial portion 1021 (for example, the third direction D3) is the same as the extension direction of the trench structure 105 above in the second epitaxial portion 1022 (for example, the third direction D3). These doped portions 104 can be pillars having a second conductivity type, for example, P-type pillars, wherein these P-type pillars are arranged at a distance from each other in the first epitaxial portion 1021 and extend along the same direction. However, the doped portion 104 and the trench structure 105 of the present application are not limited to the above configuration. The extension directions of the doped portion 104 and the trench structure 105 of the embodiment can be the same or different (for example, perpendicular to each other), and the shape of the doped portion 104 is not particularly limited.

[0131] The following describes configurations of the doped portion 104 and the trench structure 105 that are applicable to some (but not all) embodiments.

[0132] Figure 3 FIG. 1 is a schematic top view of a doping portion and a trench structure of a semiconductor device according to some embodiments of the present application. In some embodiments, the doping portion 304 and the trench structure 305 have different extension directions. Figure 3 As shown, the trench structure 305 extends along the third direction D3 in the second epitaxial portion 1022 , and the doped portion 304 of the embodiment extends along the second direction D2 in the first epitaxial portion 1021 , wherein the second direction D2 is perpendicular to the third direction D3 .

[0133] In addition, in some other embodiments, the extension direction of the doped portion 104 and the extension direction of the trench structure 105 may have an angle (not shown), and the angle is in a range from greater than 0 degrees to less than 90 degrees.

[0134] Furthermore, the shape of the doped portion 104 of the present application may be other shapes, in addition to the second conductivity type pillars (e.g., P-type pillars) of the above-described embodiment. For example, the doped portion 104 may be island blocks of the second conductivity type. When viewing the epitaxial layer 102 from above, the top surfaces of these island blocks may be rectangular, square, circular, elliptical, hexagonal, other polygonal, annular, or other suitable shapes. This application does not specifically limit this.

[0135] Figures 4A to 4C FIG. 1 is a top view of a doped portion and a trench structure of a semiconductor device according to some embodiments of the present application. Figures 4A to 4C As shown, doped portions 404A, 404B, and 404C are islands of the second conductivity type. These islands are spaced apart from each other in the first epitaxial portion 1021, and the bottom of each trench structure 305 may contact one or more islands. Furthermore, the islands corresponding to adjacent trench structures 305 can be arranged in multiple rows or staggered.

[0136] like Figure 4A As shown, in some embodiments, the doped portions 404A are islands with rectangular top surfaces and are spaced apart in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404A.

[0137] like Figure 4B As shown, in some embodiments, the doped portions 404B are islands with rounded top surfaces and are spaced apart in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404B.

[0138] like Figure 4C As shown, in some embodiments, the doped portions 404C are islands with hexagonal top surfaces and are spaced apart in the first epitaxial portion 1021 , wherein the bottom of the trench structure 305 contacts two or more doped portions 404C.

[0139] Figure 5 FIG. 1 is a schematic top view of a doping portion and a trench structure of a semiconductor device according to some embodiments of the present application. Figure 5 As shown, in some embodiments, the doped portions 504 are hollow pillars of the second conductivity type. These hollow pillars have an annular top surface in the first epitaxial portion 1021. The bottom of the trench structure 305 is in contact with the doped portions 504. Furthermore, these doped portions 504 are, for example, arranged in a concentric arrangement.

[0140] For details on the configuration, materials and manufacturing methods of the doped portions 304, 404A, 404B, 404C, 504 and the trench structure 305, please refer to the above Figures 1A to 1D The description about the doping portion 104 and the trench structure 105 will not be repeated here.

[0141] In summary, the semiconductor device proposed in the embodiment has many advantages. For example, a device design suitable for lower voltage operation (including a smaller cell pitch and a narrower trench structure) can be used in conjunction with the doped portion below to realize a semiconductor device suitable for high voltage operation. Therefore, more semiconductor units of the embodiment can be formed under the same unit area. Furthermore, the semiconductor device proposed in the above embodiment can effectively reduce the on-resistance and improve the electrical performance of the semiconductor device. Furthermore, the doped portion proposed in the embodiment can reduce the electric field strength at the bottom of the trench insulating layer, thereby avoiding the formation of a leakage path or even a short circuit between the bottom of the insulating layer and the substrate to which high voltage is applied, so the semiconductor device proposed in the embodiment can have better reliability. Furthermore, the method for forming the semiconductor device proposed in the embodiment can be obtained through a simple process, for example, only a mask needs to be added to form the doped portion of the embodiment in the lower part of the epitaxial layer, and the semiconductor device of the embodiment can be obtained. The process is simple and compatible with existing processes.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; an epitaxial layer located above the substrate, and having the first conductivity type, wherein the epitaxial layer comprises: a first epitaxial portion located on the substrate; and a second extension portion, located on the first extension portion; a plurality of doped portions disposed in the first epitaxial portion, wherein the doped portions have a second conductivity type; a trench structure disposed in the second epitaxial portion and extending downward from a top surface of the second epitaxial portion, wherein the trench structure includes a conductive portion and an insulating layer covering sidewalls and a bottom of the conductive portion, and the insulating layer of the trench structure contacts one of the doped portions; a well region extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, the well region having the second conductivity type, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region opposite to the first sidewall contacts the second epitaxial portion; and A gate structure is formed on the top surface of the second epitaxial portion and corresponds to the well region.

2. The semiconductor device according to claim 1, wherein The conductive portion of the trench structure and the corresponding contacted doped portion are electrically isolated by the insulating layer of the trench structure.

3. The semiconductor device according to claim 1, wherein A top surface of the doped portion is coplanar with a top surface of the first epitaxial portion.

4. The semiconductor device according to claim 1, wherein A bottom surface of the conductive portion of the trench structure is lower than a bottom surface of the well region, and the bottom surface of the conductive portion is higher than a top surface of the first epitaxial portion.

5. The semiconductor device according to claim 1, wherein The doping concentration of the doping portion disposed in the first epitaxial portion is equal to the doping concentration of the first epitaxial portion.

6. The semiconductor device according to claim 1, wherein Also includes: a first heavily doped portion formed in the well region and extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, wherein the first heavily doped portion has the first conductivity type, The doping concentration of the doping portion disposed in the first epitaxial portion is lower than the doping concentration of the first heavily doped portion.

7. The semiconductor device according to claim 6, wherein: Also includes: a second heavily doped portion formed in the well region and adjacent to the trench structure, wherein the second heavily doped portion has the second conductivity type; The doping concentration of the doped portion disposed in the first epitaxial portion is lower than the doping concentration of the second heavily doped portion.

8. The semiconductor device according to claim 1, wherein A ratio of a depth of the doped portion in the first epitaxial portion to a depth of the trench structure in the second epitaxial portion is in a range from 0.5 to 1.

5.

9. The semiconductor device according to claim 1, wherein A ratio of a depth of the doped portion in the first epitaxial portion to a thickness of the first epitaxial portion is in a range from 0.4 to 0.

9.

10. The semiconductor device according to claim 1, wherein An extending direction of the doped portion in the first epitaxial portion is the same as an extending direction of the trench structure in the second epitaxial portion.

11. The semiconductor device according to claim 1, wherein An extending direction of the doped portion in the first epitaxial portion is different from an extending direction of the trench structure in the second epitaxial portion.

12. The semiconductor device according to claim 1, wherein The doped portions are columns having the second conductivity type. The columns are spaced apart from each other in the first epitaxial portion and extend along a same direction.

13. The semiconductor device according to claim 12, wherein: The width of the bottom surface of the trench structure is smaller than the width of the top surface of the pillar in contact therewith.

14. The semiconductor device according to claim 1, wherein The doped portion is an island block having the second conductivity type, and the island blocks are arranged at a distance from each other in the first epitaxial portion. The bottom of the trench structure contacts two or more island blocks.

15. The semiconductor device according to claim 14, wherein Looking down at the epitaxial layer, the top surface of the island block is rectangular, square, circular, elliptical, hexagonal, or other polygonal shapes.

16. The semiconductor device according to claim 1, wherein The doped portion is a hollow tube column having the second conductivity type, and the hollow tube column has a ring-shaped top surface in the first epitaxial portion.

17. The semiconductor device according to claim 1, wherein The conductive portion of the trench structure is electrically connected to a source terminal of the semiconductor device.

18. The semiconductor device according to claim 1, wherein The conductive portion of the trench structure is electrically connected to the gate structure.

19. A method for forming a semiconductor device, characterized in that: include: Providing a substrate having a first conductivity type; forming a first epitaxial portion having the first conductivity type on the substrate; forming a plurality of doped portions in the first epitaxial portion, wherein the doped portions have a second conductivity type, wherein the doped portions extend downward from a top surface of the first epitaxial portion into the first epitaxial portion; forming a second epitaxial portion having the first conductivity type on the first epitaxial portion, wherein the first epitaxial portion and the second epitaxial portion form an epitaxial layer; forming a trench structure extending downward from a top surface of the second epitaxial portion and contacting a corresponding one of the doped portions, wherein the trench structure comprises a conductive portion and an insulating layer covering sidewalls and a bottom of the conductive portion, the insulating layer directly contacting the corresponding doped portion; forming a well region extending downward from the top surface of the second epitaxial portion into the second epitaxial portion, wherein the well region has the second conductivity type, wherein a first sidewall of the well region contacts the trench structure, and a second sidewall of the well region opposite to the first sidewall and contacting the second epitaxial portion; as well as A gate structure is formed on the top surface of the second epitaxial portion, and the gate structure corresponds to the well region below.

20. The method for forming a semiconductor device according to claim 19, wherein: The doped portion is formed after forming the first epitaxial portion and before forming the second epitaxial portion.

21. The method for forming a semiconductor device according to claim 19, wherein: Forming the doping portion includes: forming a mask above the first epitaxial portion, wherein the mask has a pattern corresponding to the doped portion; performing an ion implantation process on the first epitaxial portion through the pattern of the mask to form a plurality of doped regions in the first epitaxial portion, wherein the doped regions contain dopants of the second conductivity type; and A thermal drive-in process is performed to diffuse the doped region to form the doped portion.

22. The method for forming a semiconductor device according to claim 19, wherein: Forming the doping portion includes: forming a plurality of holes in the first extension portion, wherein the holes extend downwardly from the top surface of the first extension portion into the first extension portion; and The hole is filled with a material having the second conductivity type to form the doped portion.

23. The method for forming a semiconductor device according to claim 19, wherein: The doped portion and the first epitaxial portion include the same semiconductor material.

24. The method for forming a semiconductor device according to claim 19, wherein: The conductive portion of the trench structure is electrically isolated from the corresponding contacted doped portion by the insulating layer of the trench structure.

25. The method for forming a semiconductor device according to claim 19, wherein: The doping concentration of the doping portion formed in the first epitaxial portion is equal to the doping concentration of the first epitaxial portion.

26. The method for forming a semiconductor device according to claim 19, wherein: A depth of the doped portion formed in the first epitaxial portion relative to a depth of the trench structure formed in the second epitaxial portion has a ratio ranging from 0.5 to 1.

5.

27. The method for forming a semiconductor device according to claim 19, wherein: Before forming the gate structure, the method further includes: doping the well region from the top surface of the second epitaxial portion to form a first heavily doped portion, wherein the first heavily doped portion has the first conductivity type, wherein the doping concentration of the first heavily doped portion is greater than the doping concentration of the doped portion, and The gate structure corresponds to the first heavily doped portion thereunder.

28. The method for forming a semiconductor device according to claim 27, wherein: After forming the gate structure, the forming method further includes: forming an interlayer dielectric layer on the top surface of the second epitaxial portion and covering the gate structure, the first heavily doped portion and the trench structure; removing a portion of the interlayer dielectric layer, a portion of the first heavily doped region, and a portion of the well region to form a contact hole, wherein a bottom of the contact hole exposes the well region; doping in the well region through the contact hole to form a second heavily doped portion below the contact hole, wherein the doping concentration of the doped portion formed in the first epitaxial portion is lower than the doping concentration of the second heavily doped portion; and A contact plug is formed in the contact hole. The contact plug is located between the gate structure and the trench structure, and a bottom of the contact plug contacts the second heavily doped portion.

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