Semiconductor device terminal structure and preparation method thereof, and semiconductor device

Abstract

The invention relates to a semiconductor device terminal structure and a preparation method thereof, and a semiconductor device, in the semiconductor device terminal structure, a substrate of a first conductive type comprises a cellular region and a terminal region; the doped region of the second conductive type is located in the cellular region; the at least one field limiting ring is sequentially distributed in the terminal region along the direction far away from the doped region; the ion implantation layer of the second conduction type is at least located between the adjacent doped regions and the field limiting rings and between the adjacent field limiting rings; the isolation layer covers the doped region, the at least one field limiting ring and the ion implantation layer; the isolation layer comprises a first isolation structure embedded in the doped region and a plurality of second isolation structures located right above the ion implantation layer; the plurality of conductive field plates are distributed on the isolation layer at intervals, and comprise a first field plate electrically connected with the doped region and a second field plate electrically connected with the field limiting ring. The voltage-withstanding amplitude and the voltage-withstanding stability of the semiconductor device terminal structure can be improved at least under the condition that the size and the volume of the device are not increased.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device terminal structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] As one of the core and fundamental components of power electronics technology, semiconductor devices play a vital role in fields such as energy, transportation, consumer electronics, and communications. Modern society places increasingly stringent demands on the performance, reliability, and safety of semiconductor devices. Whether it's second- or third-generation semiconductors, the terminal is an integral part of the semiconductor device and plays a crucial role. Its performance, reliability, and safety directly impact that of the semiconductor device itself.

[0003] However, in related technologies, the interface between the cylindrical and spherical junctions in the terminal region of semiconductor devices is prone to electric field concentration, leading to breakdown failure. Improving the voltage stability and withstand capability of the terminal without increasing device size is a pressing technical challenge facing researchers. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device terminal structure and its preparation method, and a semiconductor device to address the technical problems in the above-mentioned background technology, which can at least improve the voltage resistance amplitude and voltage resistance stability of the semiconductor device terminal structure without increasing the size and volume of the device.

[0005] To achieve the above-mentioned and other purposes, the first aspect of the present disclosure provides a semiconductor device terminal structure, comprising: a substrate of a first conductive type, a doped region of a second conductive type, at least one field limiting ring, an ion implantation layer of a second conductive type, an isolation layer, and a plurality of conductive field plates; the substrate of the first conductive type comprises a cell region and a terminal region; the doped region of the second conductive type is located in the cell region; at least one field limiting ring is sequentially distributed in the terminal region in a direction away from the doped region; the ion implantation layer of the second conductive type is at least located between adjacent doped regions and field limiting rings, and between adjacent field limiting rings; the isolation layer covers the doped region, at least one field limiting ring, and the ion implantation layer; wherein the isolation layer comprises a first isolation structure embedded in the doped region, and a plurality of second isolation structures located directly above the ion implantation layer; a plurality of conductive field plates are spaced apart on the isolation layer, including a first field plate electrically connected to the doped region, and a second field plate electrically connected to the field limiting ring.

[0006] In the semiconductor device terminal structure in the above embodiment, the second conductive type doped region and the first conductive type substrate in the cell region form a main junction, at least one field limiting ring and the main junction can be prepared simultaneously in the same process step, and the field limiting ring can be electrically connected to a one-to-one conductive field plate to form a bias field plate structure; a PN junction is formed between the second conductive type ion implantation layer and the first conductive type substrate thereunder, so that the first isolation structure between adjacent doped regions and field limiting rings, and the second isolation structure between adjacent field limiting rings are respectively isolated from the substrate via the PN junction, thereby optimizing the electric field distribution, weakening the electric field strength of the field limiting ring adjacent to the main junction, increasing the dielectric breakdown amplitude, increasing the depletion region inside the substrate, and improving the overall voltage withstand amplitude of the device, thereby achieving the improvement of the voltage withstand amplitude and voltage withstand stability of the semiconductor device terminal structure without increasing the size and volume of the device.

[0007] In some embodiments, the terminal region is located at the periphery of the cell region, and a PN junction is formed between the second conductive type ion implantation layer in the terminal region and the first conductive type substrate thereunder, so that the first isolation structure between adjacent doped regions and field limiting rings, and the second isolation structure between adjacent field limiting rings are respectively isolated from the substrate via the PN junction, thereby optimizing the electric field distribution, weakening the electric field strength of the field limiting rings adjacent to the main junction, increasing the dielectric breakdown amplitude, increasing the depletion region inside the substrate, and improving the overall voltage withstand amplitude of the device.

[0008] In some embodiments, the doping concentration of the ion implantation layer is lower than the doping concentration of the doping region. The ion implantation layer between adjacent doping regions, between field limiting rings, and between adjacent field limiting rings is used to increase the depletion region inside the substrate, optimize the electric field distribution, and weaken the electric field strength of the field limiting ring adjacent to the main junction.

[0009] In some embodiments, the process steps of the isolation layer precede the process steps of the ion implantation layer, so that the ion implantation process can be performed directly using the grooves of the isolation layer to form the ion implantation layer, avoiding the addition of additional masks due to the introduction of the second conductive type ion implantation layer, thereby reducing the complexity and cost of the preparation process.

[0010] In some embodiments, the semiconductor device terminal structure further includes a plurality of conductive plugs penetrating the isolation layer, the plurality of conductive plugs including a first sub-plug and a second sub-plug, the first sub-plug being located between the first field plate and the doped region; the second sub-plug being located between the second field plate and the field limiting ring.

[0011] In some embodiments, multiple conductive plugs are fabricated simultaneously in the same process step to reduce the complexity and cost of the fabrication process.

[0012] In some embodiments, the semiconductor device terminal structure further includes a cutoff ring of the first conductivity type, which is located in the terminal region on the side of at least one field limiting ring away from the doped region. By providing a cutoff ring at the outermost side of the terminal structure as a protective layer, the electric field is effectively cut off before reaching the physical edge of the device. The cutoff ring reduces or evens out the electric field strength at the terminal end, thereby avoiding electric field concentration caused by edge curvature effects and thus preventing premature breakdown. The cutoff ring can also limit the lateral expansion of the electric field, preventing the electric field from extending to inactive areas of the device (such as packaging or cutting edges), ensuring that the electric field distribution is strictly controlled within the design range.

[0013] In some embodiments, at least one field limiting ring and the doped region are fabricated simultaneously in the same process step, which can reduce the number of masks used and reduce the complexity of the fabrication process.

[0014] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0015] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0016] In some embodiments, a second aspect of the present disclosure provides a semiconductor device, comprising: a semiconductor device terminal structure as described in any of the aforementioned embodiments. A PN junction is formed between the second conductivity type ion implantation layer and the first conductivity type substrate thereunder, such that adjacent doped regions and first isolation structures between field limiting rings, as well as second isolation structures between adjacent field limiting rings, are each isolated from the substrate via the PN junction. This optimizes the electric field distribution, weakens the electric field strength of the field limiting rings adjacent to the main junction, increases the dielectric breakdown amplitude, increases the depletion region within the substrate, and improves the overall withstand voltage amplitude of the device, thereby improving the withstand voltage amplitude and withstand voltage stability of the semiconductor device terminal structure without increasing the size and volume of the device.

[0017] In some embodiments, a third aspect of the present disclosure provides a method for preparing a semiconductor device terminal structure, comprising:

[0018] Providing a substrate of a first conductivity type including a cell region and a terminal region;

[0019] forming a doped region of the second conductivity type in the cell region, and forming at least one field limiting ring in the terminal region, which is sequentially distributed in a direction away from the doped region;

[0020] Based on a target mask, etching the substrate to form a plurality of trenches, the plurality of trenches including a first sub-trench located in a doped region, and a second sub-trench located between adjacent doped regions and field limiting rings, and between adjacent field limiting rings;

[0021] Based on a target mask, an ion implantation process is performed into the substrate through the plurality of trenches to obtain an ion implantation layer of a second conductivity type, wherein the ion implantation layer is at least located between adjacent doped regions and field limiting rings, and between adjacent field limiting rings;

[0022] forming an isolation layer covering the doped region, at least one field limiting ring, and the ion implantation layer, wherein a portion of the isolation layer located in the first sub-trench constitutes a first isolation structure, and a portion of the isolation layer located in the second sub-trench constitutes a second isolation structure;

[0023] A plurality of conductive field plates are formed on the isolation layer and are distributed at intervals. The plurality of conductive field plates include a first field plate electrically connected to the doped region and a second field plate electrically connected to the field limiting ring.

[0024] In the method for preparing the terminal structure of the semiconductor device in the above embodiment, after forming a second conductive type doping region in the cell region at the same time, and forming at least one field limiting ring distributed in a direction away from the doping region in sequence in the terminal region; based on the target mask, forming a first sub-groove located in the doping region, and a second sub-groove located between adjacent doping regions, field limiting rings, and between adjacent field limiting rings; again based on the target mask, performing an ion implantation process into the substrate through the multiple grooves to obtain a second conductive type ion implantation layer, the ion implantation layer being located at least between adjacent doping regions, field limiting rings, and between adjacent field limiting rings; the second conductive type ion implantation layer and the first conductive type thereunder are implanted. A PN junction is formed between the substrate and the substrate of the type; an isolation layer is then formed covering the doped regions, at least one field limiting ring, and the ion implantation layer; the portion of the isolation layer located within the first sub-trench constitutes a first isolation structure, and the portion located within the second sub-trench constitutes a second isolation structure; the first isolation structure between adjacent doped regions and field limiting rings, and the second isolation structure between adjacent field limiting rings are isolated from the substrate via the PN junction; and a plurality of conductive field plates are then formed spaced apart on the isolation layer, the plurality of conductive field plates including a first field plate electrically connected to the doped regions and a second field plate electrically connected to the field limiting rings. The field limiting rings can be electrically connected to the conductive field plates arranged one-to-one to form a biased field plate structure. In this embodiment, the first isolation structure between adjacent doped regions and field limiting rings, and the second isolation structure between adjacent field limiting rings, are isolated from the substrate via the PN junction, thereby optimizing the electric field distribution, weakening the electric field strength of the field limiting rings adjacent to the main junction, increasing the dielectric breakdown amplitude, increasing the depletion region within the substrate, and improving the overall withstand voltage amplitude of the device, thereby improving the withstand voltage amplitude and withstand voltage stability of the terminal structure of the semiconductor device without increasing the size and volume of the device. The photomask for forming the ion implantation layer is the same as the photomask for forming the plurality of trenches, thereby avoiding the need for adding an additional photomask due to the introduction of the second conductive type ion implantation layer, thereby reducing the complexity and cost of the manufacturing process.

[0025] In some embodiments, the terminal region is located at the periphery of the cellular region.

[0026] In some embodiments, an ion implantation dose of the ion implantation layer is less than an ion implantation dose of the doping region, so that a doping concentration of the ion implantation layer is less than a doping concentration of the doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0028] Figure 1 A schematic cross-sectional view of a terminal structure of a semiconductor device provided in one embodiment of the present disclosure;

[0029] Figure 2 A schematic flow chart of a method for preparing a semiconductor device terminal structure according to an embodiment of the present disclosure;

[0030] Figure 3 This is a schematic cross-sectional view of a semiconductor structure obtained after forming a first sub-trench and a second sub-trench in a method for preparing a semiconductor device terminal structure provided in one embodiment of the present disclosure;

[0031] Figure 4 A schematic cross-sectional view of a terminal structure of a semiconductor device provided in a comparative embodiment of the present disclosure;

[0032] Figure 5 Schematic diagram of curve comparison of the lateral electric field distribution near the interface between the isolation structure and the substrate in different semiconductor device terminal structures.

[0033] Description of reference numerals:

[0034] 11. Cell region; 12. Terminal region; 100. Doped region; 101. Field limiting ring; 102. Conductive plug; 13. First isolation structure; 103. Second isolation structure; 141. First sub-trench; 142. Second sub-trench; 104. Stop ring; 105. Horizontal portion; 106. Insulating layer; 107. Conductive field plate; 108. Substrate; 109. Ion implantation layer; 150. Trench isolation structure. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. The terms used herein in the specification of this disclosure are for the purpose of describing specific embodiments only and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0041] The multilayer structure disclosed in the present invention may be formed layer by layer or integrally; wherein two adjacent layers may be in contact or isolated from each other.

[0042] In power semiconductor devices, by forming a series of staggered pn junctions between the n-type and p-type doped layers, charge compensation can be generated, significantly increasing the doping concentration in the device's drift region. Furthermore, without changing the device's breakdown voltage, the device's on-resistance and leakage current can be reduced. In addition, superjunction (SJ) technology can also increase device switching speeds, reduce on-resistance, and lower switching losses. Therefore, the SJ structure is widely used in power devices such as metal-oxide semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and junction field-effect transistors (JFETs).

[0043] In semiconductor devices, cells form cylindrical or planar junctions at their edges, resulting in insufficient curvature and concentrated electric fields, making them susceptible to electrical breakdown. Field-limiting rings can be added to the terminals to mitigate this field concentration. Furthermore, the electric field distribution capability of the terminal region can improve the overall withstand voltage of the semiconductor device.

[0044] Please refer to Figure 1In some embodiments, a semiconductor device terminal structure is provided, including: a first conductive type substrate 108, a second conductive type doped region 100, at least one field limiting ring 101, a second conductive type ion implantation layer 109, an isolation layer (not shown), and a plurality of conductive field plates 107; the first conductive type substrate 108 includes a cell region 11 and a terminal region 12; the second conductive type doped region 100 is located in the cell region 11.

[0045] Please refer to Figure 1 In some embodiments, multiple field limiting rings 101 are sequentially distributed in the terminal region 12 along a direction away from the doped region 100 (e.g., the ox direction); a second conductivity type ion implantation layer 109 is located at least between adjacent doped regions 100 and field limiting rings 101, and between adjacent field limiting rings 101; an isolation layer (not shown) covers the doped region 100, the multiple field limiting rings 101, and the ion implantation layer 109; wherein the isolation layer includes a first isolation structure 13 embedded in the doped region 100, and a plurality of second isolation structures 103 located directly above the ion implantation layer 109; the plurality of second isolation structures 103 can be arranged corresponding to the plurality of field limiting rings 101, for example, in a one-to-one arrangement; a plurality of conductive field plates 107 are spaced apart and distributed on the isolation layer, including a first field plate (not shown) electrically connected to the doped region 100, and a second field plate (not shown) electrically connected to the field limiting rings 101.

[0046] For example, please continue to refer to Figure 1 The second conductivity type doped region 100 forms a main junction with the first conductivity type substrate 108 within the cell region 11. At least one field limiting ring 101 and the main junction can be fabricated simultaneously in the same process step. The field limiting ring 101 can be electrically connected to a one-to-one conductive field plate 107 to form a biased field plate structure. A PN junction is formed between the second conductivity type ion implanted layer 109 and the underlying first conductivity type substrate 108. This allows the first isolation structure 13 between adjacent doped regions 100 and field limiting rings 101, as well as the second isolation structure 103 between adjacent field limiting rings 101, to be isolated from the substrate 108 via the PN junction. This optimizes the electric field distribution, weakens the electric field strength of the field limiting ring 101 adjacent to the main junction, and improves the dielectric breakdown amplitude. Furthermore, the depletion region within the substrate 108 is increased, thereby improving the overall withstand voltage amplitude of the device. This improves the withstand voltage amplitude and voltage stability of the semiconductor device terminal structure without increasing the device size and volume.

[0047] Please continue to refer to Figure 1In some embodiments, the terminal region 12 is located outside the cell region 11. A PN junction is formed between the second conductivity type ion implantation layer 109 in the terminal region 12 and the first conductivity type substrate 108 thereunder. This allows the first isolation structure 13 between adjacent doped regions 100 and field limiting rings 101, as well as the second isolation structure 103 between adjacent field limiting rings 101, to be isolated from the substrate 108 via the PN junction. This optimizes the electric field distribution, weakens the electric field strength of the field limiting rings 101 adjacent to the main junction, increases the dielectric breakdown amplitude, increases the depletion region within the substrate 108, and improves the overall withstand voltage amplitude of the device.

[0048] Please continue to refer to Figure 1 In some embodiments, the doping concentration of the ion implantation layer 109 is lower than the doping concentration of the doping region 100 . The ion implantation layer between adjacent doping regions 100 , field limiting rings 101 , and adjacent field limiting rings 101 is used to increase the depletion region inside the substrate 108 , optimize the electric field distribution, and weaken the electric field strength of the field limiting ring 101 adjacent to the main junction.

[0049] Please continue to refer to Figure 1 In some embodiments, the process steps of the isolation layer are performed before the process steps of the ion implantation layer 109, so that the ion implantation process can be performed directly using the grooves of the isolation layer to form the ion implantation layer 109, thereby avoiding the addition of additional masks due to the introduction of the second conductive type ion implantation layer 109, thereby reducing the complexity and cost of the preparation process.

[0050] Please continue to refer to Figure 1 In some embodiments, the semiconductor device terminal structure further includes multiple conductive plugs 102 penetrating the isolation layer. The multiple conductive plugs 102 include a first sub-plug (not shown) and a second sub-plug (not shown). The first sub-plug is located between the first field plate and the doped region 100; the second sub-plug is located between the second field plate and the field limiting ring 101. The first field plate is electrically connected to the doped region 100 via the first sub-plug. The first field plate can be grounded via the emitter. The second field plate is electrically connected to the field limiting ring 101 via the second sub-plug.

[0051] In some embodiments, the conductive field plate may be made of conductive polysilicon or conductive metal.

[0052] Please continue to refer to Figure 1In some embodiments, the field limiting ring 101 can alleviate the electric field concentration at the edge of the device, thereby preventing premature breakdown. In power devices, the electric field at the edge of the main junction becomes very high due to the curvature effect, which can easily lead to breakdown. The field limiting ring 101 gradually reduces the intensity of the electric field by arranging multiple annular diffusion regions around the main junction, making the electric field distribution more uniform and improving the overall breakdown voltage. The conductive field plate 107 can adjust the surface electric field distribution to avoid the electric field from concentrating on the surface. The conductive field plate 107 can optimize the electric field by changing the surface potential distribution to prevent surface breakdown. The use of the field limiting ring 101 in conjunction with the conductive field plate 107 can further enhance the device's ability to withstand voltage and resist the influence of charge.

[0053] Please continue to refer to Figure 1 In some embodiments, a plurality of conductive plugs 102 are fabricated in the same process step at the same time to reduce the complexity and cost of the fabrication process.

[0054] Please continue to refer to Figure 1 In some embodiments, the semiconductor device terminal structure further includes a cutoff ring 104 of the first conductivity type, which is located in the terminal region 12 on the side of the multiple field limiting rings 101 away from the doped region 100. By providing the cutoff ring 104 at the outermost side of the terminal structure as a protective layer, it is ensured that the electric field is effectively cut off before reaching the physical edge of the device. The cutoff ring 104 reduces or uniformizes the electric field strength at the terminal end, thereby avoiding electric field concentration caused by edge curvature effects, thereby preventing premature breakdown. The cutoff ring 104 can also limit the lateral expansion of the electric field, preventing the electric field from extending to inactive areas of the device (such as packaging or cutting edges), ensuring that the electric field distribution is strictly controlled within the design range.

[0055] In some embodiments, at least one field limiting ring 101 and the doped region 100 are fabricated simultaneously in the same process step, which can reduce the number of masks used and reduce the complexity of the fabrication process.

[0056] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0057] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0058] Please continue to refer to Figure 1In some embodiments, a semiconductor device is provided, including the semiconductor device terminal structure described in any of the aforementioned embodiments. A PN junction is formed between the second conductivity type ion implantation layer and the first conductivity type substrate 108 thereunder. This allows the first isolation structure 13 between adjacent doped regions 100 and field limiting rings 101, and the second isolation structure 103 between adjacent field limiting rings 101, to be isolated from the substrate 108 via the PN junction. This optimizes the electric field distribution, weakens the electric field strength of the field limiting rings 101 adjacent to the main junction, increases the dielectric breakdown amplitude, increases the depletion region within the substrate 108, and improves the overall withstand voltage amplitude of the device. This improves the withstand voltage amplitude and withstand voltage stability of the semiconductor device terminal structure without increasing the size and volume of the device.

[0059] Please refer to Figure 2 In some embodiments, a method for preparing a terminal structure of a semiconductor device is provided, comprising:

[0060] Step S12: providing a substrate of the first conductivity type including a cell region and a terminal region;

[0061] Step S14: forming a doped region of the second conductivity type in the cell region, and forming at least one field limiting ring in the terminal region, which is sequentially distributed in a direction away from the doped region;

[0062] Step S16: etching the substrate based on the target mask to form a plurality of trenches, wherein the plurality of trenches include a first sub-trench located in the doped region, and a second sub-trench located between adjacent doped regions and field limiting rings, and between adjacent field limiting rings;

[0063] Step S18: Based on the target mask, perform an ion implantation process into the substrate through the plurality of trenches to obtain an ion implantation layer of the second conductivity type, wherein the ion implantation layer is at least located between adjacent doped regions and field limiting rings, and between adjacent field limiting rings;

[0064] Step S110: forming an isolation layer covering the doped region, at least one field limiting ring, and the ion implantation layer, wherein the portion of the isolation layer located in the first sub-trench constitutes a first isolation structure, and the portion located in the second sub-trench constitutes a second isolation structure;

[0065] Step S112 : forming a plurality of conductive field plates spaced apart from each other on the isolation layer, the plurality of conductive field plates including a first field plate electrically connected to the doped region and a second field plate electrically connected to the field limiting ring.

[0066] Please continue to refer to Figure 1 、 Figure 2In some embodiments, a doped region 100 of the second conductivity type may be formed in the cell region 11 at the same time, and a plurality of field limiting rings 101 sequentially distributed in a direction away from the doped region 100 may be formed in the terminal region 12. Subsequently, based on a target mask, a first sub-trench is formed in the doped region 100, and a second sub-trench is formed between adjacent doped regions 100, field limiting rings 101, and between adjacent field limiting rings 101. Based on the target mask again, an ion implantation process is performed into the substrate 108 through the plurality of trenches to obtain an ion implantation layer 109 of the second conductivity type. The ion implantation layer 109 is at least located between adjacent doped regions 100, field limiting rings 101, and between adjacent field limiting rings 101. A first sub-trench is formed between the ion implantation layer 109 of the second conductivity type and the substrate 108 of the first conductivity type thereunder. A PN junction is formed; an isolation layer is then formed covering the doped region 100, the ion implantation layer 109, and the plurality of field limiting rings 101; in the isolation layer, the portion located in the first sub-trench constitutes a first isolation structure 13, and the portion located in the second sub-trench constitutes a second isolation structure 103; so that the first isolation structures 13 between adjacent doped regions 100 and field limiting rings 101, and the second isolation structures 103 between adjacent field limiting rings 101 are respectively isolated from the substrate 108 via the PN junction; then, a plurality of conductive field plates 107 are formed on the isolation layer at intervals, the plurality of conductive field plates 107 including a first field plate electrically connected to the doped region 100, and a second field plate electrically connected to the field limiting rings 101, wherein the field limiting rings 101 can be electrically connected to the conductive field plates 107 arranged one-to-one to form a biased field plate structure. In this embodiment, the first isolation structure 13 between adjacent doped regions 100 and field-limiting rings 101, as well as the second isolation structure 103 between adjacent field-limiting rings 101, are each isolated from the substrate 108 via a PN junction. This optimizes the electric field distribution, weakens the electric field strength of the field-limiting rings 101 adjacent to the main junction, increases the dielectric breakdown amplitude, increases the depletion region within the substrate 108, and improves the overall device withstand voltage amplitude. This improves the withstand voltage amplitude and withstand voltage stability of the semiconductor device terminal structure without increasing the device size and volume. The mask used to form the ion implantation layer 109 is the same as the mask used to form the multiple trenches, avoiding the need for additional masks due to the introduction of the second conductivity type ion implantation layer, thereby reducing the complexity and cost of the manufacturing process.

[0067] Please refer to Figure 2 、 Figure 3In some embodiments, the substrate 108 of the first conductivity type in step S12 may be made of a semiconductor material, a conductor material, or any combination thereof. The substrate 108 may be a single-layer structure or a multi-layer structure. For example, the substrate 108 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 108 may be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. The type of substrate 108 should not limit the scope of protection of the present disclosure.

[0068] Please refer to Figure 2 、 Figure 3 In some embodiments, in step S14, a second conductive type doping region 100 can be formed in the cell region 11 at the same time in the same process step, and a plurality of field limiting rings 101 distributed sequentially in a direction away from the doping region 100 can be formed in the terminal region 12.

[0069] Please continue to refer to Figure 2 、 Figure 3 In some embodiments, in step S14, a field-limiting ring mask is provided, including a first opening for defining the doped region 100 and a second opening for defining the field-limiting ring 101. Based on the field-limiting ring mask, an ion implantation process is then performed on the substrate 108 to form a doped region 100 of the second conductivity type in the cell region 11 and a plurality of field-limiting rings 101 sequentially distributed in a direction away from the doped region 100 in the terminal region 12. This avoids the need for additional masks required to separately fabricate multiple field-limiting rings 101, thereby reducing the complexity and cost of the fabrication process.

[0070] Please continue to refer to Figure 2 、 Figure 3 In some embodiments, in step S16, a target mask is set to include a first pattern for defining a first sub-groove 141 and a second pattern for defining a second sub-groove 142. Based on the target mask, the substrate 108 is etched to form a plurality of grooves, the plurality of grooves including a first sub-groove 141 located in the doping region 100, and a second sub-groove 142 located between adjacent doping regions 100 and field limiting rings 101, and between adjacent field limiting rings 101.

[0071] Please continue to refer to Figure 1 、 Figure 2 、 Figure 3In some embodiments, in step S18, based on a target photomask, an ion implantation process is performed into the substrate 108 through the plurality of trenches to form an ion implantation layer 109 of the second conductivity type. The ion implantation layer 109 is located at least between adjacent doped regions 100 and field limiting rings 101, and between adjacent field limiting rings 101. The ion implantation dose of the ion implantation layer 109 is less than the ion implantation dose of the doped region 100, so that the doping concentration of the ion implantation layer 109 is less than the doping concentration of the doped region 100. Since the target photomask from step S16 is reused in step S18, the number of masks used is avoided due to the introduction of the ion implantation layer 109.

[0072] Please continue to refer to Figure 3 In some embodiments, the second conductivity type is P type and the first conductivity type is N type. In step S18, based on the target mask, P type ions are injected into the substrate 108 through multiple trenches to form an ion implantation layer 109 of the second conductivity type.

[0073] For example, P-type ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, indium (In) ions, etc. N-type impurity ions may include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0074] Please continue to refer to Figure 1-Figure 3 In some embodiments, in step S110, a deposition process may be used to form an isolation layer covering the doped region 100, the plurality of field-limiting rings 101, and the ion implantation layer 109. In the isolation layer, the portion located within the first sub-trench 141 constitutes the first isolation structure 13, the portion located within the second sub-trench 142 constitutes the second isolation structure 103, and the portion located on the top surface of the doped region 100 or the top surface of the field-limiting ring 101 constitutes the horizontal portion 105. The deposition process may include, but is not limited to, one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0075] Please continue to refer to Figure 1-Figure 3In some embodiments, a plurality of conductive plugs 102 may be formed through the horizontal portion 105. The plurality of conductive plugs 102 include a first sub-plug (not shown) and a second sub-plug (not shown). The first sub-plug is located between the first field plate and the doped region 100, and the second sub-plug is located between the second field plate and the field limiting ring 101. In step S112, a plurality of conductive field plates 107 are formed on the isolation layer at intervals. The plurality of conductive field plates 107 include a first field plate electrically connected to the doped region 100 and a second field plate electrically connected to the field limiting ring 101. The first field plate is electrically connected to the doped region 100 via the first sub-plug, and the second field plate is electrically connected to the field limiting ring 101 via the second sub-plug.

[0076] Please continue to refer to Figure 1-Figure 3 In some embodiments, the multiple field-limiting rings 101 include field-limiting ring R1, field-limiting ring R2, and field-limiting ring Rn, distributed sequentially along a direction away from the doped region 100 (e.g., the ox direction), where n is a positive integer. The number of field-limiting rings is not fixed but depends on factors such as the device voltage level, material properties (such as doping concentration and dielectric constant), and structural design. Typically, high-voltage devices may require more field-limiting rings to gradually reduce the electric field. For example, in silicon-based devices, the typical number of field-limiting rings may be between 3 and 10, but the specific number needs to be optimized based on simulation and experimental results.

[0077] Please refer to Figure 4 In some embodiments, the trench isolation structure 150 is located between adjacent doped regions 100 and field limiting rings 101, and between adjacent field limiting rings 101. The bottom surface of the trench isolation structure 150 is in direct contact with the substrate 108. Figure 1 In the terminal structure shown, an ion implantation layer 109 of the second conductivity type is included between the isolation layer and the substrate 108 . Figure 1 A PN junction is formed between the second conductive type ion implantation layer 109 and the first conductive type substrate 108 thereunder, so that the first isolation structure 13 between adjacent doped regions 100 and field limiting rings 101, and the second isolation structure 103 between adjacent field limiting rings 101, are respectively isolated from the substrate 108 via the PN junction, thereby optimizing the electric field distribution, weakening the electric field strength of the field limiting rings 101 adjacent to the main junction, and improving the dielectric breakdown amplitude; increasing the depletion region inside the substrate 108, and improving the overall withstand voltage amplitude of the device. Figure 4 In the embodiment, the bottom surfaces of the trench isolation structures 150 between adjacent doped regions 100 and field limiting rings 101, as well as between adjacent field limiting rings 101, are in direct contact with the substrate 108. The doped regions 100 and field limiting rings 101 form cylindrical junctions or planar junctions at their edges, resulting in insufficient curvature, concentrated electric fields, and prone to electrical breakdown.

[0078] Please refer to Figure 5 In some embodiments, the measurement Figure 4The schematic diagram of the lateral electric field distribution near the junction of the trench isolation structure 150 and the substrate 108 is shown in FIG. Figure 5 As shown by the continuous solid line, the measurement Figure 1 The schematic diagram of the lateral electric field distribution near the junction of the isolation layer and the substrate 108 is as follows: Figure 5 By comparison Figure 5 From the dashed line and the continuous solid line, it is clear that the amplitude of the first electric field peak of the dashed line is smaller than that of the first electric field peak of the continuous solid line. This is because the amplitude of the first electric field peak can be used to represent the withstand voltage amplitude of the strongest electric field region in the device. Figure 5 The middle vertical axis uses scientific notation. For example, 1.0e+5 means 1.0 times 10 to the power of 5; 2.0e+5 means 2.0 times 10 to the power of 5; 2.5e+5 means 2.5 times 10 to the power of 5.

[0079] In some embodiments, Figure 1 The semiconductor device terminal structure shown in the example is compared with Figure 4 The semiconductor device terminal structure in the example increases the device's withstand voltage from 1192V to 1363V, an increase of 14.3%, and reduces the amplitude of the first electric field peak at the interface by 18.2%. In addition, Figure 1 The semiconductor device terminal structure exemplified in Figure 4 The terminal structure of the semiconductor device shown in the example significantly reduces the amplitude of the electric field peaks of the first few field limiting rings close to the main junction, and increases the amplitude of the electric field peaks of the field limiting rings far away from the main junction, making the electric field distribution more uniform.

[0080] The electric field concentration at the corners of the terminal layout is much greater than that of a cylindrical junction that is not located at a corner. Furthermore, the field-limiting ring near the main junction of the cell has a smaller radius of curvature, making the electric field concentration even more pronounced. Therefore, semiconductor devices are most likely to break down at the corners of the field-limiting ring near the main junction, leading to device failure. Figure 1 The exemplary semiconductor device terminal structure isolates the first isolation structure 13 between adjacent doped regions 100 and field-limiting rings 101, and the second isolation structure 103 between adjacent field-limiting rings 101, from the substrate 108 via PN junctions. This optimizes the electric field distribution, weakens the electric field strength of the field-limiting rings 101 adjacent to the main junction, and improves the dielectric breakdown amplitude. It also increases the depletion region within the substrate 108, improving the overall device withstand voltage amplitude. This improves the withstand voltage amplitude and voltage stability of the semiconductor device terminal structure without increasing the device size and volume.

[0081] In addition, the semiconductor device terminal structure provided in the embodiments of the present application is applicable to superjunction devices, such as superjunction insulated gate bipolar transistors and superjunction metal oxide semiconductors. The semiconductor device structure can be made of Si or other semiconductor materials such as SiC.

[0082] Regarding the specific limitations of the method for preparing the semiconductor device terminal structure in the above embodiment, reference may be made to the above limitations on the semiconductor device terminal structure, which will not be repeated here.

[0083] Unless otherwise specified herein, the execution order of the steps in the method for preparing a semiconductor device terminal structure in the above-described embodiments is not strictly limited, and the steps may be performed in other orders. Furthermore, at least a portion of the steps in the method may include multiple steps or multiple stages, and these steps or stages do not necessarily need to be completed at the same time, but may be performed at different times. The order in which these steps or stages are performed does not necessarily need to be sequential, but may be performed in rotation or alternation with other steps or at least a portion of steps or stages in other steps.

[0084] The method for preparing the semiconductor device terminal structure in the above embodiment is intended to schematically illustrate the formation principle of the semiconductor device terminal structure in the embodiment of the present application, and is not intended to be a specific limitation on the semiconductor device terminal structure in the embodiment of the present application. Other preparation methods can also be used to prepare the semiconductor device terminal structure in the embodiment of the present application.

[0085] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0086] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0087] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A semiconductor device terminal structure, characterized in that: include: A substrate of a first conductive type, comprising a cell region and a terminal region; A doping region of a second conductivity type, located in the cell region; At least one field limiting ring is sequentially distributed in the terminal region in a direction away from the doped region; An ion implantation layer of the second conductivity type is located at least between adjacent doping regions and field limiting rings, and between adjacent field limiting rings; an isolation layer covering the doped region, the at least one field limiting ring, and the ion implantation layer; wherein the isolation layer includes a first isolation structure embedded in the doped region and a plurality of second isolation structures located directly above the ion implantation layer; A plurality of conductive field plates are distributed on the isolation layer at intervals, including a first field plate electrically connected to the doped region and a second field plate electrically connected to the field limiting ring.

2. The semiconductor device terminal structure according to claim 1, wherein: The terminal region is located at the periphery of the cellular region; or The doping concentration of the ion implantation layer is lower than the doping concentration of the doping region.

3. The semiconductor device terminal structure according to claim 1, wherein: The process steps of the isolation layer are prior to the process steps of the ion implantation layer.

4. The semiconductor device terminal structure according to claim 1, wherein: Also includes: A plurality of conductive plugs passing through the isolation layer, including: a first sub-plug, located between the first field plate and the doped region; The second sub-plug is located between the second field plate and the field limiting ring.

5. The semiconductor device terminal structure according to claim 4, wherein: The plurality of conductive plugs are manufactured simultaneously in the same process step.

6. The semiconductor device terminal structure according to claim 1, wherein: Also includes: A cutoff ring of the first conductivity type is located in a terminal region of the at least one field limiting ring on a side away from the doped region.

7. The semiconductor device terminal structure according to claim 1, wherein: The at least one field limiting ring and the doped region are prepared simultaneously in the same process step.

8. The semiconductor device terminal structure according to any one of claims 1 to 7, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or The first conductivity type is P type, and the second conductivity type is N type.

9. A semiconductor device, characterized in that: include: The semiconductor device terminal structure according to any one of claims 1 to 8.

10. A method for preparing a semiconductor device terminal structure, characterized in that: include: Providing a substrate of a first conductivity type including a cell region and a terminal region; forming a doped region of the second conductivity type in the cell region, and forming at least one field limiting ring in the terminal region, which is sequentially distributed in a direction away from the doped region; Based on a target mask, etching the substrate to form a plurality of trenches, wherein the plurality of trenches include a first sub-trench located in the doped region, and a second sub-trench located between adjacent doped regions and the field limiting rings, and between adjacent field limiting rings; Based on the target mask, performing an ion implantation process into the substrate through the plurality of trenches to obtain an ion implantation layer of a second conductivity type, wherein the ion implantation layer is at least located between adjacent doped regions and the field limiting rings, and between adjacent field limiting rings; forming an isolation layer covering the doped region, the at least one field limiting ring, and the ion implantation layer, wherein a portion of the isolation layer located in the first sub-trench constitutes a first isolation structure, and a portion of the isolation layer located in the second sub-trench constitutes a second isolation structure; A plurality of conductive field plates are formed on the isolation layer and are spaced apart from each other. The plurality of conductive field plates include a first field plate electrically connected to the doped region and a second field plate electrically connected to the field limiting ring.

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