Gate cut-out defined within gate trench

Abstract

Techniques are provided herein for forming a semiconductor device that includes one or more gate cuts that are self-aligned within a gate trench between adjacent devices. The semiconductor device includes a gate structure surrounding or on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted by a gate cut extending through an entire thickness of the gate structure and comprising a dielectric material to electrically isolate portions of the gate structure on either side of the gate cut. In an example, a gate cut-out is defined within a gate trench such that it does not extend beyond a wall of the gate trench defined by a gate spacer structure. In addition, the gate dielectric is not formed on any surface of the gate cut-out such that the gate cut-out directly contacts the gate electrode.

Description

Background Art

[0001] As the size of integrated circuits continues to shrink, many challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult, as does reducing the pitch between devices at the device layer. As transistors become more densely packed, the formation of certain device structures that isolate adjacent transistors becomes challenging. Consequently, many significant challenges remain in the formation of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A and Figure 1B sectional views and plan views, respectively, of some semiconductor devices having gate cuts defined within gate trenches between the devices according to embodiments of the present disclosure.

[0003] Figure 2A and Figure 2B are cross-sectional and plan views illustrating a first stage in an example process for forming semiconductor devices having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0004] Figure 3A and Figure 3B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0005] Figure 4A and Figure 4B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0006] Figure 5A and Figure 5B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0007] Figure 6A and Figure 6B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0008] Figure 7A and Figure 7Bare cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0009] Figure 8A and Figure 8B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0010] Figure 9A and Figure 9B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0011] Figure 10A and Figure 10B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0012] Figure 11A and Figure 11B are cross-sectional and plan views illustrating another stage in an example process for forming a semiconductor device having gate cuts defined within gate trenches between devices according to some embodiments of the present disclosure.

[0013] Figure 12 A cross-sectional view of a chip package containing one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0014] Figure 13 is a flow chart of a process for fabricating semiconductor devices having gate cuts defined within gate trenches between devices according to an embodiment of the present disclosure.

[0015] Figure 14 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0016] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the particular configurations shown. For example, although some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies or otherwise be non-smooth, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0017] Provided herein are techniques for forming a semiconductor device comprising one or more gate cuts self-aligned within a gate trench between adjacent devices. These techniques can be used in any number of integrated circuit applications and are particularly useful for device layer transistors such as finFETs or full-gate-all-around transistors (e.g., ribbon FETs and nanowire FETs) or forksheet transistors (e.g., nanosheet FETs). In an example, a semiconductor device includes a gate structure surrounding a semiconductor region (also referred to as a channel region) or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material extending from a source region to a drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material extending from a source region to a drain region. The gate structure includes a gate dielectric (e.g., a high-k gate dielectric material) and a gate electrode (e.g., a conductive material such as a work function material and / or a gate fill metal). The gate structure can be interrupted, for example, between two transistors having a gate cut that extends through the entire thickness of the gate structure and includes a dielectric material to electrically isolate portions of the gate structure on either side of the gate cut. In some examples, the gate cut is defined within the gate trench such that the gate cut does not extend beyond the walls of the gate trench defined by the gate spacer structure. In some examples, the gate cut includes a high-k dielectric liner along the outer edge of the gate cut and a relatively low-k dielectric filler. The gate cut is also formed after the gate structure is formed such that the gate dielectric is not formed on any surface of the gate cut. Many variations and embodiments will be apparent in light of this disclosure.

[0018] General Overview

[0019] As mentioned above, there are still many important challenges with respect to integrated circuit manufacturing. In more detail, as devices become smaller and more densely packed, manufacturing many structures becomes more challenging because the critical dimensions (CD) of the structures push the limits of current manufacturing technology. Example structures such as gate cuts are used in integrated circuit design to isolate gate structures from each other. Such gate cuts can be formed in various ways, but there are disadvantages to the existing techniques for forming gate cuts. For example, gate cuts formed before manufacturing the gate structure suffer from uneven heights across multiple devices on the substrate, and gate cuts formed by etching trenches through multiple different materials may have an adverse effect on the formation of other conductive features (such as source or drain contacts), which may result in low yield.

[0020] Therefore, and in accordance with embodiments of the present disclosure, techniques are provided herein for forming a gate cut that passes through a metal gate structure and is defined within a gate trench. The configuration of the gate cut can vary from one example to the next. In some embodiments, the gate cut includes a dielectric liner along the edge of the gate cut, the dielectric liner comprising a high-k material (e.g., a material having a dielectric constant greater than the dielectric constant of silicon dioxide, 3.9, such as a dielectric having a dielectric constant greater than or equal to 6.5). The dielectric liner can comprise, for example, a conformal deposition of silicon nitride. Because the dielectric liner is along the edge of the gate cut, the dielectric liner can contact the gate electrode on either side of the gate cut. The gate cut also includes a dielectric filler on the dielectric liner and within the inner portion of the gate cut. According to some embodiments, the dielectric filler comprises a medium-low k material (e.g., a material having a dielectric constant less than or equal to 4.5). To provide a few examples, silicon dioxide, flowable silicon dioxide, or porous silicon dioxide can be used for the dielectric filler. Other gate cut examples include dielectric fillers of such dielectric materials without a liner. In any such case, the gate cut is limited by the gate trench.

[0021] According to some embodiments, an anisotropic metal etching process can be used to etch grooves through the gate electrodes between devices without significantly etching any dielectric material. The resulting groove is limited to the gate trench (e.g., where the metal gate electrode is located). In some embodiments, a suitable isotropic etching process can be used to remove any portion of the gate dielectric remaining in the groove. For example, the gate dielectric extending along the bottom of the groove is removed, which effectively causes the first end and the second end of the gate dielectric to abut the groove. One or more dielectric materials can then be deposited in the groove to form a gate cut that separates adjacent gate structures.

[0022] According to an embodiment, an integrated circuit includes: a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction above the semiconductor region; a spacer structure extending along the second direction on a sidewall of the gate structure and together with the gate structure; and a gate cut adjacent to the semiconductor device and extending through the entire height of the gate structure along a third direction. The gate structure includes a gate dielectric and a gate electrode located on the gate dielectric. The gate cut extends between the spacer structures in the first direction and does not extend beyond the spacer structures. In this manner, an end of the gate cut can effectively abut the spacer structure. The gate dielectric does not extend along the sidewalls of the gate cut that extend in the first direction, although an end of the gate dielectric can also abut the sidewalls of the gate cut.

[0023] According to an embodiment, an integrated circuit includes: a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction above the semiconductor region; a spacer structure extending along a second direction along a sidewall of the gate structure and together with the gate structure; and a gate cut adjacent to the semiconductor device and extending through the entire height of the gate structure along a third direction. The gate structure includes a gate dielectric and a gate electrode located on the gate dielectric. The gate cut includes a first sidewall extending along the first direction and directly contacting the gate electrode, and the gate cut includes a second sidewall extending along the second direction and directly contacting one of the spacer structures.

[0024] According to another embodiment, a method of forming an integrated circuit includes: forming one or more fins comprising a semiconductor material, the one or more fins extending above a substrate, and each fin extending parallel to each other in a first direction; forming a sacrificial gate extending above the semiconductor material in a second direction different from the first direction; forming a spacer structure on the sidewalls of the sacrificial gate; removing the sacrificial gate; forming a gate structure above the semiconductor material in the second direction and between the spacer structures; forming a groove extending across the gate electrode in the first direction and extending through the entire height of the gate electrode in a third direction, wherein the groove is between the spacer structures along a boundary in the first direction; and forming one or more dielectric materials within the groove.

[0025] These techniques can be used with any type of non-planar transistor, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or fork-flap transistors, to name a few examples. The source and drain regions can be epitaxial regions deposited, for example, during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-last process (sometimes called a replacement metal gate or RMG process). Any number of semiconductor materials can be used to form the transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium), or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0026] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy (including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM)); composite mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable example analytical tools. For example, in some example embodiments, such tools can be used to detect the presence of a gate cut between devices that does not extend outside the gate trench (e.g., remains confined within the spacer structure). In some examples, such tools can also be used to show that the gate dielectric surrounding the semiconductor region can abut the gate cut but does not extend up to the sidewalls of the gate cut. Many configurations and variations will be apparent in light of this disclosure.

[0027] It should be readily understood that the meaning of "above" and "over" in this disclosure should be interpreted in the broadest sense, such that "above" and "over" not only mean "directly on something," but also include the meaning of having intermediate features or layers therebetween on something. In addition, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," "top," "bottom," etc., may be used herein to describe the relationship of one element or feature to another (one or more) elements or features as shown. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can likewise be interpreted accordingly.

[0028] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved), having a relatively uniform thickness across the entire layer.

[0029] As used herein, "compositionally different" or "compositionally distinct" materials refer to two materials having different chemical compositions. This compositional difference can be achieved, for example, by virtue of an element being present in one material but not in the other (e.g., SiGe is compositionally different from silicon), or by virtue of one material having all of the same elements as the second material, but at least one of these elements being intentionally provided in a different concentration in one material relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, the materials can also have different dopants (e.g., gallium and magnesium), or the same dopants but in different concentrations. In other embodiments, compositionally different materials can further refer to two materials having different crystal orientations. For example, (110) silicon is compositionally different or distinct from (100) silicon. Creating stacks of different orientations can be achieved, for example, using blanket wafer layer transfer. If two materials are elementally different, then one material has an element that is not present in the other material.

[0030] Architecture

[0031] Figure 1A is a cross-sectional view taken across two example semiconductor devices 101 and 103 according to an embodiment of the present disclosure. Figure 1B It is cross Figure 1A The top cross-sectional view of adjacent semiconductor devices 101 and 103 is taken along the dashed line 1B-1B, and Figure 1A Shows a cross Figure 1B It should be noted that given the location of the cross section shown, some material layers (such as gate cap 119) are located in the cross section. Figure 1BEach of semiconductor devices 101 and 103 can be a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or a gate-all-around (GAA) transistor, but other transistor topologies and types can also benefit from the gate notch techniques and structures provided herein. The example embodiments shown herein use a GAA structure. Semiconductor devices 101 and 103 represent a portion of an integrated circuit that can include any number of similar semiconductor devices.

[0032] As can be seen, semiconductor devices 101 and 103 are formed on substrate 102. Any number of semiconductor devices can be formed on substrate 102, but two are used here as an example. Substrate 102 can be, for example, a bulk substrate including a Group IV semiconductor material (such as silicon, germanium, or silicon germanium), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having a desired semiconductor layer above a buried insulator layer (e.g., silicon on silicon dioxide). Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some example embodiments, a lower portion (or all) of substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing.

[0033] Each of the semiconductor devices 101 and 103 includes a plurality of electrodes extending in a direction between the source region and the drain region (eg, into and out of the source region and the drain region). Figure 1AOne or more nanoribbons 104 extending parallel to each other (in the first direction of the page in the cross-sectional view of FIG). Nanoribbon 104 is an example of a semiconductor region or semiconductor body extending between a source region and a drain region. The term nanoribbon may also encompass other similar shapes, such as nanowires or nanosheets. The semiconductor material of nanoribbon 104 may be formed from substrate 102. In some embodiments, semiconductor devices 101 and 103 may each include a fin-shaped semiconductor region, which may be, for example, native to substrate 102 (formed from the substrate itself), such as a silicon fin etched from a bulk silicon substrate. Alternatively, the fin may be formed from a material deposited on an underlying substrate. In one such example, a blanket layer of silicon germanium (SiGe) may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio capture-based process, in which the native fin is etched away to leave a fin-shaped trench, which may then be filled with an alternative semiconductor material (e.g., a Group IV or Group III-V material). In other embodiments, the fin includes alternating material layers (e.g., alternating layers of silicon and SiGe) that facilitate formation of the illustrated nanoribbon 104 during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer in the channel region, which then enables a gate-all-around (GAA) process to be performed. Likewise, according to some examples, the alternating layers can be blanket deposited and then etched into the fin or deposited into a fin-shaped trench.

[0034] As can be further seen, adjacent semiconductor devices are separated by a dielectric filler 106, which may include silicon dioxide. The dielectric filler 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices, as well as adjacent sub-fin regions 108. The dielectric filler 106 may be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxycarbon nitride.

[0035] In this example, semiconductor devices 101 and 103 each include a sub-fin region 108. According to some embodiments, sub-fin region 108 includes the same semiconductor material as substrate 102 and is adjacent to dielectric fill 106. According to some embodiments, nanoribbon 104 (or other semiconductor body) extends in a first direction between a source region and a drain region to provide an active region for the transistor (e.g., a semiconductor region under a gate). The source region and the drain region are located at Figure 1A Not shown in the cross section, but Figure 1BIt can be seen in the top view of the device 100 that the nanoribbon 104 of the semiconductor device 101 extends between the first source or drain region 110a and the second source or drain region 110b (similarly, the nanoribbon 104 of the semiconductor device 103 extends between the first source or drain region 112a and the second source or drain region 112b). Figure 1B Also shown are gate spacer structures 114 that extend around the ends of the nanoribbons 104 and along the sidewalls of the gate structure between the gate spacer structures 114. The spacer structures 114 may comprise a dielectric material, such as silicon nitride, and may be deposited in a conformal manner or other suitable deposition process and etched to a desired thickness (e.g., 2 nm to 10 nm).

[0036] According to some embodiments, the source region and the drain region are epitaxial regions provided using an etching and replacement process. In other embodiments, one or both of the source region and the drain region can be native portions of, for example, a semiconductor fin or substrate that is implanted and doped. Any semiconductor material suitable for the source and drain regions (e.g., Group IV and Group III-V semiconductor materials) can be used. The source and drain regions can include multiple layers such as a liner and a capping layer to improve contact resistance. In any such case, the composition and doping of the source and drain regions can be the same or different, depending on the polarity of the transistor. In an example, for example, one transistor is a p-type MOS (PMOS) transistor and the other transistor is an n-type MOS (NMOS) transistor. Phosphorus-doped silicon can be used for n-type source or drain regions, while boron-doped silicon germanium can be used for p-type source or drain regions. Any number of source and drain configurations and materials can be used.

[0037] In some embodiments, a first gate structure extends over the nanoribbon 104 of semiconductor device 101 along a second direction across the page, while a second gate structure extends over the nanoribbon 104 of semiconductor device 103 along a second direction. The second direction may be orthogonal to the first direction. Each gate structure includes a corresponding gate dielectric 116a / 116b and a gate electrode 118a / 118b. Gate dielectric 116a / 116b represents any number of dielectric layers present between the nanoribbon 104 and the gate electrode 118a / 118b. Gate dielectric 116a / 116b may also be present on the surface of other structures within the gate trench, such as on the sub-fin region 108. Gate dielectric 116a / 116b may include any suitable (one or more) gate dielectric materials. In some embodiments, gate dielectric 116a / 116b includes a layer of native oxide material (e.g., silicon dioxide) on the nanoribbon or other semiconductor region that constitutes the channel region of the device, and a layer of high-K dielectric material (e.g., hafnium oxide) on the native oxide.

[0038] Gate electrodes 118a / 118b can represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layer. In some embodiments, gate electrodes 118a / 118b include one or more work function metals surrounding nanoribbons 104. In some embodiments, one of semiconductor devices 101 and 103 is a p-channel device including a work function metal having titanium surrounding its nanoribbons 104, and the other semiconductor device is an n-channel device including a work function metal having tungsten surrounding its nanoribbons 104. Gate electrodes 118a / 118b can also include a filler metal or other conductive material (e.g., tungsten, ruthenium, molybdenum, cobalt) surrounding the work function metal to provide a complete gate electrode structure. In some embodiments, a gate cap 119 can be formed over gate electrodes 118a / 118b to protect underlying materials during processing. Gate cap 119 can be any suitable dielectric material, such as silicon nitride.

[0039] In some embodiments, adjacent gate structures can be separated along a second direction (e.g., across the page) by gate cuts 120, which act as a dielectric barrier or wall between the gate structures. Gate cuts 120 extend vertically (e.g., in a third direction) through at least the entire thickness of the adjacent gate structures. In some embodiments, gate cuts 120 also extend through at least a portion of dielectric filler 106. In some embodiments, gate cuts 120 are formed from various dielectric materials. For example, gate cuts 120 include a dielectric liner 122 along the outer edge of gate cuts 120, and a dielectric filler 124 on dielectric liner 122 and within an inner portion of gate cuts 120. In some embodiments, dielectric liner 122 includes a high-k dielectric material, such as silicon nitride, and dielectric filler 124 includes a medium-k or low-k dielectric material (e.g., a dielectric having a dielectric constant of approximately 4.5 or less), such as silicon dioxide, porous silicon dioxide, or a flowable oxide. The dielectric filler 124 may also include one or more air gaps or voids, which may further reduce the dielectric constant of the gate cut 120. The gate cut 120 may have a top width along the second direction between about 10 nm and about 100 nm, or between about 30 nm and about 50 nm.

[0040] According to some embodiments, the gate cut 120 extends across the entire width of the gate trench in a first direction, such as Figure 1B1. As shown, the gate cut 120 does not extend beyond the spacer structure 114 in the first direction. As will be discussed in more detail herein, the gate cut 120 is formed after the gate structure is formed so that the gate dielectric 116a / 116b does not extend along the sidewalls of the gate cut 120, although ends of the gate dielectric 116a / 116b may abut the sidewalls of the gate cut 120. Therefore, the sidewalls of the gate cut 120 extending in the first direction may directly contact the gate electrodes 118a and 118b, and the sidewalls of the gate cut 120 extending in the second direction may directly contact the spacer structure 114.

[0041] Manufacturing method

[0042] Figure 2A-11A and Figure 2B-11B Included are cross-sectional and plan views, respectively, that together illustrate an example process for forming an integrated circuit having semiconductor devices with gate cuts defined within gate trenches between the devices, according to an embodiment of the present disclosure. Figure 2A-11A Represents the performance of a semiconductor device across a range of Figure 1A Similar cross-sectional view, and Figure 2B-11B The corresponding plan views at each stage of fabrication are represented. Each set of figures sharing the same letter shows an exemplary structure resulting from the process flow up to that point in time, so the structure shown evolves as the process flow continues, ultimately appearing in Figures 11A-11B In the structure shown, it is similar to Figure 1A and Figure 1B The structure shown. Such a structure may be part of an entire integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed-signal circuitry. Thus, the integrated circuit structure shown may be part of a larger integrated circuit that includes other integrated circuit systems not shown. Example materials and process parameters are given, but other materials and process parameters may also be used, as will be understood in light of this disclosure. Although the fabrication of a single gate cut is shown in the foregoing figures, it should be understood that any number of similar gate cuts may be fabricated on an integrated circuit using the same processes discussed herein.

[0043] Figure 2A and Figure 2BA cross-sectional view through a substrate 201 and a plan view of the substrate 201 with a series of material layers formed thereon are shown, according to an embodiment of the present disclosure. Alternating material layers can be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 can be deposited on the substrate 201. The description above of the substrate 102 also applies to the substrate 201. Figure 2B The plan view of FIG. 1 shows the topmost semiconductor layer 204 of the layer stack.

[0044] According to some embodiments, sacrificial layer 202 has a different material composition than semiconductor layer 204. In some embodiments, sacrificial layer 202 is silicon germanium (SiGe), while semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a Group III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layer 202 and semiconductor layer 204, the germanium concentration between sacrificial layer 202 and semiconductor layer 204 is different. For example, sacrificial layer 202 can include a higher germanium content than semiconductor layer 204. In some examples, semiconductor layer 204 can be doped with an n-type dopant (to create a p-channel transistor) or a p-type dopant (to create an n-channel transistor).

[0045] Although the dimensions may vary from one exemplary embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer 204 may be substantially the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and the semiconductor layer 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0046] Figure 3A and Figure 3B and FIG. 3 respectively show the following embodiments after forming a cover layer 302 and subsequently forming a fin under the cover layer 302. Figure 2A and Figure 2B The capping layer 302 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 302 is patterned into a plurality of rows to form corresponding rows of fins from an alternating stack of layers of sacrificial layer 202 and semiconductor layer 204. The rows of fins are arranged in a first direction (e.g., in and out) Figure 3Aof pages) extend vertically.

[0047] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 201. The etched portion of substrate 201 may be filled with dielectric layer 304, which serves as shallow trench isolation (STI) between adjacent fins. Dielectric layer 304 may be any suitable dielectric material, such as silicon dioxide. In accordance with some embodiments, sub-fin region 306 represents the remaining portion of substrate 201 between dielectric layers 304.

[0048] Figure 4A and Figure 4B respectively show the following diagrams after forming the sacrificial gate 402 according to some embodiments. Figure 3A and Figure 3B In the cross-sectional and plan views of the structure shown, the sacrificial gate 402 extends across the fin in a second direction different from the first direction. The sacrificial gate 402 can extend across the fin in the second direction orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed as parallel strips across the integrated circuit and is removed in all areas not protected by the gate mask layer. The sacrificial gate 402 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 comprises polysilicon.

[0049] After forming the sacrificial gate 402, a spacer structure 404 may be formed on the sidewalls of the sacrificial gate 402. According to some embodiments, the dielectric material is blanket deposited over the entire structure and etched back to form the spacer structure 404 on the sidewalls of any structure extending above the substrate 201. Figure 4B As shown, the spacer structure 404 extends along the second direction and along the sides of the sacrificial gate 402. In some embodiments, the spacer structure may also be formed on the sides of the fin that are not under the sacrificial gate 402. The spacer structure 404 may be any suitable dielectric material, such as silicon nitride.

[0050] Figure 5A and Figure 5B 5. FIG. 5 shows, respectively, after removing any exposed fins and subsequently forming source or drain regions 502 at the ends of the fins, according to some embodiments. Figure 4A and Figure 4B 4. Cross-sectional and plan views of the structure shown. Any anisotropic etching process, such as reactive ion etching (RIE), can be used to remove the exposed fin portion (e.g., not protected by the sacrificial gate 402 or the spacer structure 404). According to some embodiments, removing the exposed fin portion creates source or drain trenches that alternate with the gate trenches (currently filled with the sacrificial gate 402) along a first direction.

[0051] According to some embodiments, the source or drain region 502 may be formed by the exposed end of the fin within the source / drain trench. The source or drain region may be formed in the area previously occupied by the exposed fin adjacent to the spacer structure 404. According to some embodiments, the source or drain region 502 is epitaxially grown from the exposed semiconductor material at the end of the semiconductor layer 204. In some example embodiments, either the source or drain region 502 may be an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe).

[0052] According to some embodiments, a dielectric filler 504 is provided within the source / drain trench. In some examples, the dielectric filler 504 occupies the remaining volume within the source / drain trench surrounding the source or drain region 502 and possibly above the source or drain region 502. The dielectric filler 504 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 504 extends up to the top surface of the spacer structure 404 and is flush with the top surface of the spacer structure 404 (e.g., after a polishing process).

[0053] Figure 6A and Figure 6B 4 and 4, respectively, after removing the sacrificial gate 402 and after removing the sacrificial layer 202 according to some embodiments. Figure 5A and Figure 5B Cross-sectional and plan views of the structure shown. In examples where any gate mask layers are still present, they can also be removed at this time. Once the sacrificial gate 402 is removed, the fins beneath the sacrificial gate 402 are exposed.

[0054] In examples where the fins include alternating semiconductor layers, the sacrificial layer 202 is selectively removed to release the nanoribbons 602 extending between the corresponding source or drain regions 502. Each set of vertical nanoribbons 602 represents a semiconductor or channel region of a different semiconductor device. It should be understood that the nanoribbons 602 can also be nanowires or nanosheets (e.g., from a fork-sheet arrangement) or fins (e.g., for a finFET arrangement). The sacrificial gate 402 and the sacrificial layer 202 can be removed using the same isotropic etching process or different isotropic etching processes.

[0055] Figure 7A and Figure 7B Figures 1 and 2 respectively show the gate structure after formation and subsequent polishing according to some embodiments. Figure 6A and Figure 6B6. The gate structure includes a gate dielectric 702 and a conductive gate electrode 704. Before forming the gate electrode 704, the gate dielectric 702 can first be formed around the nanoribbon 602. The gate dielectric 702 can include any suitable dielectric material (e.g., silicon dioxide and / or a high-k dielectric material). For example, examples of high-k dielectric materials include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 702 includes a hafnium oxide layer having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 702 can include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, gate dielectric 702 can include a first layer on nanoribbon 602 and a second layer on the first layer. The first layer can be, for example, an oxide of the semiconductor material of nanoribbon 602 (e.g., silicon dioxide), and the second layer can be a high-k dielectric material (e.g., hafnium oxide). More generally, gate dielectric 702 can include any number of dielectric layers. According to some embodiments, gate dielectric 702 is formed along all surfaces exposed within the gate trench, such as along the inner sidewalls of the spacer structure (e.g., Figure 7B as shown) and along the top surface of the dielectric layer 304 and the sub-fin region 306.

[0056] As described above, the gate electrode 704 can represent any number of conductive layers. To give a few examples, the conductive gate electrode 704 can be deposited using electroplating, chemical plating, CVD, PECVD, ALD or PVD. In some embodiments, the gate electrode 704 includes doped polysilicon, a metal, or a metal alloy. Suitable example metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode 704 may include, for example, a metal filler material and one or more work function layers, a resistance reduction layer and / or a barrier layer. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate. After forming the gate structure, the entire structure may be polished or planarized so that the top surface of the gate structure (e.g., the top surface of the gate electrode 704) is flush with the top surface of other semiconductor elements (such as the spacer structure 404 defining the gate trench).

[0057] Figure 8A and Figure 8B respectively show the gate cap 802 after it is formed according to some embodiments. Figure 7A and Figure 7Bsectional and plan views of the structure shown. The top of the gate electrode 704 can be recessed using any suitable isotropic etching process, and the recessed area within the gate trench can then be filled with a dielectric material to form a gate cap 802. The gate cap 802 can be any suitable dielectric material, such as silicon nitride, for protecting the underlying gate electrode 704. In some examples, the gate cap 802 is the same dielectric material as the spacer structure 404. Note that the gate dielectric 702 can be sandwiched between the gate cap 802 and the spacer structure 404, as shown in FIG. Figure 8B shown.

[0058] Figure 9A and Figure 9B and FIG. 1 , respectively, after forming a gate cut recess 902 through at least the entire thickness of the gate electrode 704 according to some embodiments. Figure 8A and Figure 8B 802. A mask structure may first be formed over the gate cap 802 and patterned to form an opening through the mask structure to expose a portion of the gate cap 802 underneath. The exposed portion of the gate cap 802 within the opening may also be removed to expose the gate electrode 704 underneath, in which a gate cut recess 902 will be formed. The gate cut recess 902 may have a height-to-width aspect ratio of 5:1 or higher, for example, between 6:1 and 10:1, and may be formed via a series of RIE and passivation steps to etch the conductive material through the gate electrode 704. The gate cut recess 902 may be tapered and have a maximum width along the top surface of the gate electrode 704 of between about 10 nm and about 100 nm, or between about 30 nm and about 50 nm. According to some embodiments, the RIE process used to form the gate cut recess 902 exhibits a high etch selectivity between metal and dielectric, such that the dielectric material of the spacer structure 404, the gate dielectric 702, and the dielectric filler 504 are not significantly etched during the formation of the gate cut recess 902. As a result, the gate cut recess 902 can be defined within the gate trench, such as Figure 9B shown.

[0059] Figure 10A and Figure 10B and FIG. 1 respectively show the gate dielectric 702 after removal from the gate cut recess 902 according to some embodiments. Figure 9A and Figure 9Bsectional and plan views of the structure shown. The gate dielectric 702 can be removed from the inner sidewalls of the spacer structure 404 within the gate cut recess 902 and also from the bottom surface of the gate cut recess 902 using any suitable isotropic etching process. In some embodiments, removing the gate dielectric 702 from the bottom of the gate cut recess 902 exposes the dielectric layer 304 at the bottom of the gate cut recess 902. In some embodiments, a metal isotropic etch can be performed briefly to remove any remaining portions of the gate electrode 704 at the bottom corners and / or edges of the gate cut recess 902.

[0060] Figure 11A and Figure 11B and FIG. 1 respectively show the gate cut 1101 formed in the gate cut groove 902 according to some embodiments. Figure 10A and Figure 10B Cross-sectional and plan views of the structure shown. Gate cut 1101 can include one or more dielectric materials within gate cut recess 902. In the example shown, gate cut 1101 includes a dielectric liner 1102 and a dielectric filler 1104. According to some embodiments, dielectric liner 1102 includes a high-k dielectric material, such as silicon nitride, or any other material having a dielectric constant of at least 6.5. For example, dielectric liner 1102 can be conformally deposited within gate cut recess 902 using ALD. After forming dielectric liner 1102, dielectric filler 1104 can be formed within the remaining volume of gate cut recess 902. According to some embodiments, dielectric filler 1104 includes a medium- or low-k dielectric material, such as silicon dioxide, a flowable oxide, or a porous oxide, or any other material having a dielectric constant of 4.5 or less, including one or more air gaps having a local dielectric constant of 1.0 to lower the overall or global dielectric constant of the dielectric gate cut structure. The dielectric filler 1104 may be deposited using any suitable plasma deposition technique, such as CVD. In other exemplary embodiments, the dielectric filler 1104 may also be conformally deposited using ALD or CVD so as to pinch off and close at a narrow portion toward the bottom of the gate cut recess 902. In some embodiments, the dielectric filler 1104 pinches off at the top of the gate cut recess 902, such that an air gap is formed in the central region of the gate cut 1101. Figure 11BAs shown, the gate cut 1101 does not extend outside the gate trench along the first direction (e.g., does not extend beyond the spacer structure 404 along the first direction). According to some embodiments, the sidewalls of the gate cut 1101 extending along the first direction directly contact the gate electrode 704 on either side, and the sidewalls of the gate cut 1101 extending along the second direction directly contact the spacer structure 404 on either side. In addition, the gate dielectric 702 does not extend up to the sidewalls of the gate cut 1101, such that the gate cut 1101 directly contacts the gate electrode 704.

[0061] Figure 12 An example embodiment of a chip package 1200 according to an embodiment of the present disclosure is shown. As can be seen, the chip package 1200 includes one or more dies 1202. The one or more dies 1202 may include at least one integrated circuit having a semiconductor device (such as any semiconductor device disclosed herein). In some example configurations, the one or more dies 1202 may include any other circuitry for interfacing with other devices formed on the die or other devices connected to the chip package 1200.

[0062] As can be further seen, chip package 1200 includes a housing 1204 bonded to a package substrate 1206. Housing 1204 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of chip package 1200. One or more dies 1202 can be conductively coupled to package substrate 1206 using connectors 1208, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonds, to name a few. Package substrate 1206 can be any standard or proprietary packaging substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and lines) extending through the dielectric material between faces of package substrate 1206 or between different locations on each face. In some embodiments, package substrate 1206 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 1212 may be provided on an opposing side of the package substrate 1206 for conductive contacting, for example, a printed circuit board (PCB). One or more vias 1210 extend through the thickness of the package substrate 1206 to provide a conductive path between one or more connectors 1208 and one or more contacts 1212. For ease of illustration, the vias 1210 are shown as a single, inline via through the package substrate 1206, but other configurations may be used (e.g., inlaid, dual inlaid, through-silicon vias, or vias that meander through the thickness of the substrate 1206 to contact one or more interconnect structures at intermediate locations therein). In other embodiments, the vias 1210 are made of multiple smaller stacked vias or are staggered at different locations across the package substrate 1206. In the embodiment shown, the contacts 1212 are solder balls (e.g., for bump-based connectors or ball grid array arrangements), but any suitable package bonding mechanism (e.g., pins in a pin grid array arrangement or pads in a land grid array arrangement) may be used. In some embodiments, solder resist is provided between contacts 1212 to inhibit short circuits.

[0063] In some embodiments, molding material 1214 can be disposed around one or more dies 1202 contained within housing 1204 (e.g., as an underfill material between die 1202 and package substrate 1206, and as an overfill material between die 1202 and housing 1204). While the size and mass of molding material 1214 can vary from one embodiment to the next, in some embodiments, molding material 1214 has a thickness of less than 1 mm. Example materials that can be used for molding material 1214 include epoxy molding materials, if appropriate. In some cases, in addition to being electrically insulating, molding material 1214 is thermally conductive.

[0064] method

[0065] Figure 13 is a flow chart of a method 1300 for forming at least a portion of an integrated circuit according to an embodiment. The various operations of the method 1300 may be performed in Figure 2A-11A and Figure 2B-11B . However, the correlation of the various operations of method 1300 with the specific components shown in the aforementioned figures is not intended to imply any architectural and / or usage limitations. Rather, the aforementioned figures provide an example embodiment of method 1300. Other operations may be performed before, during, or after any operation of method 1300. For example, method 1300 does not explicitly describe all processes that are performed to form a common transistor structure. Some operations of method 1300 may be performed in an order different from that shown.

[0066] According to some embodiments, method 1300 begins with operation 1302, where any number of parallel semiconductor fins are formed. The semiconductor material in the fins can be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed from a material deposited on an underlying substrate. In one such example, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process, wherein one type of alternating layer is selectively etched away to release the other type of alternating layer in the channel region so that a gate-all-around (GAA) process can then be performed. The alternating layers can be blanket deposited and then etched into the fins, or deposited into fin-shaped trenches. The fins can also include a cap structure over each fin that is used to define the position of the fins during, for example, an RIE process. The cap structure can be a dielectric material such as silicon nitride.

[0067] According to some embodiments, a dielectric layer is formed around the sub-fin portions of one or more fins. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate and can form the dielectric layer within the recessed portion of the substrate. Thus, the dielectric layer serves as shallow trench isolation (STI) between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide.

[0068] Method 1300 continues with operation 1304, in which a sacrificial gate and spacer structure are formed over the fin. The sacrificial gate may be patterned using a gate mask layer in strips extending orthogonally over the fin (many gate mask layers and corresponding sacrificial gates may be formed parallel to each other (e.g., forming a cross-hatched pattern with the fin)). The gate mask layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed of any suitable material that may be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon. The spacer structure may be deposited and then etched back such that the spacer structure remains mostly only on the sidewalls of any exposed structure. According to some embodiments, the spacer structure may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0069] Method 1300 continues with operation 1306, wherein a source or drain region is formed at the end of the semiconductor region of each fin. Any portion of the fin not protected by the sacrificial gate and spacer structure can be removed using, for example, an anisotropic etching process, and then the source or drain region is epitaxially grown from the exposed end of the semiconductor layer in the fin. In some example embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe). Another dielectric filler can be formed adjacent to each source or drain region for additional electrical isolation between adjacent regions. The dielectric filler can also extend above the top surface of the source or drain region. In some embodiments, a topside conductive contact can be formed through the dielectric filler to contact one or more of the source or drain regions.

[0070] Method 1300 continues with operation 1308, where the sacrificial gate is removed and replaced with a gate structure. The sacrificial gate can be removed using an isotropic etching process that selectively removes all material from the sacrificial gate, thereby exposing the individual fins between the sets of spacer structures. In the example case of a GAA transistor, any sacrificial layer within the exposed fins between the spacer structures can also be removed to release the nanoribbons, nanosheets, or nanowires of semiconductor material.

[0071] The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, a gate dielectric is first formed over the exposed semiconductor region between the spacer structures, and then a gate electrode is formed within the remaining portion of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process such as ALD. The gate electrode may include any number of layers of conductive material, such as any metal, metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples. In some embodiments, the gate electrode may be recessed and a dielectric gate cap may be formed within the recessed region. The dielectric gate cap may have a thickness, for example, between 10 nm and 20 nm, such as approximately 15 nm.

[0072] Method 1300 continues with operation 1310, where a recess is formed through the entire thickness of the gate structure. A mask structure may be formed over the gate structure, and an opening may be formed through the mask structure (and gate cap, if present) to expose a portion of the underlying gate electrode. According to some embodiments, the opening through the mask structure is located at a location where a recess will be formed through the underlying gate electrode. The mask structure may include any number of hard mask layers, such as any dielectric layer or a carbon hard mask layer. The opening may be formed using a directional RIE process. According to some embodiments, the recess through the gate electrode extends through at least the entire thickness of the gate electrode, such that the recess terminates at the gate dielectric at the bottom of the gate trench. According to some embodiments, the recess is formed using a selective anisotropic RIE process, such that metal material of the gate electrode is removed while substantially removing any exposed dielectric material, such as dielectric material from the spacer structure. As a result, according to some embodiments, the recess is confined within the gate trench (e.g., does not extend beyond the spacer structure in the first direction). Following the anisotropic metal etching process, an isotropic etching process may be performed to remove any exposed portion of the gate dielectric within the recess.

[0073] Method 1300 continues with operation 1312, where a dielectric material is formed within the recess to form a gate cut. In some embodiments, the recess is filled with a single high-k dielectric material, such as silicon nitride. In some embodiments, the gate cut includes a dielectric liner first formed within the recess and a dielectric filler formed over the dielectric liner. In some embodiments, the dielectric liner comprises a high-k dielectric material, such as silicon nitride, deposited using ALD. In some embodiments, as described above, the dielectric filler comprises a medium- or low-k dielectric material, such as silicon dioxide, a flowable oxide, or any other material having a dielectric constant of 4.5 or less. The dielectric filler may be polished back until the top surface of the dielectric filler is flush with the top surface of the spacer structure and / or the top surface of the gate cap on the gate electrode. Due to the confines of the recess within the gate trench, the resulting gate cut is also confined within the gate trench so that it does not extend beyond the spacer structure in the first direction. Furthermore, because the gate cut is formed after the gate structure is formed, no gate dielectric is formed along the sidewalls of the gate cut.

[0074] Example System

[0075] Figure 14 1400 is an example computing system implemented with one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, computing system 1400 houses a motherboard 1402. Motherboard 1402 may include a plurality of components, including, but not limited to, a processor 1404 and at least one communication chip 1406, each of which may be physically and electrically coupled to motherboard 1402 or otherwise integrated therein. It should be understood that motherboard 1402 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 1400.

[0076] Depending on its application, computing system 1400 may include one or more other components that may or may not be physically and electrically coupled to motherboard 1402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disc (CD), a digital versatile disc (DVD), etc.). Any component included in computing system 1400 may include one or more integrated circuit structures or devices configured according to example embodiments, such as a module including an integrated circuit on a substrate having semiconductor devices including one or more gate cuts that are self-aligned within gate trenches between adjacent devices. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 1406 may be part of processor 1404 or otherwise integrated into processor 1404).

[0077] The communication chip 1406 implements wireless communications for transmitting data to and from the computing system 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data via a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1406 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system 1400 may include multiple communication chips 1406. For example, the first communication chip 1406 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1406 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0078] The processor 1404 of the computing system 1400 includes an integrated circuit die packaged within the processor 1404. In some embodiments, the integrated circuit die of the processor includes onboard circuitry implemented using one or more semiconductor devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0079] The communication chip 1406 may also include an integrated circuit die packaged within the communication chip 1406. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, it is noted that multi-standard wireless capabilities may be integrated directly into the processor 1404 (e.g., where the functionality of any chip 1406 is integrated into the processor 1404, rather than having a separate communication chip). It is also noted that the processor 1404 may be a chipset that has such wireless capabilities. In short, any number of processors 1404 and / or communication chips 1406 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0080] In various embodiments, computing system 1400 may be a laptop computer, a netbook, a notebook, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

[0081] It should be understood that in some embodiments, the various components of the computing system 1400 can be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components can be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0082] Other Example Embodiments

[0083] The following examples relate to further embodiments from which numerous arrangements and configurations will be apparent.

[0084] Example 1 is an integrated circuit comprising: a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region; a spacer structure on a sidewall of the gate structure and extending along the second direction with the gate structure; and a gate cut adjacent to the semiconductor device and extending through the entire height of the gate structure along a third direction. The gate structure comprises a gate dielectric and a gate electrode located on the gate dielectric. The gate cut extends between the spacer structures in the first direction and does not extend beyond the spacer structure. In this manner, an end of the gate cut can effectively abut the spacer structure. The gate dielectric does not extend along the sidewalls of the gate cut that extend along the first direction, although an end of the gate dielectric can also abut the sidewalls of the gate cut.

[0085] Example 2 includes the integrated circuit of Example 1, wherein the gate cut comprises silicon and nitrogen.

[0086] Example 3 includes the integrated circuit of Example 1 or 2, wherein the gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

[0087] Example 4 includes the integrated circuit of Example 3, wherein the dielectric liner comprises silicon and nitrogen, and the dielectric fill comprises silicon and oxygen.

[0088] Example 5 includes the integrated circuit of any of Examples 1-4, wherein an end of the gate dielectric abuts a sidewall of the gate cut extending along the first direction.

[0089] Example 6 includes the integrated circuit of Example 5, wherein the end is a first end of the gate dielectric, and wherein a second end of the gate dielectric abuts a sidewall of the gate cut.

[0090] Example 7 includes the integrated circuit of any of Examples 1-6, wherein the gate electrode directly contacts a sidewall of the gate cut.

[0091] Example 8 includes the integrated circuit of any of Examples 1-7, wherein the sidewall of the gate cut is a first sidewall, and wherein a second sidewall of the gate cut extending along the second direction directly contacts one of the spacer structures.

[0092] Example 9 includes the integrated circuit of any of Examples 1-8, wherein a width along the second direction at a top surface of the gate cut is between approximately 25 nm and approximately 50 nm.

[0093] Example 10 includes the integrated circuit of any of Examples 1-9, wherein the semiconductor region includes a plurality of semiconductor nanoribbons.

[0094] Example 11 includes the integrated circuit of Example 10, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0095] Example 12 is a printed circuit board including the integrated circuit of any of Examples 1-11.

[0096] Example 13 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies comprises: a semiconductor region extending from a source or drain region in a first direction; a gate structure extending in a second direction over the semiconductor region; a spacer structure on a sidewall of the gate structure and extending along the second direction together with the gate structure; and a gate cutout adjacent to the semiconductor region and extending through the entire height of the gate structure along a third direction. The gate structure comprises a gate dielectric and a gate electrode located on the gate dielectric. The gate cutout extends between the spacer structures in the first direction and does not extend beyond the spacer structure. An end of the gate dielectric abuts the sidewall of the gate cutout extending along the first direction, and the gate dielectric does not extend along the sidewall of the gate cutout in the third direction.

[0097] Example 14 includes the electronic device of Example 13, wherein the gate cut comprises silicon and nitrogen.

[0098] Example 15 includes the electronic device of Example 13 or 14, wherein the gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

[0099] Example 16 includes the electronic device of Example 15, wherein the dielectric liner comprises silicon and nitrogen, and the dielectric fill comprises silicon and oxygen.

[0100] Example 17 includes the electronic device of any of Examples 13-16, wherein the gate electrode directly contacts a sidewall of the gate cut.

[0101] Example 18 includes the electronic device of any of Examples 13-17, wherein the sidewall of the gate cut is a first sidewall, and wherein a second sidewall of the gate cut extending along the second direction directly contacts one of the spacer structures.

[0102] Example 19 includes the electronic device of any of Examples 13-18, wherein a width along the second direction at a top surface of the gate cut is between about 25 nm and about 50 nm.

[0103] Example 20 includes the electronic device of any of Examples 13-19, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

[0104] Example 21 includes the electronic device of Example 20, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0105] Example 22 includes the electronic device of any of Examples 13-21, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0106] Example 23 is a method of forming an integrated circuit. The method includes forming one or more fins comprising a semiconductor material, the one or more fins extending above a substrate, and each fin extending parallel to each other in a first direction; forming a sacrificial gate extending above the semiconductor material in a second direction different from the first direction; forming a spacer structure on a sidewall of the sacrificial gate; removing the sacrificial gate; forming a gate structure above the semiconductor material in the second direction and between the spacer structures; forming a recess extending across the gate structure in the first direction and extending through the entire height of the gate structure in a third direction, wherein the recess is between the spacer structures along a boundary in the first direction; and forming one or more dielectric materials within the recess.

[0107] Example 24 includes the method of Example 23, wherein forming the gate structure includes forming a gate dielectric and forming a gate electrode on the gate dielectric.

[0108] Example 25 includes the method of Example 24, further comprising removing the exposed portion of the gate dielectric within the recess.

[0109] Example 26 includes the method of Example 24 or 25, wherein forming the recess comprises removing the gate electrode using a reactive ion etching (RIE) process while substantially not removing the gate dielectric and the spacer structure.

[0110] Example 27 includes the method of any of Examples 24-26, wherein forming the gate dielectric includes forming a high-k dielectric layer.

[0111] Example 28 includes the method of any of Examples 23-27, wherein forming the one or more dielectric materials includes forming a dielectric liner and forming a dielectric filler on the dielectric liner.

[0112] Example 29 is an integrated circuit comprising: a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region; a spacer structure on a sidewall of the gate structure and extending along the second direction together with the gate structure; and a gate cut adjacent to the semiconductor device and extending through the entire height of the gate structure along a third direction. The gate structure includes a gate dielectric and a gate electrode located on the gate dielectric. The gate cut includes a first sidewall extending along the first direction and directly contacting the gate electrode, and the gate cut includes a second sidewall extending along the second direction and directly contacting one of the spacer structures.

[0113] Example 30 includes the integrated circuit of Example 29, wherein the gate cut comprises silicon and nitrogen.

[0114] Example 31 includes the integrated circuit of Example 29 or 30, wherein the gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

[0115] Example 32 includes the integrated circuit of Example 31, wherein the dielectric liner comprises silicon and nitrogen, and the dielectric fill comprises silicon and oxygen.

[0116] Example 33 includes the integrated circuit of any of Examples 29-32, wherein an end of the gate dielectric abuts the first sidewall of the gate cut.

[0117] Example 34 includes the integrated circuit of Example 36, wherein the gate dielectric does not extend in the third direction along the first sidewall of the gate cut.

[0118] Example 35 includes the integrated circuit of any of Examples 29-34, wherein the gate cut does not extend beyond the spacer structure along the first direction.

[0119] Example 36 includes the integrated circuit of any of Examples 29-35, wherein a width along the second direction at a top surface of the gate cut is between approximately 25 nm and approximately 50 nm.

[0120] Example 37 includes the integrated circuit of any of Examples 29-36, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

[0121] Example 38 includes the integrated circuit of Example 37, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0122] Example 39 is a printed circuit board including the integrated circuit of any of Examples 29-38.

[0123] The foregoing description of the embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the present disclosure. The scope of the present disclosure is not intended to be limited by this detailed description, but rather by the following claims.

Claims

1. An integrated circuit comprising: source or drain region; a semiconductor region extending from the source or drain region in a first direction; a gate structure extending in a second direction over the semiconductor region, the gate structure comprising a gate dielectric and a gate electrode located on the gate dielectric; a spacer structure on a sidewall of the gate structure and extending along the second direction; as well as a gate cut extending through the entire height of the gate structure along a third direction, wherein the gate cut extends between the spacer structures in the first direction and does not extend beyond the spacer structures, and wherein the gate dielectric is absent on sidewalls of the gate cut extending along the first direction.

2. The integrated circuit according to claim 1, wherein: The gate cut includes silicon and nitrogen.

3. The integrated circuit according to claim 1, wherein: The gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

4. The integrated circuit according to claim 3, wherein: The dielectric liner includes silicon and nitrogen, and the dielectric fill includes silicon and oxygen.

5. The integrated circuit according to claim 1, wherein: An end portion of the gate dielectric abuts a sidewall of the gate cutout extending along the first direction.

6. The integrated circuit according to claim 5, wherein: The end is a first end of the gate dielectric, and wherein a second end of the gate dielectric abuts the sidewall of the gate cut.

7. The integrated circuit according to claim 1, wherein: The gate electrode directly contacts the sidewall of the gate cut.

8. The integrated circuit according to any one of claims 1 to 7, wherein: The sidewall of the gate cut is a first sidewall, and wherein a second sidewall of the gate cut extending along the second direction directly contacts one of the spacer structures.

9. The integrated circuit according to any one of claims 1 to 7, wherein: A width along the second direction at a top surface of the gate cut is between about 25 nm and about 50 nm.

10. The integrated circuit according to any one of claims 1 to 7, wherein: The semiconductor region includes a plurality of semiconductor nanoribbons.

11. The integrated circuit according to claim 10, wherein: The plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

12. A printed circuit board comprising the integrated circuit according to any one of claims 1 to 7.

13. An electronic device comprising: A chip package comprising one or more dies, at least one of the one or more dies comprising: a semiconductor region extending from the source or drain region in a first direction; a gate structure extending in a second direction over the semiconductor region, the gate structure comprising a gate dielectric and a gate electrode located on the gate dielectric; a spacer structure located on a sidewall of the gate structure and extending along the second direction together with the gate structure; and a gate cut adjacent to the semiconductor region and extending through the entire height of the gate structure along a third direction, wherein the gate cut extends between the spacer structures in the first direction and does not extend beyond the spacer structures, and wherein ends of the gate dielectric abut sidewalls of the gate cut extending along the first direction and the gate dielectric does not extend along the sidewalls of the gate cut in the third direction.

14. The electronic device according to claim 13, wherein The gate cut includes silicon and nitrogen.

15. The electronic device according to claim 13, wherein The gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

16. The electronic device according to claim 15, wherein The dielectric liner includes silicon and nitrogen, and the dielectric fill includes silicon and oxygen.

17. The electronic device according to any one of claims 13 to 16, wherein: The gate electrode directly contacts the sidewall of the gate cut.

18. The electronic device according to any one of claims 13 to 16, wherein: The sidewall of the gate cut is a first sidewall, and wherein a second sidewall of the gate cut extending along the second direction directly contacts one of the spacer structures.

19. The electronic device according to any one of claims 13 to 16, further comprising a printed circuit board, wherein The chip package is coupled to the printed circuit board.

20. An integrated circuit comprising: A semiconductor device comprising a semiconductor region extending from a source or drain region in a first direction, and a gate structure extending in a second direction over the semiconductor region, the second direction being orthogonal to the first direction, the gate structure comprising a gate dielectric and a gate electrode located on the gate dielectric; a spacer structure, located on a sidewall of the gate structure and extending along the second direction together with the gate structure; as well as a gate cut adjacent to the semiconductor device and extending along a third direction through the entire height of the gate structure, wherein the gate cut includes a first sidewall extending along the first direction and directly contacting the gate electrode, and wherein the gate cut includes a second sidewall extending along the second direction and directly contacting one of the spacer structures.

21. The integrated circuit of claim 20, wherein: The gate cut includes silicon and nitrogen.

22. The integrated circuit of claim 20, wherein: The gate cut includes a dielectric liner and a dielectric filler on the dielectric liner.

23. The integrated circuit of claim 20, wherein: The gate cut does not extend beyond the spacer structure along the first direction.

24. An integrated circuit according to any one of claims 20 to 23, wherein A width along the second direction at a top surface of the gate cut is between about 25 nm and about 50 nm.

25. An integrated circuit according to any one of claims 20 to 23, wherein The semiconductor region includes a plurality of semiconductor nanoribbons.

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